2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
44 vec4_visitor::nir_setup_uniforms()
46 uniforms
= nir
->num_uniforms
/ 16;
50 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
52 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
53 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
54 nir_locals
[i
] = dst_reg();
57 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
58 unsigned array_elems
=
59 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
60 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
61 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
63 if (reg
->bit_size
== 64)
64 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
67 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
69 nir_emit_cf_list(&impl
->body
);
73 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
75 exec_list_validate(list
);
76 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
79 nir_emit_if(nir_cf_node_as_if(node
));
82 case nir_cf_node_loop
:
83 nir_emit_loop(nir_cf_node_as_loop(node
));
86 case nir_cf_node_block
:
87 nir_emit_block(nir_cf_node_as_block(node
));
91 unreachable("Invalid CFG node block");
97 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
99 /* First, put the condition in f0 */
100 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
101 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
102 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
104 /* We can just predicate based on the X channel, as the condition only
105 * goes on its own line */
106 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
108 nir_emit_cf_list(&if_stmt
->then_list
);
110 /* note: if the else is empty, dead CF elimination will remove it */
111 emit(BRW_OPCODE_ELSE
);
113 nir_emit_cf_list(&if_stmt
->else_list
);
115 emit(BRW_OPCODE_ENDIF
);
119 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
123 nir_emit_cf_list(&loop
->body
);
125 emit(BRW_OPCODE_WHILE
);
129 vec4_visitor::nir_emit_block(nir_block
*block
)
131 nir_foreach_instr(instr
, block
) {
132 nir_emit_instr(instr
);
137 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
141 switch (instr
->type
) {
142 case nir_instr_type_load_const
:
143 nir_emit_load_const(nir_instr_as_load_const(instr
));
146 case nir_instr_type_intrinsic
:
147 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
150 case nir_instr_type_alu
:
151 nir_emit_alu(nir_instr_as_alu(instr
));
154 case nir_instr_type_jump
:
155 nir_emit_jump(nir_instr_as_jump(instr
));
158 case nir_instr_type_tex
:
159 nir_emit_texture(nir_instr_as_tex(instr
));
162 case nir_instr_type_ssa_undef
:
163 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
167 unreachable("VS instruction not yet implemented by NIR->vec4");
172 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
173 unsigned base_offset
, nir_src
*indirect
)
177 reg
= v
->nir_locals
[nir_reg
->index
];
178 if (nir_reg
->bit_size
== 64)
179 reg
.type
= BRW_REGISTER_TYPE_DF
;
180 reg
= offset(reg
, 8, base_offset
);
183 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
191 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
195 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
196 if (dest
.ssa
.bit_size
== 64)
197 dst
.type
= BRW_REGISTER_TYPE_DF
;
198 nir_ssa_values
[dest
.ssa
.index
] = dst
;
201 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
207 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
209 return retype(get_nir_dest(dest
), type
);
213 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
215 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
219 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
220 unsigned num_components
)
225 assert(src
.ssa
!= NULL
);
226 reg
= nir_ssa_values
[src
.ssa
->index
];
229 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
233 reg
= retype(reg
, type
);
235 src_reg reg_as_src
= src_reg(reg
);
236 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
241 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
242 unsigned num_components
)
244 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
249 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
251 /* if type is not specified, default to signed int */
252 return get_nir_src(src
, nir_type_int32
, num_components
);
256 vec4_visitor::get_nir_src_imm(const nir_src
&src
)
258 assert(nir_src_num_components(src
) == 1);
259 assert(nir_src_bit_size(src
) == 32);
260 return nir_src_is_const(src
) ? src_reg(brw_imm_d(nir_src_as_int(src
))) :
265 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
267 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
269 if (nir_src_is_const(*offset_src
)) {
270 /* The only constant offset we should find is 0. brw_nir.c's
271 * add_const_offset_to_base() will fold other constant offsets
272 * into instr->const_index[0].
274 assert(nir_src_as_uint(*offset_src
) == 0);
278 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
282 setup_imm_df(const vec4_builder
&bld
, double v
)
284 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
285 assert(devinfo
->gen
>= 7);
287 if (devinfo
->gen
>= 8)
288 return brw_imm_df(v
);
290 /* gen7.5 does not support DF immediates straighforward but the DIM
291 * instruction allows to set the 64-bit immediate value.
293 if (devinfo
->is_haswell
) {
294 const vec4_builder ubld
= bld
.exec_all();
295 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
296 ubld
.DIM(dst
, brw_imm_df(v
));
297 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
300 /* gen7 does not support DF immediates */
311 /* Write the low 32-bit of the constant to the X:UD channel and the
312 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
313 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
314 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
315 * XXXX so any access to the VGRF only reads the constant data in these
318 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
319 for (unsigned n
= 0; n
< 2; n
++) {
320 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
321 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
322 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
325 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
329 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
333 if (instr
->def
.bit_size
== 64) {
334 reg
= dst_reg(VGRF
, alloc
.allocate(2));
335 reg
.type
= BRW_REGISTER_TYPE_DF
;
337 reg
= dst_reg(VGRF
, alloc
.allocate(1));
338 reg
.type
= BRW_REGISTER_TYPE_D
;
341 const vec4_builder ibld
= vec4_builder(this).at_end();
342 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
344 /* @FIXME: consider emitting vector operations to save some MOVs in
345 * cases where the components are representable in 8 bits.
346 * For now, we emit a MOV for each distinct value.
348 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
349 unsigned writemask
= 1 << i
;
351 if ((remaining
& writemask
) == 0)
354 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
355 if ((instr
->def
.bit_size
== 32 &&
356 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
357 (instr
->def
.bit_size
== 64 &&
358 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
363 reg
.writemask
= writemask
;
364 if (instr
->def
.bit_size
== 64) {
365 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
367 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
370 remaining
&= ~writemask
;
373 /* Set final writemask */
374 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
376 nir_ssa_values
[instr
->def
.index
] = reg
;
380 vec4_visitor::get_nir_ssbo_intrinsic_index(nir_intrinsic_instr
*instr
)
382 /* SSBO stores are weird in that their index is in src[1] */
383 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
386 if (nir_src_is_const(instr
->src
[src
])) {
387 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
388 nir_src_as_uint(instr
->src
[src
]);
389 surf_index
= brw_imm_ud(index
);
390 brw_mark_surface_used(&prog_data
->base
, index
);
392 surf_index
= src_reg(this, glsl_type::uint_type
);
393 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[src
], 1),
394 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
395 surf_index
= emit_uniformize(surf_index
);
397 brw_mark_surface_used(&prog_data
->base
,
398 prog_data
->base
.binding_table
.ssbo_start
+
399 nir
->info
.num_ssbos
- 1);
406 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
411 switch (instr
->intrinsic
) {
413 case nir_intrinsic_load_input
: {
414 /* We set EmitNoIndirectInput for VS */
415 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
417 dest
= get_nir_dest(instr
->dest
);
418 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
420 src
= src_reg(ATTR
, instr
->const_index
[0] + load_offset
,
421 glsl_type::uvec4_type
);
422 src
= retype(src
, dest
.type
);
424 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
426 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
427 src
.swizzle
= BRW_SWIZZLE_XYZW
;
428 shuffle_64bit_data(tmp
, src
, false);
429 emit(MOV(dest
, src_reg(tmp
)));
431 /* Swizzle source based on component layout qualifier */
432 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
433 emit(MOV(dest
, src
));
438 case nir_intrinsic_store_output
: {
439 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
440 int varying
= instr
->const_index
[0] + store_offset
;
442 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
445 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
446 instr
->num_components
);
447 data
= src_reg(this, glsl_type::dvec4_type
);
448 shuffle_64bit_data(dst_reg(data
), src
, true);
449 src
= retype(data
, BRW_REGISTER_TYPE_F
);
451 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
452 instr
->num_components
);
455 unsigned c
= nir_intrinsic_component(instr
);
456 output_reg
[varying
][c
] = dst_reg(src
);
457 output_num_components
[varying
][c
] = instr
->num_components
;
459 unsigned num_components
= instr
->num_components
;
463 output_reg
[varying
][c
] = dst_reg(src
);
464 output_num_components
[varying
][c
] = MIN2(4, num_components
);
466 if (is_64bit
&& num_components
> 4) {
467 assert(num_components
<= 8);
468 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
469 output_num_components
[varying
+ 1][c
] = num_components
- 4;
474 case nir_intrinsic_get_buffer_size
: {
475 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
476 nir_src_as_uint(instr
->src
[0]) : 0;
478 const unsigned index
=
479 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
480 dst_reg result_dst
= get_nir_dest(instr
->dest
);
481 vec4_instruction
*inst
= new(mem_ctx
)
482 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE
, result_dst
);
485 inst
->mlen
= 1; /* always at least one */
486 inst
->src
[1] = brw_imm_ud(index
);
488 /* MRF for the first parameter */
489 src_reg lod
= brw_imm_d(0);
490 int param_base
= inst
->base_mrf
;
491 int writemask
= WRITEMASK_X
;
492 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
496 brw_mark_surface_used(&prog_data
->base
, index
);
500 case nir_intrinsic_store_ssbo
: {
501 assert(devinfo
->gen
>= 7);
503 src_reg surf_index
= get_nir_ssbo_intrinsic_index(instr
);
504 src_reg offset_reg
= retype(get_nir_src_imm(instr
->src
[2]),
505 BRW_REGISTER_TYPE_UD
);
508 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
511 unsigned write_mask
= instr
->const_index
[0];
513 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
514 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
515 * typed and untyped messages and across hardware platforms, the
516 * current implementation of the untyped messages will transparently convert
517 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
518 * and enabling only channel X on the SEND instruction.
520 * The above, works well for full vector writes, but not for partial writes
521 * where we want to write some channels and not others, like when we have
522 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
523 * quite restrictive with regards to the channel enables we can configure in
524 * the message descriptor (not all combinations are allowed) we cannot simply
525 * implement these scenarios with a single message while keeping the
526 * aforementioned symmetry in the implementation. For now we de decided that
527 * it is better to keep the symmetry to reduce complexity, so in situations
528 * such as the one described we end up emitting two untyped write messages
529 * (one for xy and another for w).
531 * The code below packs consecutive channels into a single write message,
532 * detects gaps in the vector write and if needed, sends a second message
533 * with the remaining channels. If in the future we decide that we want to
534 * emit a single message at the expense of losing the symmetry in the
535 * implementation we can:
537 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
538 * message payload. In this mode we can write up to 8 offsets and dwords
539 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
540 * and select which of the 8 channels carry data to write by setting the
541 * appropriate writemask in the dst register of the SEND instruction.
542 * It would require to write a new generator opcode specifically for
543 * IvyBridge since we would need to prepare a SIMD8 payload that could
544 * use any channel, not just X.
546 * 2) For Haswell+: Simply send a single write message but set the writemask
547 * on the dst of the SEND instruction to select the channels we want to
548 * write. It would require to modify the current messages to receive
549 * and honor the writemask provided.
551 const vec4_builder bld
= vec4_builder(this).at_end()
552 .annotate(current_annotation
, base_ir
);
554 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
555 if (type_slots
== 2) {
556 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
557 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
558 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
561 uint8_t swizzle
[4] = { 0, 0, 0, 0};
562 int num_channels
= 0;
563 unsigned skipped_channels
= 0;
564 int num_components
= instr
->num_components
;
565 for (int i
= 0; i
< num_components
; i
++) {
566 /* Read components Z/W of a dvec from the appropriate place. We will
567 * also have to adjust the swizzle (we do that with the '% 4' below)
569 if (i
== 2 && type_slots
== 2)
570 val_reg
= byte_offset(val_reg
, REG_SIZE
);
572 /* Check if this channel needs to be written. If so, record the
573 * channel we need to take the data from in the swizzle array
575 int component_mask
= 1 << i
;
576 int write_test
= write_mask
& component_mask
;
578 /* If we are writing doubles we have to write 2 channels worth of
579 * of data (64 bits) for each double component.
581 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
583 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
586 /* If we don't have to write this channel it means we have a gap in the
587 * vector, so write the channels we accumulated until now, if any. Do
588 * the same if this was the last component in the vector, if we have
589 * enough channels for a full vec4 write or if we have processed
590 * components XY of a dvec (since components ZW are not in the same
593 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
594 (i
== 1 && type_slots
== 2)) {
595 if (num_channels
> 0) {
596 /* We have channels to write, so update the offset we need to
597 * write at to skip the channels we skipped, if any.
599 if (skipped_channels
> 0) {
600 if (offset_reg
.file
== IMM
) {
601 offset_reg
.ud
+= 4 * skipped_channels
;
603 emit(ADD(dst_reg(offset_reg
), offset_reg
,
604 brw_imm_ud(4 * skipped_channels
)));
608 /* Swizzle the data register so we take the data from the channels
609 * we need to write and send the write message. This will write
610 * num_channels consecutive dwords starting at offset.
613 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
614 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
615 1 /* dims */, num_channels
/* size */,
618 /* If we have to do a second write we will have to update the
619 * offset so that we jump over the channels we have just written
622 skipped_channels
= num_channels
;
624 /* Restart the count for the next write message */
628 /* If we didn't write the channel, increase skipped count */
630 skipped_channels
+= type_slots
;
637 case nir_intrinsic_load_ssbo
: {
638 assert(devinfo
->gen
>= 7);
640 src_reg surf_index
= get_nir_ssbo_intrinsic_index(instr
);
641 src_reg offset_reg
= retype(get_nir_src_imm(instr
->src
[1]),
642 BRW_REGISTER_TYPE_UD
);
644 /* Read the vector */
645 const vec4_builder bld
= vec4_builder(this).at_end()
646 .annotate(current_annotation
, base_ir
);
649 dst_reg dest
= get_nir_dest(instr
->dest
);
650 if (type_sz(dest
.type
) < 8) {
651 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
652 1 /* dims */, 4 /* size*/,
655 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
658 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
659 1 /* dims */, 4 /* size*/,
661 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
663 if (offset_reg
.file
== IMM
)
666 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
668 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
669 1 /* dims */, 4 /* size*/,
671 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
674 read_result
= src_reg(this, glsl_type::dvec4_type
);
675 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
678 read_result
.type
= dest
.type
;
679 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
680 emit(MOV(dest
, read_result
));
684 case nir_intrinsic_ssbo_atomic_add
: {
685 int op
= BRW_AOP_ADD
;
687 if (nir_src_is_const(instr
->src
[2])) {
688 int add_val
= nir_src_as_int(instr
->src
[2]);
691 else if (add_val
== -1)
695 nir_emit_ssbo_atomic(op
, instr
);
698 case nir_intrinsic_ssbo_atomic_imin
:
699 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
701 case nir_intrinsic_ssbo_atomic_umin
:
702 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
704 case nir_intrinsic_ssbo_atomic_imax
:
705 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
707 case nir_intrinsic_ssbo_atomic_umax
:
708 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
710 case nir_intrinsic_ssbo_atomic_and
:
711 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
713 case nir_intrinsic_ssbo_atomic_or
:
714 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
716 case nir_intrinsic_ssbo_atomic_xor
:
717 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
719 case nir_intrinsic_ssbo_atomic_exchange
:
720 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
722 case nir_intrinsic_ssbo_atomic_comp_swap
:
723 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
726 case nir_intrinsic_load_vertex_id
:
727 unreachable("should be lowered by lower_vertex_id()");
729 case nir_intrinsic_load_vertex_id_zero_base
:
730 case nir_intrinsic_load_base_vertex
:
731 case nir_intrinsic_load_instance_id
:
732 case nir_intrinsic_load_base_instance
:
733 case nir_intrinsic_load_draw_id
:
734 case nir_intrinsic_load_invocation_id
:
735 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
737 case nir_intrinsic_load_uniform
: {
738 /* Offsets are in bytes but they should always be multiples of 4 */
739 assert(nir_intrinsic_base(instr
) % 4 == 0);
741 dest
= get_nir_dest(instr
->dest
);
743 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
744 src
.type
= dest
.type
;
746 /* Uniforms don't actually have to be vec4 aligned. In the case that
747 * it isn't, we have to use a swizzle to shift things around. They
748 * do still have the std140 alignment requirement that vec2's have to
749 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
751 * The swizzle also works in the indirect case as the generator adds
752 * the swizzle to the offset for us.
754 const int type_size
= type_sz(src
.type
);
755 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / type_size
;
756 assert(shift
+ instr
->num_components
<= 4);
758 if (nir_src_is_const(instr
->src
[0])) {
759 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
760 /* Offsets are in bytes but they should always be multiples of 4 */
761 assert(load_offset
% 4 == 0);
763 src
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
764 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
765 unsigned offset
= load_offset
+ shift
* type_size
;
766 src
.offset
= ROUND_DOWN_TO(offset
, 16);
767 shift
= (offset
% 16) / type_size
;
768 assert(shift
+ instr
->num_components
<= 4);
769 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
771 emit(MOV(dest
, src
));
773 /* Uniform arrays are vec4 aligned, because of std140 alignment
778 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
780 /* MOV_INDIRECT is going to stomp the whole thing anyway */
781 dest
.writemask
= WRITEMASK_XYZW
;
783 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
784 indirect
, brw_imm_ud(instr
->const_index
[1]));
789 case nir_intrinsic_load_ubo
: {
792 dest
= get_nir_dest(instr
->dest
);
794 if (nir_src_is_const(instr
->src
[0])) {
795 /* The block index is a constant, so just emit the binding table entry
798 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
799 nir_src_as_uint(instr
->src
[0]);
800 surf_index
= brw_imm_ud(index
);
801 brw_mark_surface_used(&prog_data
->base
, index
);
803 /* The block index is not a constant. Evaluate the index expression
804 * per-channel and add the base UBO index; we have to select a value
805 * from any live channel.
807 surf_index
= src_reg(this, glsl_type::uint_type
);
808 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
809 instr
->num_components
),
810 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
811 surf_index
= emit_uniformize(surf_index
);
813 /* Assume this may touch any UBO. It would be nice to provide
814 * a tighter bound, but the array information is already lowered away.
816 brw_mark_surface_used(&prog_data
->base
,
817 prog_data
->base
.binding_table
.ubo_start
+
818 nir
->info
.num_ubos
- 1);
822 if (nir_src_is_const(instr
->src
[1])) {
823 unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
824 offset_reg
= brw_imm_ud(load_offset
& ~15);
826 offset_reg
= src_reg(this, glsl_type::uint_type
);
827 emit(MOV(dst_reg(offset_reg
),
828 get_nir_src(instr
->src
[1], nir_type_uint32
, 1)));
831 src_reg packed_consts
;
832 if (nir_dest_bit_size(instr
->dest
) == 32) {
833 packed_consts
= src_reg(this, glsl_type::vec4_type
);
834 emit_pull_constant_load_reg(dst_reg(packed_consts
),
837 NULL
, NULL
/* before_block/inst */);
839 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
840 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
842 emit_pull_constant_load_reg(dst_reg(temp_float
),
843 surf_index
, offset_reg
, NULL
, NULL
);
844 if (offset_reg
.file
== IMM
)
847 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
848 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
849 surf_index
, offset_reg
, NULL
, NULL
);
851 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
852 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
855 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
856 if (nir_src_is_const(instr
->src
[1])) {
857 unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
858 unsigned type_size
= type_sz(dest
.type
);
859 packed_consts
.swizzle
+=
860 BRW_SWIZZLE4(load_offset
% 16 / type_size
,
861 load_offset
% 16 / type_size
,
862 load_offset
% 16 / type_size
,
863 load_offset
% 16 / type_size
);
866 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
871 case nir_intrinsic_memory_barrier
: {
872 const vec4_builder bld
=
873 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
874 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
875 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
876 ->size_written
= 2 * REG_SIZE
;
880 case nir_intrinsic_shader_clock
: {
881 /* We cannot do anything if there is an event, so ignore it for now */
882 const src_reg shader_clock
= get_timestamp();
883 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
885 dest
= get_nir_dest(instr
->dest
, type
);
886 emit(MOV(dest
, shader_clock
));
891 unreachable("Unknown intrinsic");
896 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
899 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
900 dest
= get_nir_dest(instr
->dest
);
902 src_reg surface
= get_nir_ssbo_intrinsic_index(instr
);
903 src_reg offset
= get_nir_src(instr
->src
[1], 1);
905 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
906 data1
= get_nir_src(instr
->src
[2], 1);
908 if (op
== BRW_AOP_CMPWR
)
909 data2
= get_nir_src(instr
->src
[3], 1);
911 /* Emit the actual atomic operation operation */
912 const vec4_builder bld
=
913 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
915 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
917 1 /* dims */, 1 /* rsize */,
920 dest
.type
= atomic_result
.type
;
921 bld
.MOV(dest
, atomic_result
);
925 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
927 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
930 static enum brw_conditional_mod
931 brw_conditional_for_nir_comparison(nir_op op
)
937 return BRW_CONDITIONAL_L
;
942 return BRW_CONDITIONAL_GE
;
946 case nir_op_ball_fequal2
:
947 case nir_op_ball_iequal2
:
948 case nir_op_ball_fequal3
:
949 case nir_op_ball_iequal3
:
950 case nir_op_ball_fequal4
:
951 case nir_op_ball_iequal4
:
952 return BRW_CONDITIONAL_Z
;
956 case nir_op_bany_fnequal2
:
957 case nir_op_bany_inequal2
:
958 case nir_op_bany_fnequal3
:
959 case nir_op_bany_inequal3
:
960 case nir_op_bany_fnequal4
:
961 case nir_op_bany_inequal4
:
962 return BRW_CONDITIONAL_NZ
;
965 unreachable("not reached: bad operation for comparison");
970 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
971 enum brw_predicate
*predicate
)
973 if (!instr
->src
[0].src
.is_ssa
||
974 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
977 nir_alu_instr
*cmp_instr
=
978 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
980 switch (cmp_instr
->op
) {
981 case nir_op_bany_fnequal2
:
982 case nir_op_bany_inequal2
:
983 case nir_op_bany_fnequal3
:
984 case nir_op_bany_inequal3
:
985 case nir_op_bany_fnequal4
:
986 case nir_op_bany_inequal4
:
987 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
989 case nir_op_ball_fequal2
:
990 case nir_op_ball_iequal2
:
991 case nir_op_ball_fequal3
:
992 case nir_op_ball_iequal3
:
993 case nir_op_ball_fequal4
:
994 case nir_op_ball_iequal4
:
995 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1001 unsigned size_swizzle
=
1002 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1005 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1006 for (unsigned i
= 0; i
< 2; i
++) {
1007 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1008 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1009 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1010 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1011 unsigned base_swizzle
=
1012 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1013 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1014 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1015 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1018 emit(CMP(dst_null_d(), op
[0], op
[1],
1019 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1025 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1030 vec4_instruction
*inst
;
1034 /* LZD of an absolute value source almost always does the right
1035 * thing. There are two problem values:
1037 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1038 * 0. However, findMSB(int(0x80000000)) == 30.
1040 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1041 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1043 * For a value of zero or negative one, -1 will be returned.
1045 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1046 * findMSB(-(1<<x)) should return x-1.
1048 * For all negative number cases, including 0x80000000 and
1049 * 0xffffffff, the correct value is obtained from LZD if instead of
1050 * negating the (already negative) value the logical-not is used. A
1051 * conditonal logical-not can be achieved in two instructions.
1053 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1055 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1056 bld
.XOR(dst_reg(temp
), temp
, src
);
1059 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1060 retype(temp
, BRW_REGISTER_TYPE_UD
));
1062 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1063 * from the LSB side. Subtract the result from 31 to convert the MSB count
1064 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1065 * which is exactly what findMSB() is supposed to return.
1067 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1069 inst
->src
[0].negate
= true;
1073 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1076 /* BDW PRM vol 15 - workarounds:
1077 * DF->f format conversion for Align16 has wrong emask calculation when
1078 * source is immediate.
1080 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1081 src
.file
== BRW_IMMEDIATE_VALUE
) {
1082 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1083 inst
->saturate
= saturate
;
1089 case BRW_REGISTER_TYPE_D
:
1090 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1092 case BRW_REGISTER_TYPE_UD
:
1093 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1095 case BRW_REGISTER_TYPE_F
:
1096 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1099 unreachable("Unknown conversion");
1102 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1103 emit(MOV(temp
, src
));
1104 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1105 emit(op
, temp2
, src_reg(temp
));
1107 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1108 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1109 inst
->saturate
= saturate
;
1113 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1116 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1117 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1118 emit(MOV(dst_reg(tmp_src
), src
));
1119 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1120 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1121 inst
->saturate
= saturate
;
1125 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1127 vec4_instruction
*inst
;
1129 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1130 nir_dest_bit_size(instr
->dest
.dest
));
1131 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1132 dst
.writemask
= instr
->dest
.write_mask
;
1135 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1136 nir_alu_type src_type
= (nir_alu_type
)
1137 (nir_op_infos
[instr
->op
].input_types
[i
] |
1138 nir_src_bit_size(instr
->src
[i
].src
));
1139 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1140 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1141 op
[i
].abs
= instr
->src
[i
].abs
;
1142 op
[i
].negate
= instr
->src
[i
].negate
;
1145 switch (instr
->op
) {
1148 inst
= emit(MOV(dst
, op
[0]));
1149 inst
->saturate
= instr
->dest
.saturate
;
1155 unreachable("not reached: should be handled by lower_vec_to_movs()");
1159 inst
= emit(MOV(dst
, op
[0]));
1160 inst
->saturate
= instr
->dest
.saturate
;
1166 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1167 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1169 inst
= emit(MOV(dst
, op
[0]));
1175 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1179 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1182 inst
= emit(ADD(dst
, op
[0], op
[1]));
1183 inst
->saturate
= instr
->dest
.saturate
;
1187 inst
= emit(MUL(dst
, op
[0], op
[1]));
1188 inst
->saturate
= instr
->dest
.saturate
;
1192 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1193 if (devinfo
->gen
< 8) {
1194 /* For integer multiplication, the MUL uses the low 16 bits of one of
1195 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1196 * accumulates in the contribution of the upper 16 bits of that
1197 * operand. If we can determine that one of the args is in the low
1198 * 16 bits, though, we can just emit a single MUL.
1200 if (nir_src_is_const(instr
->src
[0].src
) &&
1201 nir_alu_instr_src_read_mask(instr
, 0) == 1 &&
1202 nir_src_comp_as_uint(instr
->src
[0].src
, 0) < (1 << 16)) {
1203 if (devinfo
->gen
< 7)
1204 emit(MUL(dst
, op
[0], op
[1]));
1206 emit(MUL(dst
, op
[1], op
[0]));
1207 } else if (nir_src_is_const(instr
->src
[1].src
) &&
1208 nir_alu_instr_src_read_mask(instr
, 1) == 1 &&
1209 nir_src_comp_as_uint(instr
->src
[1].src
, 0) < (1 << 16)) {
1210 if (devinfo
->gen
< 7)
1211 emit(MUL(dst
, op
[1], op
[0]));
1213 emit(MUL(dst
, op
[0], op
[1]));
1215 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1217 emit(MUL(acc
, op
[0], op
[1]));
1218 emit(MACH(dst_null_d(), op
[0], op
[1]));
1219 emit(MOV(dst
, src_reg(acc
)));
1222 emit(MUL(dst
, op
[0], op
[1]));
1227 case nir_op_imul_high
:
1228 case nir_op_umul_high
: {
1229 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1230 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1232 if (devinfo
->gen
>= 8)
1233 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1235 emit(MUL(acc
, op
[0], op
[1]));
1237 emit(MACH(dst
, op
[0], op
[1]));
1242 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1243 inst
->saturate
= instr
->dest
.saturate
;
1247 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1248 inst
->saturate
= instr
->dest
.saturate
;
1252 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1253 inst
->saturate
= instr
->dest
.saturate
;
1257 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1258 inst
->saturate
= instr
->dest
.saturate
;
1262 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1263 inst
->saturate
= instr
->dest
.saturate
;
1268 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1269 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1274 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1275 * appears that our hardware just does the right thing for signed
1278 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1279 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1283 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1284 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1286 /* Math instructions don't support conditional mod */
1287 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1288 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1290 /* Now, we need to determine if signs of the sources are different.
1291 * When we XOR the sources, the top bit is 0 if they are the same and 1
1292 * if they are different. We can then use a conditional modifier to
1293 * turn that into a predicate. This leads us to an XOR.l instruction.
1295 * Technically, according to the PRM, you're not allowed to use .l on a
1296 * XOR instruction. However, emperical experiments and Curro's reading
1297 * of the simulator source both indicate that it's safe.
1299 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1300 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1301 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1302 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1304 /* If the result of the initial remainder operation is non-zero and the
1305 * two sources have different signs, add in a copy of op[1] to get the
1306 * final integer modulus value.
1308 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1309 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1314 unreachable("not reached: should be handled by ldexp_to_arith()");
1317 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1318 inst
->saturate
= instr
->dest
.saturate
;
1322 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1323 inst
->saturate
= instr
->dest
.saturate
;
1327 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1328 inst
->saturate
= instr
->dest
.saturate
;
1331 case nir_op_uadd_carry
: {
1332 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1333 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1335 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1336 emit(MOV(dst
, src_reg(acc
)));
1340 case nir_op_usub_borrow
: {
1341 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1342 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1344 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1345 emit(MOV(dst
, src_reg(acc
)));
1350 inst
= emit(RNDZ(dst
, op
[0]));
1351 inst
->saturate
= instr
->dest
.saturate
;
1354 case nir_op_fceil
: {
1355 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1357 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1358 instr
->src
[0].src
.ssa
->num_components
:
1359 instr
->src
[0].src
.reg
.reg
->num_components
);
1361 op
[0].negate
= !op
[0].negate
;
1362 emit(RNDD(dst_reg(tmp
), op
[0]));
1364 inst
= emit(MOV(dst
, tmp
));
1365 inst
->saturate
= instr
->dest
.saturate
;
1370 inst
= emit(RNDD(dst
, op
[0]));
1371 inst
->saturate
= instr
->dest
.saturate
;
1375 inst
= emit(FRC(dst
, op
[0]));
1376 inst
->saturate
= instr
->dest
.saturate
;
1379 case nir_op_fround_even
:
1380 inst
= emit(RNDE(dst
, op
[0]));
1381 inst
->saturate
= instr
->dest
.saturate
;
1384 case nir_op_fquantize2f16
: {
1385 /* See also vec4_visitor::emit_pack_half_2x16() */
1386 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1387 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1388 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1390 /* Check for denormal */
1391 src_reg abs_src0
= op
[0];
1392 abs_src0
.abs
= true;
1393 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1394 BRW_CONDITIONAL_L
));
1395 /* Get the appropriately signed zero */
1396 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1397 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1398 brw_imm_ud(0x80000000)));
1399 /* Do the actual F32 -> F16 -> F32 conversion */
1400 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1401 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1402 /* Select that or zero based on normal status */
1403 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1404 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1405 inst
->saturate
= instr
->dest
.saturate
;
1411 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1414 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1415 inst
->saturate
= instr
->dest
.saturate
;
1420 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1423 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1424 inst
->saturate
= instr
->dest
.saturate
;
1428 case nir_op_fddx_coarse
:
1429 case nir_op_fddx_fine
:
1431 case nir_op_fddy_coarse
:
1432 case nir_op_fddy_fine
:
1433 unreachable("derivatives are not valid in vertex shaders");
1441 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1447 enum brw_conditional_mod conditional_mod
=
1448 brw_conditional_for_nir_comparison(instr
->op
);
1450 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1451 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1453 /* Produce a 32-bit boolean result from the DF comparison by selecting
1454 * only the low 32-bit in each DF produced. Do this in a temporary
1455 * so we can then move from there to the result using align16 again
1456 * to honor the original writemask.
1458 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1459 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1460 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1461 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1462 emit(MOV(dst
, src_reg(result
)));
1467 case nir_op_ball_iequal2
:
1468 case nir_op_ball_iequal3
:
1469 case nir_op_ball_iequal4
:
1470 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1472 case nir_op_ball_fequal2
:
1473 case nir_op_ball_fequal3
:
1474 case nir_op_ball_fequal4
: {
1476 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1478 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1479 brw_conditional_for_nir_comparison(instr
->op
)));
1480 emit(MOV(dst
, brw_imm_d(0)));
1481 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1482 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1486 case nir_op_bany_inequal2
:
1487 case nir_op_bany_inequal3
:
1488 case nir_op_bany_inequal4
:
1489 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1491 case nir_op_bany_fnequal2
:
1492 case nir_op_bany_fnequal3
:
1493 case nir_op_bany_fnequal4
: {
1495 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1497 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1498 brw_conditional_for_nir_comparison(instr
->op
)));
1500 emit(MOV(dst
, brw_imm_d(0)));
1501 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1502 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1507 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1508 if (devinfo
->gen
>= 8) {
1509 op
[0] = resolve_source_modifiers(op
[0]);
1511 emit(NOT(dst
, op
[0]));
1515 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1516 if (devinfo
->gen
>= 8) {
1517 op
[0] = resolve_source_modifiers(op
[0]);
1518 op
[1] = resolve_source_modifiers(op
[1]);
1520 emit(XOR(dst
, op
[0], op
[1]));
1524 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1525 if (devinfo
->gen
>= 8) {
1526 op
[0] = resolve_source_modifiers(op
[0]);
1527 op
[1] = resolve_source_modifiers(op
[1]);
1529 emit(OR(dst
, op
[0], op
[1]));
1533 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1534 if (devinfo
->gen
>= 8) {
1535 op
[0] = resolve_source_modifiers(op
[0]);
1536 op
[1] = resolve_source_modifiers(op
[1]);
1538 emit(AND(dst
, op
[0], op
[1]));
1543 if (nir_dest_bit_size(instr
->dest
.dest
) > 32) {
1544 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
1545 emit_conversion_to_double(dst
, negate(op
[0]), false);
1547 emit(MOV(dst
, negate(op
[0])));
1552 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1553 /* We use a MOV with conditional_mod to check if the provided value is
1554 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1555 * source modifier on the source operand to trigger this, as source
1556 * modifiers don't affect the result of the testing against 0.0.
1558 src_reg value
= op
[0];
1560 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1561 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1563 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1564 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1565 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1566 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1568 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1573 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1576 case nir_op_fnoise1_1
:
1577 case nir_op_fnoise1_2
:
1578 case nir_op_fnoise1_3
:
1579 case nir_op_fnoise1_4
:
1580 case nir_op_fnoise2_1
:
1581 case nir_op_fnoise2_2
:
1582 case nir_op_fnoise2_3
:
1583 case nir_op_fnoise2_4
:
1584 case nir_op_fnoise3_1
:
1585 case nir_op_fnoise3_2
:
1586 case nir_op_fnoise3_3
:
1587 case nir_op_fnoise3_4
:
1588 case nir_op_fnoise4_1
:
1589 case nir_op_fnoise4_2
:
1590 case nir_op_fnoise4_3
:
1591 case nir_op_fnoise4_4
:
1592 unreachable("not reached: should be handled by lower_noise");
1594 case nir_op_unpack_half_2x16_split_x
:
1595 case nir_op_unpack_half_2x16_split_y
:
1596 case nir_op_pack_half_2x16_split
:
1597 unreachable("not reached: should not occur in vertex shader");
1599 case nir_op_unpack_snorm_2x16
:
1600 case nir_op_unpack_unorm_2x16
:
1601 case nir_op_pack_snorm_2x16
:
1602 case nir_op_pack_unorm_2x16
:
1603 unreachable("not reached: should be handled by lower_packing_builtins");
1605 case nir_op_pack_uvec4_to_uint
:
1606 unreachable("not reached");
1608 case nir_op_pack_uvec2_to_uint
: {
1609 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1610 tmp1
.writemask
= WRITEMASK_X
;
1611 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1612 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1614 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1615 tmp2
.writemask
= WRITEMASK_X
;
1616 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1617 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1619 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1623 case nir_op_pack_64_2x32_split
: {
1624 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1625 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1626 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1627 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1628 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1629 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1630 emit(MOV(dst
, src_reg(result
)));
1634 case nir_op_unpack_64_2x32_split_x
:
1635 case nir_op_unpack_64_2x32_split_y
: {
1636 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1637 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1638 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1639 emit(MOV(tmp
, op
[0]));
1640 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1641 emit(oper
, tmp2
, src_reg(tmp
));
1642 emit(MOV(dst
, src_reg(tmp2
)));
1646 case nir_op_unpack_half_2x16
:
1647 /* As NIR does not guarantee that we have a correct swizzle outside the
1648 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1649 * uses the source operand in an operation with WRITEMASK_Y while our
1650 * source operand has only size 1, it accessed incorrect data producing
1651 * regressions in Piglit. We repeat the swizzle of the first component on the
1652 * rest of components to avoid regressions. In the vec4_visitor IR code path
1653 * this is not needed because the operand has already the correct swizzle.
1655 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1656 emit_unpack_half_2x16(dst
, op
[0]);
1659 case nir_op_pack_half_2x16
:
1660 emit_pack_half_2x16(dst
, op
[0]);
1663 case nir_op_unpack_unorm_4x8
:
1664 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1665 emit_unpack_unorm_4x8(dst
, op
[0]);
1668 case nir_op_pack_unorm_4x8
:
1669 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1670 emit_pack_unorm_4x8(dst
, op
[0]);
1673 case nir_op_unpack_snorm_4x8
:
1674 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1675 emit_unpack_snorm_4x8(dst
, op
[0]);
1678 case nir_op_pack_snorm_4x8
:
1679 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1680 emit_pack_snorm_4x8(dst
, op
[0]);
1683 case nir_op_bitfield_reverse
:
1684 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1685 emit(BFREV(dst
, op
[0]));
1688 case nir_op_bit_count
:
1689 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1690 emit(CBIT(dst
, op
[0]));
1693 case nir_op_ufind_msb
:
1694 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1695 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1698 case nir_op_ifind_msb
: {
1699 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1700 vec4_builder bld
= vec4_builder(this).at_end();
1703 if (devinfo
->gen
< 7) {
1704 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1706 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1708 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1709 * count from the LSB side. If FBH didn't return an error
1710 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1711 * count into an LSB count.
1713 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1715 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1716 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1717 inst
->src
[0].negate
= true;
1722 case nir_op_find_lsb
: {
1723 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1724 vec4_builder bld
= vec4_builder(this).at_end();
1726 if (devinfo
->gen
< 7) {
1727 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1729 /* (x & -x) generates a value that consists of only the LSB of x.
1730 * For all powers of 2, findMSB(y) == findLSB(y).
1732 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1733 src_reg negated_src
= src
;
1735 /* One must be negated, and the other must be non-negated. It
1736 * doesn't matter which is which.
1738 negated_src
.negate
= true;
1741 bld
.AND(temp
, src
, negated_src
);
1742 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1744 bld
.FBL(dst
, op
[0]);
1749 case nir_op_ubitfield_extract
:
1750 case nir_op_ibitfield_extract
:
1751 unreachable("should have been lowered");
1754 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1755 op
[0] = fix_3src_operand(op
[0]);
1756 op
[1] = fix_3src_operand(op
[1]);
1757 op
[2] = fix_3src_operand(op
[2]);
1759 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1763 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1764 emit(BFI1(dst
, op
[0], op
[1]));
1768 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1769 op
[0] = fix_3src_operand(op
[0]);
1770 op
[1] = fix_3src_operand(op
[1]);
1771 op
[2] = fix_3src_operand(op
[2]);
1773 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1776 case nir_op_bitfield_insert
:
1777 unreachable("not reached: should have been lowered");
1780 assert(!instr
->dest
.saturate
);
1782 /* Straightforward since the source can be assumed to be either
1783 * strictly >= 0 or strictly <= 0 depending on the setting of the
1786 inst
= emit(MOV(dst
, op
[0]));
1787 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1789 inst
= (op
[0].negate
)
1790 ? emit(MOV(dst
, brw_imm_f(-1.0f
)))
1791 : emit(MOV(dst
, brw_imm_f(1.0f
)));
1792 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1793 } else if (type_sz(op
[0].type
) < 8) {
1794 /* AND(val, 0x80000000) gives the sign bit.
1796 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1799 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1801 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1802 dst
.type
= BRW_REGISTER_TYPE_UD
;
1803 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1805 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1806 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1807 dst
.type
= BRW_REGISTER_TYPE_F
;
1809 /* For doubles we do the same but we need to consider:
1811 * - We use a MOV with conditional_mod instead of a CMP so that we can
1812 * skip loading a 0.0 immediate. We use a source modifier on the
1813 * source of the MOV so that we flush denormalized values to 0.
1814 * Since we want to compare against 0, this won't alter the result.
1815 * - We need to extract the high 32-bit of each DF where the sign
1817 * - We need to produce a DF result.
1820 /* Check for zero */
1821 src_reg value
= op
[0];
1823 inst
= emit(MOV(dst_null_df(), value
));
1824 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1826 /* AND each high 32-bit channel with 0x80000000u */
1827 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1828 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1829 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1831 /* Add 1.0 to each channel, predicated to skip the cases where the
1832 * channel's value was 0
1834 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1835 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1837 /* Now convert the result from float to double */
1838 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1839 BRW_REGISTER_TYPE_F
),
1845 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1846 * -> non-negative val generates 0x00000000.
1847 * Predicated OR sets 1 if val is positive.
1849 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1850 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1851 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1852 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1853 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1857 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1858 emit(SHL(dst
, op
[0], op
[1]));
1862 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1863 emit(ASR(dst
, op
[0], op
[1]));
1867 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1868 emit(SHR(dst
, op
[0], op
[1]));
1872 if (type_sz(dst
.type
) == 8) {
1873 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1874 emit(MUL(mul_dst
, op
[1], op
[0]));
1875 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1876 inst
->saturate
= instr
->dest
.saturate
;
1878 op
[0] = fix_3src_operand(op
[0]);
1879 op
[1] = fix_3src_operand(op
[1]);
1880 op
[2] = fix_3src_operand(op
[2]);
1882 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1883 inst
->saturate
= instr
->dest
.saturate
;
1888 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1889 inst
->saturate
= instr
->dest
.saturate
;
1893 enum brw_predicate predicate
;
1894 if (!optimize_predicate(instr
, &predicate
)) {
1895 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1896 switch (dst
.writemask
) {
1898 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1901 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1904 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1907 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1910 predicate
= BRW_PREDICATE_NORMAL
;
1914 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1915 inst
->predicate
= predicate
;
1918 case nir_op_fdot_replicated2
:
1919 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1920 inst
->saturate
= instr
->dest
.saturate
;
1923 case nir_op_fdot_replicated3
:
1924 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1925 inst
->saturate
= instr
->dest
.saturate
;
1928 case nir_op_fdot_replicated4
:
1929 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1930 inst
->saturate
= instr
->dest
.saturate
;
1933 case nir_op_fdph_replicated
:
1934 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1935 inst
->saturate
= instr
->dest
.saturate
;
1940 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1945 unreachable("not reached: should be lowered by lower_source mods");
1948 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1951 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1955 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1958 unreachable("Unimplemented ALU operation");
1961 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1962 * to sign extend the low bit to 0/~0
1964 if (devinfo
->gen
<= 5 &&
1965 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1966 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1967 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1968 masked
.writemask
= dst
.writemask
;
1969 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1970 src_reg masked_neg
= src_reg(masked
);
1971 masked_neg
.negate
= true;
1972 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1977 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1979 switch (instr
->type
) {
1980 case nir_jump_break
:
1981 emit(BRW_OPCODE_BREAK
);
1984 case nir_jump_continue
:
1985 emit(BRW_OPCODE_CONTINUE
);
1988 case nir_jump_return
:
1991 unreachable("unknown jump");
1995 static enum ir_texture_opcode
1996 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1998 enum ir_texture_opcode op
;
2001 case nir_texop_lod
: op
= ir_lod
; break;
2002 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2003 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2004 case nir_texop_tex
: op
= ir_tex
; break;
2005 case nir_texop_tg4
: op
= ir_tg4
; break;
2006 case nir_texop_txb
: op
= ir_txb
; break;
2007 case nir_texop_txd
: op
= ir_txd
; break;
2008 case nir_texop_txf
: op
= ir_txf
; break;
2009 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2010 case nir_texop_txl
: op
= ir_txl
; break;
2011 case nir_texop_txs
: op
= ir_txs
; break;
2012 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2014 unreachable("unknown texture opcode");
2020 static const glsl_type
*
2021 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2022 unsigned components
)
2024 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2029 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2031 unsigned texture
= instr
->texture_index
;
2032 unsigned sampler
= instr
->sampler_index
;
2033 src_reg texture_reg
= brw_imm_ud(texture
);
2034 src_reg sampler_reg
= brw_imm_ud(sampler
);
2036 const glsl_type
*coord_type
= NULL
;
2037 src_reg shadow_comparator
;
2038 src_reg offset_value
;
2040 src_reg sample_index
;
2043 const glsl_type
*dest_type
=
2044 glsl_type_for_nir_alu_type(instr
->dest_type
,
2045 nir_tex_instr_dest_size(instr
));
2046 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2048 /* The hardware requires a LOD for buffer textures */
2049 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2052 /* Load the texture operation sources */
2053 uint32_t constant_offset
= 0;
2054 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2055 switch (instr
->src
[i
].src_type
) {
2056 case nir_tex_src_comparator
:
2057 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2058 BRW_REGISTER_TYPE_F
, 1);
2061 case nir_tex_src_coord
: {
2062 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2064 switch (instr
->op
) {
2066 case nir_texop_txf_ms
:
2067 case nir_texop_samples_identical
:
2068 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2070 coord_type
= glsl_type::ivec(src_size
);
2074 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2076 coord_type
= glsl_type::vec(src_size
);
2082 case nir_tex_src_ddx
:
2083 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2084 nir_tex_instr_src_size(instr
, i
));
2087 case nir_tex_src_ddy
:
2088 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2089 nir_tex_instr_src_size(instr
, i
));
2092 case nir_tex_src_lod
:
2093 switch (instr
->op
) {
2096 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2100 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2105 case nir_tex_src_ms_index
: {
2106 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2110 case nir_tex_src_offset
: {
2111 nir_const_value
*const_offset
=
2112 nir_src_as_const_value(instr
->src
[i
].src
);
2113 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
2114 if (!const_offset
||
2115 !brw_texture_offset(const_offset
->i32
,
2116 nir_tex_instr_src_size(instr
, i
),
2117 &constant_offset
)) {
2119 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2124 case nir_tex_src_texture_offset
: {
2125 /* The highest texture which may be used by this operation is
2126 * the last element of the array. Mark it here, because the generator
2127 * doesn't have enough information to determine the bound.
2129 uint32_t array_size
= instr
->texture_array_size
;
2130 uint32_t max_used
= texture
+ array_size
- 1;
2131 if (instr
->op
== nir_texop_tg4
) {
2132 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2134 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2137 brw_mark_surface_used(&prog_data
->base
, max_used
);
2139 /* Emit code to evaluate the actual indexing expression */
2140 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2141 src_reg
temp(this, glsl_type::uint_type
);
2142 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2143 texture_reg
= emit_uniformize(temp
);
2147 case nir_tex_src_sampler_offset
: {
2148 /* Emit code to evaluate the actual indexing expression */
2149 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2150 src_reg
temp(this, glsl_type::uint_type
);
2151 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2152 sampler_reg
= emit_uniformize(temp
);
2156 case nir_tex_src_projector
:
2157 unreachable("Should be lowered by do_lower_texture_projection");
2159 case nir_tex_src_bias
:
2160 unreachable("LOD bias is not valid for vertex shaders.\n");
2163 unreachable("unknown texture source");
2167 if (instr
->op
== nir_texop_txf_ms
||
2168 instr
->op
== nir_texop_samples_identical
) {
2169 assert(coord_type
!= NULL
);
2170 if (devinfo
->gen
>= 7 &&
2171 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2172 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2174 mcs
= brw_imm_ud(0u);
2178 /* Stuff the channel select bits in the top of the texture offset */
2179 if (instr
->op
== nir_texop_tg4
) {
2180 if (instr
->component
== 1 &&
2181 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2182 /* gather4 sampler is broken for green channel on RG32F --
2183 * we must ask for blue instead.
2185 constant_offset
|= 2 << 16;
2187 constant_offset
|= instr
->component
<< 16;
2191 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2193 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2195 lod
, lod2
, sample_index
,
2196 constant_offset
, offset_value
, mcs
,
2197 texture
, texture_reg
, sampler_reg
);
2201 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2203 nir_ssa_values
[instr
->def
.index
] =
2204 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2207 /* SIMD4x2 64bit data is stored in register space like this:
2209 * r0.0:DF x0 y0 z0 w0
2210 * r1.0:DF x1 y1 z1 w1
2212 * When we need to write data such as this to memory using 32-bit write
2213 * messages we need to shuffle it in this fashion:
2215 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2216 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2218 * We need to do the inverse operation when we read using 32-bit messages,
2219 * which we can do by applying the same exact shuffling on the 64-bit data
2220 * read, only that because the data for each vertex is positioned differently
2221 * we need to apply different channel enables.
2223 * This function takes 64bit data and shuffles it as explained above.
2225 * The @for_write parameter is used to specify if the shuffling is being done
2226 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2227 * write message (for_write = true), or instead we are doing the inverse
2228 * operation and we have just read 64-bit data using a 32-bit messages that we
2229 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2231 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2232 * otherwise the instructions are emitted normally at the end. The function
2233 * returns the last instruction inserted.
2235 * Notice that @src and @dst cannot be the same register.
2238 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2239 bblock_t
*block
, vec4_instruction
*ref
)
2241 assert(type_sz(src
.type
) == 8);
2242 assert(type_sz(dst
.type
) == 8);
2243 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2244 assert(!ref
== !block
);
2246 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2247 vec4_builder(this).at(block
, ref
->next
);
2249 /* Resolve swizzle in src */
2250 vec4_instruction
*inst
;
2251 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2252 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2253 inst
= bld
.MOV(data
, src
);
2254 src
= src_reg(data
);
2257 /* dst+0.XY = src+0.XY */
2258 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2260 /* dst+0.ZW = src+1.XY */
2261 inst
= bld
.group(4, for_write
? 1 : 0)
2262 .MOV(writemask(dst
, WRITEMASK_ZW
),
2263 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2265 /* dst+1.XY = src+0.ZW */
2266 inst
= bld
.group(4, for_write
? 0 : 1)
2267 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2268 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2270 /* dst+1.ZW = src+1.ZW */
2271 inst
= bld
.group(4, 1)
2272 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2273 byte_offset(src
, REG_SIZE
));