2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 /* get the main function and emit it */
41 nir_foreach_function(function
, nir
) {
42 assert(strcmp(function
->name
, "main") == 0);
43 assert(function
->impl
);
44 nir_emit_impl(function
->impl
);
49 vec4_visitor::nir_setup_uniforms()
51 uniforms
= nir
->num_uniforms
/ 16;
55 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
57 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
58 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
59 nir_locals
[i
] = dst_reg();
62 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
63 unsigned array_elems
=
64 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
65 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
66 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
68 if (reg
->bit_size
== 64)
69 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
72 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
74 nir_emit_cf_list(&impl
->body
);
78 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
80 exec_list_validate(list
);
81 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
84 nir_emit_if(nir_cf_node_as_if(node
));
87 case nir_cf_node_loop
:
88 nir_emit_loop(nir_cf_node_as_loop(node
));
91 case nir_cf_node_block
:
92 nir_emit_block(nir_cf_node_as_block(node
));
96 unreachable("Invalid CFG node block");
102 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
104 /* First, put the condition in f0 */
105 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
106 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
107 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
109 /* We can just predicate based on the X channel, as the condition only
110 * goes on its own line */
111 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
113 nir_emit_cf_list(&if_stmt
->then_list
);
115 /* note: if the else is empty, dead CF elimination will remove it */
116 emit(BRW_OPCODE_ELSE
);
118 nir_emit_cf_list(&if_stmt
->else_list
);
120 emit(BRW_OPCODE_ENDIF
);
124 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
128 nir_emit_cf_list(&loop
->body
);
130 emit(BRW_OPCODE_WHILE
);
134 vec4_visitor::nir_emit_block(nir_block
*block
)
136 nir_foreach_instr(instr
, block
) {
137 nir_emit_instr(instr
);
142 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
146 switch (instr
->type
) {
147 case nir_instr_type_load_const
:
148 nir_emit_load_const(nir_instr_as_load_const(instr
));
151 case nir_instr_type_intrinsic
:
152 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
155 case nir_instr_type_alu
:
156 nir_emit_alu(nir_instr_as_alu(instr
));
159 case nir_instr_type_jump
:
160 nir_emit_jump(nir_instr_as_jump(instr
));
163 case nir_instr_type_tex
:
164 nir_emit_texture(nir_instr_as_tex(instr
));
167 case nir_instr_type_ssa_undef
:
168 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
172 unreachable("VS instruction not yet implemented by NIR->vec4");
177 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
178 unsigned base_offset
, nir_src
*indirect
)
182 reg
= v
->nir_locals
[nir_reg
->index
];
183 if (nir_reg
->bit_size
== 64)
184 reg
.type
= BRW_REGISTER_TYPE_DF
;
185 reg
= offset(reg
, 8, base_offset
);
188 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
196 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
200 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
201 if (dest
.ssa
.bit_size
== 64)
202 dst
.type
= BRW_REGISTER_TYPE_DF
;
203 nir_ssa_values
[dest
.ssa
.index
] = dst
;
206 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
212 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
214 return retype(get_nir_dest(dest
), type
);
218 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
220 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
224 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
225 unsigned num_components
)
230 assert(src
.ssa
!= NULL
);
231 reg
= nir_ssa_values
[src
.ssa
->index
];
234 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
238 reg
= retype(reg
, type
);
240 src_reg reg_as_src
= src_reg(reg
);
241 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
246 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
247 unsigned num_components
)
249 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
254 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
256 /* if type is not specified, default to signed int */
257 return get_nir_src(src
, nir_type_int32
, num_components
);
261 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
263 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
264 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
267 /* The only constant offset we should find is 0. brw_nir.c's
268 * add_const_offset_to_base() will fold other constant offsets
269 * into instr->const_index[0].
271 assert(const_value
->u32
[0] == 0);
275 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
279 setup_imm_df(const vec4_builder
&bld
, double v
)
281 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
282 assert(devinfo
->gen
>= 7);
284 if (devinfo
->gen
>= 8)
285 return brw_imm_df(v
);
287 /* gen7.5 does not support DF immediates straighforward but the DIM
288 * instruction allows to set the 64-bit immediate value.
290 if (devinfo
->is_haswell
) {
291 const vec4_builder ubld
= bld
.exec_all();
292 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
293 ubld
.DIM(dst
, brw_imm_df(v
));
294 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
297 /* gen7 does not support DF immediates */
308 /* Write the low 32-bit of the constant to the X:UD channel and the
309 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
310 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
311 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
312 * XXXX so any access to the VGRF only reads the constant data in these
315 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
316 for (unsigned n
= 0; n
< 2; n
++) {
317 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
318 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
319 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
322 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
326 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
330 if (instr
->def
.bit_size
== 64) {
331 reg
= dst_reg(VGRF
, alloc
.allocate(2));
332 reg
.type
= BRW_REGISTER_TYPE_DF
;
334 reg
= dst_reg(VGRF
, alloc
.allocate(1));
335 reg
.type
= BRW_REGISTER_TYPE_D
;
338 const vec4_builder ibld
= vec4_builder(this).at_end();
339 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
341 /* @FIXME: consider emitting vector operations to save some MOVs in
342 * cases where the components are representable in 8 bits.
343 * For now, we emit a MOV for each distinct value.
345 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
346 unsigned writemask
= 1 << i
;
348 if ((remaining
& writemask
) == 0)
351 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
352 if ((instr
->def
.bit_size
== 32 &&
353 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
354 (instr
->def
.bit_size
== 64 &&
355 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
360 reg
.writemask
= writemask
;
361 if (instr
->def
.bit_size
== 64) {
362 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
364 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
367 remaining
&= ~writemask
;
370 /* Set final writemask */
371 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
373 nir_ssa_values
[instr
->def
.index
] = reg
;
377 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
382 switch (instr
->intrinsic
) {
384 case nir_intrinsic_load_input
: {
385 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
387 /* We set EmitNoIndirectInput for VS */
388 assert(const_offset
);
390 dest
= get_nir_dest(instr
->dest
);
391 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
393 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
394 glsl_type::uvec4_type
);
395 src
= retype(src
, dest
.type
);
397 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
399 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
400 src
.swizzle
= BRW_SWIZZLE_XYZW
;
401 shuffle_64bit_data(tmp
, src
, false);
402 emit(MOV(dest
, src_reg(tmp
)));
404 /* Swizzle source based on component layout qualifier */
405 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
406 emit(MOV(dest
, src
));
411 case nir_intrinsic_store_output
: {
412 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
413 assert(const_offset
);
415 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
417 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
420 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
421 instr
->num_components
);
422 data
= src_reg(this, glsl_type::dvec4_type
);
423 shuffle_64bit_data(dst_reg(data
), src
, true);
424 src
= retype(data
, BRW_REGISTER_TYPE_F
);
426 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
427 instr
->num_components
);
430 unsigned c
= nir_intrinsic_component(instr
);
431 output_reg
[varying
][c
] = dst_reg(src
);
432 output_num_components
[varying
][c
] = instr
->num_components
;
434 unsigned num_components
= instr
->num_components
;
438 output_reg
[varying
][c
] = dst_reg(src
);
439 output_num_components
[varying
][c
] = MIN2(4, num_components
);
441 if (is_64bit
&& num_components
> 4) {
442 assert(num_components
<= 8);
443 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
444 output_num_components
[varying
+ 1][c
] = num_components
- 4;
449 case nir_intrinsic_get_buffer_size
: {
450 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
451 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
453 const unsigned index
=
454 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
455 dst_reg result_dst
= get_nir_dest(instr
->dest
);
456 vec4_instruction
*inst
= new(mem_ctx
)
457 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE
, result_dst
);
460 inst
->mlen
= 1; /* always at least one */
461 inst
->src
[1] = brw_imm_ud(index
);
463 /* MRF for the first parameter */
464 src_reg lod
= brw_imm_d(0);
465 int param_base
= inst
->base_mrf
;
466 int writemask
= WRITEMASK_X
;
467 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
471 brw_mark_surface_used(&prog_data
->base
, index
);
475 case nir_intrinsic_store_ssbo
: {
476 assert(devinfo
->gen
>= 7);
480 nir_const_value
*const_uniform_block
=
481 nir_src_as_const_value(instr
->src
[1]);
482 if (const_uniform_block
) {
483 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
484 const_uniform_block
->u32
[0];
485 surf_index
= brw_imm_ud(index
);
486 brw_mark_surface_used(&prog_data
->base
, index
);
488 surf_index
= src_reg(this, glsl_type::uint_type
);
489 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
490 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
491 surf_index
= emit_uniformize(surf_index
);
493 brw_mark_surface_used(&prog_data
->base
,
494 prog_data
->base
.binding_table
.ssbo_start
+
495 nir
->info
.num_ssbos
- 1);
500 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
502 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
504 offset_reg
= get_nir_src(instr
->src
[2], 1);
508 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
511 unsigned write_mask
= instr
->const_index
[0];
513 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
514 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
515 * typed and untyped messages and across hardware platforms, the
516 * current implementation of the untyped messages will transparently convert
517 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
518 * and enabling only channel X on the SEND instruction.
520 * The above, works well for full vector writes, but not for partial writes
521 * where we want to write some channels and not others, like when we have
522 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
523 * quite restrictive with regards to the channel enables we can configure in
524 * the message descriptor (not all combinations are allowed) we cannot simply
525 * implement these scenarios with a single message while keeping the
526 * aforementioned symmetry in the implementation. For now we de decided that
527 * it is better to keep the symmetry to reduce complexity, so in situations
528 * such as the one described we end up emitting two untyped write messages
529 * (one for xy and another for w).
531 * The code below packs consecutive channels into a single write message,
532 * detects gaps in the vector write and if needed, sends a second message
533 * with the remaining channels. If in the future we decide that we want to
534 * emit a single message at the expense of losing the symmetry in the
535 * implementation we can:
537 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
538 * message payload. In this mode we can write up to 8 offsets and dwords
539 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
540 * and select which of the 8 channels carry data to write by setting the
541 * appropriate writemask in the dst register of the SEND instruction.
542 * It would require to write a new generator opcode specifically for
543 * IvyBridge since we would need to prepare a SIMD8 payload that could
544 * use any channel, not just X.
546 * 2) For Haswell+: Simply send a single write message but set the writemask
547 * on the dst of the SEND instruction to select the channels we want to
548 * write. It would require to modify the current messages to receive
549 * and honor the writemask provided.
551 const vec4_builder bld
= vec4_builder(this).at_end()
552 .annotate(current_annotation
, base_ir
);
554 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
555 if (type_slots
== 2) {
556 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
557 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
558 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
561 uint8_t swizzle
[4] = { 0, 0, 0, 0};
562 int num_channels
= 0;
563 unsigned skipped_channels
= 0;
564 int num_components
= instr
->num_components
;
565 for (int i
= 0; i
< num_components
; i
++) {
566 /* Read components Z/W of a dvec from the appropriate place. We will
567 * also have to adjust the swizzle (we do that with the '% 4' below)
569 if (i
== 2 && type_slots
== 2)
570 val_reg
= byte_offset(val_reg
, REG_SIZE
);
572 /* Check if this channel needs to be written. If so, record the
573 * channel we need to take the data from in the swizzle array
575 int component_mask
= 1 << i
;
576 int write_test
= write_mask
& component_mask
;
578 /* If we are writing doubles we have to write 2 channels worth of
579 * of data (64 bits) for each double component.
581 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
583 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
586 /* If we don't have to write this channel it means we have a gap in the
587 * vector, so write the channels we accumulated until now, if any. Do
588 * the same if this was the last component in the vector, if we have
589 * enough channels for a full vec4 write or if we have processed
590 * components XY of a dvec (since components ZW are not in the same
593 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
594 (i
== 1 && type_slots
== 2)) {
595 if (num_channels
> 0) {
596 /* We have channels to write, so update the offset we need to
597 * write at to skip the channels we skipped, if any.
599 if (skipped_channels
> 0) {
600 if (offset_reg
.file
== IMM
) {
601 offset_reg
.ud
+= 4 * skipped_channels
;
603 emit(ADD(dst_reg(offset_reg
), offset_reg
,
604 brw_imm_ud(4 * skipped_channels
)));
608 /* Swizzle the data register so we take the data from the channels
609 * we need to write and send the write message. This will write
610 * num_channels consecutive dwords starting at offset.
613 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
614 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
615 1 /* dims */, num_channels
/* size */,
618 /* If we have to do a second write we will have to update the
619 * offset so that we jump over the channels we have just written
622 skipped_channels
= num_channels
;
624 /* Restart the count for the next write message */
628 /* If we didn't write the channel, increase skipped count */
630 skipped_channels
+= type_slots
;
637 case nir_intrinsic_load_ssbo
: {
638 assert(devinfo
->gen
>= 7);
640 nir_const_value
*const_uniform_block
=
641 nir_src_as_const_value(instr
->src
[0]);
644 if (const_uniform_block
) {
645 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
646 const_uniform_block
->u32
[0];
647 surf_index
= brw_imm_ud(index
);
649 brw_mark_surface_used(&prog_data
->base
, index
);
651 surf_index
= src_reg(this, glsl_type::uint_type
);
652 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
653 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
654 surf_index
= emit_uniformize(surf_index
);
656 /* Assume this may touch any UBO. It would be nice to provide
657 * a tighter bound, but the array information is already lowered away.
659 brw_mark_surface_used(&prog_data
->base
,
660 prog_data
->base
.binding_table
.ssbo_start
+
661 nir
->info
.num_ssbos
- 1);
665 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
667 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
669 offset_reg
= get_nir_src(instr
->src
[1], 1);
672 /* Read the vector */
673 const vec4_builder bld
= vec4_builder(this).at_end()
674 .annotate(current_annotation
, base_ir
);
677 dst_reg dest
= get_nir_dest(instr
->dest
);
678 if (type_sz(dest
.type
) < 8) {
679 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
680 1 /* dims */, 4 /* size*/,
683 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
686 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
687 1 /* dims */, 4 /* size*/,
689 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
691 if (offset_reg
.file
== IMM
)
694 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
696 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
697 1 /* dims */, 4 /* size*/,
699 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
702 read_result
= src_reg(this, glsl_type::dvec4_type
);
703 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
706 read_result
.type
= dest
.type
;
707 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
708 emit(MOV(dest
, read_result
));
712 case nir_intrinsic_ssbo_atomic_add
:
713 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
715 case nir_intrinsic_ssbo_atomic_imin
:
716 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
718 case nir_intrinsic_ssbo_atomic_umin
:
719 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
721 case nir_intrinsic_ssbo_atomic_imax
:
722 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
724 case nir_intrinsic_ssbo_atomic_umax
:
725 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
727 case nir_intrinsic_ssbo_atomic_and
:
728 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
730 case nir_intrinsic_ssbo_atomic_or
:
731 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
733 case nir_intrinsic_ssbo_atomic_xor
:
734 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
736 case nir_intrinsic_ssbo_atomic_exchange
:
737 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
739 case nir_intrinsic_ssbo_atomic_comp_swap
:
740 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
743 case nir_intrinsic_load_vertex_id
:
744 unreachable("should be lowered by lower_vertex_id()");
746 case nir_intrinsic_load_vertex_id_zero_base
:
747 case nir_intrinsic_load_base_vertex
:
748 case nir_intrinsic_load_instance_id
:
749 case nir_intrinsic_load_base_instance
:
750 case nir_intrinsic_load_draw_id
:
751 case nir_intrinsic_load_invocation_id
:
752 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
754 case nir_intrinsic_load_uniform
: {
755 /* Offsets are in bytes but they should always be multiples of 4 */
756 assert(nir_intrinsic_base(instr
) % 4 == 0);
758 dest
= get_nir_dest(instr
->dest
);
760 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
761 src
.type
= dest
.type
;
763 /* Uniforms don't actually have to be vec4 aligned. In the case that
764 * it isn't, we have to use a swizzle to shift things around. They
765 * do still have the std140 alignment requirement that vec2's have to
766 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
768 * The swizzle also works in the indirect case as the generator adds
769 * the swizzle to the offset for us.
771 const int type_size
= type_sz(src
.type
);
772 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / type_size
;
773 assert(shift
+ instr
->num_components
<= 4);
775 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
777 /* Offsets are in bytes but they should always be multiples of 4 */
778 assert(const_offset
->u32
[0] % 4 == 0);
780 src
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
781 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
782 unsigned offset
= const_offset
->u32
[0] + shift
* type_size
;
783 src
.offset
= ROUND_DOWN_TO(offset
, 16);
784 shift
= (offset
% 16) / type_size
;
785 assert(shift
+ instr
->num_components
<= 4);
786 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
788 emit(MOV(dest
, src
));
790 /* Uniform arrays are vec4 aligned, because of std140 alignment
795 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
797 /* MOV_INDIRECT is going to stomp the whole thing anyway */
798 dest
.writemask
= WRITEMASK_XYZW
;
800 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
801 indirect
, brw_imm_ud(instr
->const_index
[1]));
806 case nir_intrinsic_load_ubo
: {
807 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
810 dest
= get_nir_dest(instr
->dest
);
812 if (const_block_index
) {
813 /* The block index is a constant, so just emit the binding table entry
816 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
817 const_block_index
->u32
[0];
818 surf_index
= brw_imm_ud(index
);
819 brw_mark_surface_used(&prog_data
->base
, index
);
821 /* The block index is not a constant. Evaluate the index expression
822 * per-channel and add the base UBO index; we have to select a value
823 * from any live channel.
825 surf_index
= src_reg(this, glsl_type::uint_type
);
826 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
827 instr
->num_components
),
828 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
829 surf_index
= emit_uniformize(surf_index
);
831 /* Assume this may touch any UBO. It would be nice to provide
832 * a tighter bound, but the array information is already lowered away.
834 brw_mark_surface_used(&prog_data
->base
,
835 prog_data
->base
.binding_table
.ubo_start
+
836 nir
->info
.num_ubos
- 1);
840 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
842 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
844 offset_reg
= src_reg(this, glsl_type::uint_type
);
845 emit(MOV(dst_reg(offset_reg
),
846 get_nir_src(instr
->src
[1], nir_type_uint32
, 1)));
849 src_reg packed_consts
;
850 if (nir_dest_bit_size(instr
->dest
) == 32) {
851 packed_consts
= src_reg(this, glsl_type::vec4_type
);
852 emit_pull_constant_load_reg(dst_reg(packed_consts
),
855 NULL
, NULL
/* before_block/inst */);
857 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
858 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
860 emit_pull_constant_load_reg(dst_reg(temp_float
),
861 surf_index
, offset_reg
, NULL
, NULL
);
862 if (offset_reg
.file
== IMM
)
865 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
866 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
867 surf_index
, offset_reg
, NULL
, NULL
);
869 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
870 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
873 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
875 unsigned type_size
= type_sz(dest
.type
);
876 packed_consts
.swizzle
+=
877 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
878 const_offset
->u32
[0] % 16 / type_size
,
879 const_offset
->u32
[0] % 16 / type_size
,
880 const_offset
->u32
[0] % 16 / type_size
);
883 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
888 case nir_intrinsic_memory_barrier
: {
889 const vec4_builder bld
=
890 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
891 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
892 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
893 ->size_written
= 2 * REG_SIZE
;
897 case nir_intrinsic_shader_clock
: {
898 /* We cannot do anything if there is an event, so ignore it for now */
899 const src_reg shader_clock
= get_timestamp();
900 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
902 dest
= get_nir_dest(instr
->dest
, type
);
903 emit(MOV(dest
, shader_clock
));
908 unreachable("Unknown intrinsic");
913 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
916 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
917 dest
= get_nir_dest(instr
->dest
);
920 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
922 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
923 const_surface
->u32
[0];
924 surface
= brw_imm_ud(surf_index
);
925 brw_mark_surface_used(&prog_data
->base
, surf_index
);
927 surface
= src_reg(this, glsl_type::uint_type
);
928 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
929 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
931 /* Assume this may touch any UBO. This is the same we do for other
932 * UBO/SSBO accesses with non-constant surface.
934 brw_mark_surface_used(&prog_data
->base
,
935 prog_data
->base
.binding_table
.ssbo_start
+
936 nir
->info
.num_ssbos
- 1);
939 src_reg offset
= get_nir_src(instr
->src
[1], 1);
940 src_reg data1
= get_nir_src(instr
->src
[2], 1);
942 if (op
== BRW_AOP_CMPWR
)
943 data2
= get_nir_src(instr
->src
[3], 1);
945 /* Emit the actual atomic operation operation */
946 const vec4_builder bld
=
947 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
949 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
951 1 /* dims */, 1 /* rsize */,
954 dest
.type
= atomic_result
.type
;
955 bld
.MOV(dest
, atomic_result
);
959 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
961 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
964 static enum brw_conditional_mod
965 brw_conditional_for_nir_comparison(nir_op op
)
971 return BRW_CONDITIONAL_L
;
976 return BRW_CONDITIONAL_GE
;
980 case nir_op_ball_fequal2
:
981 case nir_op_ball_iequal2
:
982 case nir_op_ball_fequal3
:
983 case nir_op_ball_iequal3
:
984 case nir_op_ball_fequal4
:
985 case nir_op_ball_iequal4
:
986 return BRW_CONDITIONAL_Z
;
990 case nir_op_bany_fnequal2
:
991 case nir_op_bany_inequal2
:
992 case nir_op_bany_fnequal3
:
993 case nir_op_bany_inequal3
:
994 case nir_op_bany_fnequal4
:
995 case nir_op_bany_inequal4
:
996 return BRW_CONDITIONAL_NZ
;
999 unreachable("not reached: bad operation for comparison");
1004 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
1005 enum brw_predicate
*predicate
)
1007 if (!instr
->src
[0].src
.is_ssa
||
1008 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1011 nir_alu_instr
*cmp_instr
=
1012 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1014 switch (cmp_instr
->op
) {
1015 case nir_op_bany_fnequal2
:
1016 case nir_op_bany_inequal2
:
1017 case nir_op_bany_fnequal3
:
1018 case nir_op_bany_inequal3
:
1019 case nir_op_bany_fnequal4
:
1020 case nir_op_bany_inequal4
:
1021 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1023 case nir_op_ball_fequal2
:
1024 case nir_op_ball_iequal2
:
1025 case nir_op_ball_fequal3
:
1026 case nir_op_ball_iequal3
:
1027 case nir_op_ball_fequal4
:
1028 case nir_op_ball_iequal4
:
1029 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1035 unsigned size_swizzle
=
1036 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1039 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1040 for (unsigned i
= 0; i
< 2; i
++) {
1041 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1042 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1043 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1044 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1045 unsigned base_swizzle
=
1046 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1047 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1048 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1049 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1052 emit(CMP(dst_null_d(), op
[0], op
[1],
1053 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1059 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1064 vec4_instruction
*inst
;
1068 /* LZD of an absolute value source almost always does the right
1069 * thing. There are two problem values:
1071 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1072 * 0. However, findMSB(int(0x80000000)) == 30.
1074 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1075 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1077 * For a value of zero or negative one, -1 will be returned.
1079 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1080 * findMSB(-(1<<x)) should return x-1.
1082 * For all negative number cases, including 0x80000000 and
1083 * 0xffffffff, the correct value is obtained from LZD if instead of
1084 * negating the (already negative) value the logical-not is used. A
1085 * conditonal logical-not can be achieved in two instructions.
1087 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1089 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1090 bld
.XOR(dst_reg(temp
), temp
, src
);
1093 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1094 retype(temp
, BRW_REGISTER_TYPE_UD
));
1096 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1097 * from the LSB side. Subtract the result from 31 to convert the MSB count
1098 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1099 * which is exactly what findMSB() is supposed to return.
1101 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1103 inst
->src
[0].negate
= true;
1107 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1110 /* BDW PRM vol 15 - workarounds:
1111 * DF->f format conversion for Align16 has wrong emask calculation when
1112 * source is immediate.
1114 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1115 src
.file
== BRW_IMMEDIATE_VALUE
) {
1116 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1117 inst
->saturate
= saturate
;
1123 case BRW_REGISTER_TYPE_D
:
1124 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1126 case BRW_REGISTER_TYPE_UD
:
1127 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1129 case BRW_REGISTER_TYPE_F
:
1130 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1133 unreachable("Unknown conversion");
1136 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1137 emit(MOV(temp
, src
));
1138 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1139 emit(op
, temp2
, src_reg(temp
));
1141 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1142 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1143 inst
->saturate
= saturate
;
1147 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1150 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1151 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1152 emit(MOV(dst_reg(tmp_src
), src
));
1153 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1154 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1155 inst
->saturate
= saturate
;
1159 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1161 vec4_instruction
*inst
;
1163 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1164 nir_dest_bit_size(instr
->dest
.dest
));
1165 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1166 dst
.writemask
= instr
->dest
.write_mask
;
1169 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1170 nir_alu_type src_type
= (nir_alu_type
)
1171 (nir_op_infos
[instr
->op
].input_types
[i
] |
1172 nir_src_bit_size(instr
->src
[i
].src
));
1173 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1174 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1175 op
[i
].abs
= instr
->src
[i
].abs
;
1176 op
[i
].negate
= instr
->src
[i
].negate
;
1179 switch (instr
->op
) {
1182 inst
= emit(MOV(dst
, op
[0]));
1183 inst
->saturate
= instr
->dest
.saturate
;
1189 unreachable("not reached: should be handled by lower_vec_to_movs()");
1193 inst
= emit(MOV(dst
, op
[0]));
1194 inst
->saturate
= instr
->dest
.saturate
;
1200 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1201 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1203 inst
= emit(MOV(dst
, op
[0]));
1209 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1213 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1216 inst
= emit(ADD(dst
, op
[0], op
[1]));
1217 inst
->saturate
= instr
->dest
.saturate
;
1221 inst
= emit(MUL(dst
, op
[0], op
[1]));
1222 inst
->saturate
= instr
->dest
.saturate
;
1226 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1227 if (devinfo
->gen
< 8) {
1228 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1229 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1231 /* For integer multiplication, the MUL uses the low 16 bits of one of
1232 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1233 * accumulates in the contribution of the upper 16 bits of that
1234 * operand. If we can determine that one of the args is in the low
1235 * 16 bits, though, we can just emit a single MUL.
1237 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1238 if (devinfo
->gen
< 7)
1239 emit(MUL(dst
, op
[0], op
[1]));
1241 emit(MUL(dst
, op
[1], op
[0]));
1242 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1243 if (devinfo
->gen
< 7)
1244 emit(MUL(dst
, op
[1], op
[0]));
1246 emit(MUL(dst
, op
[0], op
[1]));
1248 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1250 emit(MUL(acc
, op
[0], op
[1]));
1251 emit(MACH(dst_null_d(), op
[0], op
[1]));
1252 emit(MOV(dst
, src_reg(acc
)));
1255 emit(MUL(dst
, op
[0], op
[1]));
1260 case nir_op_imul_high
:
1261 case nir_op_umul_high
: {
1262 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1263 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1265 if (devinfo
->gen
>= 8)
1266 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1268 emit(MUL(acc
, op
[0], op
[1]));
1270 emit(MACH(dst
, op
[0], op
[1]));
1275 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1276 inst
->saturate
= instr
->dest
.saturate
;
1280 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1281 inst
->saturate
= instr
->dest
.saturate
;
1285 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1286 inst
->saturate
= instr
->dest
.saturate
;
1290 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1291 inst
->saturate
= instr
->dest
.saturate
;
1295 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1296 inst
->saturate
= instr
->dest
.saturate
;
1301 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1302 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1307 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1308 * appears that our hardware just does the right thing for signed
1311 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1312 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1316 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1317 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1319 /* Math instructions don't support conditional mod */
1320 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1321 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1323 /* Now, we need to determine if signs of the sources are different.
1324 * When we XOR the sources, the top bit is 0 if they are the same and 1
1325 * if they are different. We can then use a conditional modifier to
1326 * turn that into a predicate. This leads us to an XOR.l instruction.
1328 * Technically, according to the PRM, you're not allowed to use .l on a
1329 * XOR instruction. However, emperical experiments and Curro's reading
1330 * of the simulator source both indicate that it's safe.
1332 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1333 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1334 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1335 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1337 /* If the result of the initial remainder operation is non-zero and the
1338 * two sources have different signs, add in a copy of op[1] to get the
1339 * final integer modulus value.
1341 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1342 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1347 unreachable("not reached: should be handled by ldexp_to_arith()");
1350 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1351 inst
->saturate
= instr
->dest
.saturate
;
1355 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1356 inst
->saturate
= instr
->dest
.saturate
;
1360 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1361 inst
->saturate
= instr
->dest
.saturate
;
1364 case nir_op_uadd_carry
: {
1365 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1366 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1368 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1369 emit(MOV(dst
, src_reg(acc
)));
1373 case nir_op_usub_borrow
: {
1374 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1375 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1377 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1378 emit(MOV(dst
, src_reg(acc
)));
1383 inst
= emit(RNDZ(dst
, op
[0]));
1384 inst
->saturate
= instr
->dest
.saturate
;
1387 case nir_op_fceil
: {
1388 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1390 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1391 instr
->src
[0].src
.ssa
->num_components
:
1392 instr
->src
[0].src
.reg
.reg
->num_components
);
1394 op
[0].negate
= !op
[0].negate
;
1395 emit(RNDD(dst_reg(tmp
), op
[0]));
1397 inst
= emit(MOV(dst
, tmp
));
1398 inst
->saturate
= instr
->dest
.saturate
;
1403 inst
= emit(RNDD(dst
, op
[0]));
1404 inst
->saturate
= instr
->dest
.saturate
;
1408 inst
= emit(FRC(dst
, op
[0]));
1409 inst
->saturate
= instr
->dest
.saturate
;
1412 case nir_op_fround_even
:
1413 inst
= emit(RNDE(dst
, op
[0]));
1414 inst
->saturate
= instr
->dest
.saturate
;
1417 case nir_op_fquantize2f16
: {
1418 /* See also vec4_visitor::emit_pack_half_2x16() */
1419 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1420 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1421 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1423 /* Check for denormal */
1424 src_reg abs_src0
= op
[0];
1425 abs_src0
.abs
= true;
1426 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1427 BRW_CONDITIONAL_L
));
1428 /* Get the appropriately signed zero */
1429 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1430 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1431 brw_imm_ud(0x80000000)));
1432 /* Do the actual F32 -> F16 -> F32 conversion */
1433 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1434 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1435 /* Select that or zero based on normal status */
1436 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1437 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1438 inst
->saturate
= instr
->dest
.saturate
;
1444 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1447 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1448 inst
->saturate
= instr
->dest
.saturate
;
1453 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1456 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1457 inst
->saturate
= instr
->dest
.saturate
;
1461 case nir_op_fddx_coarse
:
1462 case nir_op_fddx_fine
:
1464 case nir_op_fddy_coarse
:
1465 case nir_op_fddy_fine
:
1466 unreachable("derivatives are not valid in vertex shaders");
1474 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1480 enum brw_conditional_mod conditional_mod
=
1481 brw_conditional_for_nir_comparison(instr
->op
);
1483 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1484 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1486 /* Produce a 32-bit boolean result from the DF comparison by selecting
1487 * only the low 32-bit in each DF produced. Do this in a temporary
1488 * so we can then move from there to the result using align16 again
1489 * to honor the original writemask.
1491 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1492 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1493 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1494 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1495 emit(MOV(dst
, src_reg(result
)));
1500 case nir_op_ball_iequal2
:
1501 case nir_op_ball_iequal3
:
1502 case nir_op_ball_iequal4
:
1503 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1505 case nir_op_ball_fequal2
:
1506 case nir_op_ball_fequal3
:
1507 case nir_op_ball_fequal4
: {
1509 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1511 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1512 brw_conditional_for_nir_comparison(instr
->op
)));
1513 emit(MOV(dst
, brw_imm_d(0)));
1514 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1515 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1519 case nir_op_bany_inequal2
:
1520 case nir_op_bany_inequal3
:
1521 case nir_op_bany_inequal4
:
1522 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1524 case nir_op_bany_fnequal2
:
1525 case nir_op_bany_fnequal3
:
1526 case nir_op_bany_fnequal4
: {
1528 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1530 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1531 brw_conditional_for_nir_comparison(instr
->op
)));
1533 emit(MOV(dst
, brw_imm_d(0)));
1534 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1535 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1540 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1541 if (devinfo
->gen
>= 8) {
1542 op
[0] = resolve_source_modifiers(op
[0]);
1544 emit(NOT(dst
, op
[0]));
1548 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1549 if (devinfo
->gen
>= 8) {
1550 op
[0] = resolve_source_modifiers(op
[0]);
1551 op
[1] = resolve_source_modifiers(op
[1]);
1553 emit(XOR(dst
, op
[0], op
[1]));
1557 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1558 if (devinfo
->gen
>= 8) {
1559 op
[0] = resolve_source_modifiers(op
[0]);
1560 op
[1] = resolve_source_modifiers(op
[1]);
1562 emit(OR(dst
, op
[0], op
[1]));
1566 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1567 if (devinfo
->gen
>= 8) {
1568 op
[0] = resolve_source_modifiers(op
[0]);
1569 op
[1] = resolve_source_modifiers(op
[1]);
1571 emit(AND(dst
, op
[0], op
[1]));
1576 emit(MOV(dst
, negate(op
[0])));
1580 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1581 /* We use a MOV with conditional_mod to check if the provided value is
1582 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1583 * source modifier on the source operand to trigger this, as source
1584 * modifiers don't affect the result of the testing against 0.0.
1586 src_reg value
= op
[0];
1588 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1589 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1591 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1592 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1593 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1594 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1596 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1601 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1604 case nir_op_fnoise1_1
:
1605 case nir_op_fnoise1_2
:
1606 case nir_op_fnoise1_3
:
1607 case nir_op_fnoise1_4
:
1608 case nir_op_fnoise2_1
:
1609 case nir_op_fnoise2_2
:
1610 case nir_op_fnoise2_3
:
1611 case nir_op_fnoise2_4
:
1612 case nir_op_fnoise3_1
:
1613 case nir_op_fnoise3_2
:
1614 case nir_op_fnoise3_3
:
1615 case nir_op_fnoise3_4
:
1616 case nir_op_fnoise4_1
:
1617 case nir_op_fnoise4_2
:
1618 case nir_op_fnoise4_3
:
1619 case nir_op_fnoise4_4
:
1620 unreachable("not reached: should be handled by lower_noise");
1622 case nir_op_unpack_half_2x16_split_x
:
1623 case nir_op_unpack_half_2x16_split_y
:
1624 case nir_op_pack_half_2x16_split
:
1625 unreachable("not reached: should not occur in vertex shader");
1627 case nir_op_unpack_snorm_2x16
:
1628 case nir_op_unpack_unorm_2x16
:
1629 case nir_op_pack_snorm_2x16
:
1630 case nir_op_pack_unorm_2x16
:
1631 unreachable("not reached: should be handled by lower_packing_builtins");
1633 case nir_op_pack_uvec4_to_uint
:
1634 unreachable("not reached");
1636 case nir_op_pack_uvec2_to_uint
: {
1637 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1638 tmp1
.writemask
= WRITEMASK_X
;
1639 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1640 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1642 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1643 tmp2
.writemask
= WRITEMASK_X
;
1644 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1645 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1647 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1651 case nir_op_pack_64_2x32_split
: {
1652 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1653 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1654 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1655 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1656 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1657 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1658 emit(MOV(dst
, src_reg(result
)));
1662 case nir_op_unpack_64_2x32_split_x
:
1663 case nir_op_unpack_64_2x32_split_y
: {
1664 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1665 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1666 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1667 emit(MOV(tmp
, op
[0]));
1668 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1669 emit(oper
, tmp2
, src_reg(tmp
));
1670 emit(MOV(dst
, src_reg(tmp2
)));
1674 case nir_op_unpack_half_2x16
:
1675 /* As NIR does not guarantee that we have a correct swizzle outside the
1676 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1677 * uses the source operand in an operation with WRITEMASK_Y while our
1678 * source operand has only size 1, it accessed incorrect data producing
1679 * regressions in Piglit. We repeat the swizzle of the first component on the
1680 * rest of components to avoid regressions. In the vec4_visitor IR code path
1681 * this is not needed because the operand has already the correct swizzle.
1683 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1684 emit_unpack_half_2x16(dst
, op
[0]);
1687 case nir_op_pack_half_2x16
:
1688 emit_pack_half_2x16(dst
, op
[0]);
1691 case nir_op_unpack_unorm_4x8
:
1692 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1693 emit_unpack_unorm_4x8(dst
, op
[0]);
1696 case nir_op_pack_unorm_4x8
:
1697 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1698 emit_pack_unorm_4x8(dst
, op
[0]);
1701 case nir_op_unpack_snorm_4x8
:
1702 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1703 emit_unpack_snorm_4x8(dst
, op
[0]);
1706 case nir_op_pack_snorm_4x8
:
1707 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1708 emit_pack_snorm_4x8(dst
, op
[0]);
1711 case nir_op_bitfield_reverse
:
1712 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1713 emit(BFREV(dst
, op
[0]));
1716 case nir_op_bit_count
:
1717 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1718 emit(CBIT(dst
, op
[0]));
1721 case nir_op_ufind_msb
:
1722 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1723 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1726 case nir_op_ifind_msb
: {
1727 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1728 vec4_builder bld
= vec4_builder(this).at_end();
1731 if (devinfo
->gen
< 7) {
1732 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1734 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1736 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1737 * count from the LSB side. If FBH didn't return an error
1738 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1739 * count into an LSB count.
1741 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1743 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1744 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1745 inst
->src
[0].negate
= true;
1750 case nir_op_find_lsb
: {
1751 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1752 vec4_builder bld
= vec4_builder(this).at_end();
1754 if (devinfo
->gen
< 7) {
1755 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1757 /* (x & -x) generates a value that consists of only the LSB of x.
1758 * For all powers of 2, findMSB(y) == findLSB(y).
1760 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1761 src_reg negated_src
= src
;
1763 /* One must be negated, and the other must be non-negated. It
1764 * doesn't matter which is which.
1766 negated_src
.negate
= true;
1769 bld
.AND(temp
, src
, negated_src
);
1770 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1772 bld
.FBL(dst
, op
[0]);
1777 case nir_op_ubitfield_extract
:
1778 case nir_op_ibitfield_extract
:
1779 unreachable("should have been lowered");
1782 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1783 op
[0] = fix_3src_operand(op
[0]);
1784 op
[1] = fix_3src_operand(op
[1]);
1785 op
[2] = fix_3src_operand(op
[2]);
1787 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1791 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1792 emit(BFI1(dst
, op
[0], op
[1]));
1796 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1797 op
[0] = fix_3src_operand(op
[0]);
1798 op
[1] = fix_3src_operand(op
[1]);
1799 op
[2] = fix_3src_operand(op
[2]);
1801 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1804 case nir_op_bitfield_insert
:
1805 unreachable("not reached: should have been lowered");
1808 if (type_sz(op
[0].type
) < 8) {
1809 /* AND(val, 0x80000000) gives the sign bit.
1811 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1814 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1816 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1817 dst
.type
= BRW_REGISTER_TYPE_UD
;
1818 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1820 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1821 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1822 dst
.type
= BRW_REGISTER_TYPE_F
;
1824 if (instr
->dest
.saturate
) {
1825 inst
= emit(MOV(dst
, src_reg(dst
)));
1826 inst
->saturate
= true;
1829 /* For doubles we do the same but we need to consider:
1831 * - We use a MOV with conditional_mod instead of a CMP so that we can
1832 * skip loading a 0.0 immediate. We use a source modifier on the
1833 * source of the MOV so that we flush denormalized values to 0.
1834 * Since we want to compare against 0, this won't alter the result.
1835 * - We need to extract the high 32-bit of each DF where the sign
1837 * - We need to produce a DF result.
1840 /* Check for zero */
1841 src_reg value
= op
[0];
1843 inst
= emit(MOV(dst_null_df(), value
));
1844 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1846 /* AND each high 32-bit channel with 0x80000000u */
1847 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1848 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1849 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1851 /* Add 1.0 to each channel, predicated to skip the cases where the
1852 * channel's value was 0
1854 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1855 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1857 /* Now convert the result from float to double */
1858 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1859 BRW_REGISTER_TYPE_F
),
1860 instr
->dest
.saturate
);
1865 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1866 * -> non-negative val generates 0x00000000.
1867 * Predicated OR sets 1 if val is positive.
1869 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1870 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1871 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1872 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1873 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1877 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1878 emit(SHL(dst
, op
[0], op
[1]));
1882 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1883 emit(ASR(dst
, op
[0], op
[1]));
1887 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1888 emit(SHR(dst
, op
[0], op
[1]));
1892 if (type_sz(dst
.type
) == 8) {
1893 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1894 emit(MUL(mul_dst
, op
[1], op
[0]));
1895 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1896 inst
->saturate
= instr
->dest
.saturate
;
1898 op
[0] = fix_3src_operand(op
[0]);
1899 op
[1] = fix_3src_operand(op
[1]);
1900 op
[2] = fix_3src_operand(op
[2]);
1902 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1903 inst
->saturate
= instr
->dest
.saturate
;
1908 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1909 inst
->saturate
= instr
->dest
.saturate
;
1913 enum brw_predicate predicate
;
1914 if (!optimize_predicate(instr
, &predicate
)) {
1915 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1916 switch (dst
.writemask
) {
1918 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1921 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1924 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1927 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1930 predicate
= BRW_PREDICATE_NORMAL
;
1934 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1935 inst
->predicate
= predicate
;
1938 case nir_op_fdot_replicated2
:
1939 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1940 inst
->saturate
= instr
->dest
.saturate
;
1943 case nir_op_fdot_replicated3
:
1944 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1945 inst
->saturate
= instr
->dest
.saturate
;
1948 case nir_op_fdot_replicated4
:
1949 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1950 inst
->saturate
= instr
->dest
.saturate
;
1953 case nir_op_fdph_replicated
:
1954 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1955 inst
->saturate
= instr
->dest
.saturate
;
1960 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1965 unreachable("not reached: should be lowered by lower_source mods");
1968 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1971 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1975 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1978 unreachable("Unimplemented ALU operation");
1981 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1982 * to sign extend the low bit to 0/~0
1984 if (devinfo
->gen
<= 5 &&
1985 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1986 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1987 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1988 masked
.writemask
= dst
.writemask
;
1989 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1990 src_reg masked_neg
= src_reg(masked
);
1991 masked_neg
.negate
= true;
1992 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1997 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1999 switch (instr
->type
) {
2000 case nir_jump_break
:
2001 emit(BRW_OPCODE_BREAK
);
2004 case nir_jump_continue
:
2005 emit(BRW_OPCODE_CONTINUE
);
2008 case nir_jump_return
:
2011 unreachable("unknown jump");
2015 static enum ir_texture_opcode
2016 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2018 enum ir_texture_opcode op
;
2021 case nir_texop_lod
: op
= ir_lod
; break;
2022 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2023 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2024 case nir_texop_tex
: op
= ir_tex
; break;
2025 case nir_texop_tg4
: op
= ir_tg4
; break;
2026 case nir_texop_txb
: op
= ir_txb
; break;
2027 case nir_texop_txd
: op
= ir_txd
; break;
2028 case nir_texop_txf
: op
= ir_txf
; break;
2029 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2030 case nir_texop_txl
: op
= ir_txl
; break;
2031 case nir_texop_txs
: op
= ir_txs
; break;
2032 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2034 unreachable("unknown texture opcode");
2040 static const glsl_type
*
2041 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2042 unsigned components
)
2044 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2049 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2051 unsigned texture
= instr
->texture_index
;
2052 unsigned sampler
= instr
->sampler_index
;
2053 src_reg texture_reg
= brw_imm_ud(texture
);
2054 src_reg sampler_reg
= brw_imm_ud(sampler
);
2056 const glsl_type
*coord_type
= NULL
;
2057 src_reg shadow_comparator
;
2058 src_reg offset_value
;
2060 src_reg sample_index
;
2063 const glsl_type
*dest_type
=
2064 glsl_type_for_nir_alu_type(instr
->dest_type
,
2065 nir_tex_instr_dest_size(instr
));
2066 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2068 /* The hardware requires a LOD for buffer textures */
2069 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2072 /* Load the texture operation sources */
2073 uint32_t constant_offset
= 0;
2074 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2075 switch (instr
->src
[i
].src_type
) {
2076 case nir_tex_src_comparator
:
2077 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2078 BRW_REGISTER_TYPE_F
, 1);
2081 case nir_tex_src_coord
: {
2082 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2084 switch (instr
->op
) {
2086 case nir_texop_txf_ms
:
2087 case nir_texop_samples_identical
:
2088 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2090 coord_type
= glsl_type::ivec(src_size
);
2094 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2096 coord_type
= glsl_type::vec(src_size
);
2102 case nir_tex_src_ddx
:
2103 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2104 nir_tex_instr_src_size(instr
, i
));
2107 case nir_tex_src_ddy
:
2108 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2109 nir_tex_instr_src_size(instr
, i
));
2112 case nir_tex_src_lod
:
2113 switch (instr
->op
) {
2116 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2120 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2125 case nir_tex_src_ms_index
: {
2126 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2130 case nir_tex_src_offset
: {
2131 nir_const_value
*const_offset
=
2132 nir_src_as_const_value(instr
->src
[i
].src
);
2133 if (!const_offset
||
2134 !brw_texture_offset(const_offset
->i32
,
2135 nir_tex_instr_src_size(instr
, i
),
2136 &constant_offset
)) {
2138 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2143 case nir_tex_src_texture_offset
: {
2144 /* The highest texture which may be used by this operation is
2145 * the last element of the array. Mark it here, because the generator
2146 * doesn't have enough information to determine the bound.
2148 uint32_t array_size
= instr
->texture_array_size
;
2149 uint32_t max_used
= texture
+ array_size
- 1;
2150 if (instr
->op
== nir_texop_tg4
) {
2151 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2153 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2156 brw_mark_surface_used(&prog_data
->base
, max_used
);
2158 /* Emit code to evaluate the actual indexing expression */
2159 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2160 src_reg
temp(this, glsl_type::uint_type
);
2161 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2162 texture_reg
= emit_uniformize(temp
);
2166 case nir_tex_src_sampler_offset
: {
2167 /* Emit code to evaluate the actual indexing expression */
2168 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2169 src_reg
temp(this, glsl_type::uint_type
);
2170 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2171 sampler_reg
= emit_uniformize(temp
);
2175 case nir_tex_src_projector
:
2176 unreachable("Should be lowered by do_lower_texture_projection");
2178 case nir_tex_src_bias
:
2179 unreachable("LOD bias is not valid for vertex shaders.\n");
2182 unreachable("unknown texture source");
2186 if (instr
->op
== nir_texop_txf_ms
||
2187 instr
->op
== nir_texop_samples_identical
) {
2188 assert(coord_type
!= NULL
);
2189 if (devinfo
->gen
>= 7 &&
2190 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2191 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2193 mcs
= brw_imm_ud(0u);
2197 /* Stuff the channel select bits in the top of the texture offset */
2198 if (instr
->op
== nir_texop_tg4
) {
2199 if (instr
->component
== 1 &&
2200 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2201 /* gather4 sampler is broken for green channel on RG32F --
2202 * we must ask for blue instead.
2204 constant_offset
|= 2 << 16;
2206 constant_offset
|= instr
->component
<< 16;
2210 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2212 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2214 lod
, lod2
, sample_index
,
2215 constant_offset
, offset_value
, mcs
,
2216 texture
, texture_reg
, sampler_reg
);
2220 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2222 nir_ssa_values
[instr
->def
.index
] =
2223 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2226 /* SIMD4x2 64bit data is stored in register space like this:
2228 * r0.0:DF x0 y0 z0 w0
2229 * r1.0:DF x1 y1 z1 w1
2231 * When we need to write data such as this to memory using 32-bit write
2232 * messages we need to shuffle it in this fashion:
2234 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2235 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2237 * We need to do the inverse operation when we read using 32-bit messages,
2238 * which we can do by applying the same exact shuffling on the 64-bit data
2239 * read, only that because the data for each vertex is positioned differently
2240 * we need to apply different channel enables.
2242 * This function takes 64bit data and shuffles it as explained above.
2244 * The @for_write parameter is used to specify if the shuffling is being done
2245 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2246 * write message (for_write = true), or instead we are doing the inverse
2247 * operation and we have just read 64-bit data using a 32-bit messages that we
2248 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2250 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2251 * otherwise the instructions are emitted normally at the end. The function
2252 * returns the last instruction inserted.
2254 * Notice that @src and @dst cannot be the same register.
2257 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2258 bblock_t
*block
, vec4_instruction
*ref
)
2260 assert(type_sz(src
.type
) == 8);
2261 assert(type_sz(dst
.type
) == 8);
2262 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2263 assert(!ref
== !block
);
2265 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2266 vec4_builder(this).at(block
, ref
->next
);
2268 /* Resolve swizzle in src */
2269 vec4_instruction
*inst
;
2270 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2271 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2272 inst
= bld
.MOV(data
, src
);
2273 src
= src_reg(data
);
2276 /* dst+0.XY = src+0.XY */
2277 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2279 /* dst+0.ZW = src+1.XY */
2280 inst
= bld
.group(4, for_write
? 1 : 0)
2281 .MOV(writemask(dst
, WRITEMASK_ZW
),
2282 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2284 /* dst+1.XY = src+0.ZW */
2285 inst
= bld
.group(4, for_write
? 0 : 1)
2286 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2287 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2289 /* dst+1.ZW = src+1.ZW */
2290 inst
= bld
.group(4, 1)
2291 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2292 byte_offset(src
, REG_SIZE
));