2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
44 vec4_visitor::nir_setup_uniforms()
46 uniforms
= nir
->num_uniforms
/ 16;
50 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
52 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
53 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
54 nir_locals
[i
] = dst_reg();
57 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
58 unsigned array_elems
=
59 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
60 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
61 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
63 if (reg
->bit_size
== 64)
64 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
67 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
69 nir_emit_cf_list(&impl
->body
);
73 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
75 exec_list_validate(list
);
76 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
79 nir_emit_if(nir_cf_node_as_if(node
));
82 case nir_cf_node_loop
:
83 nir_emit_loop(nir_cf_node_as_loop(node
));
86 case nir_cf_node_block
:
87 nir_emit_block(nir_cf_node_as_block(node
));
91 unreachable("Invalid CFG node block");
97 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
99 /* First, put the condition in f0 */
100 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
101 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
102 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
104 /* We can just predicate based on the X channel, as the condition only
105 * goes on its own line */
106 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
108 nir_emit_cf_list(&if_stmt
->then_list
);
110 /* note: if the else is empty, dead CF elimination will remove it */
111 emit(BRW_OPCODE_ELSE
);
113 nir_emit_cf_list(&if_stmt
->else_list
);
115 emit(BRW_OPCODE_ENDIF
);
119 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
123 nir_emit_cf_list(&loop
->body
);
125 emit(BRW_OPCODE_WHILE
);
129 vec4_visitor::nir_emit_block(nir_block
*block
)
131 nir_foreach_instr(instr
, block
) {
132 nir_emit_instr(instr
);
137 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
141 switch (instr
->type
) {
142 case nir_instr_type_load_const
:
143 nir_emit_load_const(nir_instr_as_load_const(instr
));
146 case nir_instr_type_intrinsic
:
147 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
150 case nir_instr_type_alu
:
151 nir_emit_alu(nir_instr_as_alu(instr
));
154 case nir_instr_type_jump
:
155 nir_emit_jump(nir_instr_as_jump(instr
));
158 case nir_instr_type_tex
:
159 nir_emit_texture(nir_instr_as_tex(instr
));
162 case nir_instr_type_ssa_undef
:
163 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
167 unreachable("VS instruction not yet implemented by NIR->vec4");
172 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
173 unsigned base_offset
, nir_src
*indirect
)
177 reg
= v
->nir_locals
[nir_reg
->index
];
178 if (nir_reg
->bit_size
== 64)
179 reg
.type
= BRW_REGISTER_TYPE_DF
;
180 reg
= offset(reg
, 8, base_offset
);
183 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
191 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
195 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
196 if (dest
.ssa
.bit_size
== 64)
197 dst
.type
= BRW_REGISTER_TYPE_DF
;
198 nir_ssa_values
[dest
.ssa
.index
] = dst
;
201 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
207 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
209 return retype(get_nir_dest(dest
), type
);
213 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
215 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
219 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
220 unsigned num_components
)
225 assert(src
.ssa
!= NULL
);
226 reg
= nir_ssa_values
[src
.ssa
->index
];
229 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
233 reg
= retype(reg
, type
);
235 src_reg reg_as_src
= src_reg(reg
);
236 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
241 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
242 unsigned num_components
)
244 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
249 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
251 /* if type is not specified, default to signed int */
252 return get_nir_src(src
, nir_type_int32
, num_components
);
256 vec4_visitor::get_nir_src_imm(const nir_src
&src
)
258 assert(nir_src_num_components(src
) == 1);
259 assert(nir_src_bit_size(src
) == 32);
260 return nir_src_is_const(src
) ? src_reg(brw_imm_d(nir_src_as_int(src
))) :
265 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
267 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
269 if (nir_src_is_const(*offset_src
)) {
270 /* The only constant offset we should find is 0. brw_nir.c's
271 * add_const_offset_to_base() will fold other constant offsets
272 * into instr->const_index[0].
274 assert(nir_src_as_uint(*offset_src
) == 0);
278 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
282 setup_imm_df(const vec4_builder
&bld
, double v
)
284 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
285 assert(devinfo
->gen
>= 7);
287 if (devinfo
->gen
>= 8)
288 return brw_imm_df(v
);
290 /* gen7.5 does not support DF immediates straighforward but the DIM
291 * instruction allows to set the 64-bit immediate value.
293 if (devinfo
->is_haswell
) {
294 const vec4_builder ubld
= bld
.exec_all();
295 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
296 ubld
.DIM(dst
, brw_imm_df(v
));
297 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
300 /* gen7 does not support DF immediates */
311 /* Write the low 32-bit of the constant to the X:UD channel and the
312 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
313 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
314 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
315 * XXXX so any access to the VGRF only reads the constant data in these
318 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
319 for (unsigned n
= 0; n
< 2; n
++) {
320 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
321 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
322 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
325 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
329 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
333 if (instr
->def
.bit_size
== 64) {
334 reg
= dst_reg(VGRF
, alloc
.allocate(2));
335 reg
.type
= BRW_REGISTER_TYPE_DF
;
337 reg
= dst_reg(VGRF
, alloc
.allocate(1));
338 reg
.type
= BRW_REGISTER_TYPE_D
;
341 const vec4_builder ibld
= vec4_builder(this).at_end();
342 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
344 /* @FIXME: consider emitting vector operations to save some MOVs in
345 * cases where the components are representable in 8 bits.
346 * For now, we emit a MOV for each distinct value.
348 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
349 unsigned writemask
= 1 << i
;
351 if ((remaining
& writemask
) == 0)
354 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
355 if ((instr
->def
.bit_size
== 32 &&
356 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
357 (instr
->def
.bit_size
== 64 &&
358 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
363 reg
.writemask
= writemask
;
364 if (instr
->def
.bit_size
== 64) {
365 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
367 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
370 remaining
&= ~writemask
;
373 /* Set final writemask */
374 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
376 nir_ssa_values
[instr
->def
.index
] = reg
;
380 vec4_visitor::get_nir_ssbo_intrinsic_index(nir_intrinsic_instr
*instr
)
382 /* SSBO stores are weird in that their index is in src[1] */
383 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
386 if (nir_src_is_const(instr
->src
[src
])) {
387 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
388 nir_src_as_uint(instr
->src
[src
]);
389 surf_index
= brw_imm_ud(index
);
391 surf_index
= src_reg(this, glsl_type::uint_type
);
392 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[src
], 1),
393 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
394 surf_index
= emit_uniformize(surf_index
);
401 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
406 switch (instr
->intrinsic
) {
408 case nir_intrinsic_load_input
: {
409 /* We set EmitNoIndirectInput for VS */
410 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
412 dest
= get_nir_dest(instr
->dest
);
413 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
415 src
= src_reg(ATTR
, instr
->const_index
[0] + load_offset
,
416 glsl_type::uvec4_type
);
417 src
= retype(src
, dest
.type
);
419 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
421 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
422 src
.swizzle
= BRW_SWIZZLE_XYZW
;
423 shuffle_64bit_data(tmp
, src
, false);
424 emit(MOV(dest
, src_reg(tmp
)));
426 /* Swizzle source based on component layout qualifier */
427 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
428 emit(MOV(dest
, src
));
433 case nir_intrinsic_store_output
: {
434 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
435 int varying
= instr
->const_index
[0] + store_offset
;
437 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
440 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
441 instr
->num_components
);
442 data
= src_reg(this, glsl_type::dvec4_type
);
443 shuffle_64bit_data(dst_reg(data
), src
, true);
444 src
= retype(data
, BRW_REGISTER_TYPE_F
);
446 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
447 instr
->num_components
);
450 unsigned c
= nir_intrinsic_component(instr
);
451 output_reg
[varying
][c
] = dst_reg(src
);
452 output_num_components
[varying
][c
] = instr
->num_components
;
454 unsigned num_components
= instr
->num_components
;
458 output_reg
[varying
][c
] = dst_reg(src
);
459 output_num_components
[varying
][c
] = MIN2(4, num_components
);
461 if (is_64bit
&& num_components
> 4) {
462 assert(num_components
<= 8);
463 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
464 output_num_components
[varying
+ 1][c
] = num_components
- 4;
469 case nir_intrinsic_get_buffer_size
: {
470 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
471 nir_src_as_uint(instr
->src
[0]) : 0;
473 const unsigned index
=
474 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
475 dst_reg result_dst
= get_nir_dest(instr
->dest
);
476 vec4_instruction
*inst
= new(mem_ctx
)
477 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE
, result_dst
);
480 inst
->mlen
= 1; /* always at least one */
481 inst
->src
[1] = brw_imm_ud(index
);
483 /* MRF for the first parameter */
484 src_reg lod
= brw_imm_d(0);
485 int param_base
= inst
->base_mrf
;
486 int writemask
= WRITEMASK_X
;
487 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
493 case nir_intrinsic_store_ssbo
: {
494 assert(devinfo
->gen
>= 7);
496 /* brw_nir_lower_mem_access_bit_sizes takes care of this */
497 assert(nir_src_bit_size(instr
->src
[0]) == 32);
498 assert(nir_intrinsic_write_mask(instr
) ==
499 (1u << instr
->num_components
) - 1);
501 src_reg surf_index
= get_nir_ssbo_intrinsic_index(instr
);
502 src_reg offset_reg
= retype(get_nir_src_imm(instr
->src
[2]),
503 BRW_REGISTER_TYPE_UD
);
506 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
508 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
509 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
510 * typed and untyped messages and across hardware platforms, the
511 * current implementation of the untyped messages will transparently convert
512 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
513 * and enabling only channel X on the SEND instruction.
515 * The above, works well for full vector writes, but not for partial writes
516 * where we want to write some channels and not others, like when we have
517 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
518 * quite restrictive with regards to the channel enables we can configure in
519 * the message descriptor (not all combinations are allowed) we cannot simply
520 * implement these scenarios with a single message while keeping the
521 * aforementioned symmetry in the implementation. For now we de decided that
522 * it is better to keep the symmetry to reduce complexity, so in situations
523 * such as the one described we end up emitting two untyped write messages
524 * (one for xy and another for w).
526 * The code below packs consecutive channels into a single write message,
527 * detects gaps in the vector write and if needed, sends a second message
528 * with the remaining channels. If in the future we decide that we want to
529 * emit a single message at the expense of losing the symmetry in the
530 * implementation we can:
532 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
533 * message payload. In this mode we can write up to 8 offsets and dwords
534 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
535 * and select which of the 8 channels carry data to write by setting the
536 * appropriate writemask in the dst register of the SEND instruction.
537 * It would require to write a new generator opcode specifically for
538 * IvyBridge since we would need to prepare a SIMD8 payload that could
539 * use any channel, not just X.
541 * 2) For Haswell+: Simply send a single write message but set the writemask
542 * on the dst of the SEND instruction to select the channels we want to
543 * write. It would require to modify the current messages to receive
544 * and honor the writemask provided.
546 const vec4_builder bld
= vec4_builder(this).at_end()
547 .annotate(current_annotation
, base_ir
);
549 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
550 1 /* dims */, instr
->num_components
/* size */,
555 case nir_intrinsic_load_ssbo
: {
556 assert(devinfo
->gen
>= 7);
558 /* brw_nir_lower_mem_access_bit_sizes takes care of this */
559 assert(nir_dest_bit_size(instr
->dest
) == 32);
561 src_reg surf_index
= get_nir_ssbo_intrinsic_index(instr
);
562 src_reg offset_reg
= retype(get_nir_src_imm(instr
->src
[1]),
563 BRW_REGISTER_TYPE_UD
);
565 /* Read the vector */
566 const vec4_builder bld
= vec4_builder(this).at_end()
567 .annotate(current_annotation
, base_ir
);
569 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
570 1 /* dims */, 4 /* size*/,
572 dst_reg dest
= get_nir_dest(instr
->dest
);
573 read_result
.type
= dest
.type
;
574 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
575 emit(MOV(dest
, read_result
));
579 case nir_intrinsic_ssbo_atomic_add
: {
580 int op
= BRW_AOP_ADD
;
582 if (nir_src_is_const(instr
->src
[2])) {
583 int add_val
= nir_src_as_int(instr
->src
[2]);
586 else if (add_val
== -1)
590 nir_emit_ssbo_atomic(op
, instr
);
593 case nir_intrinsic_ssbo_atomic_imin
:
594 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
596 case nir_intrinsic_ssbo_atomic_umin
:
597 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
599 case nir_intrinsic_ssbo_atomic_imax
:
600 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
602 case nir_intrinsic_ssbo_atomic_umax
:
603 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
605 case nir_intrinsic_ssbo_atomic_and
:
606 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
608 case nir_intrinsic_ssbo_atomic_or
:
609 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
611 case nir_intrinsic_ssbo_atomic_xor
:
612 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
614 case nir_intrinsic_ssbo_atomic_exchange
:
615 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
617 case nir_intrinsic_ssbo_atomic_comp_swap
:
618 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
621 case nir_intrinsic_load_vertex_id
:
622 unreachable("should be lowered by lower_vertex_id()");
624 case nir_intrinsic_load_vertex_id_zero_base
:
625 case nir_intrinsic_load_base_vertex
:
626 case nir_intrinsic_load_instance_id
:
627 case nir_intrinsic_load_base_instance
:
628 case nir_intrinsic_load_draw_id
:
629 case nir_intrinsic_load_invocation_id
:
630 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
632 case nir_intrinsic_load_uniform
: {
633 /* Offsets are in bytes but they should always be multiples of 4 */
634 assert(nir_intrinsic_base(instr
) % 4 == 0);
636 dest
= get_nir_dest(instr
->dest
);
638 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
639 src
.type
= dest
.type
;
641 /* Uniforms don't actually have to be vec4 aligned. In the case that
642 * it isn't, we have to use a swizzle to shift things around. They
643 * do still have the std140 alignment requirement that vec2's have to
644 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
646 * The swizzle also works in the indirect case as the generator adds
647 * the swizzle to the offset for us.
649 const int type_size
= type_sz(src
.type
);
650 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / type_size
;
651 assert(shift
+ instr
->num_components
<= 4);
653 if (nir_src_is_const(instr
->src
[0])) {
654 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
655 /* Offsets are in bytes but they should always be multiples of 4 */
656 assert(load_offset
% 4 == 0);
658 src
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
659 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
660 unsigned offset
= load_offset
+ shift
* type_size
;
661 src
.offset
= ROUND_DOWN_TO(offset
, 16);
662 shift
= (offset
% 16) / type_size
;
663 assert(shift
+ instr
->num_components
<= 4);
664 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
666 emit(MOV(dest
, src
));
668 /* Uniform arrays are vec4 aligned, because of std140 alignment
673 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
675 /* MOV_INDIRECT is going to stomp the whole thing anyway */
676 dest
.writemask
= WRITEMASK_XYZW
;
678 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
679 indirect
, brw_imm_ud(instr
->const_index
[1]));
684 case nir_intrinsic_load_ubo
: {
687 dest
= get_nir_dest(instr
->dest
);
689 if (nir_src_is_const(instr
->src
[0])) {
690 /* The block index is a constant, so just emit the binding table entry
693 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
694 nir_src_as_uint(instr
->src
[0]);
695 surf_index
= brw_imm_ud(index
);
697 /* The block index is not a constant. Evaluate the index expression
698 * per-channel and add the base UBO index; we have to select a value
699 * from any live channel.
701 surf_index
= src_reg(this, glsl_type::uint_type
);
702 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
703 instr
->num_components
),
704 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
705 surf_index
= emit_uniformize(surf_index
);
709 if (nir_src_is_const(instr
->src
[1])) {
710 unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
711 offset_reg
= brw_imm_ud(load_offset
& ~15);
713 offset_reg
= src_reg(this, glsl_type::uint_type
);
714 emit(MOV(dst_reg(offset_reg
),
715 get_nir_src(instr
->src
[1], nir_type_uint32
, 1)));
718 src_reg packed_consts
;
719 if (nir_dest_bit_size(instr
->dest
) == 32) {
720 packed_consts
= src_reg(this, glsl_type::vec4_type
);
721 emit_pull_constant_load_reg(dst_reg(packed_consts
),
724 NULL
, NULL
/* before_block/inst */);
726 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
727 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
729 emit_pull_constant_load_reg(dst_reg(temp_float
),
730 surf_index
, offset_reg
, NULL
, NULL
);
731 if (offset_reg
.file
== IMM
)
734 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
735 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
736 surf_index
, offset_reg
, NULL
, NULL
);
738 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
739 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
742 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
743 if (nir_src_is_const(instr
->src
[1])) {
744 unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
745 unsigned type_size
= type_sz(dest
.type
);
746 packed_consts
.swizzle
+=
747 BRW_SWIZZLE4(load_offset
% 16 / type_size
,
748 load_offset
% 16 / type_size
,
749 load_offset
% 16 / type_size
,
750 load_offset
% 16 / type_size
);
753 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
758 case nir_intrinsic_memory_barrier
: {
759 const vec4_builder bld
=
760 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
761 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
762 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
763 ->size_written
= 2 * REG_SIZE
;
767 case nir_intrinsic_shader_clock
: {
768 /* We cannot do anything if there is an event, so ignore it for now */
769 const src_reg shader_clock
= get_timestamp();
770 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
772 dest
= get_nir_dest(instr
->dest
, type
);
773 emit(MOV(dest
, shader_clock
));
778 unreachable("Unknown intrinsic");
783 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
786 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
787 dest
= get_nir_dest(instr
->dest
);
789 src_reg surface
= get_nir_ssbo_intrinsic_index(instr
);
790 src_reg offset
= get_nir_src(instr
->src
[1], 1);
792 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
793 data1
= get_nir_src(instr
->src
[2], 1);
795 if (op
== BRW_AOP_CMPWR
)
796 data2
= get_nir_src(instr
->src
[3], 1);
798 /* Emit the actual atomic operation operation */
799 const vec4_builder bld
=
800 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
802 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
804 1 /* dims */, 1 /* rsize */,
807 dest
.type
= atomic_result
.type
;
808 bld
.MOV(dest
, atomic_result
);
812 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
814 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
817 static enum brw_conditional_mod
818 brw_conditional_for_nir_comparison(nir_op op
)
824 return BRW_CONDITIONAL_L
;
829 return BRW_CONDITIONAL_GE
;
833 case nir_op_b32all_fequal2
:
834 case nir_op_b32all_iequal2
:
835 case nir_op_b32all_fequal3
:
836 case nir_op_b32all_iequal3
:
837 case nir_op_b32all_fequal4
:
838 case nir_op_b32all_iequal4
:
839 return BRW_CONDITIONAL_Z
;
843 case nir_op_b32any_fnequal2
:
844 case nir_op_b32any_inequal2
:
845 case nir_op_b32any_fnequal3
:
846 case nir_op_b32any_inequal3
:
847 case nir_op_b32any_fnequal4
:
848 case nir_op_b32any_inequal4
:
849 return BRW_CONDITIONAL_NZ
;
852 unreachable("not reached: bad operation for comparison");
857 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
858 enum brw_predicate
*predicate
)
860 if (!instr
->src
[0].src
.is_ssa
||
861 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
864 nir_alu_instr
*cmp_instr
=
865 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
867 switch (cmp_instr
->op
) {
868 case nir_op_b32any_fnequal2
:
869 case nir_op_b32any_inequal2
:
870 case nir_op_b32any_fnequal3
:
871 case nir_op_b32any_inequal3
:
872 case nir_op_b32any_fnequal4
:
873 case nir_op_b32any_inequal4
:
874 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
876 case nir_op_b32all_fequal2
:
877 case nir_op_b32all_iequal2
:
878 case nir_op_b32all_fequal3
:
879 case nir_op_b32all_iequal3
:
880 case nir_op_b32all_fequal4
:
881 case nir_op_b32all_iequal4
:
882 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
888 unsigned size_swizzle
=
889 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
892 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
893 for (unsigned i
= 0; i
< 2; i
++) {
894 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
895 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
896 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
897 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
898 unsigned base_swizzle
=
899 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
900 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
901 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
902 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
905 emit(CMP(dst_null_d(), op
[0], op
[1],
906 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
912 emit_find_msb_using_lzd(const vec4_builder
&bld
,
917 vec4_instruction
*inst
;
921 /* LZD of an absolute value source almost always does the right
922 * thing. There are two problem values:
924 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
925 * 0. However, findMSB(int(0x80000000)) == 30.
927 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
928 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
930 * For a value of zero or negative one, -1 will be returned.
932 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
933 * findMSB(-(1<<x)) should return x-1.
935 * For all negative number cases, including 0x80000000 and
936 * 0xffffffff, the correct value is obtained from LZD if instead of
937 * negating the (already negative) value the logical-not is used. A
938 * conditonal logical-not can be achieved in two instructions.
940 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
942 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
943 bld
.XOR(dst_reg(temp
), temp
, src
);
946 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
947 retype(temp
, BRW_REGISTER_TYPE_UD
));
949 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
950 * from the LSB side. Subtract the result from 31 to convert the MSB count
951 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
952 * which is exactly what findMSB() is supposed to return.
954 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
956 inst
->src
[0].negate
= true;
960 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
963 /* BDW PRM vol 15 - workarounds:
964 * DF->f format conversion for Align16 has wrong emask calculation when
965 * source is immediate.
967 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
968 src
.file
== BRW_IMMEDIATE_VALUE
) {
969 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
970 inst
->saturate
= saturate
;
976 case BRW_REGISTER_TYPE_D
:
977 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
979 case BRW_REGISTER_TYPE_UD
:
980 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
982 case BRW_REGISTER_TYPE_F
:
983 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
986 unreachable("Unknown conversion");
989 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
990 emit(MOV(temp
, src
));
991 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
992 emit(op
, temp2
, src_reg(temp
));
994 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
995 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
996 inst
->saturate
= saturate
;
1000 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1003 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1004 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1005 emit(MOV(dst_reg(tmp_src
), src
));
1006 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1007 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1008 inst
->saturate
= saturate
;
1012 * Try to use an immediate value for source 1
1014 * In cases of flow control, constant propagation is sometimes unable to
1015 * determine that a register contains a constant value. To work around this,
1016 * try to emit a literal as the second source here.
1019 try_immediate_source(const nir_alu_instr
*instr
, src_reg
*op
,
1020 MAYBE_UNUSED
const gen_device_info
*devinfo
)
1022 if (nir_src_num_components(instr
->src
[1].src
) != 1 ||
1023 nir_src_bit_size(instr
->src
[1].src
) != 32 ||
1024 !nir_src_is_const(instr
->src
[1].src
))
1027 const enum brw_reg_type old_type
= op
->type
;
1030 case BRW_REGISTER_TYPE_D
:
1031 case BRW_REGISTER_TYPE_UD
: {
1032 int d
= nir_src_as_int(instr
->src
[1].src
);
1038 /* On Gen8+ a negation source modifier on a logical operation means
1039 * something different. Nothing should generate this, so assert that
1040 * it does not occur.
1042 assert(devinfo
->gen
< 8 || (instr
->op
!= nir_op_iand
&&
1043 instr
->op
!= nir_op_ior
&&
1044 instr
->op
!= nir_op_ixor
));
1048 *op
= retype(src_reg(brw_imm_d(d
)), old_type
);
1052 case BRW_REGISTER_TYPE_F
: {
1053 float f
= nir_src_as_float(instr
->src
[1].src
);
1061 *op
= src_reg(brw_imm_f(f
));
1062 assert(op
->type
== old_type
);
1067 unreachable("Non-32bit type.");
1072 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1074 vec4_instruction
*inst
;
1076 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1077 nir_dest_bit_size(instr
->dest
.dest
));
1078 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1079 dst
.writemask
= instr
->dest
.write_mask
;
1082 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1083 nir_alu_type src_type
= (nir_alu_type
)
1084 (nir_op_infos
[instr
->op
].input_types
[i
] |
1085 nir_src_bit_size(instr
->src
[i
].src
));
1086 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1087 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1088 op
[i
].abs
= instr
->src
[i
].abs
;
1089 op
[i
].negate
= instr
->src
[i
].negate
;
1092 switch (instr
->op
) {
1095 inst
= emit(MOV(dst
, op
[0]));
1096 inst
->saturate
= instr
->dest
.saturate
;
1102 unreachable("not reached: should be handled by lower_vec_to_movs()");
1106 inst
= emit(MOV(dst
, op
[0]));
1107 inst
->saturate
= instr
->dest
.saturate
;
1113 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1114 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1116 inst
= emit(MOV(dst
, op
[0]));
1122 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1126 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1129 try_immediate_source(instr
, &op
[1], devinfo
);
1130 inst
= emit(ADD(dst
, op
[0], op
[1]));
1131 inst
->saturate
= instr
->dest
.saturate
;
1134 case nir_op_uadd_sat
:
1135 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1136 inst
= emit(ADD(dst
, op
[0], op
[1]));
1137 inst
->saturate
= true;
1141 try_immediate_source(instr
, &op
[1], devinfo
);
1142 inst
= emit(MUL(dst
, op
[0], op
[1]));
1143 inst
->saturate
= instr
->dest
.saturate
;
1147 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1148 if (devinfo
->gen
< 8) {
1149 /* For integer multiplication, the MUL uses the low 16 bits of one of
1150 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1151 * accumulates in the contribution of the upper 16 bits of that
1152 * operand. If we can determine that one of the args is in the low
1153 * 16 bits, though, we can just emit a single MUL.
1155 if (nir_src_is_const(instr
->src
[0].src
) &&
1156 nir_alu_instr_src_read_mask(instr
, 0) == 1 &&
1157 nir_src_comp_as_uint(instr
->src
[0].src
, 0) < (1 << 16)) {
1158 if (devinfo
->gen
< 7)
1159 emit(MUL(dst
, op
[0], op
[1]));
1161 emit(MUL(dst
, op
[1], op
[0]));
1162 } else if (nir_src_is_const(instr
->src
[1].src
) &&
1163 nir_alu_instr_src_read_mask(instr
, 1) == 1 &&
1164 nir_src_comp_as_uint(instr
->src
[1].src
, 0) < (1 << 16)) {
1165 if (devinfo
->gen
< 7)
1166 emit(MUL(dst
, op
[1], op
[0]));
1168 emit(MUL(dst
, op
[0], op
[1]));
1170 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1172 emit(MUL(acc
, op
[0], op
[1]));
1173 emit(MACH(dst_null_d(), op
[0], op
[1]));
1174 emit(MOV(dst
, src_reg(acc
)));
1177 emit(MUL(dst
, op
[0], op
[1]));
1182 case nir_op_imul_high
:
1183 case nir_op_umul_high
: {
1184 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1185 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1187 if (devinfo
->gen
>= 8)
1188 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1190 emit(MUL(acc
, op
[0], op
[1]));
1192 emit(MACH(dst
, op
[0], op
[1]));
1197 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1198 inst
->saturate
= instr
->dest
.saturate
;
1202 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1203 inst
->saturate
= instr
->dest
.saturate
;
1207 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1208 inst
->saturate
= instr
->dest
.saturate
;
1212 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1213 inst
->saturate
= instr
->dest
.saturate
;
1217 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1218 inst
->saturate
= instr
->dest
.saturate
;
1223 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1224 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1229 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1230 * appears that our hardware just does the right thing for signed
1233 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1234 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1238 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1239 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1241 /* Math instructions don't support conditional mod */
1242 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1243 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1245 /* Now, we need to determine if signs of the sources are different.
1246 * When we XOR the sources, the top bit is 0 if they are the same and 1
1247 * if they are different. We can then use a conditional modifier to
1248 * turn that into a predicate. This leads us to an XOR.l instruction.
1250 * Technically, according to the PRM, you're not allowed to use .l on a
1251 * XOR instruction. However, emperical experiments and Curro's reading
1252 * of the simulator source both indicate that it's safe.
1254 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1255 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1256 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1257 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1259 /* If the result of the initial remainder operation is non-zero and the
1260 * two sources have different signs, add in a copy of op[1] to get the
1261 * final integer modulus value.
1263 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1264 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1269 unreachable("not reached: should be handled by ldexp_to_arith()");
1272 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1273 inst
->saturate
= instr
->dest
.saturate
;
1277 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1278 inst
->saturate
= instr
->dest
.saturate
;
1282 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1283 inst
->saturate
= instr
->dest
.saturate
;
1286 case nir_op_uadd_carry
: {
1287 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1288 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1290 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1291 emit(MOV(dst
, src_reg(acc
)));
1295 case nir_op_usub_borrow
: {
1296 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1297 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1299 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1300 emit(MOV(dst
, src_reg(acc
)));
1305 inst
= emit(RNDZ(dst
, op
[0]));
1306 inst
->saturate
= instr
->dest
.saturate
;
1309 case nir_op_fceil
: {
1310 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1312 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1313 instr
->src
[0].src
.ssa
->num_components
:
1314 instr
->src
[0].src
.reg
.reg
->num_components
);
1316 op
[0].negate
= !op
[0].negate
;
1317 emit(RNDD(dst_reg(tmp
), op
[0]));
1319 inst
= emit(MOV(dst
, tmp
));
1320 inst
->saturate
= instr
->dest
.saturate
;
1325 inst
= emit(RNDD(dst
, op
[0]));
1326 inst
->saturate
= instr
->dest
.saturate
;
1330 inst
= emit(FRC(dst
, op
[0]));
1331 inst
->saturate
= instr
->dest
.saturate
;
1334 case nir_op_fround_even
:
1335 inst
= emit(RNDE(dst
, op
[0]));
1336 inst
->saturate
= instr
->dest
.saturate
;
1339 case nir_op_fquantize2f16
: {
1340 /* See also vec4_visitor::emit_pack_half_2x16() */
1341 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1342 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1343 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1345 /* Check for denormal */
1346 src_reg abs_src0
= op
[0];
1347 abs_src0
.abs
= true;
1348 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1349 BRW_CONDITIONAL_L
));
1350 /* Get the appropriately signed zero */
1351 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1352 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1353 brw_imm_ud(0x80000000)));
1354 /* Do the actual F32 -> F16 -> F32 conversion */
1355 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1356 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1357 /* Select that or zero based on normal status */
1358 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1359 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1360 inst
->saturate
= instr
->dest
.saturate
;
1366 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1369 try_immediate_source(instr
, &op
[1], devinfo
);
1370 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1371 inst
->saturate
= instr
->dest
.saturate
;
1376 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1379 try_immediate_source(instr
, &op
[1], devinfo
);
1380 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1381 inst
->saturate
= instr
->dest
.saturate
;
1385 case nir_op_fddx_coarse
:
1386 case nir_op_fddx_fine
:
1388 case nir_op_fddy_coarse
:
1389 case nir_op_fddy_fine
:
1390 unreachable("derivatives are not valid in vertex shaders");
1398 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1403 case nir_op_fne32
: {
1404 enum brw_conditional_mod conditional_mod
=
1405 brw_conditional_for_nir_comparison(instr
->op
);
1407 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1408 try_immediate_source(instr
, &op
[1], devinfo
);
1409 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1411 /* Produce a 32-bit boolean result from the DF comparison by selecting
1412 * only the low 32-bit in each DF produced. Do this in a temporary
1413 * so we can then move from there to the result using align16 again
1414 * to honor the original writemask.
1416 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1417 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1418 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1419 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1420 emit(MOV(dst
, src_reg(result
)));
1425 case nir_op_b32all_iequal2
:
1426 case nir_op_b32all_iequal3
:
1427 case nir_op_b32all_iequal4
:
1428 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1430 case nir_op_b32all_fequal2
:
1431 case nir_op_b32all_fequal3
:
1432 case nir_op_b32all_fequal4
: {
1434 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1436 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1437 brw_conditional_for_nir_comparison(instr
->op
)));
1438 emit(MOV(dst
, brw_imm_d(0)));
1439 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1440 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1444 case nir_op_b32any_inequal2
:
1445 case nir_op_b32any_inequal3
:
1446 case nir_op_b32any_inequal4
:
1447 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1449 case nir_op_b32any_fnequal2
:
1450 case nir_op_b32any_fnequal3
:
1451 case nir_op_b32any_fnequal4
: {
1453 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1455 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1456 brw_conditional_for_nir_comparison(instr
->op
)));
1458 emit(MOV(dst
, brw_imm_d(0)));
1459 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1460 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1465 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1466 if (devinfo
->gen
>= 8) {
1467 op
[0] = resolve_source_modifiers(op
[0]);
1469 emit(NOT(dst
, op
[0]));
1473 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1474 if (devinfo
->gen
>= 8) {
1475 op
[0] = resolve_source_modifiers(op
[0]);
1476 op
[1] = resolve_source_modifiers(op
[1]);
1478 try_immediate_source(instr
, &op
[1], devinfo
);
1479 emit(XOR(dst
, op
[0], op
[1]));
1483 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1484 if (devinfo
->gen
>= 8) {
1485 op
[0] = resolve_source_modifiers(op
[0]);
1486 op
[1] = resolve_source_modifiers(op
[1]);
1488 try_immediate_source(instr
, &op
[1], devinfo
);
1489 emit(OR(dst
, op
[0], op
[1]));
1493 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1494 if (devinfo
->gen
>= 8) {
1495 op
[0] = resolve_source_modifiers(op
[0]);
1496 op
[1] = resolve_source_modifiers(op
[1]);
1498 try_immediate_source(instr
, &op
[1], devinfo
);
1499 emit(AND(dst
, op
[0], op
[1]));
1505 if (nir_dest_bit_size(instr
->dest
.dest
) > 32) {
1506 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
1507 emit_conversion_to_double(dst
, negate(op
[0]), false);
1509 emit(MOV(dst
, negate(op
[0])));
1514 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1515 /* We use a MOV with conditional_mod to check if the provided value is
1516 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1517 * source modifier on the source operand to trigger this, as source
1518 * modifiers don't affect the result of the testing against 0.0.
1520 src_reg value
= op
[0];
1522 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1523 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1525 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1526 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1527 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1528 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1530 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1535 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1538 case nir_op_fnoise1_1
:
1539 case nir_op_fnoise1_2
:
1540 case nir_op_fnoise1_3
:
1541 case nir_op_fnoise1_4
:
1542 case nir_op_fnoise2_1
:
1543 case nir_op_fnoise2_2
:
1544 case nir_op_fnoise2_3
:
1545 case nir_op_fnoise2_4
:
1546 case nir_op_fnoise3_1
:
1547 case nir_op_fnoise3_2
:
1548 case nir_op_fnoise3_3
:
1549 case nir_op_fnoise3_4
:
1550 case nir_op_fnoise4_1
:
1551 case nir_op_fnoise4_2
:
1552 case nir_op_fnoise4_3
:
1553 case nir_op_fnoise4_4
:
1554 unreachable("not reached: should be handled by lower_noise");
1556 case nir_op_unpack_half_2x16_split_x
:
1557 case nir_op_unpack_half_2x16_split_y
:
1558 case nir_op_pack_half_2x16_split
:
1559 unreachable("not reached: should not occur in vertex shader");
1561 case nir_op_unpack_snorm_2x16
:
1562 case nir_op_unpack_unorm_2x16
:
1563 case nir_op_pack_snorm_2x16
:
1564 case nir_op_pack_unorm_2x16
:
1565 unreachable("not reached: should be handled by lower_packing_builtins");
1567 case nir_op_pack_uvec4_to_uint
:
1568 unreachable("not reached");
1570 case nir_op_pack_uvec2_to_uint
: {
1571 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1572 tmp1
.writemask
= WRITEMASK_X
;
1573 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1574 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1576 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1577 tmp2
.writemask
= WRITEMASK_X
;
1578 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1579 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1581 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1585 case nir_op_pack_64_2x32_split
: {
1586 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1587 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1588 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1589 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1590 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1591 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1592 emit(MOV(dst
, src_reg(result
)));
1596 case nir_op_unpack_64_2x32_split_x
:
1597 case nir_op_unpack_64_2x32_split_y
: {
1598 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1599 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1600 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1601 emit(MOV(tmp
, op
[0]));
1602 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1603 emit(oper
, tmp2
, src_reg(tmp
));
1604 emit(MOV(dst
, src_reg(tmp2
)));
1608 case nir_op_unpack_half_2x16
:
1609 /* As NIR does not guarantee that we have a correct swizzle outside the
1610 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1611 * uses the source operand in an operation with WRITEMASK_Y while our
1612 * source operand has only size 1, it accessed incorrect data producing
1613 * regressions in Piglit. We repeat the swizzle of the first component on the
1614 * rest of components to avoid regressions. In the vec4_visitor IR code path
1615 * this is not needed because the operand has already the correct swizzle.
1617 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1618 emit_unpack_half_2x16(dst
, op
[0]);
1621 case nir_op_pack_half_2x16
:
1622 emit_pack_half_2x16(dst
, op
[0]);
1625 case nir_op_unpack_unorm_4x8
:
1626 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1627 emit_unpack_unorm_4x8(dst
, op
[0]);
1630 case nir_op_pack_unorm_4x8
:
1631 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1632 emit_pack_unorm_4x8(dst
, op
[0]);
1635 case nir_op_unpack_snorm_4x8
:
1636 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1637 emit_unpack_snorm_4x8(dst
, op
[0]);
1640 case nir_op_pack_snorm_4x8
:
1641 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1642 emit_pack_snorm_4x8(dst
, op
[0]);
1645 case nir_op_bitfield_reverse
:
1646 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1647 emit(BFREV(dst
, op
[0]));
1650 case nir_op_bit_count
:
1651 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1652 emit(CBIT(dst
, op
[0]));
1655 case nir_op_ufind_msb
:
1656 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1657 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1660 case nir_op_ifind_msb
: {
1661 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1662 vec4_builder bld
= vec4_builder(this).at_end();
1665 if (devinfo
->gen
< 7) {
1666 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1668 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1670 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1671 * count from the LSB side. If FBH didn't return an error
1672 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1673 * count into an LSB count.
1675 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1677 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1678 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1679 inst
->src
[0].negate
= true;
1684 case nir_op_find_lsb
: {
1685 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1686 vec4_builder bld
= vec4_builder(this).at_end();
1688 if (devinfo
->gen
< 7) {
1689 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1691 /* (x & -x) generates a value that consists of only the LSB of x.
1692 * For all powers of 2, findMSB(y) == findLSB(y).
1694 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1695 src_reg negated_src
= src
;
1697 /* One must be negated, and the other must be non-negated. It
1698 * doesn't matter which is which.
1700 negated_src
.negate
= true;
1703 bld
.AND(temp
, src
, negated_src
);
1704 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1706 bld
.FBL(dst
, op
[0]);
1711 case nir_op_ubitfield_extract
:
1712 case nir_op_ibitfield_extract
:
1713 unreachable("should have been lowered");
1716 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1717 op
[0] = fix_3src_operand(op
[0]);
1718 op
[1] = fix_3src_operand(op
[1]);
1719 op
[2] = fix_3src_operand(op
[2]);
1721 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1725 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1726 emit(BFI1(dst
, op
[0], op
[1]));
1730 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1731 op
[0] = fix_3src_operand(op
[0]);
1732 op
[1] = fix_3src_operand(op
[1]);
1733 op
[2] = fix_3src_operand(op
[2]);
1735 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1738 case nir_op_bitfield_insert
:
1739 unreachable("not reached: should have been lowered");
1742 assert(!instr
->dest
.saturate
);
1744 /* Straightforward since the source can be assumed to be either
1745 * strictly >= 0 or strictly <= 0 depending on the setting of the
1748 inst
= emit(MOV(dst
, op
[0]));
1749 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1751 inst
= (op
[0].negate
)
1752 ? emit(MOV(dst
, brw_imm_f(-1.0f
)))
1753 : emit(MOV(dst
, brw_imm_f(1.0f
)));
1754 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1755 } else if (type_sz(op
[0].type
) < 8) {
1756 /* AND(val, 0x80000000) gives the sign bit.
1758 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1761 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1763 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1764 dst
.type
= BRW_REGISTER_TYPE_UD
;
1765 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1767 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1768 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1769 dst
.type
= BRW_REGISTER_TYPE_F
;
1771 /* For doubles we do the same but we need to consider:
1773 * - We use a MOV with conditional_mod instead of a CMP so that we can
1774 * skip loading a 0.0 immediate. We use a source modifier on the
1775 * source of the MOV so that we flush denormalized values to 0.
1776 * Since we want to compare against 0, this won't alter the result.
1777 * - We need to extract the high 32-bit of each DF where the sign
1779 * - We need to produce a DF result.
1782 /* Check for zero */
1783 src_reg value
= op
[0];
1785 inst
= emit(MOV(dst_null_df(), value
));
1786 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1788 /* AND each high 32-bit channel with 0x80000000u */
1789 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1790 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1791 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1793 /* Add 1.0 to each channel, predicated to skip the cases where the
1794 * channel's value was 0
1796 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1797 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1799 /* Now convert the result from float to double */
1800 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1801 BRW_REGISTER_TYPE_F
),
1807 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1808 try_immediate_source(instr
, &op
[1], devinfo
);
1809 emit(SHL(dst
, op
[0], op
[1]));
1813 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1814 try_immediate_source(instr
, &op
[1], devinfo
);
1815 emit(ASR(dst
, op
[0], op
[1]));
1819 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1820 try_immediate_source(instr
, &op
[1], devinfo
);
1821 emit(SHR(dst
, op
[0], op
[1]));
1825 if (type_sz(dst
.type
) == 8) {
1826 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1827 emit(MUL(mul_dst
, op
[1], op
[0]));
1828 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1829 inst
->saturate
= instr
->dest
.saturate
;
1831 op
[0] = fix_3src_operand(op
[0]);
1832 op
[1] = fix_3src_operand(op
[1]);
1833 op
[2] = fix_3src_operand(op
[2]);
1835 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1836 inst
->saturate
= instr
->dest
.saturate
;
1841 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1842 inst
->saturate
= instr
->dest
.saturate
;
1845 case nir_op_b32csel
:
1846 enum brw_predicate predicate
;
1847 if (!optimize_predicate(instr
, &predicate
)) {
1848 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1849 switch (dst
.writemask
) {
1851 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1854 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1857 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1860 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1863 predicate
= BRW_PREDICATE_NORMAL
;
1867 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1868 inst
->predicate
= predicate
;
1871 case nir_op_fdot_replicated2
:
1872 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1873 inst
->saturate
= instr
->dest
.saturate
;
1876 case nir_op_fdot_replicated3
:
1877 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1878 inst
->saturate
= instr
->dest
.saturate
;
1881 case nir_op_fdot_replicated4
:
1882 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1883 inst
->saturate
= instr
->dest
.saturate
;
1886 case nir_op_fdph_replicated
:
1887 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1888 inst
->saturate
= instr
->dest
.saturate
;
1893 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1898 unreachable("not reached: should be lowered by lower_source mods");
1901 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1904 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1908 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1911 unreachable("Unimplemented ALU operation");
1914 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1915 * to sign extend the low bit to 0/~0
1917 if (devinfo
->gen
<= 5 &&
1918 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1919 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1920 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1921 masked
.writemask
= dst
.writemask
;
1922 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1923 src_reg masked_neg
= src_reg(masked
);
1924 masked_neg
.negate
= true;
1925 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1930 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1932 switch (instr
->type
) {
1933 case nir_jump_break
:
1934 emit(BRW_OPCODE_BREAK
);
1937 case nir_jump_continue
:
1938 emit(BRW_OPCODE_CONTINUE
);
1941 case nir_jump_return
:
1944 unreachable("unknown jump");
1948 static enum ir_texture_opcode
1949 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1951 enum ir_texture_opcode op
;
1954 case nir_texop_lod
: op
= ir_lod
; break;
1955 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1956 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1957 case nir_texop_tex
: op
= ir_tex
; break;
1958 case nir_texop_tg4
: op
= ir_tg4
; break;
1959 case nir_texop_txb
: op
= ir_txb
; break;
1960 case nir_texop_txd
: op
= ir_txd
; break;
1961 case nir_texop_txf
: op
= ir_txf
; break;
1962 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1963 case nir_texop_txl
: op
= ir_txl
; break;
1964 case nir_texop_txs
: op
= ir_txs
; break;
1965 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
1967 unreachable("unknown texture opcode");
1973 static const glsl_type
*
1974 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1975 unsigned components
)
1977 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
1982 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1984 unsigned texture
= instr
->texture_index
;
1985 unsigned sampler
= instr
->sampler_index
;
1986 src_reg texture_reg
= brw_imm_ud(texture
);
1987 src_reg sampler_reg
= brw_imm_ud(sampler
);
1989 const glsl_type
*coord_type
= NULL
;
1990 src_reg shadow_comparator
;
1991 src_reg offset_value
;
1993 src_reg sample_index
;
1996 const glsl_type
*dest_type
=
1997 glsl_type_for_nir_alu_type(instr
->dest_type
,
1998 nir_tex_instr_dest_size(instr
));
1999 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2001 /* The hardware requires a LOD for buffer textures */
2002 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2005 /* Load the texture operation sources */
2006 uint32_t constant_offset
= 0;
2007 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2008 switch (instr
->src
[i
].src_type
) {
2009 case nir_tex_src_comparator
:
2010 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2011 BRW_REGISTER_TYPE_F
, 1);
2014 case nir_tex_src_coord
: {
2015 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2017 switch (instr
->op
) {
2019 case nir_texop_txf_ms
:
2020 case nir_texop_samples_identical
:
2021 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2023 coord_type
= glsl_type::ivec(src_size
);
2027 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2029 coord_type
= glsl_type::vec(src_size
);
2035 case nir_tex_src_ddx
:
2036 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2037 nir_tex_instr_src_size(instr
, i
));
2040 case nir_tex_src_ddy
:
2041 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2042 nir_tex_instr_src_size(instr
, i
));
2045 case nir_tex_src_lod
:
2046 switch (instr
->op
) {
2049 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2053 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2058 case nir_tex_src_ms_index
: {
2059 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2063 case nir_tex_src_offset
: {
2064 nir_const_value
*const_offset
=
2065 nir_src_as_const_value(instr
->src
[i
].src
);
2066 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
2067 if (!const_offset
||
2068 !brw_texture_offset(const_offset
->i32
,
2069 nir_tex_instr_src_size(instr
, i
),
2070 &constant_offset
)) {
2072 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2077 case nir_tex_src_texture_offset
: {
2078 /* Emit code to evaluate the actual indexing expression */
2079 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2080 src_reg
temp(this, glsl_type::uint_type
);
2081 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2082 texture_reg
= emit_uniformize(temp
);
2086 case nir_tex_src_sampler_offset
: {
2087 /* Emit code to evaluate the actual indexing expression */
2088 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2089 src_reg
temp(this, glsl_type::uint_type
);
2090 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2091 sampler_reg
= emit_uniformize(temp
);
2095 case nir_tex_src_projector
:
2096 unreachable("Should be lowered by do_lower_texture_projection");
2098 case nir_tex_src_bias
:
2099 unreachable("LOD bias is not valid for vertex shaders.\n");
2102 unreachable("unknown texture source");
2106 if (instr
->op
== nir_texop_txf_ms
||
2107 instr
->op
== nir_texop_samples_identical
) {
2108 assert(coord_type
!= NULL
);
2109 if (devinfo
->gen
>= 7 &&
2110 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2111 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2113 mcs
= brw_imm_ud(0u);
2117 /* Stuff the channel select bits in the top of the texture offset */
2118 if (instr
->op
== nir_texop_tg4
) {
2119 if (instr
->component
== 1 &&
2120 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2121 /* gather4 sampler is broken for green channel on RG32F --
2122 * we must ask for blue instead.
2124 constant_offset
|= 2 << 16;
2126 constant_offset
|= instr
->component
<< 16;
2130 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2132 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2134 lod
, lod2
, sample_index
,
2135 constant_offset
, offset_value
, mcs
,
2136 texture
, texture_reg
, sampler_reg
);
2140 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2142 nir_ssa_values
[instr
->def
.index
] =
2143 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2146 /* SIMD4x2 64bit data is stored in register space like this:
2148 * r0.0:DF x0 y0 z0 w0
2149 * r1.0:DF x1 y1 z1 w1
2151 * When we need to write data such as this to memory using 32-bit write
2152 * messages we need to shuffle it in this fashion:
2154 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2155 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2157 * We need to do the inverse operation when we read using 32-bit messages,
2158 * which we can do by applying the same exact shuffling on the 64-bit data
2159 * read, only that because the data for each vertex is positioned differently
2160 * we need to apply different channel enables.
2162 * This function takes 64bit data and shuffles it as explained above.
2164 * The @for_write parameter is used to specify if the shuffling is being done
2165 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2166 * write message (for_write = true), or instead we are doing the inverse
2167 * operation and we have just read 64-bit data using a 32-bit messages that we
2168 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2170 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2171 * otherwise the instructions are emitted normally at the end. The function
2172 * returns the last instruction inserted.
2174 * Notice that @src and @dst cannot be the same register.
2177 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2178 bblock_t
*block
, vec4_instruction
*ref
)
2180 assert(type_sz(src
.type
) == 8);
2181 assert(type_sz(dst
.type
) == 8);
2182 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2183 assert(!ref
== !block
);
2185 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2186 vec4_builder(this).at(block
, ref
->next
);
2188 /* Resolve swizzle in src */
2189 vec4_instruction
*inst
;
2190 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2191 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2192 inst
= bld
.MOV(data
, src
);
2193 src
= src_reg(data
);
2196 /* dst+0.XY = src+0.XY */
2197 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2199 /* dst+0.ZW = src+1.XY */
2200 inst
= bld
.group(4, for_write
? 1 : 0)
2201 .MOV(writemask(dst
, WRITEMASK_ZW
),
2202 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2204 /* dst+1.XY = src+0.ZW */
2205 inst
= bld
.group(4, for_write
? 0 : 1)
2206 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2207 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2209 /* dst+1.ZW = src+1.ZW */
2210 inst
= bld
.group(4, 1)
2211 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2212 byte_offset(src
, REG_SIZE
));