src/intel/compiler/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32 #include "brw_fs.h"
  33 #include "dev/gen_debug.h"
  34
  35 namespace brw {
  36
  37 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  38                                    void *log_data,
  39                                    const struct brw_tcs_prog_key *key,
  40                                    struct brw_tcs_prog_data *prog_data,
  41                                    const nir_shader *nir,
  42                                    void *mem_ctx,
  43                                    int shader_time_index,
  44                                    const struct brw_vue_map *input_vue_map)
  45    : vec4_visitor(compiler, log_data, &key->base.tex, &prog_data->base,
  46                   nir, mem_ctx, false, shader_time_index),
  47      input_vue_map(input_vue_map), key(key)
  48 {
  49 }
  50
  51
  52 void
  53 vec4_tcs_visitor::setup_payload()
  54 {
  55    int reg = 0;
  56
  57    /* The payload always contains important data in r0, which contains
  58     * the URB handles that are passed on to the URB write at the end
  59     * of the thread.
  60     */
  61    reg++;
  62
  63    /* r1.0 - r4.7 may contain the input control point URB handles,
  64     * which we use to pull vertex data.
  65     */
  66    reg += 4;
  67
  68    /* Push constants may start at r5.0 */
  69    reg = setup_uniforms(reg);
  70
  71    this->first_non_payload_grf = reg;
  72 }
  73
  74
  75 void
  76 vec4_tcs_visitor::emit_prolog()
  77 {
  78    invocation_id = src_reg(this, glsl_type::uint_type);
  79    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
  80
  81    /* HS threads are dispatched with the dispatch mask set to 0xFF.
  82     * If there are an odd number of output vertices, then the final
  83     * HS instance dispatched will only have its bottom half doing real
  84     * work, and so we need to disable the upper half:
  85     */
  86    if (nir->info.tess.tcs_vertices_out % 2) {
  87       emit(CMP(dst_null_d(), invocation_id,
  88                brw_imm_ud(nir->info.tess.tcs_vertices_out),
  89                BRW_CONDITIONAL_L));
  90
  91       /* Matching ENDIF is in emit_thread_end() */
  92       emit(IF(BRW_PREDICATE_NORMAL));
  93    }
  94 }
  95
  96
  97 void
  98 vec4_tcs_visitor::emit_thread_end()
  99 {
 100    vec4_instruction *inst;
 101    current_annotation = "thread end";
 102
 103    if (nir->info.tess.tcs_vertices_out % 2) {
 104       emit(BRW_OPCODE_ENDIF);
 105    }
 106
 107    if (devinfo->gen == 7) {
 108       struct brw_tcs_prog_data *tcs_prog_data =
 109          (struct brw_tcs_prog_data *) prog_data;
 110
 111       current_annotation = "release input vertices";
 112
 113       /* Synchronize all threads, so we know that no one is still
 114        * using the input URB handles.
 115        */
 116       if (tcs_prog_data->instances > 1) {
 117          dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 118          emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 119          emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 120       }
 121
 122       /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
 123        * We want to compare the bottom half of invocation_id with 0, but
 124        * use that truth value for the top half as well.  Unfortunately,
 125        * we don't have stride in the vec4 world, nor UV immediates in
 126        * align16, so we need an opcode to get invocation_id<0,4,0>.
 127        */
 128       set_condmod(BRW_CONDITIONAL_Z,
 129                   emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
 130                        invocation_id));
 131       emit(IF(BRW_PREDICATE_NORMAL));
 132       for (unsigned i = 0; i < key->input_vertices; i += 2) {
 133          /* If we have an odd number of input vertices, the last will be
 134           * unpaired.  We don't want to use an interleaved URB write in
 135           * that case.
 136           */
 137          const bool is_unpaired = i == key->input_vertices - 1;
 138
 139          dst_reg header(this, glsl_type::uvec4_type);
 140          emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
 141               brw_imm_ud(is_unpaired));
 142       }
 143       emit(BRW_OPCODE_ENDIF);
 144    }
 145
 146    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 147       emit_shader_time_end();
 148
 149    inst = emit(TCS_OPCODE_THREAD_END);
 150    inst->base_mrf = 14;
 151    inst->mlen = 2;
 152 }
 153
 154
 155 void
 156 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 157                                       const src_reg &vertex_index,
 158                                       unsigned base_offset,
 159                                       unsigned first_component,
 160                                       const src_reg &indirect_offset)
 161 {
 162    vec4_instruction *inst;
 163    dst_reg temp(this, glsl_type::ivec4_type);
 164    temp.type = dst.type;
 165
 166    /* Set up the message header to reference the proper parts of the URB */
 167    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 168    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 169                indirect_offset);
 170    inst->force_writemask_all = true;
 171
 172    /* Read into a temporary, ignoring writemasking. */
 173    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 174    inst->offset = base_offset;
 175    inst->mlen = 1;
 176    inst->base_mrf = -1;
 177
 178    /* Copy the temporary to the destination to deal with writemasking.
 179     *
 180     * Also attempt to deal with gl_PointSize being in the .w component.
 181     */
 182    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 183       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 184    } else {
 185       src_reg src = src_reg(temp);
 186       src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
 187       emit(MOV(dst, src));
 188    }
 189 }
 190
 191 void
 192 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 193                                        unsigned base_offset,
 194                                        unsigned first_component,
 195                                        const src_reg &indirect_offset)
 196 {
 197    vec4_instruction *inst;
 198
 199    /* Set up the message header to reference the proper parts of the URB */
 200    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 201    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 202                brw_imm_ud(dst.writemask << first_component), indirect_offset);
 203    inst->force_writemask_all = true;
 204
 205    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 206    read->offset = base_offset;
 207    read->mlen = 1;
 208    read->base_mrf = -1;
 209
 210    if (first_component) {
 211       /* Read into a temporary and copy with a swizzle and writemask. */
 212       read->dst = retype(dst_reg(this, glsl_type::ivec4_type), dst.type);
 213       emit(MOV(dst, swizzle(src_reg(read->dst),
 214                             BRW_SWZ_COMP_INPUT(first_component))));
 215    }
 216 }
 217
 218 void
 219 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 220                                  unsigned writemask,
 221                                  unsigned base_offset,
 222                                  const src_reg &indirect_offset)
 223 {
 224    if (writemask == 0)
 225       return;
 226
 227    src_reg message(this, glsl_type::uvec4_type, 2);
 228    vec4_instruction *inst;
 229
 230    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 231                brw_imm_ud(writemask), indirect_offset);
 232    inst->force_writemask_all = true;
 233    inst = emit(MOV(byte_offset(dst_reg(retype(message, value.type)), REG_SIZE),
 234                    value));
 235    inst->force_writemask_all = true;
 236
 237    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 238    inst->offset = base_offset;
 239    inst->mlen = 2;
 240    inst->base_mrf = -1;
 241 }
 242
 243 void
 244 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 245 {
 246    switch (instr->intrinsic) {
 247    case nir_intrinsic_load_invocation_id:
 248       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 249                invocation_id));
 250       break;
 251    case nir_intrinsic_load_primitive_id:
 252       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 253            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 254       break;
 255    case nir_intrinsic_load_patch_vertices_in:
 256       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 257                brw_imm_d(key->input_vertices)));
 258       break;
 259    case nir_intrinsic_load_per_vertex_input: {
 260       src_reg indirect_offset = get_indirect_offset(instr);
 261       unsigned imm_offset = instr->const_index[0];
 262
 263       src_reg vertex_index = retype(get_nir_src_imm(instr->src[0]),
 264                                     BRW_REGISTER_TYPE_UD);
 265
 266       unsigned first_component = nir_intrinsic_component(instr);
 267       if (nir_dest_bit_size(instr->dest) == 64) {
 268          /* We need to emit up to two 32-bit URB reads, then shuffle
 269           * the result into a temporary, then move to the destination
 270           * honoring the writemask
 271           *
 272           * We don't need to divide first_component by 2 because
 273           * emit_input_urb_read takes a 32-bit type.
 274           */
 275          dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
 276          dst_reg tmp_d = retype(tmp, BRW_REGISTER_TYPE_D);
 277          emit_input_urb_read(tmp_d, vertex_index, imm_offset,
 278                              first_component, indirect_offset);
 279          if (instr->num_components > 2) {
 280             emit_input_urb_read(byte_offset(tmp_d, REG_SIZE), vertex_index,
 281                                 imm_offset + 1, 0, indirect_offset);
 282          }
 283
 284          src_reg tmp_src = retype(src_reg(tmp_d), BRW_REGISTER_TYPE_DF);
 285          dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type);
 286          shuffle_64bit_data(shuffled, tmp_src, false);
 287
 288          dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_DF);
 289          dst.writemask = brw_writemask_for_size(instr->num_components);
 290          emit(MOV(dst, src_reg(shuffled)));
 291       } else {
 292          dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 293          dst.writemask = brw_writemask_for_size(instr->num_components);
 294          emit_input_urb_read(dst, vertex_index, imm_offset,
 295                              first_component, indirect_offset);
 296       }
 297       break;
 298    }
 299    case nir_intrinsic_load_input:
 300       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 301       break;
 302    case nir_intrinsic_load_output:
 303    case nir_intrinsic_load_per_vertex_output: {
 304       src_reg indirect_offset = get_indirect_offset(instr);
 305       unsigned imm_offset = instr->const_index[0];
 306
 307       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 308       dst.writemask = brw_writemask_for_size(instr->num_components);
 309
 310       emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr),
 311                            indirect_offset);
 312       break;
 313    }
 314    case nir_intrinsic_store_output:
 315    case nir_intrinsic_store_per_vertex_output: {
 316       src_reg value = get_nir_src(instr->src[0]);
 317       unsigned mask = instr->const_index[1];
 318       unsigned swiz = BRW_SWIZZLE_XYZW;
 319
 320       src_reg indirect_offset = get_indirect_offset(instr);
 321       unsigned imm_offset = instr->const_index[0];
 322
 323       unsigned first_component = nir_intrinsic_component(instr);
 324       if (first_component) {
 325          if (nir_src_bit_size(instr->src[0]) == 64)
 326             first_component /= 2;
 327          assert(swiz == BRW_SWIZZLE_XYZW);
 328          swiz = BRW_SWZ_COMP_OUTPUT(first_component);
 329          mask = mask << first_component;
 330       }
 331
 332       if (nir_src_bit_size(instr->src[0]) == 64) {
 333          /* For 64-bit data we need to shuffle the data before we write and
 334           * emit two messages. Also, since each channel is twice as large we
 335           * need to fix the writemask in each 32-bit message to account for it.
 336           */
 337          value = swizzle(retype(value, BRW_REGISTER_TYPE_DF), swiz);
 338          dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type);
 339          shuffle_64bit_data(shuffled, value, true);
 340          src_reg shuffled_float = src_reg(retype(shuffled, BRW_REGISTER_TYPE_F));
 341
 342          for (int n = 0; n < 2; n++) {
 343             unsigned fixed_mask = 0;
 344             if (mask & WRITEMASK_X)
 345                fixed_mask |= WRITEMASK_XY;
 346             if (mask & WRITEMASK_Y)
 347                fixed_mask |= WRITEMASK_ZW;
 348             emit_urb_write(shuffled_float, fixed_mask,
 349                            imm_offset, indirect_offset);
 350
 351             shuffled_float = byte_offset(shuffled_float, REG_SIZE);
 352             mask >>= 2;
 353             imm_offset++;
 354          }
 355       } else {
 356          emit_urb_write(swizzle(value, swiz), mask,
 357                         imm_offset, indirect_offset);
 358       }
 359       break;
 360    }
 361
 362    case nir_intrinsic_barrier: {
 363       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 364       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 365       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 366       break;
 367    }
 368
 369    default:
 370       vec4_visitor::nir_emit_intrinsic(instr);
 371    }
 372 }
 373
 374
 375 extern "C" const unsigned *
 376 brw_compile_tcs(const struct brw_compiler *compiler,
 377                 void *log_data,
 378                 void *mem_ctx,
 379                 const struct brw_tcs_prog_key *key,
 380                 struct brw_tcs_prog_data *prog_data,
 381                 nir_shader *nir,
 382                 int shader_time_index,
 383                 char **error_str)
 384 {
 385    const struct gen_device_info *devinfo = compiler->devinfo;
 386    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 387    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 388    const unsigned *assembly;
 389
 390    nir->info.outputs_written = key->outputs_written;
 391    nir->info.patch_outputs_written = key->patch_outputs_written;
 392
 393    struct brw_vue_map input_vue_map;
 394    brw_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read,
 395                        nir->info.separate_shader);
 396    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 397                             nir->info.outputs_written,
 398                             nir->info.patch_outputs_written);
 399
 400    brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
 401    brw_nir_lower_vue_inputs(nir, &input_vue_map);
 402    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
 403                              key->tes_primitive_mode);
 404    if (key->quads_workaround)
 405       brw_nir_apply_tcs_quads_workaround(nir);
 406
 407    brw_postprocess_nir(nir, compiler, is_scalar);
 408
 409    bool has_primitive_id =
 410       nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID);
 411
 412    if (compiler->use_tcs_8_patch &&
 413        nir->info.tess.tcs_vertices_out <= 16 &&
 414        2 + has_primitive_id + key->input_vertices <= 31) {
 415       /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode.  First,
 416        * the "Instance" field limits the number of output vertices to [1, 16].
 417        * Secondly, the "Dispatch GRF Start Register for URB Data" field is
 418        * limited to [0, 31] - which imposes a limit on the input vertices.
 419        */
 420       vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH;
 421       prog_data->instances = nir->info.tess.tcs_vertices_out;
 422       prog_data->include_primitive_id = has_primitive_id;
 423    } else {
 424       unsigned verts_per_thread = is_scalar ? 8 : 2;
 425       vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_SINGLE_PATCH;
 426       prog_data->instances =
 427          DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, verts_per_thread);
 428    }
 429
 430    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 431     * That divides up as follows:
 432     *
 433     *     32 bytes for the patch header (tessellation factors)
 434     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 435     *              gl_MaxTessPatchComponents = 120)
 436     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 437     *              gl_MaxPatchVertices = 32 and
 438     *              gl_MaxTessControlOutputComponents = 128)
 439     *
 440     *  15808 bytes left for varying packing overhead
 441     */
 442    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 443    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 444    unsigned output_size_bytes = 0;
 445    /* Note that the patch header is counted in num_per_patch_slots. */
 446    output_size_bytes += num_per_patch_slots * 16;
 447    output_size_bytes += nir->info.tess.tcs_vertices_out *
 448                         num_per_vertex_slots * 16;
 449
 450    assert(output_size_bytes >= 1);
 451    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 452       return NULL;
 453
 454    /* URB entry sizes are stored as a multiple of 64 bytes. */
 455    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 456
 457    /* On Cannonlake software shall not program an allocation size that
 458     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
 459     */
 460    if (devinfo->gen == 10 &&
 461        vue_prog_data->urb_entry_size % 3 == 0)
 462       vue_prog_data->urb_entry_size++;
 463
 464    /* HS does not use the usual payload pushing from URB to GRFs,
 465     * because we don't have enough registers for a full-size payload, and
 466     * the hardware is broken on Haswell anyway.
 467     */
 468    vue_prog_data->urb_read_length = 0;
 469
 470    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 471       fprintf(stderr, "TCS Input ");
 472       brw_print_vue_map(stderr, &input_vue_map);
 473       fprintf(stderr, "TCS Output ");
 474       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 475    }
 476
 477    if (is_scalar) {
 478       fs_visitor v(compiler, log_data, mem_ctx, &key->base,
 479                    &prog_data->base.base, NULL, nir, 8,
 480                    shader_time_index, &input_vue_map);
 481       if (!v.run_tcs()) {
 482          if (error_str)
 483             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 484          return NULL;
 485       }
 486
 487       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
 488
 489       fs_generator g(compiler, log_data, mem_ctx,
 490                      &prog_data->base.base, v.shader_stats, false,
 491                      MESA_SHADER_TESS_CTRL);
 492       if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 493          g.enable_debug(ralloc_asprintf(mem_ctx,
 494                                         "%s tessellation control shader %s",
 495                                         nir->info.label ? nir->info.label
 496                                                         : "unnamed",
 497                                         nir->info.name));
 498       }
 499
 500       g.generate_code(v.cfg, 8);
 501
 502       assembly = g.get_assembly();
 503    } else {
 504       vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 505                          nir, mem_ctx, shader_time_index, &input_vue_map);
 506       if (!v.run()) {
 507          if (error_str)
 508             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 509          return NULL;
 510       }
 511
 512       if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 513          v.dump_instructions();
 514
 515
 516       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 517                                             &prog_data->base, v.cfg);
 518    }
 519
 520    return assembly;
 521 }
 522
 523
 524 } /* namespace brw */