2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
36 #include "drm-uapi/i915_drm.h"
69 * Get the PCI ID for the device name.
71 * Returns -1 if the device is not known.
74 gen_device_name_to_pci_device_id(const char *name
)
76 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
77 if (!strcmp(name_map
[i
].name
, name
))
78 return name_map
[i
].pci_id
;
84 static const struct gen_device_info gen_device_info_i965
= {
86 .has_negative_rhw_bug
= true,
88 .num_subslices
= { 1, },
89 .num_eu_per_subslice
= 8,
90 .num_thread_per_eu
= 4,
93 .max_wm_threads
= 8 * 4,
97 .timestamp_frequency
= 12500000,
101 static const struct gen_device_info gen_device_info_g4x
= {
105 .has_surface_tile_offset
= true,
108 .num_subslices
= { 1, },
109 .num_eu_per_subslice
= 10,
110 .num_thread_per_eu
= 5,
111 .max_vs_threads
= 32,
113 .max_wm_threads
= 10 * 5,
117 .timestamp_frequency
= 12500000,
121 static const struct gen_device_info gen_device_info_ilk
= {
125 .has_surface_tile_offset
= true,
127 .num_subslices
= { 1, },
128 .num_eu_per_subslice
= 12,
129 .num_thread_per_eu
= 6,
130 .max_vs_threads
= 72,
131 .max_gs_threads
= 32,
132 .max_wm_threads
= 12 * 6,
136 .timestamp_frequency
= 12500000,
140 static const struct gen_device_info gen_device_info_snb_gt1
= {
143 .has_hiz_and_separate_stencil
= true,
146 .has_surface_tile_offset
= true,
147 .needs_unlit_centroid_workaround
= true,
149 .num_subslices
= { 1, },
150 .num_eu_per_subslice
= 6,
151 .num_thread_per_eu
= 6, /* Not confirmed */
152 .max_vs_threads
= 24,
153 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
154 .max_wm_threads
= 40,
158 [MESA_SHADER_VERTEX
] = 24,
161 [MESA_SHADER_VERTEX
] = 256,
162 [MESA_SHADER_GEOMETRY
] = 256,
165 .timestamp_frequency
= 12500000,
169 static const struct gen_device_info gen_device_info_snb_gt2
= {
172 .has_hiz_and_separate_stencil
= true,
175 .has_surface_tile_offset
= true,
176 .needs_unlit_centroid_workaround
= true,
178 .num_subslices
= { 1, },
179 .num_eu_per_subslice
= 12,
180 .num_thread_per_eu
= 6, /* Not confirmed */
181 .max_vs_threads
= 60,
182 .max_gs_threads
= 60,
183 .max_wm_threads
= 80,
187 [MESA_SHADER_VERTEX
] = 24,
190 [MESA_SHADER_VERTEX
] = 256,
191 [MESA_SHADER_GEOMETRY
] = 256,
194 .timestamp_frequency
= 12500000,
198 #define GEN7_FEATURES \
200 .has_hiz_and_separate_stencil = true, \
201 .must_use_separate_stencil = true, \
204 .has_64bit_float = true, \
205 .has_surface_tile_offset = true, \
206 .timestamp_frequency = 12500000
208 static const struct gen_device_info gen_device_info_ivb_gt1
= {
209 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
211 .num_subslices
= { 1, },
212 .num_eu_per_subslice
= 6,
213 .num_thread_per_eu
= 6,
215 .max_vs_threads
= 36,
216 .max_tcs_threads
= 36,
217 .max_tes_threads
= 36,
218 .max_gs_threads
= 36,
219 .max_wm_threads
= 48,
220 .max_cs_threads
= 36,
223 [MESA_SHADER_VERTEX
] = 32,
224 [MESA_SHADER_TESS_EVAL
] = 10,
227 [MESA_SHADER_VERTEX
] = 512,
228 [MESA_SHADER_TESS_CTRL
] = 32,
229 [MESA_SHADER_TESS_EVAL
] = 288,
230 [MESA_SHADER_GEOMETRY
] = 192,
236 static const struct gen_device_info gen_device_info_ivb_gt2
= {
237 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
239 .num_subslices
= { 1, },
240 .num_eu_per_subslice
= 12,
241 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
242 * @max_wm_threads ... */
244 .max_vs_threads
= 128,
245 .max_tcs_threads
= 128,
246 .max_tes_threads
= 128,
247 .max_gs_threads
= 128,
248 .max_wm_threads
= 172,
249 .max_cs_threads
= 64,
252 [MESA_SHADER_VERTEX
] = 32,
253 [MESA_SHADER_TESS_EVAL
] = 10,
256 [MESA_SHADER_VERTEX
] = 704,
257 [MESA_SHADER_TESS_CTRL
] = 64,
258 [MESA_SHADER_TESS_EVAL
] = 448,
259 [MESA_SHADER_GEOMETRY
] = 320,
265 static const struct gen_device_info gen_device_info_byt
= {
266 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
268 .num_subslices
= { 1, },
269 .num_eu_per_subslice
= 4,
270 .num_thread_per_eu
= 8,
273 .max_vs_threads
= 36,
274 .max_tcs_threads
= 36,
275 .max_tes_threads
= 36,
276 .max_gs_threads
= 36,
277 .max_wm_threads
= 48,
278 .max_cs_threads
= 32,
281 [MESA_SHADER_VERTEX
] = 32,
282 [MESA_SHADER_TESS_EVAL
] = 10,
285 [MESA_SHADER_VERTEX
] = 512,
286 [MESA_SHADER_TESS_CTRL
] = 32,
287 [MESA_SHADER_TESS_EVAL
] = 288,
288 [MESA_SHADER_GEOMETRY
] = 192,
294 #define HSW_FEATURES \
296 .is_haswell = true, \
297 .supports_simd16_3src = true, \
298 .has_resource_streamer = true
300 static const struct gen_device_info gen_device_info_hsw_gt1
= {
301 HSW_FEATURES
, .gt
= 1,
303 .num_subslices
= { 1, },
304 .num_eu_per_subslice
= 10,
305 .num_thread_per_eu
= 7,
307 .max_vs_threads
= 70,
308 .max_tcs_threads
= 70,
309 .max_tes_threads
= 70,
310 .max_gs_threads
= 70,
311 .max_wm_threads
= 102,
312 .max_cs_threads
= 70,
315 [MESA_SHADER_VERTEX
] = 32,
316 [MESA_SHADER_TESS_EVAL
] = 10,
319 [MESA_SHADER_VERTEX
] = 640,
320 [MESA_SHADER_TESS_CTRL
] = 64,
321 [MESA_SHADER_TESS_EVAL
] = 384,
322 [MESA_SHADER_GEOMETRY
] = 256,
328 static const struct gen_device_info gen_device_info_hsw_gt2
= {
329 HSW_FEATURES
, .gt
= 2,
331 .num_subslices
= { 2, },
332 .num_eu_per_subslice
= 10,
333 .num_thread_per_eu
= 7,
335 .max_vs_threads
= 280,
336 .max_tcs_threads
= 256,
337 .max_tes_threads
= 280,
338 .max_gs_threads
= 256,
339 .max_wm_threads
= 204,
340 .max_cs_threads
= 70,
343 [MESA_SHADER_VERTEX
] = 64,
344 [MESA_SHADER_TESS_EVAL
] = 10,
347 [MESA_SHADER_VERTEX
] = 1664,
348 [MESA_SHADER_TESS_CTRL
] = 128,
349 [MESA_SHADER_TESS_EVAL
] = 960,
350 [MESA_SHADER_GEOMETRY
] = 640,
356 static const struct gen_device_info gen_device_info_hsw_gt3
= {
357 HSW_FEATURES
, .gt
= 3,
359 .num_subslices
= { 2, },
360 .num_eu_per_subslice
= 10,
361 .num_thread_per_eu
= 7,
363 .max_vs_threads
= 280,
364 .max_tcs_threads
= 256,
365 .max_tes_threads
= 280,
366 .max_gs_threads
= 256,
367 .max_wm_threads
= 408,
368 .max_cs_threads
= 70,
371 [MESA_SHADER_VERTEX
] = 64,
372 [MESA_SHADER_TESS_EVAL
] = 10,
375 [MESA_SHADER_VERTEX
] = 1664,
376 [MESA_SHADER_TESS_CTRL
] = 128,
377 [MESA_SHADER_TESS_EVAL
] = 960,
378 [MESA_SHADER_GEOMETRY
] = 640,
384 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
385 * so keep things conservative for now and set has_sample_with_hiz = false.
387 #define GEN8_FEATURES \
389 .has_hiz_and_separate_stencil = true, \
390 .has_resource_streamer = true, \
391 .must_use_separate_stencil = true, \
393 .has_sample_with_hiz = false, \
395 .has_integer_dword_mul = true, \
396 .has_64bit_float = true, \
397 .has_64bit_int = true, \
398 .supports_simd16_3src = true, \
399 .has_surface_tile_offset = true, \
400 .num_thread_per_eu = 7, \
401 .max_vs_threads = 504, \
402 .max_tcs_threads = 504, \
403 .max_tes_threads = 504, \
404 .max_gs_threads = 504, \
405 .max_wm_threads = 384, \
406 .timestamp_frequency = 12500000
408 static const struct gen_device_info gen_device_info_bdw_gt1
= {
409 GEN8_FEATURES
, .gt
= 1,
410 .is_broadwell
= true,
412 .num_subslices
= { 2, },
413 .num_eu_per_subslice
= 6,
415 .max_cs_threads
= 42,
418 [MESA_SHADER_VERTEX
] = 64,
419 [MESA_SHADER_TESS_EVAL
] = 34,
422 [MESA_SHADER_VERTEX
] = 2560,
423 [MESA_SHADER_TESS_CTRL
] = 504,
424 [MESA_SHADER_TESS_EVAL
] = 1536,
425 /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */
426 [MESA_SHADER_GEOMETRY
] = 690,
432 static const struct gen_device_info gen_device_info_bdw_gt2
= {
433 GEN8_FEATURES
, .gt
= 2,
434 .is_broadwell
= true,
436 .num_subslices
= { 3, },
437 .num_eu_per_subslice
= 8,
439 .max_cs_threads
= 56,
442 [MESA_SHADER_VERTEX
] = 64,
443 [MESA_SHADER_TESS_EVAL
] = 34,
446 [MESA_SHADER_VERTEX
] = 2560,
447 [MESA_SHADER_TESS_CTRL
] = 504,
448 [MESA_SHADER_TESS_EVAL
] = 1536,
449 [MESA_SHADER_GEOMETRY
] = 960,
455 static const struct gen_device_info gen_device_info_bdw_gt3
= {
456 GEN8_FEATURES
, .gt
= 3,
457 .is_broadwell
= true,
459 .num_subslices
= { 3, 3, },
460 .num_eu_per_subslice
= 8,
462 .max_cs_threads
= 56,
465 [MESA_SHADER_VERTEX
] = 64,
466 [MESA_SHADER_TESS_EVAL
] = 34,
469 [MESA_SHADER_VERTEX
] = 2560,
470 [MESA_SHADER_TESS_CTRL
] = 504,
471 [MESA_SHADER_TESS_EVAL
] = 1536,
472 [MESA_SHADER_GEOMETRY
] = 960,
478 static const struct gen_device_info gen_device_info_chv
= {
479 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
481 .has_integer_dword_mul
= false,
483 .num_subslices
= { 2, },
484 .num_eu_per_subslice
= 8,
486 .max_vs_threads
= 80,
487 .max_tcs_threads
= 80,
488 .max_tes_threads
= 80,
489 .max_gs_threads
= 80,
490 .max_wm_threads
= 128,
491 .max_cs_threads
= 6 * 7,
494 [MESA_SHADER_VERTEX
] = 34,
495 [MESA_SHADER_TESS_EVAL
] = 34,
498 [MESA_SHADER_VERTEX
] = 640,
499 [MESA_SHADER_TESS_CTRL
] = 80,
500 [MESA_SHADER_TESS_EVAL
] = 384,
501 [MESA_SHADER_GEOMETRY
] = 256,
507 #define GEN9_HW_INFO \
509 .max_vs_threads = 336, \
510 .max_gs_threads = 336, \
511 .max_tcs_threads = 336, \
512 .max_tes_threads = 336, \
513 .max_cs_threads = 56, \
514 .timestamp_frequency = 12000000, \
517 [MESA_SHADER_VERTEX] = 64, \
518 [MESA_SHADER_TESS_EVAL] = 34, \
521 [MESA_SHADER_VERTEX] = 1856, \
522 [MESA_SHADER_TESS_CTRL] = 672, \
523 [MESA_SHADER_TESS_EVAL] = 1120, \
524 [MESA_SHADER_GEOMETRY] = 640, \
528 #define GEN9_LP_FEATURES \
531 .has_integer_dword_mul = false, \
534 .has_sample_with_hiz = true, \
536 .num_thread_per_eu = 6, \
537 .max_vs_threads = 112, \
538 .max_tcs_threads = 112, \
539 .max_tes_threads = 112, \
540 .max_gs_threads = 112, \
541 .max_cs_threads = 6 * 6, \
542 .timestamp_frequency = 19200000, \
545 [MESA_SHADER_VERTEX] = 34, \
546 [MESA_SHADER_TESS_EVAL] = 34, \
549 [MESA_SHADER_VERTEX] = 704, \
550 [MESA_SHADER_TESS_CTRL] = 256, \
551 [MESA_SHADER_TESS_EVAL] = 416, \
552 [MESA_SHADER_GEOMETRY] = 256, \
556 #define GEN9_LP_FEATURES_3X6 \
558 .num_subslices = { 3, }, \
559 .num_eu_per_subslice = 6
561 #define GEN9_LP_FEATURES_2X6 \
563 .num_subslices = { 2, }, \
564 .num_eu_per_subslice = 6, \
565 .max_vs_threads = 56, \
566 .max_tcs_threads = 56, \
567 .max_tes_threads = 56, \
568 .max_gs_threads = 56, \
569 .max_cs_threads = 6 * 6, \
572 [MESA_SHADER_VERTEX] = 34, \
573 [MESA_SHADER_TESS_EVAL] = 34, \
576 [MESA_SHADER_VERTEX] = 352, \
577 [MESA_SHADER_TESS_CTRL] = 128, \
578 [MESA_SHADER_TESS_EVAL] = 208, \
579 [MESA_SHADER_GEOMETRY] = 128, \
583 #define GEN9_FEATURES \
586 .has_sample_with_hiz = true
588 static const struct gen_device_info gen_device_info_skl_gt1
= {
589 GEN9_FEATURES
, .gt
= 1,
592 .num_subslices
= { 2, },
593 .num_eu_per_subslice
= 6,
595 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
596 * leading to some vertices to go missing if we use too much URB.
598 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
602 static const struct gen_device_info gen_device_info_skl_gt2
= {
603 GEN9_FEATURES
, .gt
= 2,
606 .num_subslices
= { 3, },
607 .num_eu_per_subslice
= 8,
612 static const struct gen_device_info gen_device_info_skl_gt3
= {
613 GEN9_FEATURES
, .gt
= 3,
616 .num_subslices
= { 3, 3, },
617 .num_eu_per_subslice
= 8,
622 static const struct gen_device_info gen_device_info_skl_gt4
= {
623 GEN9_FEATURES
, .gt
= 4,
626 .num_subslices
= { 3, 3, 3, },
627 .num_eu_per_subslice
= 8,
629 /* From the "L3 Allocation and Programming" documentation:
631 * "URB is limited to 1008KB due to programming restrictions. This is not a
632 * restriction of the L3 implementation, but of the FF and other clients.
633 * Therefore, in a GT4 implementation it is possible for the programmed
634 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
635 * only 1008KB of this will be used."
640 static const struct gen_device_info gen_device_info_bxt
= {
641 GEN9_LP_FEATURES_3X6
,
647 static const struct gen_device_info gen_device_info_bxt_2x6
= {
648 GEN9_LP_FEATURES_2X6
,
654 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
655 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
658 static const struct gen_device_info gen_device_info_kbl_gt1
= {
663 .max_cs_threads
= 7 * 6,
665 .num_subslices
= { 2, },
666 .num_eu_per_subslice
= 6,
668 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
669 * leading to some vertices to go missing if we use too much URB.
671 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
675 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
680 .max_cs_threads
= 7 * 6,
682 .num_subslices
= { 3, },
683 .num_eu_per_subslice
= 6,
688 static const struct gen_device_info gen_device_info_kbl_gt2
= {
694 .num_subslices
= { 3, },
695 .num_eu_per_subslice
= 8,
700 static const struct gen_device_info gen_device_info_kbl_gt3
= {
706 .num_subslices
= { 3, 3, },
707 .num_eu_per_subslice
= 8,
712 static const struct gen_device_info gen_device_info_kbl_gt4
= {
718 * From the "L3 Allocation and Programming" documentation:
720 * "URB is limited to 1008KB due to programming restrictions. This
721 * is not a restriction of the L3 implementation, but of the FF and
722 * other clients. Therefore, in a GT4 implementation it is
723 * possible for the programmed allocation of the L3 data array to
724 * provide 3*384KB=1152KB for URB, but only 1008KB of this
728 .num_subslices
= { 3, 3, 3, },
729 .num_eu_per_subslice
= 8,
734 static const struct gen_device_info gen_device_info_glk
= {
735 GEN9_LP_FEATURES_3X6
,
736 .is_geminilake
= true,
741 static const struct gen_device_info gen_device_info_glk_2x6
= {
742 GEN9_LP_FEATURES_2X6
,
743 .is_geminilake
= true,
748 static const struct gen_device_info gen_device_info_cfl_gt1
= {
750 .is_coffeelake
= true,
754 .num_subslices
= { 2, },
755 .num_eu_per_subslice
= 6,
757 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
758 * leading to some vertices to go missing if we use too much URB.
760 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
763 static const struct gen_device_info gen_device_info_cfl_gt2
= {
765 .is_coffeelake
= true,
769 .num_subslices
= { 3, },
770 .num_eu_per_subslice
= 8,
775 static const struct gen_device_info gen_device_info_cfl_gt3
= {
777 .is_coffeelake
= true,
781 .num_subslices
= { 3, 3, },
782 .num_eu_per_subslice
= 8,
787 #define GEN10_HW_INFO \
789 .num_thread_per_eu = 7, \
790 .max_vs_threads = 728, \
791 .max_gs_threads = 432, \
792 .max_tcs_threads = 432, \
793 .max_tes_threads = 624, \
794 .max_cs_threads = 56, \
795 .timestamp_frequency = 19200000, \
798 [MESA_SHADER_VERTEX] = 64, \
799 [MESA_SHADER_TESS_EVAL] = 34, \
802 [MESA_SHADER_VERTEX] = 3936, \
803 [MESA_SHADER_TESS_CTRL] = 896, \
804 [MESA_SHADER_TESS_EVAL] = 2064, \
805 [MESA_SHADER_GEOMETRY] = 832, \
809 #define subslices(args...) { args, }
811 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
814 .has_sample_with_hiz = true, \
816 .num_slices = _slices, \
817 .num_subslices = _subslices, \
818 .num_eu_per_subslice = 8, \
821 static const struct gen_device_info gen_device_info_cnl_gt0_5
= {
823 GEN10_FEATURES(1, 1, subslices(2), 2),
824 .is_cannonlake
= true,
828 static const struct gen_device_info gen_device_info_cnl_gt1
= {
830 GEN10_FEATURES(1, 1, subslices(3), 3),
831 .is_cannonlake
= true,
835 static const struct gen_device_info gen_device_info_cnl_gt1_5
= {
837 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
838 .is_cannonlake
= true,
842 static const struct gen_device_info gen_device_info_cnl_gt2
= {
844 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
845 .is_cannonlake
= true,
849 #define GEN11_HW_INFO \
852 .max_vs_threads = 364, \
853 .max_gs_threads = 224, \
854 .max_tcs_threads = 224, \
855 .max_tes_threads = 364, \
858 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
861 .has_64bit_float = false, \
862 .has_64bit_int = false, \
863 .has_integer_dword_mul = false, \
864 .has_sample_with_hiz = false, \
865 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
866 .num_subslices = _subslices, \
867 .num_eu_per_subslice = 8
869 #define GEN11_URB_MIN_MAX_ENTRIES \
871 [MESA_SHADER_VERTEX] = 64, \
872 [MESA_SHADER_TESS_EVAL] = 34, \
875 [MESA_SHADER_VERTEX] = 2384, \
876 [MESA_SHADER_TESS_CTRL] = 1032, \
877 [MESA_SHADER_TESS_EVAL] = 2384, \
878 [MESA_SHADER_GEOMETRY] = 1032, \
881 static const struct gen_device_info gen_device_info_icl_gt2
= {
882 GEN11_FEATURES(2, 1, subslices(8), 8),
884 GEN11_URB_MIN_MAX_ENTRIES
,
889 static const struct gen_device_info gen_device_info_icl_gt1_5
= {
890 GEN11_FEATURES(1, 1, subslices(6), 6),
892 GEN11_URB_MIN_MAX_ENTRIES
,
897 static const struct gen_device_info gen_device_info_icl_gt1
= {
898 GEN11_FEATURES(1, 1, subslices(4), 6),
900 GEN11_URB_MIN_MAX_ENTRIES
,
905 static const struct gen_device_info gen_device_info_icl_gt0_5
= {
906 GEN11_FEATURES(1, 1, subslices(1), 6),
908 GEN11_URB_MIN_MAX_ENTRIES
,
913 #define GEN11_LP_FEATURES \
914 .is_elkhartlake = true, \
916 GEN11_URB_MIN_MAX_ENTRIES, \
918 .disable_ccs_repack = true, \
921 static const struct gen_device_info gen_device_info_ehl_4x8
= {
922 GEN11_FEATURES(1, 1, subslices(4), 4),
926 static const struct gen_device_info gen_device_info_ehl_4x6
= {
927 GEN11_FEATURES(1, 1, subslices(4), 4),
929 .num_eu_per_subslice
= 6,
932 static const struct gen_device_info gen_device_info_ehl_4x5
= {
933 GEN11_FEATURES(1, 1, subslices(4), 4),
935 .num_eu_per_subslice
= 5,
938 static const struct gen_device_info gen_device_info_ehl_4x4
= {
939 GEN11_FEATURES(1, 1, subslices(4), 4),
941 .num_eu_per_subslice
= 4,
944 static const struct gen_device_info gen_device_info_ehl_2x8
= {
945 GEN11_FEATURES(1, 1, subslices(2), 4),
949 static const struct gen_device_info gen_device_info_ehl_2x4
= {
950 GEN11_FEATURES(1, 1, subslices(2), 4),
952 .num_eu_per_subslice
=4,
955 #define GEN12_URB_MIN_MAX_ENTRIES \
957 [MESA_SHADER_VERTEX] = 64, \
958 [MESA_SHADER_TESS_EVAL] = 34, \
961 [MESA_SHADER_VERTEX] = 3576, \
962 [MESA_SHADER_TESS_CTRL] = 1548, \
963 [MESA_SHADER_TESS_EVAL] = 3576, \
964 [MESA_SHADER_GEOMETRY] = 1548, \
967 #define GEN12_HW_INFO \
970 .has_sample_with_hiz = false, \
971 .has_aux_map = true, \
972 .max_vs_threads = 546, \
973 .max_gs_threads = 336, \
974 .max_tcs_threads = 336, \
975 .max_tes_threads = 546, \
976 .max_cs_threads = 112, /* threads per DSS */ \
978 GEN12_URB_MIN_MAX_ENTRIES, \
981 #define GEN12_FEATURES(_gt, _slices, _l3) \
984 .has_64bit_float = false, \
985 .has_64bit_int = false, \
986 .has_integer_dword_mul = false, \
987 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
988 .simulator_id = 22, \
989 .num_eu_per_subslice = 16
991 #define dual_subslices(args...) { args, }
993 #define GEN12_GT05_FEATURES \
994 GEN12_FEATURES(1, 1, 4), \
995 .num_subslices = dual_subslices(1)
997 #define GEN12_GT_FEATURES(_gt) \
998 GEN12_FEATURES(_gt, 1, _gt == 1 ? 4 : 8), \
999 .num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
1001 static const struct gen_device_info gen_device_info_tgl_gt1
= {
1002 GEN12_GT_FEATURES(1),
1005 static const struct gen_device_info gen_device_info_tgl_gt2
= {
1006 GEN12_GT_FEATURES(2),
1009 static const struct gen_device_info gen_device_info_rkl_gt05
= {
1010 GEN12_GT05_FEATURES
,
1013 static const struct gen_device_info gen_device_info_rkl_gt1
= {
1014 GEN12_GT_FEATURES(1),
1017 #define GEN12_DG1_FEATURES \
1018 GEN12_GT_FEATURES(2), \
1024 UNUSED
static const struct gen_device_info gen_device_info_dg1
= {
1029 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1034 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1035 subslice
* devinfo
->eu_subslice_stride
;
1037 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1038 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1039 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1043 /* Generate slice/subslice/eu masks from number of
1044 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1047 * These can be overridden with values reported by the kernel either from
1048 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1049 * through the i915 query uapi.
1052 fill_masks(struct gen_device_info
*devinfo
)
1054 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1056 /* Subslice masks */
1057 unsigned max_subslices
= 0;
1058 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1059 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1060 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1062 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1063 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1064 (1U << devinfo
->num_subslices
[s
]) - 1;
1068 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1069 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1071 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1072 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1073 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1074 (1U << devinfo
->num_eu_per_subslice
) - 1);
1080 reset_masks(struct gen_device_info
*devinfo
)
1082 devinfo
->subslice_slice_stride
= 0;
1083 devinfo
->eu_subslice_stride
= 0;
1084 devinfo
->eu_slice_stride
= 0;
1086 devinfo
->num_slices
= 0;
1087 devinfo
->num_eu_per_subslice
= 0;
1088 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1090 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1091 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1092 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1093 memset(devinfo
->ppipe_subslices
, 0, sizeof(devinfo
->ppipe_subslices
));
1097 update_from_topology(struct gen_device_info
*devinfo
,
1098 const struct drm_i915_query_topology_info
*topology
)
1100 reset_masks(devinfo
);
1102 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1104 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1105 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1107 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1108 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1109 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1111 uint32_t subslice_mask_len
=
1112 topology
->max_slices
* topology
->subslice_stride
;
1113 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1114 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1117 uint32_t n_subslices
= 0;
1118 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1119 if ((devinfo
->slice_masks
& (1 << s
)) == 0)
1122 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1123 devinfo
->num_subslices
[s
] +=
1124 __builtin_popcount(devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
+ b
]);
1126 n_subslices
+= devinfo
->num_subslices
[s
];
1128 assert(n_subslices
> 0);
1130 if (devinfo
->gen
== 11) {
1131 /* On ICL we only have one slice */
1132 assert(devinfo
->slice_masks
== 1);
1134 /* Count the number of subslices on each pixel pipe. Assume that
1135 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1137 unsigned subslices
= devinfo
->subslice_masks
[0];
1139 while (subslices
> 0) {
1141 devinfo
->ppipe_subslices
[ss
>= 4 ? 1 : 0] += 1;
1147 if (devinfo
->gen
== 12 && devinfo
->num_slices
== 1) {
1148 if (n_subslices
>= 6) {
1149 assert(n_subslices
== 6);
1150 devinfo
->l3_banks
= 8;
1151 } else if (n_subslices
> 2) {
1152 devinfo
->l3_banks
= 6;
1154 devinfo
->l3_banks
= 4;
1158 uint32_t eu_mask_len
=
1159 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1160 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1161 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1164 for (int b
= 0; b
< eu_mask_len
; b
++)
1165 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1167 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1171 update_from_masks(struct gen_device_info
*devinfo
, uint32_t slice_mask
,
1172 uint32_t subslice_mask
, uint32_t n_eus
)
1174 struct drm_i915_query_topology_info
*topology
;
1176 assert((slice_mask
& 0xff) == slice_mask
);
1178 size_t data_length
= 100;
1180 topology
= calloc(1, sizeof(*topology
) + data_length
);
1184 topology
->max_slices
= util_last_bit(slice_mask
);
1185 topology
->max_subslices
= util_last_bit(subslice_mask
);
1187 topology
->subslice_offset
= DIV_ROUND_UP(topology
->max_slices
, 8);
1188 topology
->subslice_stride
= DIV_ROUND_UP(topology
->max_subslices
, 8);
1190 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1191 __builtin_popcount(subslice_mask
);
1192 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1193 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1195 topology
->eu_offset
= topology
->subslice_offset
+
1196 DIV_ROUND_UP(topology
->max_subslices
, 8);
1197 topology
->eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1199 /* Set slice mask in topology */
1200 for (int b
= 0; b
< topology
->subslice_offset
; b
++)
1201 topology
->data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1203 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1205 /* Set subslice mask in topology */
1206 for (int b
= 0; b
< topology
->subslice_stride
; b
++) {
1207 int subslice_offset
= topology
->subslice_offset
+
1208 s
* topology
->subslice_stride
+ b
;
1210 topology
->data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1213 /* Set eu mask in topology */
1214 for (int ss
= 0; ss
< topology
->max_subslices
; ss
++) {
1215 for (int b
= 0; b
< topology
->eu_stride
; b
++) {
1216 int eu_offset
= topology
->eu_offset
+
1217 (s
* topology
->max_subslices
+ ss
) * topology
->eu_stride
+ b
;
1219 topology
->data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1224 update_from_topology(devinfo
, topology
);
1231 getparam(int fd
, uint32_t param
, int *value
)
1235 struct drm_i915_getparam gp
= {
1240 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
1249 gen_get_device_info_from_pci_id(int pci_id
,
1250 struct gen_device_info
*devinfo
)
1254 #define CHIPSET(id, family, fam_str, name) \
1255 case id: *devinfo = gen_device_info_##family; break;
1256 #include "pci_ids/i965_pci_ids.h"
1257 #include "pci_ids/iris_pci_ids.h"
1259 fprintf(stderr
, "Driver does not support the 0x%x PCI ID.\n", pci_id
);
1263 fill_masks(devinfo
);
1265 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1267 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1268 * allocate scratch space enough so that each slice has 4 slices allowed."
1270 * The equivalent internal documentation says that this programming note
1271 * applies to all Gen9+ platforms.
1273 * The hardware typically calculates the scratch space pointer by taking
1274 * the base address, and adding per-thread-scratch-space * thread ID.
1275 * Extra padding can be necessary depending how the thread IDs are
1276 * calculated for a particular shader stage.
1279 switch(devinfo
->gen
) {
1282 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1283 * devinfo
->num_slices
1284 * 4; /* effective subslices per slice */
1288 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1289 * devinfo
->num_slices
1290 * 8; /* subslices per slice */
1293 assert(devinfo
->gen
< 9);
1297 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1299 devinfo
->chipset_id
= pci_id
;
1304 gen_get_device_name(int devid
)
1308 #define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break;
1309 #include "pci_ids/i965_pci_ids.h"
1310 #include "pci_ids/iris_pci_ids.h"
1317 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1321 getparam_topology(struct gen_device_info
*devinfo
, int fd
)
1324 if (!getparam(fd
, I915_PARAM_SLICE_MASK
, &slice_mask
))
1328 if (!getparam(fd
, I915_PARAM_EU_TOTAL
, &n_eus
))
1331 int subslice_mask
= 0;
1332 if (!getparam(fd
, I915_PARAM_SUBSLICE_MASK
, &subslice_mask
))
1335 return update_from_masks(devinfo
, slice_mask
, subslice_mask
, n_eus
);
1339 * preferred API for updating the topology in devinfo (kernel 4.17+)
1342 query_topology(struct gen_device_info
*devinfo
, int fd
)
1344 struct drm_i915_query_item item
= {
1345 .query_id
= DRM_I915_QUERY_TOPOLOGY_INFO
,
1347 struct drm_i915_query query
= {
1349 .items_ptr
= (uintptr_t) &item
,
1352 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
))
1355 if (item
.length
< 0)
1358 struct drm_i915_query_topology_info
*topo_info
=
1359 (struct drm_i915_query_topology_info
*) calloc(1, item
.length
);
1360 item
.data_ptr
= (uintptr_t) topo_info
;
1362 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
) ||
1366 update_from_topology(devinfo
, topo_info
);
1375 gen_get_aperture_size(int fd
, uint64_t *size
)
1377 struct drm_i915_gem_get_aperture aperture
= { 0 };
1379 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
);
1380 if (ret
== 0 && size
)
1381 *size
= aperture
.aper_size
;
1387 gen_has_get_tiling(int fd
)
1391 struct drm_i915_gem_create gem_create
= {
1395 if (gen_ioctl(fd
, DRM_IOCTL_I915_GEM_CREATE
, &gem_create
)) {
1396 unreachable("Failed to create GEM BO");
1400 struct drm_i915_gem_get_tiling get_tiling
= {
1401 .handle
= gem_create
.handle
,
1403 ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &get_tiling
);
1405 struct drm_gem_close close
= {
1406 .handle
= gem_create
.handle
,
1408 gen_ioctl(fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
1414 gen_get_device_info_from_fd(int fd
, struct gen_device_info
*devinfo
)
1418 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
1419 if (devid_override
&& strlen(devid_override
) > 0) {
1420 if (geteuid() == getuid()) {
1421 devid
= gen_device_name_to_pci_device_id(devid_override
);
1422 /* Fallback to PCI ID. */
1424 devid
= strtol(devid_override
, NULL
, 0);
1426 fprintf(stderr
, "Invalid INTEL_DEVID_OVERRIDE=\"%s\". "
1427 "Use a valid numeric PCI ID or one of the supported "
1428 "platform names: %s", devid_override
, name_map
[0].name
);
1429 for (unsigned i
= 1; i
< ARRAY_SIZE(name_map
); i
++)
1430 fprintf(stderr
, ", %s", name_map
[i
].name
);
1431 fprintf(stderr
, "\n");
1435 fprintf(stderr
, "Ignoring INTEL_DEVID_OVERRIDE=\"%s\" because "
1436 "real and effective user ID don't match.\n", devid_override
);
1441 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1443 devinfo
->no_hw
= true;
1445 /* query the device id */
1446 if (!getparam(fd
, I915_PARAM_CHIPSET_ID
, &devid
))
1448 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1450 devinfo
->no_hw
= false;
1453 /* remaining initializion queries the kernel for device info */
1457 int timestamp_frequency
;
1458 if (getparam(fd
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1459 ×tamp_frequency
))
1460 devinfo
->timestamp_frequency
= timestamp_frequency
;
1461 else if (devinfo
->gen
>= 10)
1462 /* gen10 and later requires the timestamp_frequency to be updated */
1465 if (!getparam(fd
, I915_PARAM_REVISION
, &devinfo
->revision
))
1466 devinfo
->revision
= 0;
1468 if (!query_topology(devinfo
, fd
)) {
1469 if (devinfo
->gen
>= 10) {
1470 /* topology uAPI required for CNL+ (kernel 4.17+) */
1474 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1475 * will be wrong, affecting GPU metrics. In this case, fail silently.
1477 getparam_topology(devinfo
, fd
);
1480 gen_get_aperture_size(fd
, &devinfo
->aperture_bytes
);
1481 devinfo
->has_tiling_uapi
= gen_has_get_tiling(fd
);