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intel: Introducing Amber Lake platform
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include <unistd.h>
29 #include "gen_device_info.h"
30 #include "compiler/shader_enums.h"
31 #include "util/bitscan.h"
32 #include "util/macros.h"
33
34 #include <i915_drm.h>
35
36 /**
37 * Get the PCI ID for the device name.
38 *
39 * Returns -1 if the device is not known.
40 */
41 int
42 gen_device_name_to_pci_device_id(const char *name)
43 {
44 static const struct {
45 const char *name;
46 int pci_id;
47 } name_map[] = {
48 { "brw", 0x2a02 },
49 { "g4x", 0x2a42 },
50 { "ilk", 0x0042 },
51 { "snb", 0x0126 },
52 { "ivb", 0x016a },
53 { "hsw", 0x0d2e },
54 { "byt", 0x0f33 },
55 { "bdw", 0x162e },
56 { "chv", 0x22B3 },
57 { "skl", 0x1912 },
58 { "bxt", 0x5A85 },
59 { "kbl", 0x5912 },
60 { "aml", 0x591C },
61 { "glk", 0x3185 },
62 { "cfl", 0x3E9B },
63 { "cnl", 0x5a52 },
64 { "icl", 0x8a52 },
65 };
66
67 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
68 if (!strcmp(name_map[i].name, name))
69 return name_map[i].pci_id;
70 }
71
72 return -1;
73 }
74
75 /**
76 * Get the overridden PCI ID for the device. This is set with the
77 * INTEL_DEVID_OVERRIDE environment variable.
78 *
79 * Returns -1 if the override is not set.
80 */
81 int
82 gen_get_pci_device_id_override(void)
83 {
84 if (geteuid() == getuid()) {
85 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
86 if (devid_override) {
87 const int id = gen_device_name_to_pci_device_id(devid_override);
88 return id >= 0 ? id : strtol(devid_override, NULL, 0);
89 }
90 }
91
92 return -1;
93 }
94
95 static const struct gen_device_info gen_device_info_i965 = {
96 .gen = 4,
97 .has_negative_rhw_bug = true,
98 .num_slices = 1,
99 .num_subslices = { 1, },
100 .num_eu_per_subslice = 8,
101 .num_thread_per_eu = 4,
102 .max_vs_threads = 16,
103 .max_gs_threads = 2,
104 .max_wm_threads = 8 * 4,
105 .urb = {
106 .size = 256,
107 },
108 .timestamp_frequency = 12500000,
109 .simulator_id = -1,
110 };
111
112 static const struct gen_device_info gen_device_info_g4x = {
113 .gen = 4,
114 .has_pln = true,
115 .has_compr4 = true,
116 .has_surface_tile_offset = true,
117 .is_g4x = true,
118 .num_slices = 1,
119 .num_subslices = { 1, },
120 .num_eu_per_subslice = 10,
121 .num_thread_per_eu = 5,
122 .max_vs_threads = 32,
123 .max_gs_threads = 2,
124 .max_wm_threads = 10 * 5,
125 .urb = {
126 .size = 384,
127 },
128 .timestamp_frequency = 12500000,
129 .simulator_id = -1,
130 };
131
132 static const struct gen_device_info gen_device_info_ilk = {
133 .gen = 5,
134 .has_pln = true,
135 .has_compr4 = true,
136 .has_surface_tile_offset = true,
137 .num_slices = 1,
138 .num_subslices = { 1, },
139 .num_eu_per_subslice = 12,
140 .num_thread_per_eu = 6,
141 .max_vs_threads = 72,
142 .max_gs_threads = 32,
143 .max_wm_threads = 12 * 6,
144 .urb = {
145 .size = 1024,
146 },
147 .timestamp_frequency = 12500000,
148 .simulator_id = -1,
149 };
150
151 static const struct gen_device_info gen_device_info_snb_gt1 = {
152 .gen = 6,
153 .gt = 1,
154 .has_hiz_and_separate_stencil = true,
155 .has_llc = true,
156 .has_pln = true,
157 .has_surface_tile_offset = true,
158 .needs_unlit_centroid_workaround = true,
159 .num_slices = 1,
160 .num_subslices = { 1, },
161 .num_eu_per_subslice = 6,
162 .num_thread_per_eu = 6, /* Not confirmed */
163 .max_vs_threads = 24,
164 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
165 .max_wm_threads = 40,
166 .urb = {
167 .size = 32,
168 .min_entries = {
169 [MESA_SHADER_VERTEX] = 24,
170 },
171 .max_entries = {
172 [MESA_SHADER_VERTEX] = 256,
173 [MESA_SHADER_GEOMETRY] = 256,
174 },
175 },
176 .timestamp_frequency = 12500000,
177 .simulator_id = -1,
178 };
179
180 static const struct gen_device_info gen_device_info_snb_gt2 = {
181 .gen = 6,
182 .gt = 2,
183 .has_hiz_and_separate_stencil = true,
184 .has_llc = true,
185 .has_pln = true,
186 .has_surface_tile_offset = true,
187 .needs_unlit_centroid_workaround = true,
188 .num_slices = 1,
189 .num_subslices = { 1, },
190 .num_eu_per_subslice = 12,
191 .num_thread_per_eu = 6, /* Not confirmed */
192 .max_vs_threads = 60,
193 .max_gs_threads = 60,
194 .max_wm_threads = 80,
195 .urb = {
196 .size = 64,
197 .min_entries = {
198 [MESA_SHADER_VERTEX] = 24,
199 },
200 .max_entries = {
201 [MESA_SHADER_VERTEX] = 256,
202 [MESA_SHADER_GEOMETRY] = 256,
203 },
204 },
205 .timestamp_frequency = 12500000,
206 .simulator_id = -1,
207 };
208
209 #define GEN7_FEATURES \
210 .gen = 7, \
211 .has_hiz_and_separate_stencil = true, \
212 .must_use_separate_stencil = true, \
213 .has_llc = true, \
214 .has_pln = true, \
215 .has_64bit_types = true, \
216 .has_surface_tile_offset = true, \
217 .timestamp_frequency = 12500000
218
219 static const struct gen_device_info gen_device_info_ivb_gt1 = {
220 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
221 .num_slices = 1,
222 .num_subslices = { 1, },
223 .num_eu_per_subslice = 6,
224 .num_thread_per_eu = 6,
225 .l3_banks = 2,
226 .max_vs_threads = 36,
227 .max_tcs_threads = 36,
228 .max_tes_threads = 36,
229 .max_gs_threads = 36,
230 .max_wm_threads = 48,
231 .max_cs_threads = 36,
232 .urb = {
233 .size = 128,
234 .min_entries = {
235 [MESA_SHADER_VERTEX] = 32,
236 [MESA_SHADER_TESS_EVAL] = 10,
237 },
238 .max_entries = {
239 [MESA_SHADER_VERTEX] = 512,
240 [MESA_SHADER_TESS_CTRL] = 32,
241 [MESA_SHADER_TESS_EVAL] = 288,
242 [MESA_SHADER_GEOMETRY] = 192,
243 },
244 },
245 .simulator_id = 7,
246 };
247
248 static const struct gen_device_info gen_device_info_ivb_gt2 = {
249 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
250 .num_slices = 1,
251 .num_subslices = { 1, },
252 .num_eu_per_subslice = 12,
253 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
254 * @max_wm_threads ... */
255 .l3_banks = 4,
256 .max_vs_threads = 128,
257 .max_tcs_threads = 128,
258 .max_tes_threads = 128,
259 .max_gs_threads = 128,
260 .max_wm_threads = 172,
261 .max_cs_threads = 64,
262 .urb = {
263 .size = 256,
264 .min_entries = {
265 [MESA_SHADER_VERTEX] = 32,
266 [MESA_SHADER_TESS_EVAL] = 10,
267 },
268 .max_entries = {
269 [MESA_SHADER_VERTEX] = 704,
270 [MESA_SHADER_TESS_CTRL] = 64,
271 [MESA_SHADER_TESS_EVAL] = 448,
272 [MESA_SHADER_GEOMETRY] = 320,
273 },
274 },
275 .simulator_id = 7,
276 };
277
278 static const struct gen_device_info gen_device_info_byt = {
279 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
280 .num_slices = 1,
281 .num_subslices = { 1, },
282 .num_eu_per_subslice = 4,
283 .num_thread_per_eu = 8,
284 .l3_banks = 1,
285 .has_llc = false,
286 .max_vs_threads = 36,
287 .max_tcs_threads = 36,
288 .max_tes_threads = 36,
289 .max_gs_threads = 36,
290 .max_wm_threads = 48,
291 .max_cs_threads = 32,
292 .urb = {
293 .size = 128,
294 .min_entries = {
295 [MESA_SHADER_VERTEX] = 32,
296 [MESA_SHADER_TESS_EVAL] = 10,
297 },
298 .max_entries = {
299 [MESA_SHADER_VERTEX] = 512,
300 [MESA_SHADER_TESS_CTRL] = 32,
301 [MESA_SHADER_TESS_EVAL] = 288,
302 [MESA_SHADER_GEOMETRY] = 192,
303 },
304 },
305 .simulator_id = 10,
306 };
307
308 #define HSW_FEATURES \
309 GEN7_FEATURES, \
310 .is_haswell = true, \
311 .supports_simd16_3src = true, \
312 .has_resource_streamer = true
313
314 static const struct gen_device_info gen_device_info_hsw_gt1 = {
315 HSW_FEATURES, .gt = 1,
316 .num_slices = 1,
317 .num_subslices = { 1, },
318 .num_eu_per_subslice = 10,
319 .num_thread_per_eu = 7,
320 .l3_banks = 2,
321 .max_vs_threads = 70,
322 .max_tcs_threads = 70,
323 .max_tes_threads = 70,
324 .max_gs_threads = 70,
325 .max_wm_threads = 102,
326 .max_cs_threads = 70,
327 .urb = {
328 .size = 128,
329 .min_entries = {
330 [MESA_SHADER_VERTEX] = 32,
331 [MESA_SHADER_TESS_EVAL] = 10,
332 },
333 .max_entries = {
334 [MESA_SHADER_VERTEX] = 640,
335 [MESA_SHADER_TESS_CTRL] = 64,
336 [MESA_SHADER_TESS_EVAL] = 384,
337 [MESA_SHADER_GEOMETRY] = 256,
338 },
339 },
340 .simulator_id = 9,
341 };
342
343 static const struct gen_device_info gen_device_info_hsw_gt2 = {
344 HSW_FEATURES, .gt = 2,
345 .num_slices = 1,
346 .num_subslices = { 2, },
347 .num_eu_per_subslice = 10,
348 .num_thread_per_eu = 7,
349 .l3_banks = 4,
350 .max_vs_threads = 280,
351 .max_tcs_threads = 256,
352 .max_tes_threads = 280,
353 .max_gs_threads = 256,
354 .max_wm_threads = 204,
355 .max_cs_threads = 70,
356 .urb = {
357 .size = 256,
358 .min_entries = {
359 [MESA_SHADER_VERTEX] = 64,
360 [MESA_SHADER_TESS_EVAL] = 10,
361 },
362 .max_entries = {
363 [MESA_SHADER_VERTEX] = 1664,
364 [MESA_SHADER_TESS_CTRL] = 128,
365 [MESA_SHADER_TESS_EVAL] = 960,
366 [MESA_SHADER_GEOMETRY] = 640,
367 },
368 },
369 .simulator_id = 9,
370 };
371
372 static const struct gen_device_info gen_device_info_hsw_gt3 = {
373 HSW_FEATURES, .gt = 3,
374 .num_slices = 2,
375 .num_subslices = { 2, },
376 .num_eu_per_subslice = 10,
377 .num_thread_per_eu = 7,
378 .l3_banks = 8,
379 .max_vs_threads = 280,
380 .max_tcs_threads = 256,
381 .max_tes_threads = 280,
382 .max_gs_threads = 256,
383 .max_wm_threads = 408,
384 .max_cs_threads = 70,
385 .urb = {
386 .size = 512,
387 .min_entries = {
388 [MESA_SHADER_VERTEX] = 64,
389 [MESA_SHADER_TESS_EVAL] = 10,
390 },
391 .max_entries = {
392 [MESA_SHADER_VERTEX] = 1664,
393 [MESA_SHADER_TESS_CTRL] = 128,
394 [MESA_SHADER_TESS_EVAL] = 960,
395 [MESA_SHADER_GEOMETRY] = 640,
396 },
397 },
398 .simulator_id = 9,
399 };
400
401 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
402 * so keep things conservative for now and set has_sample_with_hiz = false.
403 */
404 #define GEN8_FEATURES \
405 .gen = 8, \
406 .has_hiz_and_separate_stencil = true, \
407 .has_resource_streamer = true, \
408 .must_use_separate_stencil = true, \
409 .has_llc = true, \
410 .has_sample_with_hiz = false, \
411 .has_pln = true, \
412 .has_integer_dword_mul = true, \
413 .has_64bit_types = true, \
414 .supports_simd16_3src = true, \
415 .has_surface_tile_offset = true, \
416 .max_vs_threads = 504, \
417 .max_tcs_threads = 504, \
418 .max_tes_threads = 504, \
419 .max_gs_threads = 504, \
420 .max_wm_threads = 384, \
421 .timestamp_frequency = 12500000
422
423 static const struct gen_device_info gen_device_info_bdw_gt1 = {
424 GEN8_FEATURES, .gt = 1,
425 .is_broadwell = true,
426 .num_slices = 1,
427 .num_subslices = { 2, },
428 .num_eu_per_subslice = 8,
429 .num_thread_per_eu = 7,
430 .l3_banks = 2,
431 .max_cs_threads = 42,
432 .urb = {
433 .size = 192,
434 .min_entries = {
435 [MESA_SHADER_VERTEX] = 64,
436 [MESA_SHADER_TESS_EVAL] = 34,
437 },
438 .max_entries = {
439 [MESA_SHADER_VERTEX] = 2560,
440 [MESA_SHADER_TESS_CTRL] = 504,
441 [MESA_SHADER_TESS_EVAL] = 1536,
442 [MESA_SHADER_GEOMETRY] = 960,
443 },
444 },
445 .simulator_id = 11,
446 };
447
448 static const struct gen_device_info gen_device_info_bdw_gt2 = {
449 GEN8_FEATURES, .gt = 2,
450 .is_broadwell = true,
451 .num_slices = 1,
452 .num_subslices = { 3, },
453 .num_eu_per_subslice = 8,
454 .num_thread_per_eu = 7,
455 .l3_banks = 4,
456 .max_cs_threads = 56,
457 .urb = {
458 .size = 384,
459 .min_entries = {
460 [MESA_SHADER_VERTEX] = 64,
461 [MESA_SHADER_TESS_EVAL] = 34,
462 },
463 .max_entries = {
464 [MESA_SHADER_VERTEX] = 2560,
465 [MESA_SHADER_TESS_CTRL] = 504,
466 [MESA_SHADER_TESS_EVAL] = 1536,
467 [MESA_SHADER_GEOMETRY] = 960,
468 },
469 },
470 .simulator_id = 11,
471 };
472
473 static const struct gen_device_info gen_device_info_bdw_gt3 = {
474 GEN8_FEATURES, .gt = 3,
475 .is_broadwell = true,
476 .num_slices = 2,
477 .num_subslices = { 3, 3, },
478 .num_eu_per_subslice = 8,
479 .num_thread_per_eu = 7,
480 .l3_banks = 8,
481 .max_cs_threads = 56,
482 .urb = {
483 .size = 384,
484 .min_entries = {
485 [MESA_SHADER_VERTEX] = 64,
486 [MESA_SHADER_TESS_EVAL] = 34,
487 },
488 .max_entries = {
489 [MESA_SHADER_VERTEX] = 2560,
490 [MESA_SHADER_TESS_CTRL] = 504,
491 [MESA_SHADER_TESS_EVAL] = 1536,
492 [MESA_SHADER_GEOMETRY] = 960,
493 },
494 },
495 .simulator_id = 11,
496 };
497
498 static const struct gen_device_info gen_device_info_chv = {
499 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
500 .has_llc = false,
501 .has_integer_dword_mul = false,
502 .num_slices = 1,
503 .num_subslices = { 2, },
504 .num_eu_per_subslice = 8,
505 .num_thread_per_eu = 7,
506 .l3_banks = 2,
507 .max_vs_threads = 80,
508 .max_tcs_threads = 80,
509 .max_tes_threads = 80,
510 .max_gs_threads = 80,
511 .max_wm_threads = 128,
512 .max_cs_threads = 6 * 7,
513 .urb = {
514 .size = 192,
515 .min_entries = {
516 [MESA_SHADER_VERTEX] = 34,
517 [MESA_SHADER_TESS_EVAL] = 34,
518 },
519 .max_entries = {
520 [MESA_SHADER_VERTEX] = 640,
521 [MESA_SHADER_TESS_CTRL] = 80,
522 [MESA_SHADER_TESS_EVAL] = 384,
523 [MESA_SHADER_GEOMETRY] = 256,
524 },
525 },
526 .simulator_id = 13,
527 };
528
529 #define GEN9_HW_INFO \
530 .gen = 9, \
531 .max_vs_threads = 336, \
532 .max_gs_threads = 336, \
533 .max_tcs_threads = 336, \
534 .max_tes_threads = 336, \
535 .max_cs_threads = 56, \
536 .timestamp_frequency = 12000000, \
537 .urb = { \
538 .size = 384, \
539 .min_entries = { \
540 [MESA_SHADER_VERTEX] = 64, \
541 [MESA_SHADER_TESS_EVAL] = 34, \
542 }, \
543 .max_entries = { \
544 [MESA_SHADER_VERTEX] = 1856, \
545 [MESA_SHADER_TESS_CTRL] = 672, \
546 [MESA_SHADER_TESS_EVAL] = 1120, \
547 [MESA_SHADER_GEOMETRY] = 640, \
548 }, \
549 }
550
551 #define GEN9_LP_FEATURES \
552 GEN8_FEATURES, \
553 GEN9_HW_INFO, \
554 .has_integer_dword_mul = false, \
555 .gt = 1, \
556 .has_llc = false, \
557 .has_sample_with_hiz = true, \
558 .num_slices = 1, \
559 .num_thread_per_eu = 6, \
560 .max_vs_threads = 112, \
561 .max_tcs_threads = 112, \
562 .max_tes_threads = 112, \
563 .max_gs_threads = 112, \
564 .max_cs_threads = 6 * 6, \
565 .timestamp_frequency = 19200000, \
566 .urb = { \
567 .size = 192, \
568 .min_entries = { \
569 [MESA_SHADER_VERTEX] = 34, \
570 [MESA_SHADER_TESS_EVAL] = 34, \
571 }, \
572 .max_entries = { \
573 [MESA_SHADER_VERTEX] = 704, \
574 [MESA_SHADER_TESS_CTRL] = 256, \
575 [MESA_SHADER_TESS_EVAL] = 416, \
576 [MESA_SHADER_GEOMETRY] = 256, \
577 }, \
578 }
579
580 #define GEN9_LP_FEATURES_3X6 \
581 GEN9_LP_FEATURES, \
582 .num_subslices = { 3, }, \
583 .num_eu_per_subslice = 6
584
585 #define GEN9_LP_FEATURES_2X6 \
586 GEN9_LP_FEATURES, \
587 .num_subslices = { 2, }, \
588 .num_eu_per_subslice = 6, \
589 .max_vs_threads = 56, \
590 .max_tcs_threads = 56, \
591 .max_tes_threads = 56, \
592 .max_gs_threads = 56, \
593 .max_cs_threads = 6 * 6, \
594 .urb = { \
595 .size = 128, \
596 .min_entries = { \
597 [MESA_SHADER_VERTEX] = 34, \
598 [MESA_SHADER_TESS_EVAL] = 34, \
599 }, \
600 .max_entries = { \
601 [MESA_SHADER_VERTEX] = 352, \
602 [MESA_SHADER_TESS_CTRL] = 128, \
603 [MESA_SHADER_TESS_EVAL] = 208, \
604 [MESA_SHADER_GEOMETRY] = 128, \
605 }, \
606 }
607
608 #define GEN9_FEATURES \
609 GEN8_FEATURES, \
610 GEN9_HW_INFO, \
611 .has_sample_with_hiz = true, \
612 .num_thread_per_eu = 7
613
614 static const struct gen_device_info gen_device_info_skl_gt1 = {
615 GEN9_FEATURES, .gt = 1,
616 .is_skylake = true,
617 .num_slices = 1,
618 .num_subslices = { 2, },
619 .num_eu_per_subslice = 6,
620 .l3_banks = 2,
621 .urb.size = 192,
622 .simulator_id = 12,
623 };
624
625 static const struct gen_device_info gen_device_info_skl_gt2 = {
626 GEN9_FEATURES, .gt = 2,
627 .is_skylake = true,
628 .num_slices = 1,
629 .num_subslices = { 3, },
630 .num_eu_per_subslice = 8,
631 .l3_banks = 4,
632 .simulator_id = 12,
633 };
634
635 static const struct gen_device_info gen_device_info_skl_gt3 = {
636 GEN9_FEATURES, .gt = 3,
637 .is_skylake = true,
638 .num_slices = 2,
639 .num_subslices = { 3, 3, },
640 .num_eu_per_subslice = 8,
641 .l3_banks = 8,
642 .simulator_id = 12,
643 };
644
645 static const struct gen_device_info gen_device_info_skl_gt4 = {
646 GEN9_FEATURES, .gt = 4,
647 .is_skylake = true,
648 .num_slices = 3,
649 .num_subslices = { 3, 3, 3, },
650 .num_eu_per_subslice = 8,
651 .l3_banks = 12,
652 /* From the "L3 Allocation and Programming" documentation:
653 *
654 * "URB is limited to 1008KB due to programming restrictions. This is not a
655 * restriction of the L3 implementation, but of the FF and other clients.
656 * Therefore, in a GT4 implementation it is possible for the programmed
657 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
658 * only 1008KB of this will be used."
659 */
660 .urb.size = 1008 / 3,
661 .simulator_id = 12,
662 };
663
664 static const struct gen_device_info gen_device_info_bxt = {
665 GEN9_LP_FEATURES_3X6,
666 .is_broxton = true,
667 .l3_banks = 2,
668 .simulator_id = 14,
669 };
670
671 static const struct gen_device_info gen_device_info_bxt_2x6 = {
672 GEN9_LP_FEATURES_2X6,
673 .is_broxton = true,
674 .l3_banks = 1,
675 .simulator_id = 14,
676 };
677 /*
678 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
679 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
680 */
681
682 static const struct gen_device_info gen_device_info_kbl_gt1 = {
683 GEN9_FEATURES,
684 .is_kabylake = true,
685 .gt = 1,
686
687 .max_cs_threads = 7 * 6,
688 .urb.size = 192,
689 .num_slices = 1,
690 .num_subslices = { 2, },
691 .num_eu_per_subslice = 6,
692 .l3_banks = 2,
693 .simulator_id = 16,
694 };
695
696 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
697 GEN9_FEATURES,
698 .is_kabylake = true,
699 .gt = 1,
700
701 .max_cs_threads = 7 * 6,
702 .num_slices = 1,
703 .num_subslices = { 3, },
704 .num_eu_per_subslice = 6,
705 .l3_banks = 4,
706 .simulator_id = 16,
707 };
708
709 static const struct gen_device_info gen_device_info_kbl_gt2 = {
710 GEN9_FEATURES,
711 .is_kabylake = true,
712 .gt = 2,
713
714 .num_slices = 1,
715 .num_subslices = { 3, },
716 .num_eu_per_subslice = 8,
717 .l3_banks = 4,
718 .simulator_id = 16,
719 };
720
721 static const struct gen_device_info gen_device_info_kbl_gt3 = {
722 GEN9_FEATURES,
723 .is_kabylake = true,
724 .gt = 3,
725
726 .num_slices = 2,
727 .num_subslices = { 3, 3, },
728 .num_eu_per_subslice = 8,
729 .l3_banks = 8,
730 .simulator_id = 16,
731 };
732
733 static const struct gen_device_info gen_device_info_kbl_gt4 = {
734 GEN9_FEATURES,
735 .is_kabylake = true,
736 .gt = 4,
737
738 /*
739 * From the "L3 Allocation and Programming" documentation:
740 *
741 * "URB is limited to 1008KB due to programming restrictions. This
742 * is not a restriction of the L3 implementation, but of the FF and
743 * other clients. Therefore, in a GT4 implementation it is
744 * possible for the programmed allocation of the L3 data array to
745 * provide 3*384KB=1152KB for URB, but only 1008KB of this
746 * will be used."
747 */
748 .urb.size = 1008 / 3,
749 .num_slices = 3,
750 .num_subslices = { 3, 3, 3, },
751 .num_eu_per_subslice = 8,
752 .l3_banks = 12,
753 .simulator_id = 16,
754 };
755
756 static const struct gen_device_info gen_device_info_glk = {
757 GEN9_LP_FEATURES_3X6,
758 .is_geminilake = true,
759 .l3_banks = 2,
760 .simulator_id = 17,
761 };
762
763 static const struct gen_device_info gen_device_info_glk_2x6 = {
764 GEN9_LP_FEATURES_2X6,
765 .is_geminilake = true,
766 .l3_banks = 2,
767 .simulator_id = 17,
768 };
769
770 static const struct gen_device_info gen_device_info_cfl_gt1 = {
771 GEN9_FEATURES,
772 .is_coffeelake = true,
773 .gt = 1,
774
775 .num_slices = 1,
776 .num_subslices = { 2, },
777 .num_eu_per_subslice = 6,
778 .l3_banks = 2,
779 .simulator_id = 24,
780 };
781 static const struct gen_device_info gen_device_info_cfl_gt2 = {
782 GEN9_FEATURES,
783 .is_coffeelake = true,
784 .gt = 2,
785
786 .num_slices = 1,
787 .num_subslices = { 3, },
788 .num_eu_per_subslice = 8,
789 .l3_banks = 4,
790 .simulator_id = 24,
791 };
792
793 static const struct gen_device_info gen_device_info_cfl_gt3 = {
794 GEN9_FEATURES,
795 .is_coffeelake = true,
796 .gt = 3,
797
798 .num_slices = 2,
799 .num_subslices = { 3, 3, },
800 .num_eu_per_subslice = 8,
801 .l3_banks = 8,
802 .simulator_id = 24,
803 };
804
805 #define GEN10_HW_INFO \
806 .gen = 10, \
807 .num_thread_per_eu = 7, \
808 .max_vs_threads = 728, \
809 .max_gs_threads = 432, \
810 .max_tcs_threads = 432, \
811 .max_tes_threads = 624, \
812 .max_cs_threads = 56, \
813 .timestamp_frequency = 19200000, \
814 .urb = { \
815 .size = 256, \
816 .min_entries = { \
817 [MESA_SHADER_VERTEX] = 64, \
818 [MESA_SHADER_TESS_EVAL] = 34, \
819 }, \
820 .max_entries = { \
821 [MESA_SHADER_VERTEX] = 3936, \
822 [MESA_SHADER_TESS_CTRL] = 896, \
823 [MESA_SHADER_TESS_EVAL] = 2064, \
824 [MESA_SHADER_GEOMETRY] = 832, \
825 }, \
826 }
827
828 #define subslices(args...) { args, }
829
830 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
831 GEN8_FEATURES, \
832 GEN10_HW_INFO, \
833 .has_sample_with_hiz = true, \
834 .gt = _gt, \
835 .num_slices = _slices, \
836 .num_subslices = _subslices, \
837 .num_eu_per_subslice = 8, \
838 .l3_banks = _l3
839
840 static const struct gen_device_info gen_device_info_cnl_2x8 = {
841 /* GT0.5 */
842 GEN10_FEATURES(1, 1, subslices(2), 2),
843 .is_cannonlake = true,
844 .simulator_id = 15,
845 };
846
847 static const struct gen_device_info gen_device_info_cnl_3x8 = {
848 /* GT1 */
849 GEN10_FEATURES(1, 1, subslices(3), 3),
850 .is_cannonlake = true,
851 .simulator_id = 15,
852 };
853
854 static const struct gen_device_info gen_device_info_cnl_4x8 = {
855 /* GT 1.5 */
856 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
857 .is_cannonlake = true,
858 .simulator_id = 15,
859 };
860
861 static const struct gen_device_info gen_device_info_cnl_5x8 = {
862 /* GT2 */
863 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
864 .is_cannonlake = true,
865 .simulator_id = 15,
866 };
867
868 #define GEN11_HW_INFO \
869 .gen = 11, \
870 .has_pln = false, \
871 .max_vs_threads = 364, \
872 .max_gs_threads = 224, \
873 .max_tcs_threads = 224, \
874 .max_tes_threads = 364, \
875 .max_cs_threads = 56, \
876 .urb = { \
877 .size = 1024, \
878 .min_entries = { \
879 [MESA_SHADER_VERTEX] = 64, \
880 [MESA_SHADER_TESS_EVAL] = 34, \
881 }, \
882 .max_entries = { \
883 [MESA_SHADER_VERTEX] = 2384, \
884 [MESA_SHADER_TESS_CTRL] = 1032, \
885 [MESA_SHADER_TESS_EVAL] = 2384, \
886 [MESA_SHADER_GEOMETRY] = 1032, \
887 }, \
888 }
889
890 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
891 GEN8_FEATURES, \
892 GEN11_HW_INFO, \
893 .has_64bit_types = false, \
894 .has_integer_dword_mul = false, \
895 .has_sample_with_hiz = false, \
896 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
897 .num_subslices = _subslices, \
898 .num_eu_per_subslice = 8
899
900 static const struct gen_device_info gen_device_info_icl_8x8 = {
901 GEN11_FEATURES(2, 1, subslices(8), 8),
902 .simulator_id = 19,
903 };
904
905 static const struct gen_device_info gen_device_info_icl_6x8 = {
906 GEN11_FEATURES(1, 1, subslices(6), 6),
907 .simulator_id = 19,
908 };
909
910 static const struct gen_device_info gen_device_info_icl_4x8 = {
911 GEN11_FEATURES(1, 1, subslices(4), 6),
912 .simulator_id = 19,
913 };
914
915 static const struct gen_device_info gen_device_info_icl_1x8 = {
916 GEN11_FEATURES(1, 1, subslices(1), 6),
917 .simulator_id = 19,
918 };
919
920 static void
921 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
922 unsigned slice,
923 unsigned subslice,
924 unsigned eu_mask)
925 {
926 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
927 subslice * devinfo->eu_subslice_stride;
928
929 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
930 devinfo->eu_masks[subslice_offset + b_eu] =
931 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
932 }
933 }
934
935 /* Generate slice/subslice/eu masks from number of
936 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
937 * structure.
938 *
939 * These can be overridden with values reported by the kernel either from
940 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
941 * through the i915 query uapi.
942 */
943 static void
944 fill_masks(struct gen_device_info *devinfo)
945 {
946 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
947
948 /* Subslice masks */
949 unsigned max_subslices = 0;
950 for (int s = 0; s < devinfo->num_slices; s++)
951 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
952 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
953
954 for (int s = 0; s < devinfo->num_slices; s++) {
955 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
956 (1U << devinfo->num_subslices[s]) - 1;
957 }
958
959 /* EU masks */
960 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
961 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
962
963 for (int s = 0; s < devinfo->num_slices; s++) {
964 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
965 gen_device_info_set_eu_mask(devinfo, s, ss,
966 (1U << devinfo->num_eu_per_subslice) - 1);
967 }
968 }
969 }
970
971 void
972 gen_device_info_update_from_masks(struct gen_device_info *devinfo,
973 uint32_t slice_mask,
974 uint32_t subslice_mask,
975 uint32_t n_eus)
976 {
977 struct {
978 struct drm_i915_query_topology_info base;
979 uint8_t data[100];
980 } topology;
981
982 assert((slice_mask & 0xff) == slice_mask);
983
984 memset(&topology, 0, sizeof(topology));
985
986 topology.base.max_slices = util_last_bit(slice_mask);
987 topology.base.max_subslices = util_last_bit(subslice_mask);
988
989 topology.base.subslice_offset = DIV_ROUND_UP(topology.base.max_slices, 8);
990 topology.base.subslice_stride = DIV_ROUND_UP(topology.base.max_subslices, 8);
991
992 uint32_t n_subslices = __builtin_popcount(slice_mask) *
993 __builtin_popcount(subslice_mask);
994 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
995 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
996
997 topology.base.eu_offset = topology.base.subslice_offset +
998 DIV_ROUND_UP(topology.base.max_subslices, 8);
999 topology.base.eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1000
1001 /* Set slice mask in topology */
1002 for (int b = 0; b < topology.base.subslice_offset; b++)
1003 topology.base.data[b] = (slice_mask >> (b * 8)) & 0xff;
1004
1005 for (int s = 0; s < topology.base.max_slices; s++) {
1006
1007 /* Set subslice mask in topology */
1008 for (int b = 0; b < topology.base.subslice_stride; b++) {
1009 int subslice_offset = topology.base.subslice_offset +
1010 s * topology.base.subslice_stride + b;
1011
1012 topology.base.data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1013 }
1014
1015 /* Set eu mask in topology */
1016 for (int ss = 0; ss < topology.base.max_subslices; ss++) {
1017 for (int b = 0; b < topology.base.eu_stride; b++) {
1018 int eu_offset = topology.base.eu_offset +
1019 (s * topology.base.max_subslices + ss) * topology.base.eu_stride + b;
1020
1021 topology.base.data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1022 }
1023 }
1024 }
1025
1026 gen_device_info_update_from_topology(devinfo, &topology.base);
1027 }
1028
1029 static void
1030 reset_masks(struct gen_device_info *devinfo)
1031 {
1032 devinfo->subslice_slice_stride = 0;
1033 devinfo->eu_subslice_stride = 0;
1034 devinfo->eu_slice_stride = 0;
1035
1036 devinfo->num_slices = 0;
1037 devinfo->num_eu_per_subslice = 0;
1038 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1039
1040 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1041 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1042 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1043 }
1044
1045 void
1046 gen_device_info_update_from_topology(struct gen_device_info *devinfo,
1047 const struct drm_i915_query_topology_info *topology)
1048 {
1049 reset_masks(devinfo);
1050
1051 devinfo->subslice_slice_stride = topology->subslice_stride;
1052
1053 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1054 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1055
1056 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1057 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1058 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1059
1060 uint32_t subslice_mask_len =
1061 topology->max_slices * topology->subslice_stride;
1062 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1063 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1064 subslice_mask_len);
1065
1066 uint32_t n_subslices = 0;
1067 for (int s = 0; s < topology->max_slices; s++) {
1068 if ((devinfo->slice_masks & (1UL << s)) == 0)
1069 continue;
1070
1071 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1072 devinfo->num_subslices[s] +=
1073 __builtin_popcount(devinfo->subslice_masks[b]);
1074 }
1075 n_subslices += devinfo->num_subslices[s];
1076 }
1077 assert(n_subslices > 0);
1078
1079 uint32_t eu_mask_len =
1080 topology->eu_stride * topology->max_subslices * topology->max_slices;
1081 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1082 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1083
1084 uint32_t n_eus = 0;
1085 for (int b = 0; b < eu_mask_len; b++)
1086 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1087
1088 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1089 }
1090
1091 bool
1092 gen_get_device_info(int devid, struct gen_device_info *devinfo)
1093 {
1094 switch (devid) {
1095 #undef CHIPSET
1096 #define CHIPSET(id, family, name) \
1097 case id: *devinfo = gen_device_info_##family; break;
1098 #include "pci_ids/i965_pci_ids.h"
1099 default:
1100 fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
1101 return false;
1102 }
1103
1104 fill_masks(devinfo);
1105
1106 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1107 *
1108 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1109 * allocate scratch space enough so that each slice has 4 slices allowed."
1110 *
1111 * The equivalent internal documentation says that this programming note
1112 * applies to all Gen9+ platforms.
1113 *
1114 * The hardware typically calculates the scratch space pointer by taking
1115 * the base address, and adding per-thread-scratch-space * thread ID.
1116 * Extra padding can be necessary depending how the thread IDs are
1117 * calculated for a particular shader stage.
1118 */
1119
1120 switch(devinfo->gen) {
1121 case 9:
1122 case 10:
1123 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1124 * devinfo->num_slices
1125 * 4; /* effective subslices per slice */
1126 break;
1127 case 11:
1128 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1129 * devinfo->num_slices
1130 * 8; /* subslices per slice */
1131 break;
1132 default:
1133 break;
1134 }
1135
1136 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1137
1138 return true;
1139 }
1140
1141 const char *
1142 gen_get_device_name(int devid)
1143 {
1144 switch (devid) {
1145 #undef CHIPSET
1146 #define CHIPSET(id, family, name) case id: return name;
1147 #include "pci_ids/i965_pci_ids.h"
1148 default:
1149 return NULL;
1150 }
1151 }