2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct gen_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 ISL_DEV_GEN_SANITIZE(dev
);
63 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_bpb
/ 8;
114 struct isl_extent2d logical_el
, phys_B
;
116 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(format_bpb
));
119 case ISL_TILING_LINEAR
:
121 logical_el
= isl_extent2d(1, 1);
122 phys_B
= isl_extent2d(bs
, 1);
127 logical_el
= isl_extent2d(512 / bs
, 8);
128 phys_B
= isl_extent2d(512, 8);
133 logical_el
= isl_extent2d(128 / bs
, 32);
134 phys_B
= isl_extent2d(128, 32);
139 logical_el
= isl_extent2d(64, 64);
140 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
142 * "If the surface is a stencil buffer (and thus has Tile Mode set
143 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
144 * computed based on width, as the stencil buffer is stored with two
147 * This, together with the fact that stencil buffers are referred to as
148 * being Y-tiled in the PRMs for older hardware implies that the
149 * physical size of a W-tile is actually the same as for a Y-tile.
151 phys_B
= isl_extent2d(128, 32);
155 case ISL_TILING_Ys
: {
156 if (ISL_DEV_GEN(dev
) < 9)
159 if (!isl_is_pow2(bs
))
162 bool is_Ys
= tiling
== ISL_TILING_Ys
;
165 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
166 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
168 logical_el
= isl_extent2d(width
/ bs
, height
);
169 phys_B
= isl_extent2d(width
, height
);
174 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
175 * 128bpb format. The tiling has the same physical dimensions as
176 * Y-tiling but actually has two HiZ columns per Y-tiled column.
179 logical_el
= isl_extent2d(16, 16);
180 phys_B
= isl_extent2d(128, 32);
184 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
185 * have a block size of 1 or 2 bits per block and each CCS element
186 * corresponds to one cache-line pair in the main surface. From the Sky
187 * Lake PRM Vol. 12 in the section on planes:
189 * "The Color Control Surface (CCS) contains the compression status
190 * of the cache-line pairs. The compression state of the cache-line
191 * pair is specified by 2 bits in the CCS. Each CCS cache-line
192 * represents an area on the main surface of 16x16 sets of 128 byte
193 * Y-tiled cache-line-pairs. CCS is always Y tiled."
195 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
196 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
197 * that yields total tile area of 128x128 cache-line pairs or CCS
198 * elements. On older hardware, each CCS element is 1 bit and the tile
199 * is 128x256 elements.
201 assert(format_bpb
== 1 || format_bpb
== 2);
202 logical_el
= isl_extent2d(128, 256 / format_bpb
);
203 phys_B
= isl_extent2d(128, 32);
207 unreachable("not reached");
210 *tile_info
= (struct isl_tile_info
) {
212 .logical_extent_el
= logical_el
,
213 .phys_extent_B
= phys_B
,
220 * @param[out] tiling is set only on success
223 isl_surf_choose_tiling(const struct isl_device
*dev
,
224 const struct isl_surf_init_info
*restrict info
,
225 enum isl_tiling
*tiling
)
227 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
229 if (ISL_DEV_GEN(dev
) >= 7) {
230 gen7_filter_tiling(dev
, info
, &tiling_flags
);
232 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
233 gen7_filter_tiling(dev
, info
, &tiling_flags
);
236 #define CHOOSE(__tiling) \
238 if (tiling_flags & (1u << (__tiling))) { \
239 *tiling = (__tiling); \
244 /* Of the tiling modes remaining, choose the one that offers the best
248 if (info
->dim
== ISL_SURF_DIM_1D
) {
249 /* Prefer linear for 1D surfaces because they do not benefit from
250 * tiling. To the contrary, tiling leads to wasted memory and poor
251 * memory locality due to the swizzling and alignment restrictions
252 * required in tiled surfaces.
254 CHOOSE(ISL_TILING_LINEAR
);
257 CHOOSE(ISL_TILING_CCS
);
258 CHOOSE(ISL_TILING_HIZ
);
259 CHOOSE(ISL_TILING_Ys
);
260 CHOOSE(ISL_TILING_Yf
);
261 CHOOSE(ISL_TILING_Y0
);
262 CHOOSE(ISL_TILING_X
);
263 CHOOSE(ISL_TILING_W
);
264 CHOOSE(ISL_TILING_LINEAR
);
268 /* No tiling mode accomodates the inputs. */
273 isl_choose_msaa_layout(const struct isl_device
*dev
,
274 const struct isl_surf_init_info
*info
,
275 enum isl_tiling tiling
,
276 enum isl_msaa_layout
*msaa_layout
)
278 if (ISL_DEV_GEN(dev
) >= 8) {
279 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
280 } else if (ISL_DEV_GEN(dev
) >= 7) {
281 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
282 } else if (ISL_DEV_GEN(dev
) >= 6) {
283 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
285 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
290 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
291 uint32_t *width
, uint32_t *height
)
293 assert(isl_is_pow2(samples
));
295 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
298 * If the surface is multisampled and it is a depth or stencil surface
299 * or Multisampled Surface StorageFormat in SURFACE_STATE is
300 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
304 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
306 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
309 static enum isl_array_pitch_span
310 isl_choose_array_pitch_span(const struct isl_device
*dev
,
311 const struct isl_surf_init_info
*restrict info
,
312 enum isl_dim_layout dim_layout
,
313 const struct isl_extent4d
*phys_level0_sa
)
315 switch (dim_layout
) {
316 case ISL_DIM_LAYOUT_GEN9_1D
:
317 case ISL_DIM_LAYOUT_GEN4_2D
:
318 if (ISL_DEV_GEN(dev
) >= 8) {
319 /* QPitch becomes programmable in Broadwell. So choose the
320 * most compact QPitch possible in order to conserve memory.
322 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
323 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
325 * - Software must ensure that this field is set to a value
326 * sufficiently large such that the array slices in the surface
327 * do not overlap. Refer to the Memory Data Formats section for
328 * information on how surfaces are stored in memory.
330 * - This field specifies the distance in rows between array
331 * slices. It is used only in the following cases:
333 * - Surface Array is enabled OR
334 * - Number of Mulitsamples is not NUMSAMPLES_1 and
335 * Multisampled Surface Storage Format set to MSFMT_MSS OR
336 * - Surface Type is SURFTYPE_CUBE
338 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
339 } else if (ISL_DEV_GEN(dev
) >= 7) {
340 /* Note that Ivybridge introduces
341 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
342 * driver more control over the QPitch.
345 if (phys_level0_sa
->array_len
== 1) {
346 /* The hardware will never use the QPitch. So choose the most
347 * compact QPitch possible in order to conserve memory.
349 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
352 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
353 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
354 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
355 * Section 6.18.4.7: Surface Arrays (p112):
357 * If Surface Array Spacing is set to ARYSPC_FULL (note that
358 * the depth buffer and stencil buffer have an implied value of
361 return ISL_ARRAY_PITCH_SPAN_FULL
;
364 if (info
->levels
== 1) {
365 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
368 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
371 return ISL_ARRAY_PITCH_SPAN_FULL
;
372 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
373 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
374 isl_surf_usage_is_stencil(info
->usage
)) {
375 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
376 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
378 * The separate stencil buffer does not support mip mapping, thus
379 * the storage for LODs other than LOD 0 is not needed.
381 assert(info
->levels
== 1);
382 assert(phys_level0_sa
->array_len
== 1);
383 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
385 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
386 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
387 isl_surf_usage_is_stencil(info
->usage
)) {
388 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
389 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
391 * The separate stencil buffer does not support mip mapping,
392 * thus the storage for LODs other than LOD 0 is not needed.
394 assert(info
->levels
== 1);
395 assert(phys_level0_sa
->array_len
== 1);
396 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
399 if (phys_level0_sa
->array_len
== 1) {
400 /* The hardware will never use the QPitch. So choose the most
401 * compact QPitch possible in order to conserve memory.
403 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
406 return ISL_ARRAY_PITCH_SPAN_FULL
;
409 case ISL_DIM_LAYOUT_GEN4_3D
:
410 /* The hardware will never use the QPitch. So choose the most
411 * compact QPitch possible in order to conserve memory.
413 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
416 unreachable("bad isl_dim_layout");
417 return ISL_ARRAY_PITCH_SPAN_FULL
;
421 isl_choose_image_alignment_el(const struct isl_device
*dev
,
422 const struct isl_surf_init_info
*restrict info
,
423 enum isl_tiling tiling
,
424 enum isl_dim_layout dim_layout
,
425 enum isl_msaa_layout msaa_layout
,
426 struct isl_extent3d
*image_align_el
)
428 if (info
->format
== ISL_FORMAT_HIZ
) {
429 assert(ISL_DEV_GEN(dev
) >= 6);
430 /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
431 * which works out to 2x2 HiZ elments.
433 *image_align_el
= isl_extent3d(2, 2, 1);
437 if (ISL_DEV_GEN(dev
) >= 9) {
438 gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
439 msaa_layout
, image_align_el
);
440 } else if (ISL_DEV_GEN(dev
) >= 8) {
441 gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
442 msaa_layout
, image_align_el
);
443 } else if (ISL_DEV_GEN(dev
) >= 7) {
444 gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
445 msaa_layout
, image_align_el
);
446 } else if (ISL_DEV_GEN(dev
) >= 6) {
447 gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
448 msaa_layout
, image_align_el
);
450 gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
451 msaa_layout
, image_align_el
);
455 static enum isl_dim_layout
456 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
457 enum isl_surf_dim logical_dim
,
458 enum isl_tiling tiling
)
460 if (ISL_DEV_GEN(dev
) >= 9) {
461 switch (logical_dim
) {
462 case ISL_SURF_DIM_1D
:
463 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
465 * One-dimensional surfaces use a tiling mode of linear.
466 * Technically, they are not tiled resources, but the Tiled
467 * Resource Mode field in RENDER_SURFACE_STATE is still used to
468 * indicate the alignment requirements for this linear surface
469 * (See 1D Alignment requirements for how 4K and 64KB Tiled
470 * Resource Modes impact alignment). Alternatively, a 1D surface
471 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
474 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
475 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
477 if (tiling
== ISL_TILING_LINEAR
)
478 return ISL_DIM_LAYOUT_GEN9_1D
;
480 return ISL_DIM_LAYOUT_GEN4_2D
;
481 case ISL_SURF_DIM_2D
:
482 case ISL_SURF_DIM_3D
:
483 return ISL_DIM_LAYOUT_GEN4_2D
;
486 switch (logical_dim
) {
487 case ISL_SURF_DIM_1D
:
488 case ISL_SURF_DIM_2D
:
489 return ISL_DIM_LAYOUT_GEN4_2D
;
490 case ISL_SURF_DIM_3D
:
491 return ISL_DIM_LAYOUT_GEN4_3D
;
495 unreachable("bad isl_surf_dim");
496 return ISL_DIM_LAYOUT_GEN4_2D
;
500 * Calculate the physical extent of the surface's first level, in units of
501 * surface samples. The result is aligned to the format's compression block.
504 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
505 const struct isl_surf_init_info
*restrict info
,
506 enum isl_dim_layout dim_layout
,
507 enum isl_tiling tiling
,
508 enum isl_msaa_layout msaa_layout
,
509 struct isl_extent4d
*phys_level0_sa
)
511 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
513 if (isl_format_is_yuv(info
->format
))
514 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
517 case ISL_SURF_DIM_1D
:
518 assert(info
->height
== 1);
519 assert(info
->depth
== 1);
520 assert(info
->samples
== 1);
521 assert(!isl_format_is_compressed(info
->format
));
523 switch (dim_layout
) {
524 case ISL_DIM_LAYOUT_GEN4_3D
:
525 unreachable("bad isl_dim_layout");
527 case ISL_DIM_LAYOUT_GEN9_1D
:
528 case ISL_DIM_LAYOUT_GEN4_2D
:
529 *phys_level0_sa
= (struct isl_extent4d
) {
533 .a
= info
->array_len
,
539 case ISL_SURF_DIM_2D
:
540 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
542 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
543 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
545 switch (msaa_layout
) {
546 case ISL_MSAA_LAYOUT_NONE
:
547 assert(info
->depth
== 1);
548 assert(info
->samples
== 1);
550 *phys_level0_sa
= (struct isl_extent4d
) {
551 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
552 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
554 .a
= info
->array_len
,
558 case ISL_MSAA_LAYOUT_ARRAY
:
559 assert(info
->depth
== 1);
560 assert(info
->levels
== 1);
561 assert(!isl_format_is_compressed(info
->format
));
563 *phys_level0_sa
= (struct isl_extent4d
) {
567 .a
= info
->array_len
* info
->samples
,
571 case ISL_MSAA_LAYOUT_INTERLEAVED
:
572 assert(info
->depth
== 1);
573 assert(info
->levels
== 1);
574 assert(!isl_format_is_compressed(info
->format
));
576 *phys_level0_sa
= (struct isl_extent4d
) {
580 .a
= info
->array_len
,
583 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
590 case ISL_SURF_DIM_3D
:
591 assert(info
->array_len
== 1);
592 assert(info
->samples
== 1);
595 isl_finishme("%s:%s: compression block with depth > 1",
599 switch (dim_layout
) {
600 case ISL_DIM_LAYOUT_GEN9_1D
:
601 unreachable("bad isl_dim_layout");
603 case ISL_DIM_LAYOUT_GEN4_2D
:
604 assert(ISL_DEV_GEN(dev
) >= 9);
606 *phys_level0_sa
= (struct isl_extent4d
) {
607 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
608 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
614 case ISL_DIM_LAYOUT_GEN4_3D
:
615 assert(ISL_DEV_GEN(dev
) < 9);
616 *phys_level0_sa
= (struct isl_extent4d
) {
617 .w
= isl_align(info
->width
, fmtl
->bw
),
618 .h
= isl_align(info
->height
, fmtl
->bh
),
629 * A variant of isl_calc_phys_slice0_extent_sa() specific to
630 * ISL_DIM_LAYOUT_GEN4_2D.
633 isl_calc_phys_slice0_extent_sa_gen4_2d(
634 const struct isl_device
*dev
,
635 const struct isl_surf_init_info
*restrict info
,
636 enum isl_msaa_layout msaa_layout
,
637 const struct isl_extent3d
*image_align_sa
,
638 const struct isl_extent4d
*phys_level0_sa
,
639 struct isl_extent2d
*phys_slice0_sa
)
641 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
643 assert(phys_level0_sa
->depth
== 1);
645 if (info
->levels
== 1) {
646 /* Do not pad the surface to the image alignment. Instead, pad it only
647 * to the pixel format's block alignment.
649 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
650 * cycles on the below mipmap layout caluclations. Reducing the
651 * alignment here is safe because we later align the row pitch and array
652 * pitch to the tile boundary. It is safe even for
653 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
654 * to accomodate the interleaved samples.
656 * For linear surfaces, reducing the alignment here permits us to later
657 * choose an arbitrary, non-aligned row pitch. If the surface backs
658 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
659 * VkBufferImageCopy::bufferRowLength.
661 *phys_slice0_sa
= (struct isl_extent2d
) {
662 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
663 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
668 uint32_t slice_top_w
= 0;
669 uint32_t slice_bottom_w
= 0;
670 uint32_t slice_left_h
= 0;
671 uint32_t slice_right_h
= 0;
673 uint32_t W0
= phys_level0_sa
->w
;
674 uint32_t H0
= phys_level0_sa
->h
;
676 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
677 uint32_t W
= isl_minify(W0
, l
);
678 uint32_t H
= isl_minify(H0
, l
);
680 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
681 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
698 *phys_slice0_sa
= (struct isl_extent2d
) {
699 .w
= MAX(slice_top_w
, slice_bottom_w
),
700 .h
= MAX(slice_left_h
, slice_right_h
),
705 * A variant of isl_calc_phys_slice0_extent_sa() specific to
706 * ISL_DIM_LAYOUT_GEN4_3D.
709 isl_calc_phys_slice0_extent_sa_gen4_3d(
710 const struct isl_device
*dev
,
711 const struct isl_surf_init_info
*restrict info
,
712 const struct isl_extent3d
*image_align_sa
,
713 const struct isl_extent4d
*phys_level0_sa
,
714 struct isl_extent2d
*phys_slice0_sa
)
716 assert(info
->samples
== 1);
717 assert(phys_level0_sa
->array_len
== 1);
719 uint32_t slice_w
= 0;
720 uint32_t slice_h
= 0;
722 uint32_t W0
= phys_level0_sa
->w
;
723 uint32_t H0
= phys_level0_sa
->h
;
724 uint32_t D0
= phys_level0_sa
->d
;
726 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
727 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
728 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
729 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
731 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
732 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
734 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
735 slice_h
+= level_h
* max_layers_vert
;
738 *phys_slice0_sa
= (struct isl_extent2d
) {
745 * A variant of isl_calc_phys_slice0_extent_sa() specific to
746 * ISL_DIM_LAYOUT_GEN9_1D.
749 isl_calc_phys_slice0_extent_sa_gen9_1d(
750 const struct isl_device
*dev
,
751 const struct isl_surf_init_info
*restrict info
,
752 const struct isl_extent3d
*image_align_sa
,
753 const struct isl_extent4d
*phys_level0_sa
,
754 struct isl_extent2d
*phys_slice0_sa
)
756 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
758 assert(phys_level0_sa
->height
== 1);
759 assert(phys_level0_sa
->depth
== 1);
760 assert(info
->samples
== 1);
761 assert(image_align_sa
->w
>= fmtl
->bw
);
763 uint32_t slice_w
= 0;
764 const uint32_t W0
= phys_level0_sa
->w
;
766 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
767 uint32_t W
= isl_minify(W0
, l
);
768 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
773 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
777 * Calculate the physical extent of the surface's first array slice, in units
778 * of surface samples. If the surface is multi-leveled, then the result will
779 * be aligned to \a image_align_sa.
782 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
783 const struct isl_surf_init_info
*restrict info
,
784 enum isl_dim_layout dim_layout
,
785 enum isl_msaa_layout msaa_layout
,
786 const struct isl_extent3d
*image_align_sa
,
787 const struct isl_extent4d
*phys_level0_sa
,
788 struct isl_extent2d
*phys_slice0_sa
)
790 switch (dim_layout
) {
791 case ISL_DIM_LAYOUT_GEN9_1D
:
792 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
793 image_align_sa
, phys_level0_sa
,
796 case ISL_DIM_LAYOUT_GEN4_2D
:
797 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
798 image_align_sa
, phys_level0_sa
,
801 case ISL_DIM_LAYOUT_GEN4_3D
:
802 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
803 phys_level0_sa
, phys_slice0_sa
);
809 * Calculate the pitch between physical array slices, in units of rows of
813 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
814 const struct isl_surf_init_info
*restrict info
,
815 const struct isl_tile_info
*tile_info
,
816 enum isl_dim_layout dim_layout
,
817 enum isl_array_pitch_span array_pitch_span
,
818 const struct isl_extent3d
*image_align_sa
,
819 const struct isl_extent4d
*phys_level0_sa
,
820 const struct isl_extent2d
*phys_slice0_sa
)
822 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
823 uint32_t pitch_sa_rows
= 0;
825 switch (dim_layout
) {
826 case ISL_DIM_LAYOUT_GEN9_1D
:
827 /* Each row is an array slice */
830 case ISL_DIM_LAYOUT_GEN4_2D
:
831 switch (array_pitch_span
) {
832 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
833 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
835 case ISL_ARRAY_PITCH_SPAN_FULL
: {
836 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
837 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
838 * Surfaces >> Surface Arrays.
840 uint32_t H0_sa
= phys_level0_sa
->h
;
841 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
843 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
844 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
847 if (ISL_DEV_GEN(dev
) >= 7) {
848 /* The QPitch equation changed slightly in Ivybridge. */
854 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
856 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
857 (info
->height
% 4 == 1)) {
858 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
859 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
861 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
862 * the value calculated in the equation above , for every
863 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
865 * XXX(chadv): Is the errata natural corollary of the physical
866 * layout of interleaved samples?
871 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
876 case ISL_DIM_LAYOUT_GEN4_3D
:
877 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
878 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
881 unreachable("bad isl_dim_layout");
885 assert(pitch_sa_rows
% fmtl
->bh
== 0);
886 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
888 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
890 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
892 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
893 * layout with these alignments in the RT space: Horizontal
894 * Alignment = 128 and Vertical Alignment = 64."
896 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
898 * "For non-multisampled render target's CCS auxiliary surface,
899 * QPitch must be computed with Horizontal Alignment = 128 and
900 * Surface Vertical Alignment = 256. These alignments are only for
901 * CCS buffer and not for associated render target."
903 * The first restriction is already handled by isl_choose_image_alignment_el
904 * but the second restriction, which is an extension of the first, only
905 * applies to qpitch and must be applied here.
907 assert(fmtl
->bh
== 4);
908 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
911 if (ISL_DEV_GEN(dev
) >= 9 &&
912 info
->dim
== ISL_SURF_DIM_3D
&&
913 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
914 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
916 * Tile Mode != Linear: This field must be set to an integer multiple
919 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
922 return pitch_el_rows
;
926 * Calculate the pitch of each surface row, in bytes.
929 isl_calc_linear_row_pitch(const struct isl_device
*dev
,
930 const struct isl_surf_init_info
*restrict info
,
931 const struct isl_extent2d
*phys_slice0_sa
)
933 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
935 uint32_t row_pitch
= info
->min_pitch
;
937 /* First, align the surface to a cache line boundary, as the PRM explains
940 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
941 * Formats >> Surface Padding Requirements >> Render Target and Media
944 * The data port accesses data (pixels) outside of the surface if they
945 * are contained in the same cache request as pixels that are within the
946 * surface. These pixels will not be returned by the requesting message,
947 * however if these pixels lie outside of defined pages in the GTT,
948 * a GTT error will result when the cache request is processed. In order
949 * to avoid these GTT errors, “padding” at the bottom of the surface is
950 * sometimes necessary.
952 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
953 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
955 * The sampling engine accesses texels outside of the surface if they
956 * are contained in the same cache line as texels that are within the
957 * surface. These texels will not participate in any calculation
958 * performed by the sampling engine and will not affect the result of
959 * any sampling engine operation, however if these texels lie outside of
960 * defined pages in the GTT, a GTT error will result when the cache line
961 * is accessed. In order to avoid these GTT errors, “padding” at the
962 * bottom and right side of a sampling engine surface is sometimes
965 * It is possible that a cache line will straddle a page boundary if the
966 * base address or pitch is not aligned. All pages included in the cache
967 * lines that are part of the surface must map to valid GTT entries to
968 * avoid errors. To determine the necessary padding on the bottom and
969 * right side of the surface, refer to the table in Alignment Unit Size
970 * section for the i and j parameters for the surface format in use. The
971 * surface must then be extended to the next multiple of the alignment
972 * unit size in each dimension, and all texels contained in this
973 * extended surface must have valid GTT entries.
975 * For example, suppose the surface size is 15 texels by 10 texels and
976 * the alignment parameters are i=4 and j=2. In this case, the extended
977 * surface would be 16 by 10. Note that these calculations are done in
978 * texels, and must be converted to bytes based on the surface format
979 * being used to determine whether additional pages need to be defined.
981 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
982 const uint32_t bs
= fmtl
->bpb
/ 8;
983 row_pitch
= MAX(row_pitch
, bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
985 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
986 * RENDER_SURFACE_STATE Surface Pitch (p349):
988 * - For linear render target surfaces and surfaces accessed with the
989 * typed data port messages, the pitch must be a multiple of the
990 * element size for non-YUV surface formats. Pitch must be
991 * a multiple of 2 * element size for YUV surface formats.
993 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
994 * ignore because isl doesn't do buffers.]
996 * - For other linear surfaces, the pitch can be any multiple of
999 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1000 if (isl_format_is_yuv(info
->format
)) {
1001 row_pitch
= isl_align_npot(row_pitch
, 2 * bs
);
1003 row_pitch
= isl_align_npot(row_pitch
, bs
);
1011 * Calculate and apply any padding required for the surface.
1013 * @param[inout] total_h_el is updated with the new height
1014 * @param[out] pad_bytes is overwritten with additional padding requirements.
1017 isl_apply_surface_padding(const struct isl_device
*dev
,
1018 const struct isl_surf_init_info
*restrict info
,
1019 const struct isl_tile_info
*tile_info
,
1020 uint32_t *total_h_el
,
1021 uint32_t *pad_bytes
)
1023 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1027 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1028 * Formats >> Surface Padding Requirements >> Render Target and Media
1031 * The data port accesses data (pixels) outside of the surface if they
1032 * are contained in the same cache request as pixels that are within the
1033 * surface. These pixels will not be returned by the requesting message,
1034 * however if these pixels lie outside of defined pages in the GTT,
1035 * a GTT error will result when the cache request is processed. In
1036 * order to avoid these GTT errors, “padding” at the bottom of the
1037 * surface is sometimes necessary.
1039 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1040 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1042 * ... Lots of padding requirements, all listed separately below.
1045 /* We can safely ignore the first padding requirement, quoted below,
1046 * because isl doesn't do buffers.
1048 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1049 * requirements are different. A buffer must be padded to the next
1050 * multiple of 256 array elements, with an additional 16 bytes added
1051 * beyond that to account for the L1 cache line.
1055 * - For compressed textures [...], padding at the bottom of the surface
1056 * is to an even compressed row.
1058 if (isl_format_is_compressed(info
->format
))
1059 *total_h_el
= isl_align(*total_h_el
, 2);
1062 * - For cube surfaces, an additional two rows of padding are required
1063 * at the bottom of the surface.
1065 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1069 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1070 * additional padding is required. These surfaces require an extra row
1071 * plus 16 bytes of padding at the bottom in addition to the general
1072 * padding requirements.
1074 if (isl_format_is_yuv(info
->format
) &&
1075 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1081 * - For linear surfaces, additional padding of 64 bytes is required at
1082 * the bottom of the surface. This is in addition to the padding
1085 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1088 /* The below text weakens, not strengthens, the padding requirements for
1089 * linear surfaces. Therefore we can safely ignore it.
1091 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1092 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1093 * padding requirement is to the next aligned 64-byte boundary beyond
1094 * the end of the surface. The rest of the padding requirements
1095 * documented above do not apply to these surfaces.
1099 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1100 * height % 4 != 0, the surface must be padded with
1101 * 4-(height % 4)*Surface Pitch # of bytes.
1103 if (ISL_DEV_GEN(dev
) >= 9 &&
1104 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1105 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1106 *total_h_el
= isl_align(*total_h_el
, 4);
1110 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1111 * to 4 times the Surface Pitch # of bytes
1113 if (ISL_DEV_GEN(dev
) >= 9 &&
1114 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1115 info
->dim
== ISL_SURF_DIM_1D
) {
1121 isl_surf_init_s(const struct isl_device
*dev
,
1122 struct isl_surf
*surf
,
1123 const struct isl_surf_init_info
*restrict info
)
1125 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1127 const struct isl_extent4d logical_level0_px
= {
1131 .a
= info
->array_len
,
1134 enum isl_tiling tiling
;
1135 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1138 struct isl_tile_info tile_info
;
1139 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bpb
, &tile_info
))
1142 const enum isl_dim_layout dim_layout
=
1143 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
);
1145 enum isl_msaa_layout msaa_layout
;
1146 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1149 struct isl_extent3d image_align_el
;
1150 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1153 struct isl_extent3d image_align_sa
=
1154 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1156 struct isl_extent4d phys_level0_sa
;
1157 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1159 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1160 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1162 enum isl_array_pitch_span array_pitch_span
=
1163 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1165 struct isl_extent2d phys_slice0_sa
;
1166 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1167 &image_align_sa
, &phys_level0_sa
,
1169 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1170 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1172 const uint32_t array_pitch_el_rows
=
1173 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1174 array_pitch_span
, &image_align_sa
,
1175 &phys_level0_sa
, &phys_slice0_sa
);
1177 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1180 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1182 uint32_t row_pitch
, size
, base_alignment
;
1183 if (tiling
== ISL_TILING_LINEAR
) {
1184 row_pitch
= isl_calc_linear_row_pitch(dev
, info
, &phys_slice0_sa
);
1185 size
= row_pitch
* total_h_el
+ pad_bytes
;
1187 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1189 * "The Base Address for linear render target surfaces and surfaces
1190 * accessed with the typed surface read/write data port messages must
1191 * be element-size aligned, for non-YUV surface formats, or a
1192 * multiple of 2 element-sizes for YUV surface formats. Other linear
1193 * surfaces have no alignment requirements (byte alignment is
1196 base_alignment
= MAX(1, info
->min_alignment
);
1197 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1198 if (isl_format_is_yuv(info
->format
)) {
1199 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1201 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1204 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1206 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1207 const uint32_t total_w_el
= phys_slice0_sa
.width
/ fmtl
->bw
;
1208 const uint32_t total_w_tl
=
1209 isl_align_div(total_w_el
, tile_info
.logical_extent_el
.width
);
1211 row_pitch
= total_w_tl
* tile_info
.phys_extent_B
.width
;
1212 if (row_pitch
< info
->min_pitch
) {
1213 row_pitch
= isl_align(info
->min_pitch
, tile_info
.phys_extent_B
.width
);
1216 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1217 const uint32_t total_h_tl
=
1218 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1220 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1222 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1223 tile_info
.phys_extent_B
.height
;
1224 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1225 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1228 *surf
= (struct isl_surf
) {
1230 .dim_layout
= dim_layout
,
1231 .msaa_layout
= msaa_layout
,
1233 .format
= info
->format
,
1235 .levels
= info
->levels
,
1236 .samples
= info
->samples
,
1238 .image_alignment_el
= image_align_el
,
1239 .logical_level0_px
= logical_level0_px
,
1240 .phys_level0_sa
= phys_level0_sa
,
1243 .alignment
= base_alignment
,
1244 .row_pitch
= row_pitch
,
1245 .array_pitch_el_rows
= array_pitch_el_rows
,
1246 .array_pitch_span
= array_pitch_span
,
1248 .usage
= info
->usage
,
1255 isl_surf_get_tile_info(const struct isl_device
*dev
,
1256 const struct isl_surf
*surf
,
1257 struct isl_tile_info
*tile_info
)
1259 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1260 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bpb
, tile_info
);
1264 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1265 const struct isl_surf
*surf
,
1266 struct isl_surf
*hiz_surf
)
1268 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1270 /* Multisampled depth is always interleaved */
1271 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1272 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1274 isl_surf_init(dev
, hiz_surf
,
1275 .dim
= ISL_SURF_DIM_2D
,
1276 .format
= ISL_FORMAT_HIZ
,
1277 .width
= surf
->logical_level0_px
.width
,
1278 .height
= surf
->logical_level0_px
.height
,
1280 .levels
= surf
->levels
,
1281 .array_len
= surf
->logical_level0_px
.array_len
,
1282 /* On SKL+, HiZ is always single-sampled */
1283 .samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
,
1284 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1285 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1289 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1290 const struct isl_surf
*surf
,
1291 struct isl_surf
*mcs_surf
)
1293 /* It must be multisampled with an array layout */
1294 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1296 /* The following are true of all multisampled surfaces */
1297 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1298 assert(surf
->levels
== 1);
1299 assert(surf
->logical_level0_px
.depth
== 1);
1301 enum isl_format mcs_format
;
1302 switch (surf
->samples
) {
1303 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1304 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1305 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1306 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1308 unreachable("Invalid sample count");
1311 isl_surf_init(dev
, mcs_surf
,
1312 .dim
= ISL_SURF_DIM_2D
,
1313 .format
= mcs_format
,
1314 .width
= surf
->logical_level0_px
.width
,
1315 .height
= surf
->logical_level0_px
.height
,
1318 .array_len
= surf
->logical_level0_px
.array_len
,
1319 .samples
= 1, /* MCS surfaces are really single-sampled */
1320 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1321 .tiling_flags
= ISL_TILING_Y0_BIT
);
1325 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1326 const struct isl_surf
*surf
,
1327 struct isl_surf
*ccs_surf
)
1329 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1330 assert(ISL_DEV_GEN(dev
) >= 7);
1332 assert(ISL_DEV_GEN(dev
) >= 8 || surf
->dim
== ISL_SURF_DIM_2D
);
1334 assert(surf
->logical_level0_px
.depth
== 1);
1336 /* TODO: More conditions where it can fail. */
1338 enum isl_format ccs_format
;
1339 if (ISL_DEV_GEN(dev
) >= 9) {
1340 if (!isl_tiling_is_any_y(surf
->tiling
))
1343 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1344 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1345 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1346 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1350 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1351 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1352 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1353 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1354 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1358 } else if (surf
->tiling
== ISL_TILING_X
) {
1359 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1360 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1361 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1362 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1370 isl_surf_init(dev
, ccs_surf
,
1371 .dim
= ISL_SURF_DIM_2D
,
1372 .format
= ccs_format
,
1373 .width
= surf
->logical_level0_px
.width
,
1374 .height
= surf
->logical_level0_px
.height
,
1376 .levels
= surf
->levels
,
1377 .array_len
= surf
->logical_level0_px
.array_len
,
1379 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1380 .tiling_flags
= ISL_TILING_CCS_BIT
);
1386 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1387 const struct isl_surf_fill_state_info
*restrict info
)
1390 isl_surf_usage_flags_t _base_usage
=
1391 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1392 ISL_SURF_USAGE_TEXTURE_BIT
|
1393 ISL_SURF_USAGE_STORAGE_BIT
);
1394 /* They may only specify one of the above bits at a time */
1395 assert(__builtin_popcount(_base_usage
) == 1);
1396 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1397 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1400 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1401 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1402 info
->surf
->logical_level0_px
.depth
);
1404 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1405 info
->surf
->logical_level0_px
.array_len
);
1408 switch (ISL_DEV_GEN(dev
)) {
1410 if (ISL_DEV_IS_G4X(dev
)) {
1411 /* G45 surface state is the same as gen5 */
1412 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1414 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1418 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1421 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1424 if (ISL_DEV_IS_HASWELL(dev
)) {
1425 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1427 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1431 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1434 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1437 assert(!"Cannot fill surface state for this gen");
1442 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1443 const struct isl_buffer_fill_state_info
*restrict info
)
1445 switch (ISL_DEV_GEN(dev
)) {
1448 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1449 isl_gen5_buffer_fill_state_s(state
, info
);
1452 isl_gen6_buffer_fill_state_s(state
, info
);
1455 if (ISL_DEV_IS_HASWELL(dev
)) {
1456 isl_gen75_buffer_fill_state_s(state
, info
);
1458 isl_gen7_buffer_fill_state_s(state
, info
);
1462 isl_gen8_buffer_fill_state_s(state
, info
);
1465 isl_gen9_buffer_fill_state_s(state
, info
);
1468 assert(!"Cannot fill surface state for this gen");
1473 * A variant of isl_surf_get_image_offset_sa() specific to
1474 * ISL_DIM_LAYOUT_GEN4_2D.
1477 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1478 uint32_t level
, uint32_t logical_array_layer
,
1479 uint32_t *x_offset_sa
,
1480 uint32_t *y_offset_sa
)
1482 assert(level
< surf
->levels
);
1483 if (surf
->dim
== ISL_SURF_DIM_3D
)
1484 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1486 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1488 const struct isl_extent3d image_align_sa
=
1489 isl_surf_get_image_alignment_sa(surf
);
1491 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1492 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1494 const uint32_t phys_layer
= logical_array_layer
*
1495 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1498 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1500 for (uint32_t l
= 0; l
< level
; ++l
) {
1502 uint32_t W
= isl_minify(W0
, l
);
1503 x
+= isl_align_npot(W
, image_align_sa
.w
);
1505 uint32_t H
= isl_minify(H0
, l
);
1506 y
+= isl_align_npot(H
, image_align_sa
.h
);
1515 * A variant of isl_surf_get_image_offset_sa() specific to
1516 * ISL_DIM_LAYOUT_GEN4_3D.
1519 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1520 uint32_t level
, uint32_t logical_z_offset_px
,
1521 uint32_t *x_offset_sa
,
1522 uint32_t *y_offset_sa
)
1524 assert(level
< surf
->levels
);
1525 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1526 assert(surf
->phys_level0_sa
.array_len
== 1);
1528 const struct isl_extent3d image_align_sa
=
1529 isl_surf_get_image_alignment_sa(surf
);
1531 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1532 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1533 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1538 for (uint32_t l
= 0; l
< level
; ++l
) {
1539 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1540 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1541 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1543 y
+= level_h
* max_layers_vert
;
1546 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1547 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1548 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1550 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1552 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1553 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1560 * A variant of isl_surf_get_image_offset_sa() specific to
1561 * ISL_DIM_LAYOUT_GEN9_1D.
1564 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1565 uint32_t level
, uint32_t layer
,
1566 uint32_t *x_offset_sa
,
1567 uint32_t *y_offset_sa
)
1569 assert(level
< surf
->levels
);
1570 assert(layer
< surf
->phys_level0_sa
.array_len
);
1571 assert(surf
->phys_level0_sa
.height
== 1);
1572 assert(surf
->phys_level0_sa
.depth
== 1);
1573 assert(surf
->samples
== 1);
1575 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1576 const struct isl_extent3d image_align_sa
=
1577 isl_surf_get_image_alignment_sa(surf
);
1581 for (uint32_t l
= 0; l
< level
; ++l
) {
1582 uint32_t W
= isl_minify(W0
, l
);
1583 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1589 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1593 * Calculate the offset, in units of surface samples, to a subimage in the
1596 * @invariant level < surface levels
1597 * @invariant logical_array_layer < logical array length of surface
1598 * @invariant logical_z_offset_px < logical depth of surface at level
1601 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1603 uint32_t logical_array_layer
,
1604 uint32_t logical_z_offset_px
,
1605 uint32_t *x_offset_sa
,
1606 uint32_t *y_offset_sa
)
1608 assert(level
< surf
->levels
);
1609 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1610 assert(logical_z_offset_px
1611 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1613 switch (surf
->dim_layout
) {
1614 case ISL_DIM_LAYOUT_GEN9_1D
:
1615 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1616 x_offset_sa
, y_offset_sa
);
1618 case ISL_DIM_LAYOUT_GEN4_2D
:
1619 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1620 + logical_z_offset_px
,
1621 x_offset_sa
, y_offset_sa
);
1623 case ISL_DIM_LAYOUT_GEN4_3D
:
1624 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1625 x_offset_sa
, y_offset_sa
);
1629 unreachable("not reached");
1634 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1636 uint32_t logical_array_layer
,
1637 uint32_t logical_z_offset_px
,
1638 uint32_t *x_offset_el
,
1639 uint32_t *y_offset_el
)
1641 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1643 assert(level
< surf
->levels
);
1644 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1645 assert(logical_z_offset_px
1646 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1648 uint32_t x_offset_sa
, y_offset_sa
;
1649 isl_surf_get_image_offset_sa(surf
, level
,
1650 logical_array_layer
,
1651 logical_z_offset_px
,
1655 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1656 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1660 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1661 enum isl_tiling tiling
,
1664 uint32_t total_x_offset_el
,
1665 uint32_t total_y_offset_el
,
1666 uint32_t *base_address_offset
,
1667 uint32_t *x_offset_el
,
1668 uint32_t *y_offset_el
)
1670 /* This function only really works for power-of-two surfaces. In
1671 * theory, we could make it work for non-power-of-two surfaces by going
1672 * to the left until we find a block that is bs-aligned. The Vulkan
1673 * driver doesn't use non-power-of-two tiled surfaces so we'll leave
1674 * this unimplemented for now.
1676 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(bs
));
1678 if (tiling
== ISL_TILING_LINEAR
) {
1679 *base_address_offset
= total_y_offset_el
* row_pitch
+
1680 total_x_offset_el
* bs
;
1686 struct isl_tile_info tile_info
;
1687 isl_tiling_get_info(dev
, tiling
, bs
* 8, &tile_info
);
1689 /* Compute the offset into the tile */
1690 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
1691 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
1693 /* Compute the offset of the tile in units of whole tiles */
1694 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
1695 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
1697 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1698 *base_address_offset
=
1699 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
1700 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
1704 isl_surf_get_depth_format(const struct isl_device
*dev
,
1705 const struct isl_surf
*surf
)
1707 /* Support for separate stencil buffers began in gen5. Support for
1708 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1709 * those that supported separate and interleaved stencil, were gen5 and
1712 * For a list of all available formats, see the Sandybridge PRM >> Volume
1713 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1717 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1719 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1722 assert(ISL_DEV_GEN(dev
) < 7);
1724 switch (surf
->format
) {
1726 unreachable("bad isl depth format");
1727 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1728 assert(ISL_DEV_GEN(dev
) < 7);
1729 return 0; /* D32_FLOAT_S8X24_UINT */
1730 case ISL_FORMAT_R32_FLOAT
:
1731 assert(!has_stencil
);
1732 return 1; /* D32_FLOAT */
1733 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1735 assert(ISL_DEV_GEN(dev
) < 7);
1736 return 2; /* D24_UNORM_S8_UINT */
1738 assert(ISL_DEV_GEN(dev
) >= 5);
1739 return 3; /* D24_UNORM_X8_UINT */
1741 case ISL_FORMAT_R16_UNORM
:
1742 assert(!has_stencil
);
1743 return 5; /* D16_UNORM */