2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
38 void PRINTFLIKE(3, 4) UNUSED
39 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
45 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
48 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
55 uint8_t aux_addr_offset
;
60 [7] = {32, 32, 4, 24},
61 [8] = {64, 64, 32, 40},
62 [9] = {64, 64, 32, 40},
66 isl_device_init(struct isl_device
*dev
,
67 const struct gen_device_info
*info
,
68 bool has_bit6_swizzling
)
71 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
72 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
74 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
75 * device properties at buildtime. Verify that the macros with the device
76 * properties chosen during runtime.
78 ISL_DEV_GEN_SANITIZE(dev
);
79 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
81 /* Did we break hiz or stencil? */
82 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
83 assert(info
->has_hiz_and_separate_stencil
);
84 if (info
->must_use_separate_stencil
)
85 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
87 dev
->ss
.size
= ss_infos
[ISL_DEV_GEN(dev
)].size
;
88 dev
->ss
.align
= ss_infos
[ISL_DEV_GEN(dev
)].align
;
89 dev
->ss
.addr_offset
= ss_infos
[ISL_DEV_GEN(dev
)].addr_offset
;
90 dev
->ss
.aux_addr_offset
= ss_infos
[ISL_DEV_GEN(dev
)].aux_addr_offset
;
94 * @brief Query the set of multisamples supported by the device.
96 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
99 isl_sample_count_mask_t ATTRIBUTE_CONST
100 isl_device_get_sample_counts(struct isl_device
*dev
)
102 if (ISL_DEV_GEN(dev
) >= 9) {
103 return ISL_SAMPLE_COUNT_1_BIT
|
104 ISL_SAMPLE_COUNT_2_BIT
|
105 ISL_SAMPLE_COUNT_4_BIT
|
106 ISL_SAMPLE_COUNT_8_BIT
|
107 ISL_SAMPLE_COUNT_16_BIT
;
108 } else if (ISL_DEV_GEN(dev
) >= 8) {
109 return ISL_SAMPLE_COUNT_1_BIT
|
110 ISL_SAMPLE_COUNT_2_BIT
|
111 ISL_SAMPLE_COUNT_4_BIT
|
112 ISL_SAMPLE_COUNT_8_BIT
;
113 } else if (ISL_DEV_GEN(dev
) >= 7) {
114 return ISL_SAMPLE_COUNT_1_BIT
|
115 ISL_SAMPLE_COUNT_4_BIT
|
116 ISL_SAMPLE_COUNT_8_BIT
;
117 } else if (ISL_DEV_GEN(dev
) >= 6) {
118 return ISL_SAMPLE_COUNT_1_BIT
|
119 ISL_SAMPLE_COUNT_4_BIT
;
121 return ISL_SAMPLE_COUNT_1_BIT
;
126 * @param[out] info is written only on success
129 isl_tiling_get_info(const struct isl_device
*dev
,
130 enum isl_tiling tiling
,
132 struct isl_tile_info
*tile_info
)
134 const uint32_t bs
= format_bpb
/ 8;
135 struct isl_extent2d logical_el
, phys_B
;
137 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
138 /* It is possible to have non-power-of-two formats in a tiled buffer.
139 * The easiest way to handle this is to treat the tile as if it is three
140 * times as wide. This way no pixel will ever cross a tile boundary.
141 * This really only works on legacy X and Y tiling formats.
143 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
144 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
145 return isl_tiling_get_info(dev
, tiling
, format_bpb
/ 3, tile_info
);
149 case ISL_TILING_LINEAR
:
151 logical_el
= isl_extent2d(1, 1);
152 phys_B
= isl_extent2d(bs
, 1);
157 logical_el
= isl_extent2d(512 / bs
, 8);
158 phys_B
= isl_extent2d(512, 8);
163 logical_el
= isl_extent2d(128 / bs
, 32);
164 phys_B
= isl_extent2d(128, 32);
169 logical_el
= isl_extent2d(64, 64);
170 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
172 * "If the surface is a stencil buffer (and thus has Tile Mode set
173 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
174 * computed based on width, as the stencil buffer is stored with two
177 * This, together with the fact that stencil buffers are referred to as
178 * being Y-tiled in the PRMs for older hardware implies that the
179 * physical size of a W-tile is actually the same as for a Y-tile.
181 phys_B
= isl_extent2d(128, 32);
185 case ISL_TILING_Ys
: {
186 if (ISL_DEV_GEN(dev
) < 9)
189 if (!isl_is_pow2(bs
))
192 bool is_Ys
= tiling
== ISL_TILING_Ys
;
195 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
196 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
198 logical_el
= isl_extent2d(width
/ bs
, height
);
199 phys_B
= isl_extent2d(width
, height
);
204 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
205 * 128bpb format. The tiling has the same physical dimensions as
206 * Y-tiling but actually has two HiZ columns per Y-tiled column.
209 logical_el
= isl_extent2d(16, 16);
210 phys_B
= isl_extent2d(128, 32);
214 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
215 * have a block size of 1 or 2 bits per block and each CCS element
216 * corresponds to one cache-line pair in the main surface. From the Sky
217 * Lake PRM Vol. 12 in the section on planes:
219 * "The Color Control Surface (CCS) contains the compression status
220 * of the cache-line pairs. The compression state of the cache-line
221 * pair is specified by 2 bits in the CCS. Each CCS cache-line
222 * represents an area on the main surface of 16x16 sets of 128 byte
223 * Y-tiled cache-line-pairs. CCS is always Y tiled."
225 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
226 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
227 * that yields total tile area of 128x128 cache-line pairs or CCS
228 * elements. On older hardware, each CCS element is 1 bit and the tile
229 * is 128x256 elements.
231 assert(format_bpb
== 1 || format_bpb
== 2);
232 logical_el
= isl_extent2d(128, 256 / format_bpb
);
233 phys_B
= isl_extent2d(128, 32);
237 unreachable("not reached");
240 *tile_info
= (struct isl_tile_info
) {
242 .format_bpb
= format_bpb
,
243 .logical_extent_el
= logical_el
,
244 .phys_extent_B
= phys_B
,
251 * @param[out] tiling is set only on success
254 isl_surf_choose_tiling(const struct isl_device
*dev
,
255 const struct isl_surf_init_info
*restrict info
,
256 enum isl_tiling
*tiling
)
258 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
260 /* HiZ surfaces always use the HiZ tiling */
261 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
262 assert(info
->format
== ISL_FORMAT_HIZ
);
263 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
264 *tiling
= ISL_TILING_HIZ
;
268 /* CCS surfaces always use the CCS tiling */
269 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
270 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
271 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
272 *tiling
= ISL_TILING_CCS
;
276 if (ISL_DEV_GEN(dev
) >= 6) {
277 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
279 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
280 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
283 #define CHOOSE(__tiling) \
285 if (tiling_flags & (1u << (__tiling))) { \
286 *tiling = (__tiling); \
291 /* Of the tiling modes remaining, choose the one that offers the best
295 if (info
->dim
== ISL_SURF_DIM_1D
) {
296 /* Prefer linear for 1D surfaces because they do not benefit from
297 * tiling. To the contrary, tiling leads to wasted memory and poor
298 * memory locality due to the swizzling and alignment restrictions
299 * required in tiled surfaces.
301 CHOOSE(ISL_TILING_LINEAR
);
304 CHOOSE(ISL_TILING_Ys
);
305 CHOOSE(ISL_TILING_Yf
);
306 CHOOSE(ISL_TILING_Y0
);
307 CHOOSE(ISL_TILING_X
);
308 CHOOSE(ISL_TILING_W
);
309 CHOOSE(ISL_TILING_LINEAR
);
313 /* No tiling mode accomodates the inputs. */
318 isl_choose_msaa_layout(const struct isl_device
*dev
,
319 const struct isl_surf_init_info
*info
,
320 enum isl_tiling tiling
,
321 enum isl_msaa_layout
*msaa_layout
)
323 if (ISL_DEV_GEN(dev
) >= 8) {
324 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
325 } else if (ISL_DEV_GEN(dev
) >= 7) {
326 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
327 } else if (ISL_DEV_GEN(dev
) >= 6) {
328 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
330 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
335 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
337 assert(isl_is_pow2(samples
));
339 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
342 * If the surface is multisampled and it is a depth or stencil surface
343 * or Multisampled Surface StorageFormat in SURFACE_STATE is
344 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
347 return (struct isl_extent2d
) {
348 .width
= 1 << ((ffs(samples
) - 0) / 2),
349 .height
= 1 << ((ffs(samples
) - 1) / 2),
354 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
355 uint32_t *width
, uint32_t *height
)
357 const struct isl_extent2d px_size_sa
=
358 isl_get_interleaved_msaa_px_size_sa(samples
);
361 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
363 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
366 static enum isl_array_pitch_span
367 isl_choose_array_pitch_span(const struct isl_device
*dev
,
368 const struct isl_surf_init_info
*restrict info
,
369 enum isl_dim_layout dim_layout
,
370 const struct isl_extent4d
*phys_level0_sa
)
372 switch (dim_layout
) {
373 case ISL_DIM_LAYOUT_GEN9_1D
:
374 case ISL_DIM_LAYOUT_GEN4_2D
:
375 if (ISL_DEV_GEN(dev
) >= 8) {
376 /* QPitch becomes programmable in Broadwell. So choose the
377 * most compact QPitch possible in order to conserve memory.
379 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
380 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
382 * - Software must ensure that this field is set to a value
383 * sufficiently large such that the array slices in the surface
384 * do not overlap. Refer to the Memory Data Formats section for
385 * information on how surfaces are stored in memory.
387 * - This field specifies the distance in rows between array
388 * slices. It is used only in the following cases:
390 * - Surface Array is enabled OR
391 * - Number of Mulitsamples is not NUMSAMPLES_1 and
392 * Multisampled Surface Storage Format set to MSFMT_MSS OR
393 * - Surface Type is SURFTYPE_CUBE
395 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
396 } else if (ISL_DEV_GEN(dev
) >= 7) {
397 /* Note that Ivybridge introduces
398 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
399 * driver more control over the QPitch.
402 if (phys_level0_sa
->array_len
== 1) {
403 /* The hardware will never use the QPitch. So choose the most
404 * compact QPitch possible in order to conserve memory.
406 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
409 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
410 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
411 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
412 * Section 6.18.4.7: Surface Arrays (p112):
414 * If Surface Array Spacing is set to ARYSPC_FULL (note that
415 * the depth buffer and stencil buffer have an implied value of
418 return ISL_ARRAY_PITCH_SPAN_FULL
;
421 if (info
->levels
== 1) {
422 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
425 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
428 return ISL_ARRAY_PITCH_SPAN_FULL
;
429 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
430 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
431 isl_surf_usage_is_stencil(info
->usage
)) {
432 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
433 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
435 * The separate stencil buffer does not support mip mapping, thus
436 * the storage for LODs other than LOD 0 is not needed.
438 assert(info
->levels
== 1);
439 assert(phys_level0_sa
->array_len
== 1);
440 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
442 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
443 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
444 isl_surf_usage_is_stencil(info
->usage
)) {
445 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
446 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
448 * The separate stencil buffer does not support mip mapping,
449 * thus the storage for LODs other than LOD 0 is not needed.
451 assert(info
->levels
== 1);
452 assert(phys_level0_sa
->array_len
== 1);
453 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
456 if (phys_level0_sa
->array_len
== 1) {
457 /* The hardware will never use the QPitch. So choose the most
458 * compact QPitch possible in order to conserve memory.
460 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
463 return ISL_ARRAY_PITCH_SPAN_FULL
;
466 case ISL_DIM_LAYOUT_GEN4_3D
:
467 /* The hardware will never use the QPitch. So choose the most
468 * compact QPitch possible in order to conserve memory.
470 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
473 unreachable("bad isl_dim_layout");
474 return ISL_ARRAY_PITCH_SPAN_FULL
;
478 isl_choose_image_alignment_el(const struct isl_device
*dev
,
479 const struct isl_surf_init_info
*restrict info
,
480 enum isl_tiling tiling
,
481 enum isl_dim_layout dim_layout
,
482 enum isl_msaa_layout msaa_layout
,
483 struct isl_extent3d
*image_align_el
)
485 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
486 if (fmtl
->txc
== ISL_TXC_MCS
) {
487 assert(tiling
== ISL_TILING_Y0
);
490 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
492 * Height, width, and layout of MCS buffer in this case must match with
493 * Render Target height, width, and layout. MCS buffer is tiledY.
495 * To avoid wasting memory, choose the smallest alignment possible:
496 * HALIGN_4 and VALIGN_4.
498 *image_align_el
= isl_extent3d(4, 4, 1);
500 } else if (info
->format
== ISL_FORMAT_HIZ
) {
501 assert(ISL_DEV_GEN(dev
) >= 6);
502 /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
503 * which works out to 2x2 HiZ elments.
505 *image_align_el
= isl_extent3d(2, 2, 1);
509 if (ISL_DEV_GEN(dev
) >= 9) {
510 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
511 msaa_layout
, image_align_el
);
512 } else if (ISL_DEV_GEN(dev
) >= 8) {
513 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
514 msaa_layout
, image_align_el
);
515 } else if (ISL_DEV_GEN(dev
) >= 7) {
516 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
517 msaa_layout
, image_align_el
);
518 } else if (ISL_DEV_GEN(dev
) >= 6) {
519 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
520 msaa_layout
, image_align_el
);
522 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
523 msaa_layout
, image_align_el
);
527 static enum isl_dim_layout
528 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
529 enum isl_surf_dim logical_dim
,
530 enum isl_tiling tiling
)
532 if (ISL_DEV_GEN(dev
) >= 9) {
533 switch (logical_dim
) {
534 case ISL_SURF_DIM_1D
:
535 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
537 * One-dimensional surfaces use a tiling mode of linear.
538 * Technically, they are not tiled resources, but the Tiled
539 * Resource Mode field in RENDER_SURFACE_STATE is still used to
540 * indicate the alignment requirements for this linear surface
541 * (See 1D Alignment requirements for how 4K and 64KB Tiled
542 * Resource Modes impact alignment). Alternatively, a 1D surface
543 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
546 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
547 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
549 if (tiling
== ISL_TILING_LINEAR
)
550 return ISL_DIM_LAYOUT_GEN9_1D
;
552 return ISL_DIM_LAYOUT_GEN4_2D
;
553 case ISL_SURF_DIM_2D
:
554 case ISL_SURF_DIM_3D
:
555 return ISL_DIM_LAYOUT_GEN4_2D
;
558 switch (logical_dim
) {
559 case ISL_SURF_DIM_1D
:
560 case ISL_SURF_DIM_2D
:
561 return ISL_DIM_LAYOUT_GEN4_2D
;
562 case ISL_SURF_DIM_3D
:
563 return ISL_DIM_LAYOUT_GEN4_3D
;
567 unreachable("bad isl_surf_dim");
568 return ISL_DIM_LAYOUT_GEN4_2D
;
572 * Calculate the physical extent of the surface's first level, in units of
573 * surface samples. The result is aligned to the format's compression block.
576 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
577 const struct isl_surf_init_info
*restrict info
,
578 enum isl_dim_layout dim_layout
,
579 enum isl_tiling tiling
,
580 enum isl_msaa_layout msaa_layout
,
581 struct isl_extent4d
*phys_level0_sa
)
583 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
585 if (isl_format_is_yuv(info
->format
))
586 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
589 case ISL_SURF_DIM_1D
:
590 assert(info
->height
== 1);
591 assert(info
->depth
== 1);
592 assert(info
->samples
== 1);
594 switch (dim_layout
) {
595 case ISL_DIM_LAYOUT_GEN4_3D
:
596 unreachable("bad isl_dim_layout");
598 case ISL_DIM_LAYOUT_GEN9_1D
:
599 case ISL_DIM_LAYOUT_GEN4_2D
:
600 *phys_level0_sa
= (struct isl_extent4d
) {
601 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
604 .a
= info
->array_len
,
610 case ISL_SURF_DIM_2D
:
611 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
613 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
614 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
616 switch (msaa_layout
) {
617 case ISL_MSAA_LAYOUT_NONE
:
618 assert(info
->depth
== 1);
619 assert(info
->samples
== 1);
621 *phys_level0_sa
= (struct isl_extent4d
) {
622 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
623 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
625 .a
= info
->array_len
,
629 case ISL_MSAA_LAYOUT_ARRAY
:
630 assert(info
->depth
== 1);
631 assert(info
->levels
== 1);
632 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
633 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
635 *phys_level0_sa
= (struct isl_extent4d
) {
639 .a
= info
->array_len
* info
->samples
,
643 case ISL_MSAA_LAYOUT_INTERLEAVED
:
644 assert(info
->depth
== 1);
645 assert(info
->levels
== 1);
646 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
648 *phys_level0_sa
= (struct isl_extent4d
) {
652 .a
= info
->array_len
,
655 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
659 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
660 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
665 case ISL_SURF_DIM_3D
:
666 assert(info
->array_len
== 1);
667 assert(info
->samples
== 1);
670 isl_finishme("%s:%s: compression block with depth > 1",
674 switch (dim_layout
) {
675 case ISL_DIM_LAYOUT_GEN9_1D
:
676 unreachable("bad isl_dim_layout");
678 case ISL_DIM_LAYOUT_GEN4_2D
:
679 assert(ISL_DEV_GEN(dev
) >= 9);
681 *phys_level0_sa
= (struct isl_extent4d
) {
682 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
683 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
689 case ISL_DIM_LAYOUT_GEN4_3D
:
690 assert(ISL_DEV_GEN(dev
) < 9);
691 *phys_level0_sa
= (struct isl_extent4d
) {
692 .w
= isl_align(info
->width
, fmtl
->bw
),
693 .h
= isl_align(info
->height
, fmtl
->bh
),
704 * A variant of isl_calc_phys_slice0_extent_sa() specific to
705 * ISL_DIM_LAYOUT_GEN4_2D.
708 isl_calc_phys_slice0_extent_sa_gen4_2d(
709 const struct isl_device
*dev
,
710 const struct isl_surf_init_info
*restrict info
,
711 enum isl_msaa_layout msaa_layout
,
712 const struct isl_extent3d
*image_align_sa
,
713 const struct isl_extent4d
*phys_level0_sa
,
714 struct isl_extent2d
*phys_slice0_sa
)
716 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
718 assert(phys_level0_sa
->depth
== 1);
720 if (info
->levels
== 1) {
721 /* Do not pad the surface to the image alignment. Instead, pad it only
722 * to the pixel format's block alignment.
724 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
725 * cycles on the below mipmap layout caluclations. Reducing the
726 * alignment here is safe because we later align the row pitch and array
727 * pitch to the tile boundary. It is safe even for
728 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
729 * to accomodate the interleaved samples.
731 * For linear surfaces, reducing the alignment here permits us to later
732 * choose an arbitrary, non-aligned row pitch. If the surface backs
733 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
734 * VkBufferImageCopy::bufferRowLength.
736 *phys_slice0_sa
= (struct isl_extent2d
) {
737 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
738 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
743 uint32_t slice_top_w
= 0;
744 uint32_t slice_bottom_w
= 0;
745 uint32_t slice_left_h
= 0;
746 uint32_t slice_right_h
= 0;
748 uint32_t W0
= phys_level0_sa
->w
;
749 uint32_t H0
= phys_level0_sa
->h
;
751 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
752 uint32_t W
= isl_minify(W0
, l
);
753 uint32_t H
= isl_minify(H0
, l
);
755 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
756 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
773 *phys_slice0_sa
= (struct isl_extent2d
) {
774 .w
= MAX(slice_top_w
, slice_bottom_w
),
775 .h
= MAX(slice_left_h
, slice_right_h
),
780 * A variant of isl_calc_phys_slice0_extent_sa() specific to
781 * ISL_DIM_LAYOUT_GEN4_3D.
784 isl_calc_phys_slice0_extent_sa_gen4_3d(
785 const struct isl_device
*dev
,
786 const struct isl_surf_init_info
*restrict info
,
787 const struct isl_extent3d
*image_align_sa
,
788 const struct isl_extent4d
*phys_level0_sa
,
789 struct isl_extent2d
*phys_slice0_sa
)
791 assert(info
->samples
== 1);
792 assert(phys_level0_sa
->array_len
== 1);
794 uint32_t slice_w
= 0;
795 uint32_t slice_h
= 0;
797 uint32_t W0
= phys_level0_sa
->w
;
798 uint32_t H0
= phys_level0_sa
->h
;
799 uint32_t D0
= phys_level0_sa
->d
;
801 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
802 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
803 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
804 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
806 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
807 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
809 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
810 slice_h
+= level_h
* max_layers_vert
;
813 *phys_slice0_sa
= (struct isl_extent2d
) {
820 * A variant of isl_calc_phys_slice0_extent_sa() specific to
821 * ISL_DIM_LAYOUT_GEN9_1D.
824 isl_calc_phys_slice0_extent_sa_gen9_1d(
825 const struct isl_device
*dev
,
826 const struct isl_surf_init_info
*restrict info
,
827 const struct isl_extent3d
*image_align_sa
,
828 const struct isl_extent4d
*phys_level0_sa
,
829 struct isl_extent2d
*phys_slice0_sa
)
831 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
833 assert(phys_level0_sa
->height
== 1);
834 assert(phys_level0_sa
->depth
== 1);
835 assert(info
->samples
== 1);
836 assert(image_align_sa
->w
>= fmtl
->bw
);
838 uint32_t slice_w
= 0;
839 const uint32_t W0
= phys_level0_sa
->w
;
841 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
842 uint32_t W
= isl_minify(W0
, l
);
843 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
848 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
852 * Calculate the physical extent of the surface's first array slice, in units
853 * of surface samples. If the surface is multi-leveled, then the result will
854 * be aligned to \a image_align_sa.
857 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
858 const struct isl_surf_init_info
*restrict info
,
859 enum isl_dim_layout dim_layout
,
860 enum isl_msaa_layout msaa_layout
,
861 const struct isl_extent3d
*image_align_sa
,
862 const struct isl_extent4d
*phys_level0_sa
,
863 struct isl_extent2d
*phys_slice0_sa
)
865 switch (dim_layout
) {
866 case ISL_DIM_LAYOUT_GEN9_1D
:
867 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
868 image_align_sa
, phys_level0_sa
,
871 case ISL_DIM_LAYOUT_GEN4_2D
:
872 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
873 image_align_sa
, phys_level0_sa
,
876 case ISL_DIM_LAYOUT_GEN4_3D
:
877 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
878 phys_level0_sa
, phys_slice0_sa
);
884 * Calculate the pitch between physical array slices, in units of rows of
888 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
889 const struct isl_surf_init_info
*restrict info
,
890 const struct isl_tile_info
*tile_info
,
891 enum isl_dim_layout dim_layout
,
892 enum isl_array_pitch_span array_pitch_span
,
893 const struct isl_extent3d
*image_align_sa
,
894 const struct isl_extent4d
*phys_level0_sa
,
895 const struct isl_extent2d
*phys_slice0_sa
)
897 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
898 uint32_t pitch_sa_rows
= 0;
900 switch (dim_layout
) {
901 case ISL_DIM_LAYOUT_GEN9_1D
:
902 /* Each row is an array slice */
905 case ISL_DIM_LAYOUT_GEN4_2D
:
906 switch (array_pitch_span
) {
907 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
908 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
910 case ISL_ARRAY_PITCH_SPAN_FULL
: {
911 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
912 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
913 * Surfaces >> Surface Arrays.
915 uint32_t H0_sa
= phys_level0_sa
->h
;
916 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
918 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
919 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
922 if (ISL_DEV_GEN(dev
) >= 7) {
923 /* The QPitch equation changed slightly in Ivybridge. */
929 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
931 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
932 (info
->height
% 4 == 1)) {
933 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
934 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
936 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
937 * the value calculated in the equation above , for every
938 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
940 * XXX(chadv): Is the errata natural corollary of the physical
941 * layout of interleaved samples?
946 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
951 case ISL_DIM_LAYOUT_GEN4_3D
:
952 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
953 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
956 unreachable("bad isl_dim_layout");
960 assert(pitch_sa_rows
% fmtl
->bh
== 0);
961 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
963 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
965 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
967 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
968 * layout with these alignments in the RT space: Horizontal
969 * Alignment = 128 and Vertical Alignment = 64."
971 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
973 * "For non-multisampled render target's CCS auxiliary surface,
974 * QPitch must be computed with Horizontal Alignment = 128 and
975 * Surface Vertical Alignment = 256. These alignments are only for
976 * CCS buffer and not for associated render target."
978 * The first restriction is already handled by isl_choose_image_alignment_el
979 * but the second restriction, which is an extension of the first, only
980 * applies to qpitch and must be applied here.
982 assert(fmtl
->bh
== 4);
983 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
986 if (ISL_DEV_GEN(dev
) >= 9 &&
987 info
->dim
== ISL_SURF_DIM_3D
&&
988 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
989 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
991 * Tile Mode != Linear: This field must be set to an integer multiple
994 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
997 return pitch_el_rows
;
1001 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1002 const struct isl_tile_info
*tile_info
)
1004 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1005 return tile_info
->phys_extent_B
.width
;
1007 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1008 * RENDER_SURFACE_STATE Surface Pitch (p349):
1010 * - For linear render target surfaces and surfaces accessed with the
1011 * typed data port messages, the pitch must be a multiple of the
1012 * element size for non-YUV surface formats. Pitch must be
1013 * a multiple of 2 * element size for YUV surface formats.
1015 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1016 * ignore because isl doesn't do buffers.]
1018 * - For other linear surfaces, the pitch can be any multiple of
1021 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1022 const uint32_t bs
= fmtl
->bpb
/ 8;
1024 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1025 if (isl_format_is_yuv(surf_info
->format
)) {
1036 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1037 const struct isl_surf_init_info
*info
,
1038 const struct isl_extent2d
*phys_slice0_sa
,
1041 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1042 const uint32_t bs
= fmtl
->bpb
/ 8;
1044 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
1046 uint32_t min_row_pitch
= bs
* (phys_slice0_sa
->w
/ fmtl
->bw
);
1047 min_row_pitch
= MAX2(min_row_pitch
, info
->min_pitch
);
1048 min_row_pitch
= isl_align_npot(min_row_pitch
, alignment
);
1050 return min_row_pitch
;
1054 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1055 const struct isl_surf_init_info
*surf_info
,
1056 const struct isl_tile_info
*tile_info
,
1057 const struct isl_extent2d
*phys_slice0_sa
,
1060 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1062 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1063 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
1065 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1066 const uint32_t total_w_el
= phys_slice0_sa
->width
/ fmtl
->bw
;
1067 const uint32_t total_w_tl
=
1068 isl_align_div(total_w_el
* tile_el_scale
,
1069 tile_info
->logical_extent_el
.width
);
1071 uint32_t min_row_pitch
= total_w_tl
* tile_info
->phys_extent_B
.width
;
1072 min_row_pitch
= MAX2(min_row_pitch
, surf_info
->min_pitch
);
1073 min_row_pitch
= isl_align_npot(min_row_pitch
, alignment
);
1075 return min_row_pitch
;
1079 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1080 const struct isl_surf_init_info
*surf_info
,
1081 const struct isl_tile_info
*tile_info
,
1082 const struct isl_extent2d
*phys_slice0_sa
,
1085 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1086 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_slice0_sa
,
1089 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1090 phys_slice0_sa
, alignment
);
1095 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1096 * size is `bits` bits?
1098 * Hardware pitch fields are offset by 1. For example, if the size of
1099 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1100 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1101 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1104 pitch_in_range(uint32_t n
, uint32_t bits
)
1107 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1111 isl_calc_row_pitch(const struct isl_device
*dev
,
1112 const struct isl_surf_init_info
*surf_info
,
1113 const struct isl_tile_info
*tile_info
,
1114 enum isl_dim_layout dim_layout
,
1115 const struct isl_extent2d
*phys_slice0_sa
,
1116 uint32_t *out_row_pitch
)
1118 const uint32_t alignment
=
1119 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1121 const uint32_t min_row_pitch
=
1122 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_slice0_sa
,
1125 uint32_t row_pitch
= min_row_pitch
;
1127 if (surf_info
->row_pitch
!= 0) {
1128 row_pitch
= surf_info
->row_pitch
;
1130 if (row_pitch
< min_row_pitch
)
1133 if (row_pitch
% alignment
!= 0)
1137 const uint32_t row_pitch_tiles
= row_pitch
/ tile_info
->phys_extent_B
.width
;
1142 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1143 /* SurfacePitch is ignored for this layout. */
1147 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1148 ISL_SURF_USAGE_TEXTURE_BIT
|
1149 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1150 !pitch_in_range(row_pitch
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1153 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1154 ISL_SURF_USAGE_MCS_BIT
)) &&
1155 !pitch_in_range(row_pitch_tiles
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1158 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1159 !pitch_in_range(row_pitch
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1162 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1163 !pitch_in_range(row_pitch
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1166 if (surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
1167 isl_finishme("validate row pitch of stencil surfaces");
1170 *out_row_pitch
= row_pitch
;
1175 * Calculate and apply any padding required for the surface.
1177 * @param[inout] total_h_el is updated with the new height
1178 * @param[out] pad_bytes is overwritten with additional padding requirements.
1181 isl_apply_surface_padding(const struct isl_device
*dev
,
1182 const struct isl_surf_init_info
*restrict info
,
1183 const struct isl_tile_info
*tile_info
,
1184 uint32_t *total_h_el
,
1185 uint32_t *pad_bytes
)
1187 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1191 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1192 * Formats >> Surface Padding Requirements >> Render Target and Media
1195 * The data port accesses data (pixels) outside of the surface if they
1196 * are contained in the same cache request as pixels that are within the
1197 * surface. These pixels will not be returned by the requesting message,
1198 * however if these pixels lie outside of defined pages in the GTT,
1199 * a GTT error will result when the cache request is processed. In
1200 * order to avoid these GTT errors, “padding” at the bottom of the
1201 * surface is sometimes necessary.
1203 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1204 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1206 * ... Lots of padding requirements, all listed separately below.
1209 /* We can safely ignore the first padding requirement, quoted below,
1210 * because isl doesn't do buffers.
1212 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1213 * requirements are different. A buffer must be padded to the next
1214 * multiple of 256 array elements, with an additional 16 bytes added
1215 * beyond that to account for the L1 cache line.
1219 * - For compressed textures [...], padding at the bottom of the surface
1220 * is to an even compressed row.
1222 if (isl_format_is_compressed(info
->format
))
1223 *total_h_el
= isl_align(*total_h_el
, 2);
1226 * - For cube surfaces, an additional two rows of padding are required
1227 * at the bottom of the surface.
1229 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1233 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1234 * additional padding is required. These surfaces require an extra row
1235 * plus 16 bytes of padding at the bottom in addition to the general
1236 * padding requirements.
1238 if (isl_format_is_yuv(info
->format
) &&
1239 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1245 * - For linear surfaces, additional padding of 64 bytes is required at
1246 * the bottom of the surface. This is in addition to the padding
1249 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1252 /* The below text weakens, not strengthens, the padding requirements for
1253 * linear surfaces. Therefore we can safely ignore it.
1255 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1256 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1257 * padding requirement is to the next aligned 64-byte boundary beyond
1258 * the end of the surface. The rest of the padding requirements
1259 * documented above do not apply to these surfaces.
1263 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1264 * height % 4 != 0, the surface must be padded with
1265 * 4-(height % 4)*Surface Pitch # of bytes.
1267 if (ISL_DEV_GEN(dev
) >= 9 &&
1268 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1269 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1270 *total_h_el
= isl_align(*total_h_el
, 4);
1274 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1275 * to 4 times the Surface Pitch # of bytes
1277 if (ISL_DEV_GEN(dev
) >= 9 &&
1278 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1279 info
->dim
== ISL_SURF_DIM_1D
) {
1285 isl_surf_init_s(const struct isl_device
*dev
,
1286 struct isl_surf
*surf
,
1287 const struct isl_surf_init_info
*restrict info
)
1289 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1291 const struct isl_extent4d logical_level0_px
= {
1295 .a
= info
->array_len
,
1298 enum isl_tiling tiling
;
1299 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1302 struct isl_tile_info tile_info
;
1303 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bpb
, &tile_info
))
1306 const enum isl_dim_layout dim_layout
=
1307 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
);
1309 enum isl_msaa_layout msaa_layout
;
1310 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1313 struct isl_extent3d image_align_el
;
1314 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1317 struct isl_extent3d image_align_sa
=
1318 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1320 struct isl_extent4d phys_level0_sa
;
1321 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1323 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1324 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1326 enum isl_array_pitch_span array_pitch_span
=
1327 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1329 struct isl_extent2d phys_slice0_sa
;
1330 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1331 &image_align_sa
, &phys_level0_sa
,
1333 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1334 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1336 const uint32_t array_pitch_el_rows
=
1337 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1338 array_pitch_span
, &image_align_sa
,
1339 &phys_level0_sa
, &phys_slice0_sa
);
1341 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1344 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1347 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1348 &phys_slice0_sa
, &row_pitch
))
1351 uint32_t size
, base_alignment
;
1352 if (tiling
== ISL_TILING_LINEAR
) {
1353 size
= row_pitch
* total_h_el
+ pad_bytes
;
1355 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1357 * "The Base Address for linear render target surfaces and surfaces
1358 * accessed with the typed surface read/write data port messages must
1359 * be element-size aligned, for non-YUV surface formats, or a
1360 * multiple of 2 element-sizes for YUV surface formats. Other linear
1361 * surfaces have no alignment requirements (byte alignment is
1364 base_alignment
= MAX(1, info
->min_alignment
);
1365 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1366 if (isl_format_is_yuv(info
->format
)) {
1367 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1369 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1372 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1374 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1375 const uint32_t total_h_tl
=
1376 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1378 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1380 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1381 tile_info
.phys_extent_B
.height
;
1382 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1383 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1386 *surf
= (struct isl_surf
) {
1388 .dim_layout
= dim_layout
,
1389 .msaa_layout
= msaa_layout
,
1391 .format
= info
->format
,
1393 .levels
= info
->levels
,
1394 .samples
= info
->samples
,
1396 .image_alignment_el
= image_align_el
,
1397 .logical_level0_px
= logical_level0_px
,
1398 .phys_level0_sa
= phys_level0_sa
,
1401 .alignment
= base_alignment
,
1402 .row_pitch
= row_pitch
,
1403 .array_pitch_el_rows
= array_pitch_el_rows
,
1404 .array_pitch_span
= array_pitch_span
,
1406 .usage
= info
->usage
,
1413 isl_surf_get_tile_info(const struct isl_device
*dev
,
1414 const struct isl_surf
*surf
,
1415 struct isl_tile_info
*tile_info
)
1417 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1418 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bpb
, tile_info
);
1422 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1423 const struct isl_surf
*surf
,
1424 struct isl_surf
*hiz_surf
)
1426 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1428 /* Multisampled depth is always interleaved */
1429 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1430 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1432 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1434 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1435 * Target View Extent, and Depth Coordinate Offset X/Y of the
1436 * hierarchical depth buffer are inherited from the depth buffer. The
1437 * height and width of the hierarchical depth buffer that must be
1438 * allocated are computed by the following formulas, where HZ is the
1439 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1440 * Z_Width, and Z_Depth values given in these formulas are those present
1441 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1443 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1444 * being applied to the table below if Number of Multisamples is set to
1445 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1446 * Z_Width must be multiplied by 4 before being applied to the table
1447 * below if Number of Multisamples is set to NUMSAMPLES_8."
1449 * In the Sky Lake PRM, the second paragraph is replaced with this:
1451 * "The Z_Height and Z_Width values must equal those present in
1452 * 3DSTATE_DEPTH_BUFFER incremented by one."
1454 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1455 * block corresponds to a region of 8x4 samples in the primary depth
1456 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1457 * a region of 8x4 pixels in the primary depth surface regardless of the
1458 * number of samples. The dimensions of a HiZ block in both pixels and
1459 * samples are given in the table below:
1461 * | SNB - BDW | SKL+
1462 * ------+-----------+-------------
1463 * 1x | 8 x 4 sa | 8 x 4 sa
1464 * MSAA | 8 x 4 px | 8 x 4 px
1465 * ------+-----------+-------------
1466 * 2x | 8 x 4 sa | 16 x 4 sa
1467 * MSAA | 4 x 4 px | 8 x 4 px
1468 * ------+-----------+-------------
1469 * 4x | 8 x 4 sa | 16 x 8 sa
1470 * MSAA | 4 x 2 px | 8 x 4 px
1471 * ------+-----------+-------------
1472 * 8x | 8 x 4 sa | 32 x 8 sa
1473 * MSAA | 2 x 2 px | 8 x 4 px
1474 * ------+-----------+-------------
1475 * 16x | N/A | 32 x 16 sa
1476 * MSAA | N/A | 8 x 4 px
1477 * ------+-----------+-------------
1479 * There are a number of different ways that this discrepency could be
1480 * handled. The way we have chosen is to simply make MSAA HiZ have the
1481 * same number of samples as the parent surface pre-Sky Lake and always be
1482 * single-sampled on Sky Lake and above. Since the block sizes of
1483 * compressed formats are given in samples, this neatly handles everything
1484 * without the need for additional HiZ formats with different block sizes
1487 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1489 return isl_surf_init(dev
, hiz_surf
,
1491 .format
= ISL_FORMAT_HIZ
,
1492 .width
= surf
->logical_level0_px
.width
,
1493 .height
= surf
->logical_level0_px
.height
,
1494 .depth
= surf
->logical_level0_px
.depth
,
1495 .levels
= surf
->levels
,
1496 .array_len
= surf
->logical_level0_px
.array_len
,
1498 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1499 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1503 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1504 const struct isl_surf
*surf
,
1505 struct isl_surf
*mcs_surf
)
1507 /* It must be multisampled with an array layout */
1508 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1510 /* The following are true of all multisampled surfaces */
1511 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1512 assert(surf
->levels
== 1);
1513 assert(surf
->logical_level0_px
.depth
== 1);
1515 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1516 * bits which means the maximum pitch of a compression surface is 512
1517 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1518 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1519 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1520 * and 8x, we have enough room for the full 16k supported by the hardware.
1522 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1525 enum isl_format mcs_format
;
1526 switch (surf
->samples
) {
1527 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1528 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1529 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1530 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1532 unreachable("Invalid sample count");
1535 return isl_surf_init(dev
, mcs_surf
,
1536 .dim
= ISL_SURF_DIM_2D
,
1537 .format
= mcs_format
,
1538 .width
= surf
->logical_level0_px
.width
,
1539 .height
= surf
->logical_level0_px
.height
,
1542 .array_len
= surf
->logical_level0_px
.array_len
,
1543 .samples
= 1, /* MCS surfaces are really single-sampled */
1544 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1545 .tiling_flags
= ISL_TILING_Y0_BIT
);
1549 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1550 const struct isl_surf
*surf
,
1551 struct isl_surf
*ccs_surf
)
1553 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1554 assert(ISL_DEV_GEN(dev
) >= 7);
1556 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1559 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1562 if (isl_format_is_compressed(surf
->format
))
1565 /* TODO: More conditions where it can fail. */
1567 enum isl_format ccs_format
;
1568 if (ISL_DEV_GEN(dev
) >= 9) {
1569 if (!isl_tiling_is_any_y(surf
->tiling
))
1572 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1573 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1574 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1575 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1579 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1580 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1581 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1582 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1583 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1587 } else if (surf
->tiling
== ISL_TILING_X
) {
1588 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1589 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1590 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1591 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1599 return isl_surf_init(dev
, ccs_surf
,
1601 .format
= ccs_format
,
1602 .width
= surf
->logical_level0_px
.width
,
1603 .height
= surf
->logical_level0_px
.height
,
1604 .depth
= surf
->logical_level0_px
.depth
,
1605 .levels
= surf
->levels
,
1606 .array_len
= surf
->logical_level0_px
.array_len
,
1608 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1609 .tiling_flags
= ISL_TILING_CCS_BIT
);
1613 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1614 const struct isl_surf_fill_state_info
*restrict info
)
1617 isl_surf_usage_flags_t _base_usage
=
1618 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1619 ISL_SURF_USAGE_TEXTURE_BIT
|
1620 ISL_SURF_USAGE_STORAGE_BIT
);
1621 /* They may only specify one of the above bits at a time */
1622 assert(__builtin_popcount(_base_usage
) == 1);
1623 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1624 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1627 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1628 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1629 info
->surf
->logical_level0_px
.depth
);
1631 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1632 info
->surf
->logical_level0_px
.array_len
);
1635 switch (ISL_DEV_GEN(dev
)) {
1637 if (ISL_DEV_IS_G4X(dev
)) {
1638 /* G45 surface state is the same as gen5 */
1639 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1641 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1645 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1648 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1651 if (ISL_DEV_IS_HASWELL(dev
)) {
1652 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1654 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1658 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1661 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1664 assert(!"Cannot fill surface state for this gen");
1669 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1670 const struct isl_buffer_fill_state_info
*restrict info
)
1672 switch (ISL_DEV_GEN(dev
)) {
1675 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1676 isl_gen5_buffer_fill_state_s(state
, info
);
1679 isl_gen6_buffer_fill_state_s(state
, info
);
1682 if (ISL_DEV_IS_HASWELL(dev
)) {
1683 isl_gen75_buffer_fill_state_s(state
, info
);
1685 isl_gen7_buffer_fill_state_s(state
, info
);
1689 isl_gen8_buffer_fill_state_s(state
, info
);
1692 isl_gen9_buffer_fill_state_s(state
, info
);
1695 assert(!"Cannot fill surface state for this gen");
1700 * A variant of isl_surf_get_image_offset_sa() specific to
1701 * ISL_DIM_LAYOUT_GEN4_2D.
1704 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1705 uint32_t level
, uint32_t logical_array_layer
,
1706 uint32_t *x_offset_sa
,
1707 uint32_t *y_offset_sa
)
1709 assert(level
< surf
->levels
);
1710 if (surf
->dim
== ISL_SURF_DIM_3D
)
1711 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1713 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1715 const struct isl_extent3d image_align_sa
=
1716 isl_surf_get_image_alignment_sa(surf
);
1718 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1719 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1721 const uint32_t phys_layer
= logical_array_layer
*
1722 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1725 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1727 for (uint32_t l
= 0; l
< level
; ++l
) {
1729 uint32_t W
= isl_minify(W0
, l
);
1730 x
+= isl_align_npot(W
, image_align_sa
.w
);
1732 uint32_t H
= isl_minify(H0
, l
);
1733 y
+= isl_align_npot(H
, image_align_sa
.h
);
1742 * A variant of isl_surf_get_image_offset_sa() specific to
1743 * ISL_DIM_LAYOUT_GEN4_3D.
1746 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1747 uint32_t level
, uint32_t logical_z_offset_px
,
1748 uint32_t *x_offset_sa
,
1749 uint32_t *y_offset_sa
)
1751 assert(level
< surf
->levels
);
1752 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1753 assert(surf
->phys_level0_sa
.array_len
== 1);
1755 const struct isl_extent3d image_align_sa
=
1756 isl_surf_get_image_alignment_sa(surf
);
1758 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1759 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1760 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1765 for (uint32_t l
= 0; l
< level
; ++l
) {
1766 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1767 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1768 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1770 y
+= level_h
* max_layers_vert
;
1773 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1774 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1775 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1777 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1779 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1780 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1787 * A variant of isl_surf_get_image_offset_sa() specific to
1788 * ISL_DIM_LAYOUT_GEN9_1D.
1791 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1792 uint32_t level
, uint32_t layer
,
1793 uint32_t *x_offset_sa
,
1794 uint32_t *y_offset_sa
)
1796 assert(level
< surf
->levels
);
1797 assert(layer
< surf
->phys_level0_sa
.array_len
);
1798 assert(surf
->phys_level0_sa
.height
== 1);
1799 assert(surf
->phys_level0_sa
.depth
== 1);
1800 assert(surf
->samples
== 1);
1802 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1803 const struct isl_extent3d image_align_sa
=
1804 isl_surf_get_image_alignment_sa(surf
);
1808 for (uint32_t l
= 0; l
< level
; ++l
) {
1809 uint32_t W
= isl_minify(W0
, l
);
1810 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1816 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1820 * Calculate the offset, in units of surface samples, to a subimage in the
1823 * @invariant level < surface levels
1824 * @invariant logical_array_layer < logical array length of surface
1825 * @invariant logical_z_offset_px < logical depth of surface at level
1828 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1830 uint32_t logical_array_layer
,
1831 uint32_t logical_z_offset_px
,
1832 uint32_t *x_offset_sa
,
1833 uint32_t *y_offset_sa
)
1835 assert(level
< surf
->levels
);
1836 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1837 assert(logical_z_offset_px
1838 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1840 switch (surf
->dim_layout
) {
1841 case ISL_DIM_LAYOUT_GEN9_1D
:
1842 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1843 x_offset_sa
, y_offset_sa
);
1845 case ISL_DIM_LAYOUT_GEN4_2D
:
1846 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1847 + logical_z_offset_px
,
1848 x_offset_sa
, y_offset_sa
);
1850 case ISL_DIM_LAYOUT_GEN4_3D
:
1851 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1852 x_offset_sa
, y_offset_sa
);
1856 unreachable("not reached");
1861 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1863 uint32_t logical_array_layer
,
1864 uint32_t logical_z_offset_px
,
1865 uint32_t *x_offset_el
,
1866 uint32_t *y_offset_el
)
1868 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1870 assert(level
< surf
->levels
);
1871 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1872 assert(logical_z_offset_px
1873 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1875 uint32_t x_offset_sa
, y_offset_sa
;
1876 isl_surf_get_image_offset_sa(surf
, level
,
1877 logical_array_layer
,
1878 logical_z_offset_px
,
1882 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1883 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1887 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1888 enum isl_tiling tiling
,
1891 uint32_t total_x_offset_el
,
1892 uint32_t total_y_offset_el
,
1893 uint32_t *base_address_offset
,
1894 uint32_t *x_offset_el
,
1895 uint32_t *y_offset_el
)
1897 if (tiling
== ISL_TILING_LINEAR
) {
1898 *base_address_offset
= total_y_offset_el
* row_pitch
+
1899 total_x_offset_el
* bs
;
1905 const uint32_t bpb
= bs
* 8;
1907 struct isl_tile_info tile_info
;
1908 isl_tiling_get_info(dev
, tiling
, bpb
, &tile_info
);
1910 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1912 /* For non-power-of-two formats, we need the address to be both tile and
1913 * element-aligned. The easiest way to achieve this is to work with a tile
1914 * that is three times as wide as the regular tile.
1916 * The tile info returned by get_tile_info has a logical size that is an
1917 * integer number of tile_info.format_bpb size elements. To scale the
1918 * tile, we scale up the physical width and then treat the logical tile
1919 * size as if it has bpb size elements.
1921 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
1922 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
1924 /* Compute the offset into the tile */
1925 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
1926 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
1928 /* Compute the offset of the tile in units of whole tiles */
1929 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
1930 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
1932 *base_address_offset
=
1933 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
1934 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
1938 isl_surf_get_depth_format(const struct isl_device
*dev
,
1939 const struct isl_surf
*surf
)
1941 /* Support for separate stencil buffers began in gen5. Support for
1942 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1943 * those that supported separate and interleaved stencil, were gen5 and
1946 * For a list of all available formats, see the Sandybridge PRM >> Volume
1947 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1951 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1953 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1956 assert(ISL_DEV_GEN(dev
) < 7);
1958 switch (surf
->format
) {
1960 unreachable("bad isl depth format");
1961 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1962 assert(ISL_DEV_GEN(dev
) < 7);
1963 return 0; /* D32_FLOAT_S8X24_UINT */
1964 case ISL_FORMAT_R32_FLOAT
:
1965 assert(!has_stencil
);
1966 return 1; /* D32_FLOAT */
1967 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1969 assert(ISL_DEV_GEN(dev
) < 7);
1970 return 2; /* D24_UNORM_S8_UINT */
1972 assert(ISL_DEV_GEN(dev
) >= 5);
1973 return 3; /* D24_UNORM_X8_UINT */
1975 case ISL_FORMAT_R16_UNORM
:
1976 assert(!has_stencil
);
1977 return 5; /* D16_UNORM */