2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct brw_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 ISL_DEV_GEN_SANITIZE(dev
);
63 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
110 uint32_t format_block_size
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_block_size
;
114 uint32_t width
, height
;
119 case ISL_TILING_LINEAR
:
135 /* XXX: Should W tile be same as Y? */
141 case ISL_TILING_Ys
: {
142 if (ISL_DEV_GEN(dev
) < 9)
145 if (!isl_is_pow2(bs
))
148 bool is_Ys
= tiling
== ISL_TILING_Ys
;
150 width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
151 height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
156 unreachable("not reached");
159 *tile_info
= (struct isl_tile_info
) {
163 .size
= width
* height
,
170 * @param[out] tiling is set only on success
173 isl_surf_choose_tiling(const struct isl_device
*dev
,
174 const struct isl_surf_init_info
*restrict info
,
175 enum isl_tiling
*tiling
)
177 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
179 /* Filter if multiple tiling options are given */
180 if (!isl_is_pow2(tiling_flags
)) {
181 if (ISL_DEV_GEN(dev
) >= 7) {
182 gen7_filter_tiling(dev
, info
, &tiling_flags
);
184 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
185 gen7_filter_tiling(dev
, info
, &tiling_flags
);
189 #define CHOOSE(__tiling) \
191 if (tiling_flags & (1u << (__tiling))) { \
192 *tiling = (__tiling); \
197 /* Of the tiling modes remaining, choose the one that offers the best
201 if (info
->dim
== ISL_SURF_DIM_1D
) {
202 /* Prefer linear for 1D surfaces because they do not benefit from
203 * tiling. To the contrary, tiling leads to wasted memory and poor
204 * memory locality due to the swizzling and alignment restrictions
205 * required in tiled surfaces.
207 CHOOSE(ISL_TILING_LINEAR
);
210 CHOOSE(ISL_TILING_Ys
);
211 CHOOSE(ISL_TILING_Yf
);
212 CHOOSE(ISL_TILING_Y0
);
213 CHOOSE(ISL_TILING_X
);
214 CHOOSE(ISL_TILING_W
);
215 CHOOSE(ISL_TILING_LINEAR
);
219 /* No tiling mode accomodates the inputs. */
224 isl_choose_msaa_layout(const struct isl_device
*dev
,
225 const struct isl_surf_init_info
*info
,
226 enum isl_tiling tiling
,
227 enum isl_msaa_layout
*msaa_layout
)
229 if (ISL_DEV_GEN(dev
) >= 8) {
230 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
231 } else if (ISL_DEV_GEN(dev
) >= 7) {
232 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
233 } else if (ISL_DEV_GEN(dev
) >= 6) {
234 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
236 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
241 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
242 uint32_t *width
, uint32_t *height
)
244 assert(isl_is_pow2(samples
));
246 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
249 * If the surface is multisampled and it is a depth or stencil surface
250 * or Multisampled Surface StorageFormat in SURFACE_STATE is
251 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
255 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
257 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
260 static enum isl_array_pitch_span
261 isl_choose_array_pitch_span(const struct isl_device
*dev
,
262 const struct isl_surf_init_info
*restrict info
,
263 enum isl_dim_layout dim_layout
,
264 const struct isl_extent4d
*phys_level0_sa
)
266 switch (dim_layout
) {
267 case ISL_DIM_LAYOUT_GEN9_1D
:
268 case ISL_DIM_LAYOUT_GEN4_2D
:
269 if (ISL_DEV_GEN(dev
) >= 8) {
270 /* QPitch becomes programmable in Broadwell. So choose the
271 * most compact QPitch possible in order to conserve memory.
273 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
274 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
276 * - Software must ensure that this field is set to a value
277 * sufficiently large such that the array slices in the surface
278 * do not overlap. Refer to the Memory Data Formats section for
279 * information on how surfaces are stored in memory.
281 * - This field specifies the distance in rows between array
282 * slices. It is used only in the following cases:
284 * - Surface Array is enabled OR
285 * - Number of Mulitsamples is not NUMSAMPLES_1 and
286 * Multisampled Surface Storage Format set to MSFMT_MSS OR
287 * - Surface Type is SURFTYPE_CUBE
289 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
290 } else if (ISL_DEV_GEN(dev
) >= 7) {
291 /* Note that Ivybridge introduces
292 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
293 * driver more control over the QPitch.
296 if (phys_level0_sa
->array_len
== 1) {
297 /* The hardware will never use the QPitch. So choose the most
298 * compact QPitch possible in order to conserve memory.
300 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
303 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
304 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
305 * Section 6.18.4.7: Surface Arrays (p112):
307 * If Surface Array Spacing is set to ARYSPC_FULL (note that
308 * the depth buffer and stencil buffer have an implied value of
311 return ISL_ARRAY_PITCH_SPAN_FULL
;
314 if (info
->levels
== 1) {
315 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
318 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
321 return ISL_ARRAY_PITCH_SPAN_FULL
;
322 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
323 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
324 isl_surf_usage_is_stencil(info
->usage
)) {
325 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
326 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
328 * The separate stencil buffer does not support mip mapping, thus
329 * the storage for LODs other than LOD 0 is not needed.
331 assert(info
->levels
== 1);
332 assert(phys_level0_sa
->array_len
== 1);
333 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
335 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
336 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
337 isl_surf_usage_is_stencil(info
->usage
)) {
338 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
339 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
341 * The separate stencil buffer does not support mip mapping,
342 * thus the storage for LODs other than LOD 0 is not needed.
344 assert(info
->levels
== 1);
345 assert(phys_level0_sa
->array_len
== 1);
346 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
349 if (phys_level0_sa
->array_len
== 1) {
350 /* The hardware will never use the QPitch. So choose the most
351 * compact QPitch possible in order to conserve memory.
353 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
356 return ISL_ARRAY_PITCH_SPAN_FULL
;
359 case ISL_DIM_LAYOUT_GEN4_3D
:
360 /* The hardware will never use the QPitch. So choose the most
361 * compact QPitch possible in order to conserve memory.
363 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
366 unreachable("bad isl_dim_layout");
367 return ISL_ARRAY_PITCH_SPAN_FULL
;
371 isl_choose_image_alignment_el(const struct isl_device
*dev
,
372 const struct isl_surf_init_info
*restrict info
,
373 enum isl_tiling tiling
,
374 enum isl_msaa_layout msaa_layout
,
375 struct isl_extent3d
*image_align_el
)
377 if (ISL_DEV_GEN(dev
) >= 9) {
378 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
380 } else if (ISL_DEV_GEN(dev
) >= 8) {
381 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
383 } else if (ISL_DEV_GEN(dev
) >= 7) {
384 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
386 } else if (ISL_DEV_GEN(dev
) >= 6) {
387 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
390 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
395 static enum isl_dim_layout
396 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
397 enum isl_surf_dim logical_dim
)
399 if (ISL_DEV_GEN(dev
) >= 9) {
400 switch (logical_dim
) {
401 case ISL_SURF_DIM_1D
:
402 return ISL_DIM_LAYOUT_GEN9_1D
;
403 case ISL_SURF_DIM_2D
:
404 case ISL_SURF_DIM_3D
:
405 return ISL_DIM_LAYOUT_GEN4_2D
;
408 switch (logical_dim
) {
409 case ISL_SURF_DIM_1D
:
410 case ISL_SURF_DIM_2D
:
411 return ISL_DIM_LAYOUT_GEN4_2D
;
412 case ISL_SURF_DIM_3D
:
413 return ISL_DIM_LAYOUT_GEN4_3D
;
417 unreachable("bad isl_surf_dim");
418 return ISL_DIM_LAYOUT_GEN4_2D
;
422 * Calculate the physical extent of the surface's first level, in units of
423 * surface samples. The result is aligned to the format's compression block.
426 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
427 const struct isl_surf_init_info
*restrict info
,
428 enum isl_dim_layout dim_layout
,
429 enum isl_tiling tiling
,
430 enum isl_msaa_layout msaa_layout
,
431 struct isl_extent4d
*phys_level0_sa
)
433 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
435 if (isl_format_is_yuv(info
->format
))
436 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
439 case ISL_SURF_DIM_1D
:
440 assert(info
->height
== 1);
441 assert(info
->depth
== 1);
442 assert(info
->samples
== 1);
443 assert(!isl_format_is_compressed(info
->format
));
445 switch (dim_layout
) {
446 case ISL_DIM_LAYOUT_GEN4_3D
:
447 unreachable("bad isl_dim_layout");
449 case ISL_DIM_LAYOUT_GEN9_1D
:
450 case ISL_DIM_LAYOUT_GEN4_2D
:
451 *phys_level0_sa
= (struct isl_extent4d
) {
455 .a
= info
->array_len
,
461 case ISL_SURF_DIM_2D
:
462 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
464 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
465 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
467 switch (msaa_layout
) {
468 case ISL_MSAA_LAYOUT_NONE
:
469 assert(info
->depth
== 1);
470 assert(info
->samples
== 1);
472 *phys_level0_sa
= (struct isl_extent4d
) {
473 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
474 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
476 .a
= info
->array_len
,
480 case ISL_MSAA_LAYOUT_ARRAY
:
481 assert(info
->depth
== 1);
482 assert(info
->array_len
== 1);
483 assert(!isl_format_is_compressed(info
->format
));
485 *phys_level0_sa
= (struct isl_extent4d
) {
493 case ISL_MSAA_LAYOUT_INTERLEAVED
:
494 assert(info
->depth
== 1);
495 assert(info
->array_len
== 1);
496 assert(!isl_format_is_compressed(info
->format
));
498 *phys_level0_sa
= (struct isl_extent4d
) {
505 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
512 case ISL_SURF_DIM_3D
:
513 assert(info
->array_len
== 1);
514 assert(info
->samples
== 1);
517 isl_finishme("%s:%s: compression block with depth > 1",
521 switch (dim_layout
) {
522 case ISL_DIM_LAYOUT_GEN9_1D
:
523 unreachable("bad isl_dim_layout");
525 case ISL_DIM_LAYOUT_GEN4_2D
:
526 assert(ISL_DEV_GEN(dev
) >= 9);
528 *phys_level0_sa
= (struct isl_extent4d
) {
529 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
530 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
536 case ISL_DIM_LAYOUT_GEN4_3D
:
537 assert(ISL_DEV_GEN(dev
) < 9);
538 *phys_level0_sa
= (struct isl_extent4d
) {
539 .w
= isl_align(info
->width
, fmtl
->bw
),
540 .h
= isl_align(info
->height
, fmtl
->bh
),
551 * A variant of isl_calc_phys_slice0_extent_sa() specific to
552 * ISL_DIM_LAYOUT_GEN4_2D.
555 isl_calc_phys_slice0_extent_sa_gen4_2d(
556 const struct isl_device
*dev
,
557 const struct isl_surf_init_info
*restrict info
,
558 enum isl_msaa_layout msaa_layout
,
559 const struct isl_extent3d
*image_align_sa
,
560 const struct isl_extent4d
*phys_level0_sa
,
561 struct isl_extent2d
*phys_slice0_sa
)
563 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
565 assert(phys_level0_sa
->depth
== 1);
567 if (info
->levels
== 1 && msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
) {
568 /* Do not pad the surface to the image alignment. Instead, pad it only
569 * to the pixel format's block alignment.
571 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
572 * cycles on the below mipmap layout caluclations. Reducing the
573 * alignment here is safe because we later align the row pitch and array
574 * pitch to the tile boundary. It is safe even for
575 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
576 * to accomodate the interleaved samples.
578 * For linear surfaces, reducing the alignment here permits us to later
579 * choose an arbitrary, non-aligned row pitch. If the surface backs
580 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
581 * VkBufferImageCopy::bufferRowLength.
583 *phys_slice0_sa
= (struct isl_extent2d
) {
584 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
585 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
590 uint32_t slice_top_w
= 0;
591 uint32_t slice_bottom_w
= 0;
592 uint32_t slice_left_h
= 0;
593 uint32_t slice_right_h
= 0;
595 uint32_t W0
= phys_level0_sa
->w
;
596 uint32_t H0
= phys_level0_sa
->h
;
598 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
599 uint32_t W
= isl_minify(W0
, l
);
600 uint32_t H
= isl_minify(H0
, l
);
602 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
603 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
606 * If the surface is multisampled and it is a depth or stencil
607 * surface or Multisampled Surface StorageFormat in
608 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
609 * adjusted as follows before proceeding: [...]
611 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
614 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
615 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
632 *phys_slice0_sa
= (struct isl_extent2d
) {
633 .w
= MAX(slice_top_w
, slice_bottom_w
),
634 .h
= MAX(slice_left_h
, slice_right_h
),
639 * A variant of isl_calc_phys_slice0_extent_sa() specific to
640 * ISL_DIM_LAYOUT_GEN4_3D.
643 isl_calc_phys_slice0_extent_sa_gen4_3d(
644 const struct isl_device
*dev
,
645 const struct isl_surf_init_info
*restrict info
,
646 const struct isl_extent3d
*image_align_sa
,
647 const struct isl_extent4d
*phys_level0_sa
,
648 struct isl_extent2d
*phys_slice0_sa
)
650 assert(info
->samples
== 1);
651 assert(phys_level0_sa
->array_len
== 1);
653 uint32_t slice_w
= 0;
654 uint32_t slice_h
= 0;
656 uint32_t W0
= phys_level0_sa
->w
;
657 uint32_t H0
= phys_level0_sa
->h
;
658 uint32_t D0
= phys_level0_sa
->d
;
660 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
661 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
662 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
663 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
665 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
666 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
668 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
669 slice_h
+= level_h
* max_layers_vert
;
672 *phys_slice0_sa
= (struct isl_extent2d
) {
679 * A variant of isl_calc_phys_slice0_extent_sa() specific to
680 * ISL_DIM_LAYOUT_GEN9_1D.
683 isl_calc_phys_slice0_extent_sa_gen9_1d(
684 const struct isl_device
*dev
,
685 const struct isl_surf_init_info
*restrict info
,
686 const struct isl_extent3d
*image_align_sa
,
687 const struct isl_extent4d
*phys_level0_sa
,
688 struct isl_extent2d
*phys_slice0_sa
)
690 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
692 assert(phys_level0_sa
->height
== 1);
693 assert(phys_level0_sa
->depth
== 1);
694 assert(info
->samples
== 1);
695 assert(image_align_sa
->w
>= fmtl
->bw
);
697 uint32_t slice_w
= 0;
698 const uint32_t W0
= phys_level0_sa
->w
;
700 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
701 uint32_t W
= isl_minify(W0
, l
);
702 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
707 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
711 * Calculate the physical extent of the surface's first array slice, in units
712 * of surface samples. If the surface is multi-leveled, then the result will
713 * be aligned to \a image_align_sa.
716 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
717 const struct isl_surf_init_info
*restrict info
,
718 enum isl_dim_layout dim_layout
,
719 enum isl_msaa_layout msaa_layout
,
720 const struct isl_extent3d
*image_align_sa
,
721 const struct isl_extent4d
*phys_level0_sa
,
722 struct isl_extent2d
*phys_slice0_sa
)
724 switch (dim_layout
) {
725 case ISL_DIM_LAYOUT_GEN9_1D
:
726 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
727 image_align_sa
, phys_level0_sa
,
730 case ISL_DIM_LAYOUT_GEN4_2D
:
731 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
732 image_align_sa
, phys_level0_sa
,
735 case ISL_DIM_LAYOUT_GEN4_3D
:
736 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
737 phys_level0_sa
, phys_slice0_sa
);
743 * Calculate the pitch between physical array slices, in units of rows of
747 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
748 const struct isl_surf_init_info
*restrict info
,
749 const struct isl_tile_info
*tile_info
,
750 enum isl_dim_layout dim_layout
,
751 enum isl_array_pitch_span array_pitch_span
,
752 const struct isl_extent3d
*image_align_sa
,
753 const struct isl_extent4d
*phys_level0_sa
,
754 const struct isl_extent2d
*phys_slice0_sa
)
756 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
757 uint32_t pitch_sa_rows
= 0;
759 switch (dim_layout
) {
760 case ISL_DIM_LAYOUT_GEN9_1D
:
761 /* Each row is an array slice */
764 case ISL_DIM_LAYOUT_GEN4_2D
:
765 switch (array_pitch_span
) {
766 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
767 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
769 case ISL_ARRAY_PITCH_SPAN_FULL
: {
770 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
771 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
772 * Surfaces >> Surface Arrays.
774 uint32_t H0_sa
= phys_level0_sa
->h
;
775 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
777 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
778 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
781 if (ISL_DEV_GEN(dev
) >= 7) {
782 /* The QPitch equation changed slightly in Ivybridge. */
788 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
790 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
791 (info
->height
% 4 == 1)) {
792 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
793 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
795 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
796 * the value calculated in the equation above , for every
797 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
799 * XXX(chadv): Is the errata natural corollary of the physical
800 * layout of interleaved samples?
805 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
810 case ISL_DIM_LAYOUT_GEN4_3D
:
811 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
812 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
815 unreachable("bad isl_dim_layout");
819 assert(pitch_sa_rows
% fmtl
->bh
== 0);
820 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
822 if (ISL_DEV_GEN(dev
) >= 9 &&
823 info
->dim
== ISL_SURF_DIM_3D
&&
824 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
825 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
827 * Tile Mode != Linear: This field must be set to an integer multiple
830 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->height
);
833 return pitch_el_rows
;
837 * Calculate the pitch of each surface row, in bytes.
840 isl_calc_row_pitch(const struct isl_device
*dev
,
841 const struct isl_surf_init_info
*restrict info
,
842 const struct isl_tile_info
*tile_info
,
843 const struct isl_extent3d
*image_align_sa
,
844 const struct isl_extent2d
*phys_slice0_sa
)
846 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
848 uint32_t row_pitch
= info
->min_pitch
;
850 /* First, align the surface to a cache line boundary, as the PRM explains
853 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
854 * Formats >> Surface Padding Requirements >> Render Target and Media
857 * The data port accesses data (pixels) outside of the surface if they
858 * are contained in the same cache request as pixels that are within the
859 * surface. These pixels will not be returned by the requesting message,
860 * however if these pixels lie outside of defined pages in the GTT,
861 * a GTT error will result when the cache request is processed. In order
862 * to avoid these GTT errors, “padding” at the bottom of the surface is
863 * sometimes necessary.
865 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
866 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
868 * The sampling engine accesses texels outside of the surface if they
869 * are contained in the same cache line as texels that are within the
870 * surface. These texels will not participate in any calculation
871 * performed by the sampling engine and will not affect the result of
872 * any sampling engine operation, however if these texels lie outside of
873 * defined pages in the GTT, a GTT error will result when the cache line
874 * is accessed. In order to avoid these GTT errors, “padding” at the
875 * bottom and right side of a sampling engine surface is sometimes
878 * It is possible that a cache line will straddle a page boundary if the
879 * base address or pitch is not aligned. All pages included in the cache
880 * lines that are part of the surface must map to valid GTT entries to
881 * avoid errors. To determine the necessary padding on the bottom and
882 * right side of the surface, refer to the table in Alignment Unit Size
883 * section for the i and j parameters for the surface format in use. The
884 * surface must then be extended to the next multiple of the alignment
885 * unit size in each dimension, and all texels contained in this
886 * extended surface must have valid GTT entries.
888 * For example, suppose the surface size is 15 texels by 10 texels and
889 * the alignment parameters are i=4 and j=2. In this case, the extended
890 * surface would be 16 by 10. Note that these calculations are done in
891 * texels, and must be converted to bytes based on the surface format
892 * being used to determine whether additional pages need to be defined.
894 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
895 row_pitch
= MAX(row_pitch
, fmtl
->bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
897 switch (tile_info
->tiling
) {
898 case ISL_TILING_LINEAR
:
899 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
900 * RENDER_SURFACE_STATE Surface Pitch (p349):
902 * - For linear render target surfaces and surfaces accessed with the
903 * typed data port messages, the pitch must be a multiple of the
904 * element size for non-YUV surface formats. Pitch must be
905 * a multiple of 2 * element size for YUV surface formats.
907 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
908 * ignore because isl doesn't do buffers.]
910 * - For other linear surfaces, the pitch can be any multiple of
913 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
914 if (isl_format_is_yuv(info
->format
)) {
915 row_pitch
= isl_align_npot(row_pitch
, 2 * fmtl
->bs
);
917 row_pitch
= isl_align_npot(row_pitch
, fmtl
->bs
);
922 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
923 * RENDER_SURFACE_STATE Surface Pitch (p349):
925 * - For tiled surfaces, the pitch must be a multiple of the tile
928 row_pitch
= isl_align(row_pitch
, tile_info
->width
);
936 * Calculate the surface's total height, including padding, in units of
940 isl_calc_total_height_el(const struct isl_device
*dev
,
941 const struct isl_surf_init_info
*restrict info
,
942 const struct isl_tile_info
*tile_info
,
943 uint32_t phys_array_len
,
945 uint32_t array_pitch_el_rows
)
947 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
949 uint32_t total_h_el
= phys_array_len
* array_pitch_el_rows
;
950 uint32_t pad_bytes
= 0;
952 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
953 * Formats >> Surface Padding Requirements >> Render Target and Media
956 * The data port accesses data (pixels) outside of the surface if they
957 * are contained in the same cache request as pixels that are within the
958 * surface. These pixels will not be returned by the requesting message,
959 * however if these pixels lie outside of defined pages in the GTT,
960 * a GTT error will result when the cache request is processed. In
961 * order to avoid these GTT errors, “padding” at the bottom of the
962 * surface is sometimes necessary.
964 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
965 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
967 * ... Lots of padding requirements, all listed separately below.
970 /* We can safely ignore the first padding requirement, quoted below,
971 * because isl doesn't do buffers.
973 * - [pre-BDW] For buffers, which have no inherent “height,” padding
974 * requirements are different. A buffer must be padded to the next
975 * multiple of 256 array elements, with an additional 16 bytes added
976 * beyond that to account for the L1 cache line.
980 * - For compressed textures [...], padding at the bottom of the surface
981 * is to an even compressed row.
983 if (isl_format_is_compressed(info
->format
))
984 total_h_el
= isl_align(total_h_el
, 2);
987 * - For cube surfaces, an additional two rows of padding are required
988 * at the bottom of the surface.
990 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
994 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
995 * additional padding is required. These surfaces require an extra row
996 * plus 16 bytes of padding at the bottom in addition to the general
997 * padding requirements.
999 if (isl_format_is_yuv(info
->format
) &&
1000 (fmtl
->bs
== 96 || fmtl
->bs
== 48|| fmtl
->bs
== 24)) {
1006 * - For linear surfaces, additional padding of 64 bytes is required at
1007 * the bottom of the surface. This is in addition to the padding
1010 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1013 /* The below text weakens, not strengthens, the padding requirements for
1014 * linear surfaces. Therefore we can safely ignore it.
1016 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1017 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1018 * padding requirement is to the next aligned 64-byte boundary beyond
1019 * the end of the surface. The rest of the padding requirements
1020 * documented above do not apply to these surfaces.
1024 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1025 * height % 4 != 0, the surface must be padded with
1026 * 4-(height % 4)*Surface Pitch # of bytes.
1028 if (ISL_DEV_GEN(dev
) >= 9 &&
1029 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1030 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1031 total_h_el
= isl_align(total_h_el
, 4);
1035 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1036 * to 4 times the Surface Pitch # of bytes
1038 if (ISL_DEV_GEN(dev
) >= 9 &&
1039 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1040 info
->dim
== ISL_SURF_DIM_1D
) {
1044 /* Be sloppy. Align any leftover padding to a row boundary. */
1045 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1051 isl_surf_init_s(const struct isl_device
*dev
,
1052 struct isl_surf
*surf
,
1053 const struct isl_surf_init_info
*restrict info
)
1055 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1057 const struct isl_extent4d logical_level0_px
= {
1061 .a
= info
->array_len
,
1064 enum isl_dim_layout dim_layout
=
1065 isl_surf_choose_dim_layout(dev
, info
->dim
);
1067 enum isl_tiling tiling
;
1068 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1071 struct isl_tile_info tile_info
;
1072 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bs
, &tile_info
))
1075 enum isl_msaa_layout msaa_layout
;
1076 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1079 struct isl_extent3d image_align_el
;
1080 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1083 struct isl_extent3d image_align_sa
=
1084 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1086 struct isl_extent4d phys_level0_sa
;
1087 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1089 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1090 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1092 enum isl_array_pitch_span array_pitch_span
=
1093 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1095 struct isl_extent2d phys_slice0_sa
;
1096 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1097 &image_align_sa
, &phys_level0_sa
,
1099 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1100 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1102 const uint32_t row_pitch
= isl_calc_row_pitch(dev
, info
, &tile_info
,
1106 const uint32_t array_pitch_el_rows
=
1107 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1108 array_pitch_span
, &image_align_sa
,
1109 &phys_level0_sa
, &phys_slice0_sa
);
1111 const uint32_t total_h_el
=
1112 isl_calc_total_height_el(dev
, info
, &tile_info
,
1113 phys_level0_sa
.array_len
, row_pitch
,
1114 array_pitch_el_rows
);
1116 const uint32_t size
=
1117 row_pitch
* isl_align(total_h_el
, tile_info
.height
);
1119 /* Alignment of surface base address, in bytes */
1120 uint32_t base_alignment
= MAX(1, info
->min_alignment
);
1121 assert(isl_is_pow2(base_alignment
) && isl_is_pow2(tile_info
.size
));
1122 base_alignment
= MAX(base_alignment
, tile_info
.size
);
1124 *surf
= (struct isl_surf
) {
1126 .dim_layout
= dim_layout
,
1127 .msaa_layout
= msaa_layout
,
1129 .format
= info
->format
,
1131 .levels
= info
->levels
,
1132 .samples
= info
->samples
,
1134 .image_alignment_el
= image_align_el
,
1135 .logical_level0_px
= logical_level0_px
,
1136 .phys_level0_sa
= phys_level0_sa
,
1139 .alignment
= base_alignment
,
1140 .row_pitch
= row_pitch
,
1141 .array_pitch_el_rows
= array_pitch_el_rows
,
1142 .array_pitch_span
= array_pitch_span
,
1144 .usage
= info
->usage
,
1151 isl_surf_get_tile_info(const struct isl_device
*dev
,
1152 const struct isl_surf
*surf
,
1153 struct isl_tile_info
*tile_info
)
1155 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1156 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bs
, tile_info
);
1160 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1161 const struct isl_surf_fill_state_info
*restrict info
)
1164 isl_surf_usage_flags_t _base_usage
=
1165 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1166 ISL_SURF_USAGE_TEXTURE_BIT
|
1167 ISL_SURF_USAGE_STORAGE_BIT
);
1168 /* They may only specify one of the above bits at a time */
1169 assert(__builtin_popcount(_base_usage
) == 1);
1170 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1171 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1174 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1175 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1176 info
->surf
->logical_level0_px
.depth
);
1178 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1179 info
->surf
->logical_level0_px
.array_len
);
1182 switch (ISL_DEV_GEN(dev
)) {
1184 if (ISL_DEV_IS_HASWELL(dev
)) {
1185 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1187 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1191 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1194 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1197 assert(!"Cannot fill surface state for this gen");
1202 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1203 const struct isl_buffer_fill_state_info
*restrict info
)
1205 switch (ISL_DEV_GEN(dev
)) {
1207 if (ISL_DEV_IS_HASWELL(dev
)) {
1208 isl_gen75_buffer_fill_state_s(state
, info
);
1210 isl_gen7_buffer_fill_state_s(state
, info
);
1214 isl_gen8_buffer_fill_state_s(state
, info
);
1217 isl_gen9_buffer_fill_state_s(state
, info
);
1220 assert(!"Cannot fill surface state for this gen");
1225 * A variant of isl_surf_get_image_offset_sa() specific to
1226 * ISL_DIM_LAYOUT_GEN4_2D.
1229 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1230 uint32_t level
, uint32_t layer
,
1231 uint32_t *x_offset_sa
,
1232 uint32_t *y_offset_sa
)
1234 assert(level
< surf
->levels
);
1235 assert(layer
< surf
->phys_level0_sa
.array_len
);
1236 assert(surf
->phys_level0_sa
.depth
== 1);
1238 const struct isl_extent3d image_align_sa
=
1239 isl_surf_get_image_alignment_sa(surf
);
1241 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1242 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1245 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1247 for (uint32_t l
= 0; l
< level
; ++l
) {
1249 uint32_t W
= isl_minify(W0
, l
);
1251 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1252 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1254 x
+= isl_align_npot(W
, image_align_sa
.w
);
1256 uint32_t H
= isl_minify(H0
, l
);
1258 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1259 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1261 y
+= isl_align_npot(H
, image_align_sa
.h
);
1270 * A variant of isl_surf_get_image_offset_sa() specific to
1271 * ISL_DIM_LAYOUT_GEN4_3D.
1274 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1275 uint32_t level
, uint32_t logical_z_offset_px
,
1276 uint32_t *x_offset_sa
,
1277 uint32_t *y_offset_sa
)
1279 assert(level
< surf
->levels
);
1280 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1281 assert(surf
->phys_level0_sa
.array_len
== 1);
1283 const struct isl_extent3d image_align_sa
=
1284 isl_surf_get_image_alignment_sa(surf
);
1286 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1287 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1288 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1293 for (uint32_t l
= 0; l
< level
; ++l
) {
1294 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1295 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1296 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1298 y
+= level_h
* max_layers_vert
;
1301 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1302 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1303 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1305 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1307 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1308 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1315 * A variant of isl_surf_get_image_offset_sa() specific to
1316 * ISL_DIM_LAYOUT_GEN9_1D.
1319 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1320 uint32_t level
, uint32_t layer
,
1321 uint32_t *x_offset_sa
,
1322 uint32_t *y_offset_sa
)
1324 assert(level
< surf
->levels
);
1325 assert(layer
< surf
->phys_level0_sa
.array_len
);
1326 assert(surf
->phys_level0_sa
.height
== 1);
1327 assert(surf
->phys_level0_sa
.depth
== 1);
1328 assert(surf
->samples
== 1);
1330 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1331 const struct isl_extent3d image_align_sa
=
1332 isl_surf_get_image_alignment_sa(surf
);
1336 for (uint32_t l
= 0; l
< level
; ++l
) {
1337 uint32_t W
= isl_minify(W0
, l
);
1338 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1344 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1348 * Calculate the offset, in units of surface samples, to a subimage in the
1351 * @invariant level < surface levels
1352 * @invariant logical_array_layer < logical array length of surface
1353 * @invariant logical_z_offset_px < logical depth of surface at level
1356 get_image_offset_sa(const struct isl_surf
*surf
,
1358 uint32_t logical_array_layer
,
1359 uint32_t logical_z_offset_px
,
1360 uint32_t *x_offset_sa
,
1361 uint32_t *y_offset_sa
)
1363 assert(level
< surf
->levels
);
1364 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1365 assert(logical_z_offset_px
1366 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1368 switch (surf
->dim_layout
) {
1369 case ISL_DIM_LAYOUT_GEN9_1D
:
1370 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1371 x_offset_sa
, y_offset_sa
);
1373 case ISL_DIM_LAYOUT_GEN4_2D
:
1374 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1375 + logical_z_offset_px
,
1376 x_offset_sa
, y_offset_sa
);
1378 case ISL_DIM_LAYOUT_GEN4_3D
:
1379 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1380 x_offset_sa
, y_offset_sa
);
1384 unreachable("not reached");
1389 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1391 uint32_t logical_array_layer
,
1392 uint32_t logical_z_offset_px
,
1393 uint32_t *x_offset_el
,
1394 uint32_t *y_offset_el
)
1396 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1398 assert(level
< surf
->levels
);
1399 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1400 assert(logical_z_offset_px
1401 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1403 uint32_t x_offset_sa
, y_offset_sa
;
1404 get_image_offset_sa(surf
, level
,
1405 logical_array_layer
,
1406 logical_z_offset_px
,
1410 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1411 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1415 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1416 enum isl_tiling tiling
,
1419 uint32_t total_x_offset_el
,
1420 uint32_t total_y_offset_el
,
1421 uint32_t *base_address_offset
,
1422 uint32_t *x_offset_el
,
1423 uint32_t *y_offset_el
)
1425 struct isl_tile_info tile_info
;
1426 isl_tiling_get_info(dev
, tiling
, bs
, &tile_info
);
1428 /* This function only really works for power-of-two surfaces. In
1429 * theory, we could make it work for non-power-of-two surfaces by going
1430 * to the left until we find a block that is bs-aligned. The Vulkan
1431 * driver doesn't use non-power-of-two tiled surfaces so we'll leave
1432 * this unimplemented for now.
1434 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(bs
));
1436 uint32_t small_y_offset_el
= total_y_offset_el
% tile_info
.height
;
1437 uint32_t big_y_offset_el
= total_y_offset_el
- small_y_offset_el
;
1438 uint32_t big_y_offset_B
= big_y_offset_el
* row_pitch
;
1440 uint32_t total_x_offset_B
= total_x_offset_el
* bs
;
1441 uint32_t small_x_offset_B
= total_x_offset_B
% tile_info
.width
;
1442 uint32_t small_x_offset_el
= small_x_offset_B
/ bs
;
1443 uint32_t big_x_offset_B
= (total_x_offset_B
/ tile_info
.width
) * tile_info
.size
;
1445 *base_address_offset
= big_y_offset_B
+ big_x_offset_B
;
1446 *x_offset_el
= small_x_offset_el
;
1447 *y_offset_el
= small_y_offset_el
;
1451 isl_surf_get_depth_format(const struct isl_device
*dev
,
1452 const struct isl_surf
*surf
)
1454 /* Support for separate stencil buffers began in gen5. Support for
1455 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1456 * those that supported separate and interleaved stencil, were gen5 and
1459 * For a list of all available formats, see the Sandybridge PRM >> Volume
1460 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1464 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1466 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1469 assert(ISL_DEV_GEN(dev
) < 7);
1471 switch (surf
->format
) {
1473 unreachable("bad isl depth format");
1474 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1475 assert(ISL_DEV_GEN(dev
) < 7);
1476 return 0; /* D32_FLOAT_S8X24_UINT */
1477 case ISL_FORMAT_R32_FLOAT
:
1478 assert(!has_stencil
);
1479 return 1; /* D32_FLOAT */
1480 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1482 assert(ISL_DEV_GEN(dev
) < 7);
1483 return 2; /* D24_UNORM_S8_UINT */
1485 assert(ISL_DEV_GEN(dev
) >= 5);
1486 return 3; /* D24_UNORM_X8_UINT */
1488 case ISL_FORMAT_R16_UNORM
:
1489 assert(!has_stencil
);
1490 return 5; /* D16_UNORM */