2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
38 void PRINTFLIKE(3, 4) UNUSED
39 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
45 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
48 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
52 isl_device_init(struct isl_device
*dev
,
53 const struct gen_device_info
*info
,
54 bool has_bit6_swizzling
)
57 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
58 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
60 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
61 * device properties at buildtime. Verify that the macros with the device
62 * properties chosen during runtime.
64 ISL_DEV_GEN_SANITIZE(dev
);
65 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
67 /* Did we break hiz or stencil? */
68 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
69 assert(info
->has_hiz_and_separate_stencil
);
70 if (info
->must_use_separate_stencil
)
71 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
74 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
76 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
78 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
80 /* The "Auxiliary Surface Base Address" field starts a bit higher up
81 * because the bottom 12 bits are used for other things. Round down to
82 * the nearest dword before.
84 dev
->ss
.aux_addr_offset
=
85 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
87 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
88 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
89 dev
->ds
.depth_offset
=
90 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
92 if (dev
->use_separate_stencil
) {
93 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
94 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
95 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
97 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
98 dev
->ds
.stencil_offset
=
99 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
100 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
102 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
104 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
105 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
106 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
108 dev
->ds
.stencil_offset
= 0;
109 dev
->ds
.hiz_offset
= 0;
114 * @brief Query the set of multisamples supported by the device.
116 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
119 isl_sample_count_mask_t ATTRIBUTE_CONST
120 isl_device_get_sample_counts(struct isl_device
*dev
)
122 if (ISL_DEV_GEN(dev
) >= 9) {
123 return ISL_SAMPLE_COUNT_1_BIT
|
124 ISL_SAMPLE_COUNT_2_BIT
|
125 ISL_SAMPLE_COUNT_4_BIT
|
126 ISL_SAMPLE_COUNT_8_BIT
|
127 ISL_SAMPLE_COUNT_16_BIT
;
128 } else if (ISL_DEV_GEN(dev
) >= 8) {
129 return ISL_SAMPLE_COUNT_1_BIT
|
130 ISL_SAMPLE_COUNT_2_BIT
|
131 ISL_SAMPLE_COUNT_4_BIT
|
132 ISL_SAMPLE_COUNT_8_BIT
;
133 } else if (ISL_DEV_GEN(dev
) >= 7) {
134 return ISL_SAMPLE_COUNT_1_BIT
|
135 ISL_SAMPLE_COUNT_4_BIT
|
136 ISL_SAMPLE_COUNT_8_BIT
;
137 } else if (ISL_DEV_GEN(dev
) >= 6) {
138 return ISL_SAMPLE_COUNT_1_BIT
|
139 ISL_SAMPLE_COUNT_4_BIT
;
141 return ISL_SAMPLE_COUNT_1_BIT
;
146 * @param[out] info is written only on success
149 isl_tiling_get_info(enum isl_tiling tiling
,
151 struct isl_tile_info
*tile_info
)
153 const uint32_t bs
= format_bpb
/ 8;
154 struct isl_extent2d logical_el
, phys_B
;
156 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
157 /* It is possible to have non-power-of-two formats in a tiled buffer.
158 * The easiest way to handle this is to treat the tile as if it is three
159 * times as wide. This way no pixel will ever cross a tile boundary.
160 * This really only works on legacy X and Y tiling formats.
162 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
163 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
164 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
169 case ISL_TILING_LINEAR
:
171 logical_el
= isl_extent2d(1, 1);
172 phys_B
= isl_extent2d(bs
, 1);
177 logical_el
= isl_extent2d(512 / bs
, 8);
178 phys_B
= isl_extent2d(512, 8);
183 logical_el
= isl_extent2d(128 / bs
, 32);
184 phys_B
= isl_extent2d(128, 32);
189 logical_el
= isl_extent2d(64, 64);
190 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
192 * "If the surface is a stencil buffer (and thus has Tile Mode set
193 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
194 * computed based on width, as the stencil buffer is stored with two
197 * This, together with the fact that stencil buffers are referred to as
198 * being Y-tiled in the PRMs for older hardware implies that the
199 * physical size of a W-tile is actually the same as for a Y-tile.
201 phys_B
= isl_extent2d(128, 32);
205 case ISL_TILING_Ys
: {
206 bool is_Ys
= tiling
== ISL_TILING_Ys
;
209 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
210 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
212 logical_el
= isl_extent2d(width
/ bs
, height
);
213 phys_B
= isl_extent2d(width
, height
);
218 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
219 * 128bpb format. The tiling has the same physical dimensions as
220 * Y-tiling but actually has two HiZ columns per Y-tiled column.
223 logical_el
= isl_extent2d(16, 16);
224 phys_B
= isl_extent2d(128, 32);
228 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
229 * have a block size of 1 or 2 bits per block and each CCS element
230 * corresponds to one cache-line pair in the main surface. From the Sky
231 * Lake PRM Vol. 12 in the section on planes:
233 * "The Color Control Surface (CCS) contains the compression status
234 * of the cache-line pairs. The compression state of the cache-line
235 * pair is specified by 2 bits in the CCS. Each CCS cache-line
236 * represents an area on the main surface of 16x16 sets of 128 byte
237 * Y-tiled cache-line-pairs. CCS is always Y tiled."
239 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
240 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
241 * that yields total tile area of 128x128 cache-line pairs or CCS
242 * elements. On older hardware, each CCS element is 1 bit and the tile
243 * is 128x256 elements.
245 assert(format_bpb
== 1 || format_bpb
== 2);
246 logical_el
= isl_extent2d(128, 256 / format_bpb
);
247 phys_B
= isl_extent2d(128, 32);
251 unreachable("not reached");
254 *tile_info
= (struct isl_tile_info
) {
256 .format_bpb
= format_bpb
,
257 .logical_extent_el
= logical_el
,
258 .phys_extent_B
= phys_B
,
263 * @param[out] tiling is set only on success
266 isl_surf_choose_tiling(const struct isl_device
*dev
,
267 const struct isl_surf_init_info
*restrict info
,
268 enum isl_tiling
*tiling
)
270 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
272 /* HiZ surfaces always use the HiZ tiling */
273 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
274 assert(info
->format
== ISL_FORMAT_HIZ
);
275 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
276 *tiling
= ISL_TILING_HIZ
;
280 /* CCS surfaces always use the CCS tiling */
281 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
282 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
283 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
284 *tiling
= ISL_TILING_CCS
;
288 if (ISL_DEV_GEN(dev
) >= 6) {
289 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
291 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
294 #define CHOOSE(__tiling) \
296 if (tiling_flags & (1u << (__tiling))) { \
297 *tiling = (__tiling); \
302 /* Of the tiling modes remaining, choose the one that offers the best
306 if (info
->dim
== ISL_SURF_DIM_1D
) {
307 /* Prefer linear for 1D surfaces because they do not benefit from
308 * tiling. To the contrary, tiling leads to wasted memory and poor
309 * memory locality due to the swizzling and alignment restrictions
310 * required in tiled surfaces.
312 CHOOSE(ISL_TILING_LINEAR
);
315 CHOOSE(ISL_TILING_Ys
);
316 CHOOSE(ISL_TILING_Yf
);
317 CHOOSE(ISL_TILING_Y0
);
318 CHOOSE(ISL_TILING_X
);
319 CHOOSE(ISL_TILING_W
);
320 CHOOSE(ISL_TILING_LINEAR
);
324 /* No tiling mode accomodates the inputs. */
329 isl_choose_msaa_layout(const struct isl_device
*dev
,
330 const struct isl_surf_init_info
*info
,
331 enum isl_tiling tiling
,
332 enum isl_msaa_layout
*msaa_layout
)
334 if (ISL_DEV_GEN(dev
) >= 8) {
335 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
336 } else if (ISL_DEV_GEN(dev
) >= 7) {
337 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
338 } else if (ISL_DEV_GEN(dev
) >= 6) {
339 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
341 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
346 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
348 assert(isl_is_pow2(samples
));
350 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
353 * If the surface is multisampled and it is a depth or stencil surface
354 * or Multisampled Surface StorageFormat in SURFACE_STATE is
355 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
358 return (struct isl_extent2d
) {
359 .width
= 1 << ((ffs(samples
) - 0) / 2),
360 .height
= 1 << ((ffs(samples
) - 1) / 2),
365 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
366 uint32_t *width
, uint32_t *height
)
368 const struct isl_extent2d px_size_sa
=
369 isl_get_interleaved_msaa_px_size_sa(samples
);
372 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
374 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
377 static enum isl_array_pitch_span
378 isl_choose_array_pitch_span(const struct isl_device
*dev
,
379 const struct isl_surf_init_info
*restrict info
,
380 enum isl_dim_layout dim_layout
,
381 const struct isl_extent4d
*phys_level0_sa
)
383 switch (dim_layout
) {
384 case ISL_DIM_LAYOUT_GEN9_1D
:
385 case ISL_DIM_LAYOUT_GEN4_2D
:
386 if (ISL_DEV_GEN(dev
) >= 8) {
387 /* QPitch becomes programmable in Broadwell. So choose the
388 * most compact QPitch possible in order to conserve memory.
390 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
391 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
393 * - Software must ensure that this field is set to a value
394 * sufficiently large such that the array slices in the surface
395 * do not overlap. Refer to the Memory Data Formats section for
396 * information on how surfaces are stored in memory.
398 * - This field specifies the distance in rows between array
399 * slices. It is used only in the following cases:
401 * - Surface Array is enabled OR
402 * - Number of Mulitsamples is not NUMSAMPLES_1 and
403 * Multisampled Surface Storage Format set to MSFMT_MSS OR
404 * - Surface Type is SURFTYPE_CUBE
406 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
407 } else if (ISL_DEV_GEN(dev
) >= 7) {
408 /* Note that Ivybridge introduces
409 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
410 * driver more control over the QPitch.
413 if (phys_level0_sa
->array_len
== 1) {
414 /* The hardware will never use the QPitch. So choose the most
415 * compact QPitch possible in order to conserve memory.
417 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
420 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
421 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
422 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
423 * Section 6.18.4.7: Surface Arrays (p112):
425 * If Surface Array Spacing is set to ARYSPC_FULL (note that
426 * the depth buffer and stencil buffer have an implied value of
429 return ISL_ARRAY_PITCH_SPAN_FULL
;
432 if (info
->levels
== 1) {
433 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
436 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
439 return ISL_ARRAY_PITCH_SPAN_FULL
;
440 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
441 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
442 isl_surf_usage_is_stencil(info
->usage
)) {
443 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
444 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
446 * The separate stencil buffer does not support mip mapping, thus
447 * the storage for LODs other than LOD 0 is not needed.
449 assert(info
->levels
== 1);
450 assert(phys_level0_sa
->array_len
== 1);
451 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
453 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
454 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
455 isl_surf_usage_is_stencil(info
->usage
)) {
456 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
457 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
459 * The separate stencil buffer does not support mip mapping,
460 * thus the storage for LODs other than LOD 0 is not needed.
462 assert(info
->levels
== 1);
463 assert(phys_level0_sa
->array_len
== 1);
464 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
467 if (phys_level0_sa
->array_len
== 1) {
468 /* The hardware will never use the QPitch. So choose the most
469 * compact QPitch possible in order to conserve memory.
471 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
474 return ISL_ARRAY_PITCH_SPAN_FULL
;
477 case ISL_DIM_LAYOUT_GEN4_3D
:
478 /* The hardware will never use the QPitch. So choose the most
479 * compact QPitch possible in order to conserve memory.
481 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
483 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
484 /* Each array image in the gen6 stencil of HiZ surface is compact in the
485 * sense that every LOD is a compact array of the same size as LOD0.
487 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
490 unreachable("bad isl_dim_layout");
491 return ISL_ARRAY_PITCH_SPAN_FULL
;
495 isl_choose_image_alignment_el(const struct isl_device
*dev
,
496 const struct isl_surf_init_info
*restrict info
,
497 enum isl_tiling tiling
,
498 enum isl_dim_layout dim_layout
,
499 enum isl_msaa_layout msaa_layout
,
500 struct isl_extent3d
*image_align_el
)
502 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
503 if (fmtl
->txc
== ISL_TXC_MCS
) {
504 assert(tiling
== ISL_TILING_Y0
);
507 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
509 * Height, width, and layout of MCS buffer in this case must match with
510 * Render Target height, width, and layout. MCS buffer is tiledY.
512 * To avoid wasting memory, choose the smallest alignment possible:
513 * HALIGN_4 and VALIGN_4.
515 *image_align_el
= isl_extent3d(4, 4, 1);
517 } else if (info
->format
== ISL_FORMAT_HIZ
) {
518 assert(ISL_DEV_GEN(dev
) >= 6);
519 if (ISL_DEV_GEN(dev
) == 6) {
520 /* HiZ surfaces on Sandy Bridge are packed tightly. */
521 *image_align_el
= isl_extent3d(1, 1, 1);
523 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
524 * primary surface which works out to 2x2 HiZ elments.
526 *image_align_el
= isl_extent3d(2, 2, 1);
531 if (ISL_DEV_GEN(dev
) >= 9) {
532 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
533 msaa_layout
, image_align_el
);
534 } else if (ISL_DEV_GEN(dev
) >= 8) {
535 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
536 msaa_layout
, image_align_el
);
537 } else if (ISL_DEV_GEN(dev
) >= 7) {
538 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
539 msaa_layout
, image_align_el
);
540 } else if (ISL_DEV_GEN(dev
) >= 6) {
541 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
542 msaa_layout
, image_align_el
);
544 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
545 msaa_layout
, image_align_el
);
549 static enum isl_dim_layout
550 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
551 enum isl_surf_dim logical_dim
,
552 enum isl_tiling tiling
)
554 /* Sandy bridge needs a special layout for HiZ and stencil. */
555 if (ISL_DEV_GEN(dev
) == 6 &&
556 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
557 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
559 if (ISL_DEV_GEN(dev
) >= 9) {
560 switch (logical_dim
) {
561 case ISL_SURF_DIM_1D
:
562 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
564 * One-dimensional surfaces use a tiling mode of linear.
565 * Technically, they are not tiled resources, but the Tiled
566 * Resource Mode field in RENDER_SURFACE_STATE is still used to
567 * indicate the alignment requirements for this linear surface
568 * (See 1D Alignment requirements for how 4K and 64KB Tiled
569 * Resource Modes impact alignment). Alternatively, a 1D surface
570 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
573 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
574 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
576 if (tiling
== ISL_TILING_LINEAR
)
577 return ISL_DIM_LAYOUT_GEN9_1D
;
579 return ISL_DIM_LAYOUT_GEN4_2D
;
580 case ISL_SURF_DIM_2D
:
581 case ISL_SURF_DIM_3D
:
582 return ISL_DIM_LAYOUT_GEN4_2D
;
585 switch (logical_dim
) {
586 case ISL_SURF_DIM_1D
:
587 case ISL_SURF_DIM_2D
:
588 return ISL_DIM_LAYOUT_GEN4_2D
;
589 case ISL_SURF_DIM_3D
:
590 return ISL_DIM_LAYOUT_GEN4_3D
;
594 unreachable("bad isl_surf_dim");
595 return ISL_DIM_LAYOUT_GEN4_2D
;
599 * Calculate the physical extent of the surface's first level, in units of
600 * surface samples. The result is aligned to the format's compression block.
603 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
604 const struct isl_surf_init_info
*restrict info
,
605 enum isl_dim_layout dim_layout
,
606 enum isl_tiling tiling
,
607 enum isl_msaa_layout msaa_layout
,
608 struct isl_extent4d
*phys_level0_sa
)
610 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
612 if (isl_format_is_yuv(info
->format
))
613 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
616 case ISL_SURF_DIM_1D
:
617 assert(info
->height
== 1);
618 assert(info
->depth
== 1);
619 assert(info
->samples
== 1);
621 switch (dim_layout
) {
622 case ISL_DIM_LAYOUT_GEN4_3D
:
623 unreachable("bad isl_dim_layout");
625 case ISL_DIM_LAYOUT_GEN9_1D
:
626 case ISL_DIM_LAYOUT_GEN4_2D
:
627 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
628 *phys_level0_sa
= (struct isl_extent4d
) {
629 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
632 .a
= info
->array_len
,
638 case ISL_SURF_DIM_2D
:
639 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
640 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
642 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
643 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
645 switch (msaa_layout
) {
646 case ISL_MSAA_LAYOUT_NONE
:
647 assert(info
->depth
== 1);
648 assert(info
->samples
== 1);
650 *phys_level0_sa
= (struct isl_extent4d
) {
651 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
652 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
654 .a
= info
->array_len
,
658 case ISL_MSAA_LAYOUT_ARRAY
:
659 assert(info
->depth
== 1);
660 assert(info
->levels
== 1);
661 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
662 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
664 *phys_level0_sa
= (struct isl_extent4d
) {
668 .a
= info
->array_len
* info
->samples
,
672 case ISL_MSAA_LAYOUT_INTERLEAVED
:
673 assert(info
->depth
== 1);
674 assert(info
->levels
== 1);
675 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
677 *phys_level0_sa
= (struct isl_extent4d
) {
681 .a
= info
->array_len
,
684 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
688 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
689 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
694 case ISL_SURF_DIM_3D
:
695 assert(info
->array_len
== 1);
696 assert(info
->samples
== 1);
699 isl_finishme("%s:%s: compression block with depth > 1",
703 switch (dim_layout
) {
704 case ISL_DIM_LAYOUT_GEN9_1D
:
705 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
706 unreachable("bad isl_dim_layout");
708 case ISL_DIM_LAYOUT_GEN4_2D
:
709 assert(ISL_DEV_GEN(dev
) >= 9);
711 *phys_level0_sa
= (struct isl_extent4d
) {
712 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
713 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
719 case ISL_DIM_LAYOUT_GEN4_3D
:
720 assert(ISL_DEV_GEN(dev
) < 9);
721 *phys_level0_sa
= (struct isl_extent4d
) {
722 .w
= isl_align(info
->width
, fmtl
->bw
),
723 .h
= isl_align(info
->height
, fmtl
->bh
),
734 * Calculate the pitch between physical array slices, in units of rows of
738 isl_calc_array_pitch_el_rows_gen4_2d(
739 const struct isl_device
*dev
,
740 const struct isl_surf_init_info
*restrict info
,
741 const struct isl_tile_info
*tile_info
,
742 const struct isl_extent3d
*image_align_sa
,
743 const struct isl_extent4d
*phys_level0_sa
,
744 enum isl_array_pitch_span array_pitch_span
,
745 const struct isl_extent2d
*phys_slice0_sa
)
747 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
748 uint32_t pitch_sa_rows
= 0;
750 switch (array_pitch_span
) {
751 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
752 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
754 case ISL_ARRAY_PITCH_SPAN_FULL
: {
755 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
756 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
757 * Surfaces >> Surface Arrays.
759 uint32_t H0_sa
= phys_level0_sa
->h
;
760 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
762 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
763 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
766 if (ISL_DEV_GEN(dev
) >= 7) {
767 /* The QPitch equation changed slightly in Ivybridge. */
773 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
775 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
776 (info
->height
% 4 == 1)) {
777 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
778 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
780 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
781 * the value calculated in the equation above , for every
782 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
784 * XXX(chadv): Is the errata natural corollary of the physical
785 * layout of interleaved samples?
790 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
795 assert(pitch_sa_rows
% fmtl
->bh
== 0);
796 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
798 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
800 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
802 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
803 * layout with these alignments in the RT space: Horizontal
804 * Alignment = 128 and Vertical Alignment = 64."
806 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
808 * "For non-multisampled render target's CCS auxiliary surface,
809 * QPitch must be computed with Horizontal Alignment = 128 and
810 * Surface Vertical Alignment = 256. These alignments are only for
811 * CCS buffer and not for associated render target."
813 * The first restriction is already handled by isl_choose_image_alignment_el
814 * but the second restriction, which is an extension of the first, only
815 * applies to qpitch and must be applied here.
817 assert(fmtl
->bh
== 4);
818 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
821 if (ISL_DEV_GEN(dev
) >= 9 &&
822 info
->dim
== ISL_SURF_DIM_3D
&&
823 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
824 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
826 * Tile Mode != Linear: This field must be set to an integer multiple
829 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
832 return pitch_el_rows
;
836 * A variant of isl_calc_phys_slice0_extent_sa() specific to
837 * ISL_DIM_LAYOUT_GEN4_2D.
840 isl_calc_phys_slice0_extent_sa_gen4_2d(
841 const struct isl_device
*dev
,
842 const struct isl_surf_init_info
*restrict info
,
843 enum isl_msaa_layout msaa_layout
,
844 const struct isl_extent3d
*image_align_sa
,
845 const struct isl_extent4d
*phys_level0_sa
,
846 struct isl_extent2d
*phys_slice0_sa
)
848 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
850 assert(phys_level0_sa
->depth
== 1);
852 if (info
->levels
== 1) {
853 /* Do not pad the surface to the image alignment. Instead, pad it only
854 * to the pixel format's block alignment.
856 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
857 * cycles on the below mipmap layout caluclations. Reducing the
858 * alignment here is safe because we later align the row pitch and array
859 * pitch to the tile boundary. It is safe even for
860 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
861 * to accomodate the interleaved samples.
863 * For linear surfaces, reducing the alignment here permits us to later
864 * choose an arbitrary, non-aligned row pitch. If the surface backs
865 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
866 * VkBufferImageCopy::bufferRowLength.
868 *phys_slice0_sa
= (struct isl_extent2d
) {
869 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
870 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
875 uint32_t slice_top_w
= 0;
876 uint32_t slice_bottom_w
= 0;
877 uint32_t slice_left_h
= 0;
878 uint32_t slice_right_h
= 0;
880 uint32_t W0
= phys_level0_sa
->w
;
881 uint32_t H0
= phys_level0_sa
->h
;
883 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
884 uint32_t W
= isl_minify(W0
, l
);
885 uint32_t H
= isl_minify(H0
, l
);
887 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
888 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
905 *phys_slice0_sa
= (struct isl_extent2d
) {
906 .w
= MAX(slice_top_w
, slice_bottom_w
),
907 .h
= MAX(slice_left_h
, slice_right_h
),
912 isl_calc_phys_total_extent_el_gen4_2d(
913 const struct isl_device
*dev
,
914 const struct isl_surf_init_info
*restrict info
,
915 const struct isl_tile_info
*tile_info
,
916 enum isl_msaa_layout msaa_layout
,
917 const struct isl_extent3d
*image_align_sa
,
918 const struct isl_extent4d
*phys_level0_sa
,
919 enum isl_array_pitch_span array_pitch_span
,
920 uint32_t *array_pitch_el_rows
,
921 struct isl_extent2d
*total_extent_el
)
923 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
925 struct isl_extent2d phys_slice0_sa
;
926 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
927 image_align_sa
, phys_level0_sa
,
929 *array_pitch_el_rows
=
930 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
931 image_align_sa
, phys_level0_sa
,
934 *total_extent_el
= (struct isl_extent2d
) {
935 .w
= isl_assert_div(phys_slice0_sa
.w
, fmtl
->bw
),
936 .h
= *array_pitch_el_rows
* phys_level0_sa
->array_len
,
941 * A variant of isl_calc_phys_slice0_extent_sa() specific to
942 * ISL_DIM_LAYOUT_GEN4_3D.
945 isl_calc_phys_total_extent_el_gen4_3d(
946 const struct isl_device
*dev
,
947 const struct isl_surf_init_info
*restrict info
,
948 const struct isl_extent3d
*image_align_sa
,
949 const struct isl_extent4d
*phys_level0_sa
,
950 uint32_t *array_pitch_el_rows
,
951 struct isl_extent2d
*phys_total_el
)
953 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
955 assert(info
->samples
== 1);
956 assert(phys_level0_sa
->array_len
== 1);
958 uint32_t total_w
= 0;
959 uint32_t total_h
= 0;
961 uint32_t W0
= phys_level0_sa
->w
;
962 uint32_t H0
= phys_level0_sa
->h
;
963 uint32_t D0
= phys_level0_sa
->d
;
965 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
966 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
967 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
968 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
970 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
971 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
973 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
974 total_h
+= level_h
* max_layers_vert
;
977 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
978 * different number of horizontal and vertical layers. We have to set it
979 * to something, so at least make it true for LOD0.
981 *array_pitch_el_rows
=
982 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
983 *phys_total_el
= (struct isl_extent2d
) {
984 .w
= isl_assert_div(total_w
, fmtl
->bw
),
985 .h
= isl_assert_div(total_h
, fmtl
->bh
),
990 * A variant of isl_calc_phys_slice0_extent_sa() specific to
991 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
994 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
995 const struct isl_device
*dev
,
996 const struct isl_surf_init_info
*restrict info
,
997 const struct isl_tile_info
*tile_info
,
998 const struct isl_extent3d
*image_align_sa
,
999 const struct isl_extent4d
*phys_level0_sa
,
1000 uint32_t *array_pitch_el_rows
,
1001 struct isl_extent2d
*phys_total_el
)
1003 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1005 const struct isl_extent2d tile_extent_sa
= {
1006 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1007 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1009 /* Tile size is a multiple of image alignment */
1010 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1011 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1013 const uint32_t W0
= phys_level0_sa
->w
;
1014 const uint32_t H0
= phys_level0_sa
->h
;
1016 /* Each image has the same height as LOD0 because the hardware thinks
1017 * everything is LOD0
1019 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1021 uint32_t total_top_w
= 0;
1022 uint32_t total_bottom_w
= 0;
1023 uint32_t total_h
= 0;
1025 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1026 const uint32_t W
= isl_minify(W0
, l
);
1028 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1029 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1034 } else if (l
== 1) {
1038 total_bottom_w
+= w
;
1042 *array_pitch_el_rows
=
1043 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1044 *phys_total_el
= (struct isl_extent2d
) {
1045 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1046 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1051 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1052 * ISL_DIM_LAYOUT_GEN9_1D.
1055 isl_calc_phys_total_extent_el_gen9_1d(
1056 const struct isl_device
*dev
,
1057 const struct isl_surf_init_info
*restrict info
,
1058 const struct isl_extent3d
*image_align_sa
,
1059 const struct isl_extent4d
*phys_level0_sa
,
1060 uint32_t *array_pitch_el_rows
,
1061 struct isl_extent2d
*phys_total_el
)
1063 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1065 assert(phys_level0_sa
->height
== 1);
1066 assert(phys_level0_sa
->depth
== 1);
1067 assert(info
->samples
== 1);
1068 assert(image_align_sa
->w
>= fmtl
->bw
);
1070 uint32_t slice_w
= 0;
1071 const uint32_t W0
= phys_level0_sa
->w
;
1073 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1074 uint32_t W
= isl_minify(W0
, l
);
1075 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1080 *array_pitch_el_rows
= 1;
1081 *phys_total_el
= (struct isl_extent2d
) {
1082 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1083 .h
= phys_level0_sa
->array_len
,
1088 * Calculate the two-dimensional total physical extent of the surface, in
1089 * units of surface elements.
1092 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1093 const struct isl_surf_init_info
*restrict info
,
1094 const struct isl_tile_info
*tile_info
,
1095 enum isl_dim_layout dim_layout
,
1096 enum isl_msaa_layout msaa_layout
,
1097 const struct isl_extent3d
*image_align_sa
,
1098 const struct isl_extent4d
*phys_level0_sa
,
1099 enum isl_array_pitch_span array_pitch_span
,
1100 uint32_t *array_pitch_el_rows
,
1101 struct isl_extent2d
*total_extent_el
)
1103 switch (dim_layout
) {
1104 case ISL_DIM_LAYOUT_GEN9_1D
:
1105 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1106 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1107 image_align_sa
, phys_level0_sa
,
1108 array_pitch_el_rows
,
1111 case ISL_DIM_LAYOUT_GEN4_2D
:
1112 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1113 image_align_sa
, phys_level0_sa
,
1115 array_pitch_el_rows
,
1118 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1119 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1120 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1123 array_pitch_el_rows
,
1126 case ISL_DIM_LAYOUT_GEN4_3D
:
1127 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1128 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1129 image_align_sa
, phys_level0_sa
,
1130 array_pitch_el_rows
,
1137 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1138 const struct isl_tile_info
*tile_info
)
1140 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1141 return tile_info
->phys_extent_B
.width
;
1143 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1144 * RENDER_SURFACE_STATE Surface Pitch (p349):
1146 * - For linear render target surfaces and surfaces accessed with the
1147 * typed data port messages, the pitch must be a multiple of the
1148 * element size for non-YUV surface formats. Pitch must be
1149 * a multiple of 2 * element size for YUV surface formats.
1151 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1152 * ignore because isl doesn't do buffers.]
1154 * - For other linear surfaces, the pitch can be any multiple of
1157 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1158 const uint32_t bs
= fmtl
->bpb
/ 8;
1160 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1161 if (isl_format_is_yuv(surf_info
->format
)) {
1172 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1173 const struct isl_surf_init_info
*info
,
1174 const struct isl_extent2d
*phys_total_el
,
1177 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1178 const uint32_t bs
= fmtl
->bpb
/ 8;
1180 return isl_align_npot(bs
* phys_total_el
->w
, alignment
);
1184 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1185 const struct isl_surf_init_info
*surf_info
,
1186 const struct isl_tile_info
*tile_info
,
1187 const struct isl_extent2d
*phys_total_el
,
1190 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1192 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1194 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1195 const uint32_t total_w_tl
=
1196 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1197 tile_info
->logical_extent_el
.width
);
1199 assert(alignment
== tile_info
->phys_extent_B
.width
);
1200 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1204 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1205 const struct isl_surf_init_info
*surf_info
,
1206 const struct isl_tile_info
*tile_info
,
1207 const struct isl_extent2d
*phys_total_el
,
1210 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1211 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1214 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1215 phys_total_el
, alignment
);
1220 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1221 * size is `bits` bits?
1223 * Hardware pitch fields are offset by 1. For example, if the size of
1224 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1225 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1226 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1229 pitch_in_range(uint32_t n
, uint32_t bits
)
1232 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1236 isl_calc_row_pitch(const struct isl_device
*dev
,
1237 const struct isl_surf_init_info
*surf_info
,
1238 const struct isl_tile_info
*tile_info
,
1239 enum isl_dim_layout dim_layout
,
1240 const struct isl_extent2d
*phys_total_el
,
1241 uint32_t *out_row_pitch
)
1243 const uint32_t alignment
=
1244 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1246 const uint32_t min_row_pitch
=
1247 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1250 uint32_t row_pitch
= min_row_pitch
;
1252 if (surf_info
->row_pitch
!= 0) {
1253 row_pitch
= surf_info
->row_pitch
;
1255 if (row_pitch
< min_row_pitch
)
1258 if (row_pitch
% alignment
!= 0)
1262 const uint32_t row_pitch_tiles
= row_pitch
/ tile_info
->phys_extent_B
.width
;
1267 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1268 /* SurfacePitch is ignored for this layout. */
1272 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1273 ISL_SURF_USAGE_TEXTURE_BIT
|
1274 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1275 !pitch_in_range(row_pitch
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1278 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1279 ISL_SURF_USAGE_MCS_BIT
)) &&
1280 !pitch_in_range(row_pitch_tiles
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1283 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1284 !pitch_in_range(row_pitch
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1287 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1288 !pitch_in_range(row_pitch
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1291 if (surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
1292 isl_finishme("validate row pitch of stencil surfaces");
1295 *out_row_pitch
= row_pitch
;
1300 * Calculate and apply any padding required for the surface.
1302 * @param[inout] total_h_el is updated with the new height
1303 * @param[out] pad_bytes is overwritten with additional padding requirements.
1306 isl_apply_surface_padding(const struct isl_device
*dev
,
1307 const struct isl_surf_init_info
*restrict info
,
1308 const struct isl_tile_info
*tile_info
,
1309 uint32_t *total_h_el
,
1310 uint32_t *pad_bytes
)
1312 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1316 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1317 * Formats >> Surface Padding Requirements >> Render Target and Media
1320 * The data port accesses data (pixels) outside of the surface if they
1321 * are contained in the same cache request as pixels that are within the
1322 * surface. These pixels will not be returned by the requesting message,
1323 * however if these pixels lie outside of defined pages in the GTT,
1324 * a GTT error will result when the cache request is processed. In
1325 * order to avoid these GTT errors, “padding” at the bottom of the
1326 * surface is sometimes necessary.
1328 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1329 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1331 * ... Lots of padding requirements, all listed separately below.
1334 /* We can safely ignore the first padding requirement, quoted below,
1335 * because isl doesn't do buffers.
1337 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1338 * requirements are different. A buffer must be padded to the next
1339 * multiple of 256 array elements, with an additional 16 bytes added
1340 * beyond that to account for the L1 cache line.
1344 * - For compressed textures [...], padding at the bottom of the surface
1345 * is to an even compressed row.
1347 if (isl_format_is_compressed(info
->format
))
1348 *total_h_el
= isl_align(*total_h_el
, 2);
1351 * - For cube surfaces, an additional two rows of padding are required
1352 * at the bottom of the surface.
1354 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1358 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1359 * additional padding is required. These surfaces require an extra row
1360 * plus 16 bytes of padding at the bottom in addition to the general
1361 * padding requirements.
1363 if (isl_format_is_yuv(info
->format
) &&
1364 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1370 * - For linear surfaces, additional padding of 64 bytes is required at
1371 * the bottom of the surface. This is in addition to the padding
1374 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1377 /* The below text weakens, not strengthens, the padding requirements for
1378 * linear surfaces. Therefore we can safely ignore it.
1380 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1381 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1382 * padding requirement is to the next aligned 64-byte boundary beyond
1383 * the end of the surface. The rest of the padding requirements
1384 * documented above do not apply to these surfaces.
1388 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1389 * height % 4 != 0, the surface must be padded with
1390 * 4-(height % 4)*Surface Pitch # of bytes.
1392 if (ISL_DEV_GEN(dev
) >= 9 &&
1393 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1394 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1395 *total_h_el
= isl_align(*total_h_el
, 4);
1399 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1400 * to 4 times the Surface Pitch # of bytes
1402 if (ISL_DEV_GEN(dev
) >= 9 &&
1403 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1404 info
->dim
== ISL_SURF_DIM_1D
) {
1410 isl_surf_init_s(const struct isl_device
*dev
,
1411 struct isl_surf
*surf
,
1412 const struct isl_surf_init_info
*restrict info
)
1414 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1416 const struct isl_extent4d logical_level0_px
= {
1420 .a
= info
->array_len
,
1423 enum isl_tiling tiling
;
1424 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1427 struct isl_tile_info tile_info
;
1428 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1430 const enum isl_dim_layout dim_layout
=
1431 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
);
1433 enum isl_msaa_layout msaa_layout
;
1434 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1437 struct isl_extent3d image_align_el
;
1438 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1441 struct isl_extent3d image_align_sa
=
1442 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1444 struct isl_extent4d phys_level0_sa
;
1445 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1447 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1448 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1450 enum isl_array_pitch_span array_pitch_span
=
1451 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1453 uint32_t array_pitch_el_rows
;
1454 struct isl_extent2d phys_total_el
;
1455 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1456 dim_layout
, msaa_layout
,
1457 &image_align_sa
, &phys_level0_sa
,
1458 array_pitch_span
, &array_pitch_el_rows
,
1461 uint32_t padded_h_el
= phys_total_el
.h
;
1463 isl_apply_surface_padding(dev
, info
, &tile_info
, &padded_h_el
, &pad_bytes
);
1466 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1467 &phys_total_el
, &row_pitch
))
1470 uint32_t size
, base_alignment
;
1471 if (tiling
== ISL_TILING_LINEAR
) {
1472 size
= row_pitch
* padded_h_el
+ pad_bytes
;
1474 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1476 * "The Base Address for linear render target surfaces and surfaces
1477 * accessed with the typed surface read/write data port messages must
1478 * be element-size aligned, for non-YUV surface formats, or a
1479 * multiple of 2 element-sizes for YUV surface formats. Other linear
1480 * surfaces have no alignment requirements (byte alignment is
1483 base_alignment
= MAX(1, info
->min_alignment
);
1484 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1485 if (isl_format_is_yuv(info
->format
)) {
1486 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1488 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1491 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1493 padded_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1494 const uint32_t total_h_tl
=
1495 isl_align_div(padded_h_el
, tile_info
.logical_extent_el
.height
);
1497 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1499 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1500 tile_info
.phys_extent_B
.height
;
1501 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1502 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1505 *surf
= (struct isl_surf
) {
1507 .dim_layout
= dim_layout
,
1508 .msaa_layout
= msaa_layout
,
1510 .format
= info
->format
,
1512 .levels
= info
->levels
,
1513 .samples
= info
->samples
,
1515 .image_alignment_el
= image_align_el
,
1516 .logical_level0_px
= logical_level0_px
,
1517 .phys_level0_sa
= phys_level0_sa
,
1520 .alignment
= base_alignment
,
1521 .row_pitch
= row_pitch
,
1522 .array_pitch_el_rows
= array_pitch_el_rows
,
1523 .array_pitch_span
= array_pitch_span
,
1525 .usage
= info
->usage
,
1532 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1533 struct isl_tile_info
*tile_info
)
1535 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1536 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1540 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1541 const struct isl_surf
*surf
,
1542 struct isl_surf
*hiz_surf
)
1544 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1546 /* Multisampled depth is always interleaved */
1547 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1548 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1550 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1552 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1553 * Target View Extent, and Depth Coordinate Offset X/Y of the
1554 * hierarchical depth buffer are inherited from the depth buffer. The
1555 * height and width of the hierarchical depth buffer that must be
1556 * allocated are computed by the following formulas, where HZ is the
1557 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1558 * Z_Width, and Z_Depth values given in these formulas are those present
1559 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1561 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1562 * being applied to the table below if Number of Multisamples is set to
1563 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1564 * Z_Width must be multiplied by 4 before being applied to the table
1565 * below if Number of Multisamples is set to NUMSAMPLES_8."
1567 * In the Sky Lake PRM, the second paragraph is replaced with this:
1569 * "The Z_Height and Z_Width values must equal those present in
1570 * 3DSTATE_DEPTH_BUFFER incremented by one."
1572 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1573 * block corresponds to a region of 8x4 samples in the primary depth
1574 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1575 * a region of 8x4 pixels in the primary depth surface regardless of the
1576 * number of samples. The dimensions of a HiZ block in both pixels and
1577 * samples are given in the table below:
1579 * | SNB - BDW | SKL+
1580 * ------+-----------+-------------
1581 * 1x | 8 x 4 sa | 8 x 4 sa
1582 * MSAA | 8 x 4 px | 8 x 4 px
1583 * ------+-----------+-------------
1584 * 2x | 8 x 4 sa | 16 x 4 sa
1585 * MSAA | 4 x 4 px | 8 x 4 px
1586 * ------+-----------+-------------
1587 * 4x | 8 x 4 sa | 16 x 8 sa
1588 * MSAA | 4 x 2 px | 8 x 4 px
1589 * ------+-----------+-------------
1590 * 8x | 8 x 4 sa | 32 x 8 sa
1591 * MSAA | 2 x 2 px | 8 x 4 px
1592 * ------+-----------+-------------
1593 * 16x | N/A | 32 x 16 sa
1594 * MSAA | N/A | 8 x 4 px
1595 * ------+-----------+-------------
1597 * There are a number of different ways that this discrepency could be
1598 * handled. The way we have chosen is to simply make MSAA HiZ have the
1599 * same number of samples as the parent surface pre-Sky Lake and always be
1600 * single-sampled on Sky Lake and above. Since the block sizes of
1601 * compressed formats are given in samples, this neatly handles everything
1602 * without the need for additional HiZ formats with different block sizes
1605 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1607 return isl_surf_init(dev
, hiz_surf
,
1609 .format
= ISL_FORMAT_HIZ
,
1610 .width
= surf
->logical_level0_px
.width
,
1611 .height
= surf
->logical_level0_px
.height
,
1612 .depth
= surf
->logical_level0_px
.depth
,
1613 .levels
= surf
->levels
,
1614 .array_len
= surf
->logical_level0_px
.array_len
,
1616 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1617 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1621 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1622 const struct isl_surf
*surf
,
1623 struct isl_surf
*mcs_surf
)
1625 /* It must be multisampled with an array layout */
1626 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1628 /* The following are true of all multisampled surfaces */
1629 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1630 assert(surf
->levels
== 1);
1631 assert(surf
->logical_level0_px
.depth
== 1);
1633 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1634 * bits which means the maximum pitch of a compression surface is 512
1635 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1636 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1637 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1638 * and 8x, we have enough room for the full 16k supported by the hardware.
1640 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1643 enum isl_format mcs_format
;
1644 switch (surf
->samples
) {
1645 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1646 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1647 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1648 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1650 unreachable("Invalid sample count");
1653 return isl_surf_init(dev
, mcs_surf
,
1654 .dim
= ISL_SURF_DIM_2D
,
1655 .format
= mcs_format
,
1656 .width
= surf
->logical_level0_px
.width
,
1657 .height
= surf
->logical_level0_px
.height
,
1660 .array_len
= surf
->logical_level0_px
.array_len
,
1661 .samples
= 1, /* MCS surfaces are really single-sampled */
1662 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1663 .tiling_flags
= ISL_TILING_Y0_BIT
);
1667 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1668 const struct isl_surf
*surf
,
1669 struct isl_surf
*ccs_surf
)
1671 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1672 assert(ISL_DEV_GEN(dev
) >= 7);
1674 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1677 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1680 if (isl_format_is_compressed(surf
->format
))
1683 /* TODO: More conditions where it can fail. */
1685 enum isl_format ccs_format
;
1686 if (ISL_DEV_GEN(dev
) >= 9) {
1687 if (!isl_tiling_is_any_y(surf
->tiling
))
1690 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1691 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1692 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1693 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1697 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1698 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1699 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1700 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1701 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1705 } else if (surf
->tiling
== ISL_TILING_X
) {
1706 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1707 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1708 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1709 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1717 return isl_surf_init(dev
, ccs_surf
,
1719 .format
= ccs_format
,
1720 .width
= surf
->logical_level0_px
.width
,
1721 .height
= surf
->logical_level0_px
.height
,
1722 .depth
= surf
->logical_level0_px
.depth
,
1723 .levels
= surf
->levels
,
1724 .array_len
= surf
->logical_level0_px
.array_len
,
1726 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1727 .tiling_flags
= ISL_TILING_CCS_BIT
);
1731 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1732 const struct isl_surf_fill_state_info
*restrict info
)
1735 isl_surf_usage_flags_t _base_usage
=
1736 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1737 ISL_SURF_USAGE_TEXTURE_BIT
|
1738 ISL_SURF_USAGE_STORAGE_BIT
);
1739 /* They may only specify one of the above bits at a time */
1740 assert(__builtin_popcount(_base_usage
) == 1);
1741 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1742 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1745 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1746 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1747 info
->surf
->logical_level0_px
.depth
);
1749 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1750 info
->surf
->logical_level0_px
.array_len
);
1753 switch (ISL_DEV_GEN(dev
)) {
1755 if (ISL_DEV_IS_G4X(dev
)) {
1756 /* G45 surface state is the same as gen5 */
1757 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1759 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1763 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1766 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1769 if (ISL_DEV_IS_HASWELL(dev
)) {
1770 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1772 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1776 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1779 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1782 assert(!"Cannot fill surface state for this gen");
1787 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1788 const struct isl_buffer_fill_state_info
*restrict info
)
1790 switch (ISL_DEV_GEN(dev
)) {
1793 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1794 isl_gen5_buffer_fill_state_s(state
, info
);
1797 isl_gen6_buffer_fill_state_s(state
, info
);
1800 if (ISL_DEV_IS_HASWELL(dev
)) {
1801 isl_gen75_buffer_fill_state_s(state
, info
);
1803 isl_gen7_buffer_fill_state_s(state
, info
);
1807 isl_gen8_buffer_fill_state_s(state
, info
);
1810 isl_gen9_buffer_fill_state_s(state
, info
);
1813 assert(!"Cannot fill surface state for this gen");
1818 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1819 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
1821 if (info
->depth_surf
&& info
->stencil_surf
) {
1822 if (!dev
->info
->has_hiz_and_separate_stencil
) {
1823 assert(info
->depth_surf
== info
->stencil_surf
);
1824 assert(info
->depth_address
== info
->stencil_address
);
1826 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
1829 if (info
->depth_surf
) {
1830 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
1831 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
1832 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1833 info
->depth_surf
->logical_level0_px
.depth
);
1835 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1836 info
->depth_surf
->logical_level0_px
.array_len
);
1840 if (info
->stencil_surf
) {
1841 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
1842 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
1843 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1844 info
->stencil_surf
->logical_level0_px
.depth
);
1846 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1847 info
->stencil_surf
->logical_level0_px
.array_len
);
1851 switch (ISL_DEV_GEN(dev
)) {
1853 if (ISL_DEV_IS_G4X(dev
)) {
1854 /* G45 surface state is the same as gen5 */
1855 isl_gen5_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1857 isl_gen4_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1861 isl_gen5_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1864 isl_gen6_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1867 if (ISL_DEV_IS_HASWELL(dev
)) {
1868 isl_gen75_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1870 isl_gen7_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1874 isl_gen8_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1877 isl_gen9_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1880 assert(!"Cannot fill surface state for this gen");
1885 * A variant of isl_surf_get_image_offset_sa() specific to
1886 * ISL_DIM_LAYOUT_GEN4_2D.
1889 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1890 uint32_t level
, uint32_t logical_array_layer
,
1891 uint32_t *x_offset_sa
,
1892 uint32_t *y_offset_sa
)
1894 assert(level
< surf
->levels
);
1895 if (surf
->dim
== ISL_SURF_DIM_3D
)
1896 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1898 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1900 const struct isl_extent3d image_align_sa
=
1901 isl_surf_get_image_alignment_sa(surf
);
1903 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1904 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1906 const uint32_t phys_layer
= logical_array_layer
*
1907 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1910 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1912 for (uint32_t l
= 0; l
< level
; ++l
) {
1914 uint32_t W
= isl_minify(W0
, l
);
1915 x
+= isl_align_npot(W
, image_align_sa
.w
);
1917 uint32_t H
= isl_minify(H0
, l
);
1918 y
+= isl_align_npot(H
, image_align_sa
.h
);
1927 * A variant of isl_surf_get_image_offset_sa() specific to
1928 * ISL_DIM_LAYOUT_GEN4_3D.
1931 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1932 uint32_t level
, uint32_t logical_z_offset_px
,
1933 uint32_t *x_offset_sa
,
1934 uint32_t *y_offset_sa
)
1936 assert(level
< surf
->levels
);
1937 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1938 assert(surf
->phys_level0_sa
.array_len
== 1);
1939 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1941 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1942 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1943 assert(surf
->phys_level0_sa
.array_len
== 6);
1944 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
1947 const struct isl_extent3d image_align_sa
=
1948 isl_surf_get_image_alignment_sa(surf
);
1950 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1951 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1952 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1953 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
1958 for (uint32_t l
= 0; l
< level
; ++l
) {
1959 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1960 const uint32_t level_d
=
1961 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
1963 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1965 y
+= level_h
* max_layers_vert
;
1968 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1969 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1970 const uint32_t level_d
=
1971 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
1974 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1976 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1977 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1984 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
1986 uint32_t logical_array_layer
,
1987 uint32_t *x_offset_sa
,
1988 uint32_t *y_offset_sa
)
1990 assert(level
< surf
->levels
);
1991 assert(surf
->logical_level0_px
.depth
== 1);
1992 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1994 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1996 const struct isl_extent3d image_align_sa
=
1997 isl_surf_get_image_alignment_sa(surf
);
1999 struct isl_tile_info tile_info
;
2000 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2001 const struct isl_extent2d tile_extent_sa
= {
2002 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2003 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2005 /* Tile size is a multiple of image alignment */
2006 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2007 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2009 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2010 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2012 /* Each image has the same height as LOD0 because the hardware thinks
2013 * everything is LOD0
2015 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2017 /* Quick sanity check for consistency */
2018 if (surf
->phys_level0_sa
.array_len
> 1)
2019 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2021 uint32_t x
= 0, y
= 0;
2022 for (uint32_t l
= 0; l
< level
; ++l
) {
2023 const uint32_t W
= isl_minify(W0
, l
);
2025 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2026 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2036 y
+= H
* logical_array_layer
;
2043 * A variant of isl_surf_get_image_offset_sa() specific to
2044 * ISL_DIM_LAYOUT_GEN9_1D.
2047 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2048 uint32_t level
, uint32_t layer
,
2049 uint32_t *x_offset_sa
,
2050 uint32_t *y_offset_sa
)
2052 assert(level
< surf
->levels
);
2053 assert(layer
< surf
->phys_level0_sa
.array_len
);
2054 assert(surf
->phys_level0_sa
.height
== 1);
2055 assert(surf
->phys_level0_sa
.depth
== 1);
2056 assert(surf
->samples
== 1);
2058 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2059 const struct isl_extent3d image_align_sa
=
2060 isl_surf_get_image_alignment_sa(surf
);
2064 for (uint32_t l
= 0; l
< level
; ++l
) {
2065 uint32_t W
= isl_minify(W0
, l
);
2066 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2072 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2076 * Calculate the offset, in units of surface samples, to a subimage in the
2079 * @invariant level < surface levels
2080 * @invariant logical_array_layer < logical array length of surface
2081 * @invariant logical_z_offset_px < logical depth of surface at level
2084 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2086 uint32_t logical_array_layer
,
2087 uint32_t logical_z_offset_px
,
2088 uint32_t *x_offset_sa
,
2089 uint32_t *y_offset_sa
)
2091 assert(level
< surf
->levels
);
2092 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2093 assert(logical_z_offset_px
2094 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2096 switch (surf
->dim_layout
) {
2097 case ISL_DIM_LAYOUT_GEN9_1D
:
2098 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2099 x_offset_sa
, y_offset_sa
);
2101 case ISL_DIM_LAYOUT_GEN4_2D
:
2102 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2103 + logical_z_offset_px
,
2104 x_offset_sa
, y_offset_sa
);
2106 case ISL_DIM_LAYOUT_GEN4_3D
:
2107 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2108 logical_z_offset_px
,
2109 x_offset_sa
, y_offset_sa
);
2111 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2112 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2113 logical_z_offset_px
,
2114 x_offset_sa
, y_offset_sa
);
2118 unreachable("not reached");
2123 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2125 uint32_t logical_array_layer
,
2126 uint32_t logical_z_offset_px
,
2127 uint32_t *x_offset_el
,
2128 uint32_t *y_offset_el
)
2130 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2132 assert(level
< surf
->levels
);
2133 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2134 assert(logical_z_offset_px
2135 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2137 uint32_t x_offset_sa
, y_offset_sa
;
2138 isl_surf_get_image_offset_sa(surf
, level
,
2139 logical_array_layer
,
2140 logical_z_offset_px
,
2144 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2145 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2149 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2151 uint32_t logical_array_layer
,
2152 uint32_t logical_z_offset_px
,
2154 uint32_t *x_offset_sa
,
2155 uint32_t *y_offset_sa
)
2157 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2159 uint32_t total_x_offset_el
, total_y_offset_el
;
2160 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2161 logical_z_offset_px
,
2163 &total_y_offset_el
);
2165 uint32_t x_offset_el
, y_offset_el
;
2166 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2175 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2177 assert(x_offset_el
== 0);
2181 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2183 assert(y_offset_el
== 0);
2188 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2191 uint32_t total_x_offset_el
,
2192 uint32_t total_y_offset_el
,
2193 uint32_t *base_address_offset
,
2194 uint32_t *x_offset_el
,
2195 uint32_t *y_offset_el
)
2197 if (tiling
== ISL_TILING_LINEAR
) {
2198 assert(bpb
% 8 == 0);
2199 *base_address_offset
= total_y_offset_el
* row_pitch
+
2200 total_x_offset_el
* (bpb
/ 8);
2206 struct isl_tile_info tile_info
;
2207 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2209 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
2211 /* For non-power-of-two formats, we need the address to be both tile and
2212 * element-aligned. The easiest way to achieve this is to work with a tile
2213 * that is three times as wide as the regular tile.
2215 * The tile info returned by get_tile_info has a logical size that is an
2216 * integer number of tile_info.format_bpb size elements. To scale the
2217 * tile, we scale up the physical width and then treat the logical tile
2218 * size as if it has bpb size elements.
2220 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2221 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2223 /* Compute the offset into the tile */
2224 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2225 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2227 /* Compute the offset of the tile in units of whole tiles */
2228 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2229 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2231 *base_address_offset
=
2232 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
2233 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2237 isl_surf_get_depth_format(const struct isl_device
*dev
,
2238 const struct isl_surf
*surf
)
2240 /* Support for separate stencil buffers began in gen5. Support for
2241 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2242 * those that supported separate and interleaved stencil, were gen5 and
2245 * For a list of all available formats, see the Sandybridge PRM >> Volume
2246 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2250 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2252 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2255 assert(ISL_DEV_GEN(dev
) < 7);
2257 switch (surf
->format
) {
2259 unreachable("bad isl depth format");
2260 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2261 assert(ISL_DEV_GEN(dev
) < 7);
2262 return 0; /* D32_FLOAT_S8X24_UINT */
2263 case ISL_FORMAT_R32_FLOAT
:
2264 assert(!has_stencil
);
2265 return 1; /* D32_FLOAT */
2266 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2268 assert(ISL_DEV_GEN(dev
) < 7);
2269 return 2; /* D24_UNORM_S8_UINT */
2271 assert(ISL_DEV_GEN(dev
) >= 5);
2272 return 3; /* D24_UNORM_X8_UINT */
2274 case ISL_FORMAT_R16_UNORM
:
2275 assert(!has_stencil
);
2276 return 5; /* D16_UNORM */