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intel/isl: Move get_format_encoding function to isl
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47 #include "util/format/u_format.h"
48
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52
53 struct gen_device_info;
54 struct brw_image_param;
55
56 #ifndef ISL_DEV_GEN
57 /**
58 * @brief Get the hardware generation of isl_device.
59 *
60 * You can define this as a compile-time constant in the CFLAGS. For example,
61 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
62 */
63 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
64 #define ISL_DEV_GEN_SANITIZE(__dev)
65 #else
66 #define ISL_DEV_GEN_SANITIZE(__dev) \
67 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
68 #endif
69
70 #ifndef ISL_DEV_IS_G4X
71 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
72 #endif
73
74 #ifndef ISL_DEV_IS_HASWELL
75 /**
76 * @brief Get the hardware generation of isl_device.
77 *
78 * You can define this as a compile-time constant in the CFLAGS. For example,
79 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
80 */
81 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
82 #endif
83
84 #ifndef ISL_DEV_IS_BAYTRAIL
85 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
86 #endif
87
88 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
89 /**
90 * You can define this as a compile-time constant in the CFLAGS. For example,
91 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
92 */
93 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
94 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
95 #else
96 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
97 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
98 #endif
99
100 /**
101 * Hardware enumeration SURFACE_FORMAT.
102 *
103 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
104 * Enumerations: SURFACE_FORMAT.
105 */
106 enum isl_format {
107 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
108 ISL_FORMAT_R32G32B32A32_SINT = 1,
109 ISL_FORMAT_R32G32B32A32_UINT = 2,
110 ISL_FORMAT_R32G32B32A32_UNORM = 3,
111 ISL_FORMAT_R32G32B32A32_SNORM = 4,
112 ISL_FORMAT_R64G64_FLOAT = 5,
113 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
114 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
115 ISL_FORMAT_R32G32B32A32_USCALED = 8,
116 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
117 ISL_FORMAT_R64G64_PASSTHRU = 33,
118 ISL_FORMAT_R32G32B32_FLOAT = 64,
119 ISL_FORMAT_R32G32B32_SINT = 65,
120 ISL_FORMAT_R32G32B32_UINT = 66,
121 ISL_FORMAT_R32G32B32_UNORM = 67,
122 ISL_FORMAT_R32G32B32_SNORM = 68,
123 ISL_FORMAT_R32G32B32_SSCALED = 69,
124 ISL_FORMAT_R32G32B32_USCALED = 70,
125 ISL_FORMAT_R32G32B32_SFIXED = 80,
126 ISL_FORMAT_R16G16B16A16_UNORM = 128,
127 ISL_FORMAT_R16G16B16A16_SNORM = 129,
128 ISL_FORMAT_R16G16B16A16_SINT = 130,
129 ISL_FORMAT_R16G16B16A16_UINT = 131,
130 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
131 ISL_FORMAT_R32G32_FLOAT = 133,
132 ISL_FORMAT_R32G32_SINT = 134,
133 ISL_FORMAT_R32G32_UINT = 135,
134 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
135 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
136 ISL_FORMAT_L32A32_FLOAT = 138,
137 ISL_FORMAT_R32G32_UNORM = 139,
138 ISL_FORMAT_R32G32_SNORM = 140,
139 ISL_FORMAT_R64_FLOAT = 141,
140 ISL_FORMAT_R16G16B16X16_UNORM = 142,
141 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
142 ISL_FORMAT_A32X32_FLOAT = 144,
143 ISL_FORMAT_L32X32_FLOAT = 145,
144 ISL_FORMAT_I32X32_FLOAT = 146,
145 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
146 ISL_FORMAT_R16G16B16A16_USCALED = 148,
147 ISL_FORMAT_R32G32_SSCALED = 149,
148 ISL_FORMAT_R32G32_USCALED = 150,
149 ISL_FORMAT_R32G32_FLOAT_LD = 151,
150 ISL_FORMAT_R32G32_SFIXED = 160,
151 ISL_FORMAT_R64_PASSTHRU = 161,
152 ISL_FORMAT_B8G8R8A8_UNORM = 192,
153 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
154 ISL_FORMAT_R10G10B10A2_UNORM = 194,
155 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
156 ISL_FORMAT_R10G10B10A2_UINT = 196,
157 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
158 ISL_FORMAT_R8G8B8A8_UNORM = 199,
159 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
160 ISL_FORMAT_R8G8B8A8_SNORM = 201,
161 ISL_FORMAT_R8G8B8A8_SINT = 202,
162 ISL_FORMAT_R8G8B8A8_UINT = 203,
163 ISL_FORMAT_R16G16_UNORM = 204,
164 ISL_FORMAT_R16G16_SNORM = 205,
165 ISL_FORMAT_R16G16_SINT = 206,
166 ISL_FORMAT_R16G16_UINT = 207,
167 ISL_FORMAT_R16G16_FLOAT = 208,
168 ISL_FORMAT_B10G10R10A2_UNORM = 209,
169 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
170 ISL_FORMAT_R11G11B10_FLOAT = 211,
171 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
172 ISL_FORMAT_R32_SINT = 214,
173 ISL_FORMAT_R32_UINT = 215,
174 ISL_FORMAT_R32_FLOAT = 216,
175 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
176 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
177 ISL_FORMAT_L32_UNORM = 221,
178 ISL_FORMAT_A32_UNORM = 222,
179 ISL_FORMAT_L16A16_UNORM = 223,
180 ISL_FORMAT_I24X8_UNORM = 224,
181 ISL_FORMAT_L24X8_UNORM = 225,
182 ISL_FORMAT_A24X8_UNORM = 226,
183 ISL_FORMAT_I32_FLOAT = 227,
184 ISL_FORMAT_L32_FLOAT = 228,
185 ISL_FORMAT_A32_FLOAT = 229,
186 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
187 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
188 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
189 ISL_FORMAT_B8G8R8X8_UNORM = 233,
190 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
191 ISL_FORMAT_R8G8B8X8_UNORM = 235,
192 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
193 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
194 ISL_FORMAT_B10G10R10X2_UNORM = 238,
195 ISL_FORMAT_L16A16_FLOAT = 240,
196 ISL_FORMAT_R32_UNORM = 241,
197 ISL_FORMAT_R32_SNORM = 242,
198 ISL_FORMAT_R10G10B10X2_USCALED = 243,
199 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
200 ISL_FORMAT_R8G8B8A8_USCALED = 245,
201 ISL_FORMAT_R16G16_SSCALED = 246,
202 ISL_FORMAT_R16G16_USCALED = 247,
203 ISL_FORMAT_R32_SSCALED = 248,
204 ISL_FORMAT_R32_USCALED = 249,
205 ISL_FORMAT_B5G6R5_UNORM = 256,
206 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
207 ISL_FORMAT_B5G5R5A1_UNORM = 258,
208 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
209 ISL_FORMAT_B4G4R4A4_UNORM = 260,
210 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
211 ISL_FORMAT_R8G8_UNORM = 262,
212 ISL_FORMAT_R8G8_SNORM = 263,
213 ISL_FORMAT_R8G8_SINT = 264,
214 ISL_FORMAT_R8G8_UINT = 265,
215 ISL_FORMAT_R16_UNORM = 266,
216 ISL_FORMAT_R16_SNORM = 267,
217 ISL_FORMAT_R16_SINT = 268,
218 ISL_FORMAT_R16_UINT = 269,
219 ISL_FORMAT_R16_FLOAT = 270,
220 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
221 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
222 ISL_FORMAT_I16_UNORM = 273,
223 ISL_FORMAT_L16_UNORM = 274,
224 ISL_FORMAT_A16_UNORM = 275,
225 ISL_FORMAT_L8A8_UNORM = 276,
226 ISL_FORMAT_I16_FLOAT = 277,
227 ISL_FORMAT_L16_FLOAT = 278,
228 ISL_FORMAT_A16_FLOAT = 279,
229 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
230 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
231 ISL_FORMAT_B5G5R5X1_UNORM = 282,
232 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
233 ISL_FORMAT_R8G8_SSCALED = 284,
234 ISL_FORMAT_R8G8_USCALED = 285,
235 ISL_FORMAT_R16_SSCALED = 286,
236 ISL_FORMAT_R16_USCALED = 287,
237 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
238 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
239 ISL_FORMAT_A1B5G5R5_UNORM = 292,
240 ISL_FORMAT_A4B4G4R4_UNORM = 293,
241 ISL_FORMAT_L8A8_UINT = 294,
242 ISL_FORMAT_L8A8_SINT = 295,
243 ISL_FORMAT_R8_UNORM = 320,
244 ISL_FORMAT_R8_SNORM = 321,
245 ISL_FORMAT_R8_SINT = 322,
246 ISL_FORMAT_R8_UINT = 323,
247 ISL_FORMAT_A8_UNORM = 324,
248 ISL_FORMAT_I8_UNORM = 325,
249 ISL_FORMAT_L8_UNORM = 326,
250 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
251 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
252 ISL_FORMAT_R8_SSCALED = 329,
253 ISL_FORMAT_R8_USCALED = 330,
254 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
255 ISL_FORMAT_L8_UNORM_SRGB = 332,
256 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
257 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
258 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
259 ISL_FORMAT_Y8_UNORM = 336,
260 ISL_FORMAT_L8_UINT = 338,
261 ISL_FORMAT_L8_SINT = 339,
262 ISL_FORMAT_I8_UINT = 340,
263 ISL_FORMAT_I8_SINT = 341,
264 ISL_FORMAT_DXT1_RGB_SRGB = 384,
265 ISL_FORMAT_R1_UNORM = 385,
266 ISL_FORMAT_YCRCB_NORMAL = 386,
267 ISL_FORMAT_YCRCB_SWAPUVY = 387,
268 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
269 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
270 ISL_FORMAT_BC1_UNORM = 390,
271 ISL_FORMAT_BC2_UNORM = 391,
272 ISL_FORMAT_BC3_UNORM = 392,
273 ISL_FORMAT_BC4_UNORM = 393,
274 ISL_FORMAT_BC5_UNORM = 394,
275 ISL_FORMAT_BC1_UNORM_SRGB = 395,
276 ISL_FORMAT_BC2_UNORM_SRGB = 396,
277 ISL_FORMAT_BC3_UNORM_SRGB = 397,
278 ISL_FORMAT_MONO8 = 398,
279 ISL_FORMAT_YCRCB_SWAPUV = 399,
280 ISL_FORMAT_YCRCB_SWAPY = 400,
281 ISL_FORMAT_DXT1_RGB = 401,
282 ISL_FORMAT_FXT1 = 402,
283 ISL_FORMAT_R8G8B8_UNORM = 403,
284 ISL_FORMAT_R8G8B8_SNORM = 404,
285 ISL_FORMAT_R8G8B8_SSCALED = 405,
286 ISL_FORMAT_R8G8B8_USCALED = 406,
287 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
288 ISL_FORMAT_R64G64B64_FLOAT = 408,
289 ISL_FORMAT_BC4_SNORM = 409,
290 ISL_FORMAT_BC5_SNORM = 410,
291 ISL_FORMAT_R16G16B16_FLOAT = 411,
292 ISL_FORMAT_R16G16B16_UNORM = 412,
293 ISL_FORMAT_R16G16B16_SNORM = 413,
294 ISL_FORMAT_R16G16B16_SSCALED = 414,
295 ISL_FORMAT_R16G16B16_USCALED = 415,
296 ISL_FORMAT_BC6H_SF16 = 417,
297 ISL_FORMAT_BC7_UNORM = 418,
298 ISL_FORMAT_BC7_UNORM_SRGB = 419,
299 ISL_FORMAT_BC6H_UF16 = 420,
300 ISL_FORMAT_PLANAR_420_8 = 421,
301 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
302 ISL_FORMAT_ETC1_RGB8 = 425,
303 ISL_FORMAT_ETC2_RGB8 = 426,
304 ISL_FORMAT_EAC_R11 = 427,
305 ISL_FORMAT_EAC_RG11 = 428,
306 ISL_FORMAT_EAC_SIGNED_R11 = 429,
307 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
308 ISL_FORMAT_ETC2_SRGB8 = 431,
309 ISL_FORMAT_R16G16B16_UINT = 432,
310 ISL_FORMAT_R16G16B16_SINT = 433,
311 ISL_FORMAT_R32_SFIXED = 434,
312 ISL_FORMAT_R10G10B10A2_SNORM = 435,
313 ISL_FORMAT_R10G10B10A2_USCALED = 436,
314 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
315 ISL_FORMAT_R10G10B10A2_SINT = 438,
316 ISL_FORMAT_B10G10R10A2_SNORM = 439,
317 ISL_FORMAT_B10G10R10A2_USCALED = 440,
318 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
319 ISL_FORMAT_B10G10R10A2_UINT = 442,
320 ISL_FORMAT_B10G10R10A2_SINT = 443,
321 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
322 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
323 ISL_FORMAT_ETC2_RGB8_PTA = 448,
324 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
325 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
326 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
327 ISL_FORMAT_R8G8B8_UINT = 456,
328 ISL_FORMAT_R8G8B8_SINT = 457,
329 ISL_FORMAT_RAW = 511,
330 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
331 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
332 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
333 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
334 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
335 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
336 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
337 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
338 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
339 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
340 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
341 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
342 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
343 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
344 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
345 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
346 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
347 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
348 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
349 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
350 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
351 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
352 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
353 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
354 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
355 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
356 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
357 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
358 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
359 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
360 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
361 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
362 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
363 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
364 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
365 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
366 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
367 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
368 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
369 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
370 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
371 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
372
373 /* The formats that follow are internal to ISL and as such don't have an
374 * explicit number. We'll just let the C compiler assign it for us. Any
375 * actual hardware formats *must* come before these in the list.
376 */
377
378 /* Formats for auxiliary surfaces */
379 ISL_FORMAT_HIZ,
380 ISL_FORMAT_MCS_2X,
381 ISL_FORMAT_MCS_4X,
382 ISL_FORMAT_MCS_8X,
383 ISL_FORMAT_MCS_16X,
384 ISL_FORMAT_GEN7_CCS_32BPP_X,
385 ISL_FORMAT_GEN7_CCS_64BPP_X,
386 ISL_FORMAT_GEN7_CCS_128BPP_X,
387 ISL_FORMAT_GEN7_CCS_32BPP_Y,
388 ISL_FORMAT_GEN7_CCS_64BPP_Y,
389 ISL_FORMAT_GEN7_CCS_128BPP_Y,
390 ISL_FORMAT_GEN9_CCS_32BPP,
391 ISL_FORMAT_GEN9_CCS_64BPP,
392 ISL_FORMAT_GEN9_CCS_128BPP,
393 ISL_FORMAT_GEN12_CCS_8BPP_Y0,
394 ISL_FORMAT_GEN12_CCS_16BPP_Y0,
395 ISL_FORMAT_GEN12_CCS_32BPP_Y0,
396 ISL_FORMAT_GEN12_CCS_64BPP_Y0,
397 ISL_FORMAT_GEN12_CCS_128BPP_Y0,
398
399 /* An upper bound on the supported format enumerations */
400 ISL_NUM_FORMATS,
401
402 /* Hardware doesn't understand this out-of-band value */
403 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
404 };
405
406 /**
407 * Numerical base type for channels of isl_format.
408 */
409 enum isl_base_type {
410 ISL_VOID,
411 ISL_RAW,
412 ISL_UNORM,
413 ISL_SNORM,
414 ISL_UFLOAT,
415 ISL_SFLOAT,
416 ISL_UFIXED,
417 ISL_SFIXED,
418 ISL_UINT,
419 ISL_SINT,
420 ISL_USCALED,
421 ISL_SSCALED,
422 };
423
424 /**
425 * Colorspace of isl_format.
426 */
427 enum isl_colorspace {
428 ISL_COLORSPACE_NONE = 0,
429 ISL_COLORSPACE_LINEAR,
430 ISL_COLORSPACE_SRGB,
431 ISL_COLORSPACE_YUV,
432 };
433
434 /**
435 * Texture compression mode of isl_format.
436 */
437 enum isl_txc {
438 ISL_TXC_NONE = 0,
439 ISL_TXC_DXT1,
440 ISL_TXC_DXT3,
441 ISL_TXC_DXT5,
442 ISL_TXC_FXT1,
443 ISL_TXC_RGTC1,
444 ISL_TXC_RGTC2,
445 ISL_TXC_BPTC,
446 ISL_TXC_ETC1,
447 ISL_TXC_ETC2,
448 ISL_TXC_ASTC,
449
450 /* Used for auxiliary surface formats */
451 ISL_TXC_HIZ,
452 ISL_TXC_MCS,
453 ISL_TXC_CCS,
454 };
455
456 /**
457 * @brief Hardware tile mode
458 *
459 * WARNING: These values differ from the hardware enum values, which are
460 * unstable across hardware generations.
461 *
462 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
463 * clearly distinguish it from Yf and Ys.
464 */
465 enum isl_tiling {
466 ISL_TILING_LINEAR = 0,
467 ISL_TILING_W,
468 ISL_TILING_X,
469 ISL_TILING_Y0, /**< Legacy Y tiling */
470 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
471 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
472 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
473 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
474 ISL_TILING_GEN12_CCS, /**< Tiling format for Gen12 CCS surfaces */
475 };
476
477 /**
478 * @defgroup Tiling Flags
479 * @{
480 */
481 typedef uint32_t isl_tiling_flags_t;
482 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
483 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
484 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
485 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
486 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
487 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
488 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
489 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
490 #define ISL_TILING_GEN12_CCS_BIT (1u << ISL_TILING_GEN12_CCS)
491 #define ISL_TILING_ANY_MASK (~0u)
492 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
493
494 /** Any Y tiling, including legacy Y tiling. */
495 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
496 ISL_TILING_Yf_BIT | \
497 ISL_TILING_Ys_BIT)
498
499 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
500 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
501 ISL_TILING_Ys_BIT)
502 /** @} */
503
504 /**
505 * @brief Logical dimension of surface.
506 *
507 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
508 * as 2D array surfaces.
509 */
510 enum isl_surf_dim {
511 ISL_SURF_DIM_1D,
512 ISL_SURF_DIM_2D,
513 ISL_SURF_DIM_3D,
514 };
515
516 /**
517 * @brief Physical layout of the surface's dimensions.
518 */
519 enum isl_dim_layout {
520 /**
521 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
522 * 6.17.3: 2D Surfaces.
523 *
524 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
525 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
526 *
527 * One-dimensional surfaces are identical to 2D surfaces with height of
528 * one.
529 *
530 * @invariant isl_surf::phys_level0_sa::depth == 1
531 */
532 ISL_DIM_LAYOUT_GEN4_2D,
533
534 /**
535 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
536 * 6.17.5: 3D Surfaces.
537 *
538 * @invariant isl_surf::phys_level0_sa::array_len == 1
539 */
540 ISL_DIM_LAYOUT_GEN4_3D,
541
542 /**
543 * Special layout used for HiZ and stencil on Sandy Bridge to work around
544 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
545 * work the same as on gen7+ except that they don't technically support
546 * mipmapping. That does not, however, stop us from doing it. As far as
547 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
548 * single miplevel 2D (possibly array) image. The dimensions of that image
549 * are NOT minified.
550 *
551 * In order to implement HiZ and stencil on Sandy Bridge, we create one
552 * full-sized 2D (possibly array) image for every LOD with every image
553 * aligned to a page boundary. When the surface is used with the stencil
554 * or HiZ hardware, we manually offset to the image for the given LOD.
555 *
556 * As a memory saving measure, we pretend that the width of each miplevel
557 * is minified and we place LOD1 and above below LOD0 but horizontally
558 * adjacent to each other. When considered as full-sized images, LOD1 and
559 * above technically overlap. However, since we only write to part of that
560 * image, the hardware will never notice the overlap.
561 *
562 * This layout looks something like this:
563 *
564 * +---------+
565 * | |
566 * | |
567 * +---------+
568 * | |
569 * | |
570 * +---------+
571 *
572 * +----+ +-+ .
573 * | | +-+
574 * +----+
575 *
576 * +----+ +-+ .
577 * | | +-+
578 * +----+
579 */
580 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ,
581
582 /**
583 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
584 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
585 */
586 ISL_DIM_LAYOUT_GEN9_1D,
587 };
588
589 enum isl_aux_usage {
590 /** No Auxiliary surface is used */
591 ISL_AUX_USAGE_NONE,
592
593 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
594 ISL_AUX_USAGE_HIZ,
595
596 /** The auxiliary surface is an MCS
597 *
598 * @invariant isl_surf::samples > 1
599 */
600 ISL_AUX_USAGE_MCS,
601
602 /** The auxiliary surface is a fast-clear-only compression surface
603 *
604 * @invariant isl_surf::samples == 1
605 */
606 ISL_AUX_USAGE_CCS_D,
607
608 /** The auxiliary surface provides full lossless color compression
609 *
610 * @invariant isl_surf::samples == 1
611 */
612 ISL_AUX_USAGE_CCS_E,
613
614 /** The auxiliary surface provides full lossless media color compression
615 *
616 * @invariant isl_surf::samples == 1
617 */
618 ISL_AUX_USAGE_MC,
619
620 /** The auxiliary surface is a HiZ surface and CCS is also enabled */
621 ISL_AUX_USAGE_HIZ_CCS,
622
623 /** The auxiliary surface is an MCS and CCS is also enabled
624 *
625 * @invariant isl_surf::samples > 1
626 */
627 ISL_AUX_USAGE_MCS_CCS,
628 };
629
630 /**
631 * Enum for keeping track of the state an auxiliary compressed surface.
632 *
633 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
634 * given slice (lod + array layer) can be in one of the six states described
635 * by this enum. Draw and resolve operations may cause the slice to change
636 * from one state to another. The six valid states are:
637 *
638 * 1) Clear: In this state, each block in the auxiliary surface contains a
639 * magic value that indicates that the block is in the clear state. If
640 * a block is in the clear state, it's values in the primary surface are
641 * ignored and the color of the samples in the block is taken either the
642 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
643 * depth. Since neither the primary surface nor the auxiliary surface
644 * contains the clear value, the surface can be cleared to a different
645 * color by simply changing the clear color without modifying either
646 * surface.
647 *
648 * 2) Partial Clear: In this state, each block in the auxiliary surface
649 * contains either the magic clear or pass-through value. See Clear and
650 * Pass-through for more details.
651 *
652 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
653 * nor the primary surface has a complete representation of the data.
654 * Instead, both surfaces must be used together or else rendering
655 * corruption may occur. Depending on the auxiliary compression format
656 * and the data, any given block in the primary surface may contain all,
657 * some, or none of the data required to reconstruct the actual sample
658 * values. Blocks may also be in the clear state (see Clear) and have
659 * their value taken from outside the surface.
660 *
661 * 4) Compressed w/o Clear: This state is identical to the state above
662 * except that no blocks are in the clear state. In this state, all of
663 * the data required to reconstruct the final sample values is contained
664 * in the auxiliary and primary surface and the clear value is not
665 * considered.
666 *
667 * 5) Resolved: In this state, the primary surface contains 100% of the
668 * data. The auxiliary surface is also valid so the surface can be
669 * validly used with or without aux enabled. The auxiliary surface may,
670 * however, contain non-trivial data and any update to the primary
671 * surface with aux disabled will cause the two to get out of sync.
672 *
673 * 6) Pass-through: In this state, the primary surface contains 100% of the
674 * data and every block in the auxiliary surface contains a magic value
675 * which indicates that the auxiliary surface should be ignored and the
676 * only the primary surface should be considered. Updating the primary
677 * surface without aux works fine and can be done repeatedly in this
678 * mode. Writing to a surface in pass-through mode with aux enabled may
679 * cause the auxiliary buffer to contain non-trivial data and no longer
680 * be in the pass-through state.
681 *
682 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
683 * data and the auxiliary surface is completely bogus. Any attempt to
684 * use the auxiliary surface is liable to result in rendering
685 * corruption. The only thing that one can do to re-enable aux once
686 * this state is reached is to use an ambiguate pass to transition into
687 * the pass-through state.
688 *
689 * Drawing with or without aux enabled may implicitly cause the surface to
690 * transition between these states. There are also four types of auxiliary
691 * compression operations which cause an explicit transition which are
692 * described by the isl_aux_op enum below.
693 *
694 * Not all operations are valid or useful in all states. The diagram below
695 * contains a complete description of the states and all valid and useful
696 * transitions except clear.
697 *
698 * Draw w/ Aux
699 * +----------+
700 * | |
701 * | +-------------+ Draw w/ Aux +-------------+
702 * +------>| Compressed |<-------------------| Clear |
703 * | w/ Clear |----->----+ | |
704 * +-------------+ | +-------------+
705 * | /|\ | | |
706 * | | | | |
707 * | | +------<-----+ | Draw w/
708 * | | | | Clear Only
709 * | | Full | | +----------+
710 * Partial | | Resolve | \|/ | |
711 * Resolve | | | +-------------+ |
712 * | | | | Partial |<------+
713 * | | | | Clear |<----------+
714 * | | | +-------------+ |
715 * | | | | |
716 * | | +------>---------+ Full |
717 * | | | Resolve |
718 * Draw w/ aux | | Partial Fast Clear | |
719 * +----------+ | +--------------------------+ | |
720 * | | \|/ | \|/ |
721 * | +-------------+ Full Resolve +-------------+ |
722 * +------>| Compressed |------------------->| Resolved | |
723 * | w/o Clear |<-------------------| | |
724 * +-------------+ Draw w/ Aux +-------------+ |
725 * /|\ | | |
726 * | Draw | | Draw |
727 * | w/ Aux | | w/o Aux |
728 * | Ambiguate | | |
729 * | +--------------------------+ | |
730 * Draw w/o Aux | | | Draw w/o Aux |
731 * +----------+ | | | +----------+ |
732 * | | | \|/ \|/ | | |
733 * | +-------------+ Ambiguate +-------------+ | |
734 * +------>| Pass- |<-------------------| Aux |<------+ |
735 * +------>| through | | Invalid | |
736 * | +-------------+ +-------------+ |
737 * | | | |
738 * +----------+ +-----------------------------------------------------+
739 * Draw w/ Partial Fast Clear
740 * Clear Only
741 *
742 *
743 * While the above general theory applies to all forms of auxiliary
744 * compression on Intel hardware, not all states and operations are available
745 * on all compression types. However, each of the auxiliary states and
746 * operations can be fairly easily mapped onto the above diagram:
747 *
748 * HiZ: Hierarchical depth compression is capable of being in any of the
749 * states above. Hardware provides three HiZ operations: "Depth
750 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
751 * Clear", "Full Resolve", and "Ambiguate" respectively. The
752 * hardware provides no HiZ partial resolve operation so the only way
753 * to get into the "Compressed w/o Clear" state is to render with HiZ
754 * when the surface is in the resolved or pass-through states.
755 *
756 * MCS: Multisample compression is technically capable of being in any of
757 * the states above except that most of them aren't useful. Both the
758 * render engine and the sampler support MCS compression and, apart
759 * from clear color, MCS is format-unaware so we leave the surface
760 * compressed 100% of the time. The hardware provides no MCS
761 * operations.
762 *
763 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
764 * the simplest forms of compression since they don't do anything
765 * beyond clear color tracking. They really only support three of
766 * the six states: Clear, Partial Clear, and Pass-through. The
767 * only CCS_D operation is "Resolve" which maps to a full resolve
768 * followed by an ambiguate.
769 *
770 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
771 * is capable of being in almost all of the above states. THe only
772 * exception is that it does not have separate resolved and pass-
773 * through states. Instead, the CCS_E full resolve operation does
774 * both a resolve and an ambiguate so it goes directly into the
775 * pass-through state. CCS_E also provides fast clear and partial
776 * resolve operations which work as described above.
777 *
778 * While it is technically possible to perform a CCS_E ambiguate, it
779 * is not provided by Sky Lake hardware so we choose to avoid the aux
780 * invalid state. If the aux invalid state were determined to be
781 * useful, a CCS ambiguate could be done by carefully rendering to
782 * the CCS and filling it with zeros.
783 */
784 enum isl_aux_state {
785 ISL_AUX_STATE_CLEAR = 0,
786 ISL_AUX_STATE_PARTIAL_CLEAR,
787 ISL_AUX_STATE_COMPRESSED_CLEAR,
788 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
789 ISL_AUX_STATE_RESOLVED,
790 ISL_AUX_STATE_PASS_THROUGH,
791 ISL_AUX_STATE_AUX_INVALID,
792 };
793
794 /**
795 * Enum which describes explicit aux transition operations.
796 */
797 enum isl_aux_op {
798 ISL_AUX_OP_NONE,
799
800 /** Fast Clear
801 *
802 * This operation writes the magic "clear" value to the auxiliary surface.
803 * This operation will safely transition any slice of a surface from any
804 * state to the clear state so long as the entire slice is fast cleared at
805 * once. A fast clear that only covers part of a slice of a surface is
806 * called a partial fast clear.
807 */
808 ISL_AUX_OP_FAST_CLEAR,
809
810 /** Full Resolve
811 *
812 * This operation combines the auxiliary surface data with the primary
813 * surface data and writes the result to the primary. For HiZ, the docs
814 * call this a depth resolve. For CCS, the hardware full resolve operation
815 * does both a full resolve and an ambiguate so it actually takes you all
816 * the way to the pass-through state.
817 */
818 ISL_AUX_OP_FULL_RESOLVE,
819
820 /** Partial Resolve
821 *
822 * This operation considers blocks which are in the "clear" state and
823 * writes the clear value directly into the primary or auxiliary surface.
824 * Once this operation completes, the surface is still compressed but no
825 * longer references the clear color. This operation is only available
826 * for CCS_E.
827 */
828 ISL_AUX_OP_PARTIAL_RESOLVE,
829
830 /** Ambiguate
831 *
832 * This operation throws away the current auxiliary data and replaces it
833 * with the magic pass-through value. If an ambiguate operation is
834 * performed when the primary surface does not contain 100% of the data,
835 * data will be lost. This operation is only implemented in hardware for
836 * depth where it is called a HiZ resolve.
837 */
838 ISL_AUX_OP_AMBIGUATE,
839 };
840
841 /* TODO(chadv): Explain */
842 enum isl_array_pitch_span {
843 ISL_ARRAY_PITCH_SPAN_FULL,
844 ISL_ARRAY_PITCH_SPAN_COMPACT,
845 };
846
847 /**
848 * @defgroup Surface Usage
849 * @{
850 */
851 typedef uint64_t isl_surf_usage_flags_t;
852 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
853 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
854 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
855 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
856 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
857 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
858 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
859 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
860 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
861 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
862 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
863 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
864 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
865 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
866 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
867 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
868 /** @} */
869
870 /**
871 * @defgroup Channel Mask
872 *
873 * These #define values are chosen to match the values of
874 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
875 *
876 * @{
877 */
878 typedef uint8_t isl_channel_mask_t;
879 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
880 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
881 #define ISL_CHANNEL_RED_BIT (1 << 2)
882 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
883 /** @} */
884
885 /**
886 * @brief A channel select (also known as texture swizzle) value
887 */
888 enum PACKED isl_channel_select {
889 ISL_CHANNEL_SELECT_ZERO = 0,
890 ISL_CHANNEL_SELECT_ONE = 1,
891 ISL_CHANNEL_SELECT_RED = 4,
892 ISL_CHANNEL_SELECT_GREEN = 5,
893 ISL_CHANNEL_SELECT_BLUE = 6,
894 ISL_CHANNEL_SELECT_ALPHA = 7,
895 };
896
897 /**
898 * Identical to VkSampleCountFlagBits.
899 */
900 enum isl_sample_count {
901 ISL_SAMPLE_COUNT_1_BIT = 1u,
902 ISL_SAMPLE_COUNT_2_BIT = 2u,
903 ISL_SAMPLE_COUNT_4_BIT = 4u,
904 ISL_SAMPLE_COUNT_8_BIT = 8u,
905 ISL_SAMPLE_COUNT_16_BIT = 16u,
906 };
907 typedef uint32_t isl_sample_count_mask_t;
908
909 /**
910 * @brief Multisample Format
911 */
912 enum isl_msaa_layout {
913 /**
914 * @brief Suface is single-sampled.
915 */
916 ISL_MSAA_LAYOUT_NONE,
917
918 /**
919 * @brief [SNB+] Interleaved Multisample Format
920 *
921 * In this format, multiple samples are interleaved into each cacheline.
922 * In other words, the sample index is swizzled into the low 6 bits of the
923 * surface's virtual address space.
924 *
925 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
926 * and its pixel format is 32bpp. Then the first cacheline is arranged
927 * thus:
928 *
929 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
930 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
931 *
932 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
933 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
934 *
935 * The hardware docs refer to this format with multiple terms. In
936 * Sandybridge, this is the only multisample format; so no term is used.
937 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
938 * Multisample Surface). Later hardware docs additionally refer to this
939 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
940 * color surfaces).
941 *
942 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
943 * Surface Behavior".
944 *
945 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
946 * Multisampled Surfaces".
947 */
948 ISL_MSAA_LAYOUT_INTERLEAVED,
949
950 /**
951 * @brief [IVB+] Array Multisample Format
952 *
953 * In this format, the surface's physical layout resembles that of a
954 * 2D array surface.
955 *
956 * Suppose the multisample surface's logical extent is (w, h) and its
957 * sample count is N. Then surface's physical extent is the same as
958 * a singlesample 2D surface whose logical extent is (w, h) and array
959 * length is N. Array slice `i` contains the pixel values for sample
960 * index `i`.
961 *
962 * The Ivybridge docs refer to surfaces in this format as UMS
963 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
964 * Surface). The Broadwell docs additionally refer to this format as
965 * MSFMT_MSS (MSS=Multisample Surface Storage).
966 *
967 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
968 * Multisample Surfaces".
969 *
970 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
971 * Multisample Surfaces".
972 */
973 ISL_MSAA_LAYOUT_ARRAY,
974 };
975
976 typedef enum {
977 ISL_MEMCPY = 0,
978 ISL_MEMCPY_BGRA8,
979 ISL_MEMCPY_STREAMING_LOAD,
980 ISL_MEMCPY_INVALID,
981 } isl_memcpy_type;
982
983 struct isl_device {
984 const struct gen_device_info *info;
985 bool use_separate_stencil;
986 bool has_bit6_swizzling;
987
988 /**
989 * Describes the layout of a RENDER_SURFACE_STATE structure for the
990 * current gen.
991 */
992 struct {
993 uint8_t size;
994 uint8_t align;
995 uint8_t addr_offset;
996 uint8_t aux_addr_offset;
997
998 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
999
1000 /* size of the state buffer used to store the clear color + extra
1001 * additional space used by the hardware */
1002 uint8_t clear_color_state_size;
1003 uint8_t clear_color_state_offset;
1004 /* size of the clear color itself - used to copy it to/from a BO */
1005 uint8_t clear_value_size;
1006 uint8_t clear_value_offset;
1007 } ss;
1008
1009 /**
1010 * Describes the layout of the depth/stencil/hiz commands as emitted by
1011 * isl_emit_depth_stencil_hiz.
1012 */
1013 struct {
1014 uint8_t size;
1015 uint8_t depth_offset;
1016 uint8_t stencil_offset;
1017 uint8_t hiz_offset;
1018 } ds;
1019
1020 struct {
1021 uint32_t internal;
1022 uint32_t external;
1023 } mocs;
1024 };
1025
1026 struct isl_extent2d {
1027 union { uint32_t w, width; };
1028 union { uint32_t h, height; };
1029 };
1030
1031 struct isl_extent3d {
1032 union { uint32_t w, width; };
1033 union { uint32_t h, height; };
1034 union { uint32_t d, depth; };
1035 };
1036
1037 struct isl_extent4d {
1038 union { uint32_t w, width; };
1039 union { uint32_t h, height; };
1040 union { uint32_t d, depth; };
1041 union { uint32_t a, array_len; };
1042 };
1043
1044 struct isl_channel_layout {
1045 enum isl_base_type type;
1046 uint8_t start_bit; /**< Bit at which this channel starts */
1047 uint8_t bits; /**< Size in bits */
1048 };
1049
1050 /**
1051 * Each format has 3D block extent (width, height, depth). The block extent of
1052 * compressed formats is that of the format's compression block. For example,
1053 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1054 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1055 * is (w=1, h=1, d=1).
1056 */
1057 struct isl_format_layout {
1058 enum isl_format format;
1059 const char *name;
1060
1061 uint16_t bpb; /**< Bits per block */
1062 uint8_t bw; /**< Block width, in pixels */
1063 uint8_t bh; /**< Block height, in pixels */
1064 uint8_t bd; /**< Block depth, in pixels */
1065
1066 union {
1067 struct {
1068 struct isl_channel_layout r; /**< Red channel */
1069 struct isl_channel_layout g; /**< Green channel */
1070 struct isl_channel_layout b; /**< Blue channel */
1071 struct isl_channel_layout a; /**< Alpha channel */
1072 struct isl_channel_layout l; /**< Luminance channel */
1073 struct isl_channel_layout i; /**< Intensity channel */
1074 struct isl_channel_layout p; /**< Palette channel */
1075 } channels;
1076 struct isl_channel_layout channels_array[7];
1077 };
1078
1079 enum isl_colorspace colorspace;
1080 enum isl_txc txc;
1081 };
1082
1083 struct isl_tile_info {
1084 enum isl_tiling tiling;
1085
1086 /* The size (in bits per block) of a single surface element
1087 *
1088 * For surfaces with power-of-two formats, this is the same as
1089 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1090 * The logical_extent_el field is in terms of elements of this size.
1091 *
1092 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1093 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1094 * of the tiling formats can actually hold an integer number of 96-bit
1095 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1096 * 32-bit element size. It is the responsibility of the caller to
1097 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1098 * the width of a surface in tiles, you would do:
1099 *
1100 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1101 * tile_info.logical_extent_el.width);
1102 */
1103 uint32_t format_bpb;
1104
1105 /** The logical size of the tile in units of format_bpb size elements
1106 *
1107 * This field determines how a given surface is cut up into tiles. It is
1108 * used to compute the size of a surface in tiles and can be used to
1109 * determine the location of the tile containing any given surface element.
1110 * The exact value of this field depends heavily on the bits-per-block of
1111 * the format being used.
1112 */
1113 struct isl_extent2d logical_extent_el;
1114
1115 /** The physical size of the tile in bytes and rows of bytes
1116 *
1117 * This field determines how the tiles of a surface are physically layed
1118 * out in memory. The logical and physical tile extent are frequently the
1119 * same but this is not always the case. For instance, a W-tile (which is
1120 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1121 * its physical size is 128B x 32rows, the same as a Y-tile.
1122 *
1123 * @see isl_surf::row_pitch_B
1124 */
1125 struct isl_extent2d phys_extent_B;
1126 };
1127
1128 /**
1129 * Metadata about a DRM format modifier.
1130 */
1131 struct isl_drm_modifier_info {
1132 uint64_t modifier;
1133
1134 /** Text name of the modifier */
1135 const char *name;
1136
1137 /** ISL tiling implied by this modifier */
1138 enum isl_tiling tiling;
1139
1140 /** ISL aux usage implied by this modifier */
1141 enum isl_aux_usage aux_usage;
1142
1143 /** Whether or not this modifier supports clear color */
1144 bool supports_clear_color;
1145 };
1146
1147 /**
1148 * @brief Input to surface initialization
1149 *
1150 * @invariant width >= 1
1151 * @invariant height >= 1
1152 * @invariant depth >= 1
1153 * @invariant levels >= 1
1154 * @invariant samples >= 1
1155 * @invariant array_len >= 1
1156 *
1157 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1158 * @invariant if 2D then depth == 1
1159 * @invariant if 3D then array_len == 1 and samples == 1
1160 */
1161 struct isl_surf_init_info {
1162 enum isl_surf_dim dim;
1163 enum isl_format format;
1164
1165 uint32_t width;
1166 uint32_t height;
1167 uint32_t depth;
1168 uint32_t levels;
1169 uint32_t array_len;
1170 uint32_t samples;
1171
1172 /** Lower bound for isl_surf::alignment, in bytes. */
1173 uint32_t min_alignment_B;
1174
1175 /**
1176 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1177 * will fail if this is misaligned or out of bounds.
1178 */
1179 uint32_t row_pitch_B;
1180
1181 isl_surf_usage_flags_t usage;
1182
1183 /** Flags that alter how ISL selects isl_surf::tiling. */
1184 isl_tiling_flags_t tiling_flags;
1185 };
1186
1187 struct isl_surf {
1188 enum isl_surf_dim dim;
1189 enum isl_dim_layout dim_layout;
1190 enum isl_msaa_layout msaa_layout;
1191 enum isl_tiling tiling;
1192 enum isl_format format;
1193
1194 /**
1195 * Alignment of the upper-left sample of each subimage, in units of surface
1196 * elements.
1197 */
1198 struct isl_extent3d image_alignment_el;
1199
1200 /**
1201 * Logical extent of the surface's base level, in units of pixels. This is
1202 * identical to the extent defined in isl_surf_init_info.
1203 */
1204 struct isl_extent4d logical_level0_px;
1205
1206 /**
1207 * Physical extent of the surface's base level, in units of physical
1208 * surface samples.
1209 *
1210 * Consider isl_dim_layout as an operator that transforms a logical surface
1211 * layout to a physical surface layout. Then
1212 *
1213 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1214 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1215 */
1216 struct isl_extent4d phys_level0_sa;
1217
1218 uint32_t levels;
1219 uint32_t samples;
1220
1221 /** Total size of the surface, in bytes. */
1222 uint64_t size_B;
1223
1224 /** Required alignment for the surface's base address. */
1225 uint32_t alignment_B;
1226
1227 /**
1228 * The interpretation of this field depends on the value of
1229 * isl_tile_info::physical_extent_B. In particular, the width of the
1230 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1231 * and the distance in bytes between vertically adjacent tiles in the image
1232 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1233 *
1234 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1235 * this cleanly reduces to being the distance, in bytes, between vertically
1236 * adjacent surface elements.
1237 *
1238 * @see isl_tile_info::phys_extent_B;
1239 */
1240 uint32_t row_pitch_B;
1241
1242 /**
1243 * Pitch between physical array slices, in rows of surface elements.
1244 */
1245 uint32_t array_pitch_el_rows;
1246
1247 enum isl_array_pitch_span array_pitch_span;
1248
1249 /** Copy of isl_surf_init_info::usage. */
1250 isl_surf_usage_flags_t usage;
1251 };
1252
1253 struct isl_swizzle {
1254 enum isl_channel_select r:4;
1255 enum isl_channel_select g:4;
1256 enum isl_channel_select b:4;
1257 enum isl_channel_select a:4;
1258 };
1259
1260 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1261 .r = ISL_CHANNEL_SELECT_##R, \
1262 .g = ISL_CHANNEL_SELECT_##G, \
1263 .b = ISL_CHANNEL_SELECT_##B, \
1264 .a = ISL_CHANNEL_SELECT_##A, \
1265 })
1266
1267 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1268
1269 struct isl_view {
1270 /**
1271 * Indicates the usage of the particular view
1272 *
1273 * Normally, this is one bit. However, for a cube map texture, it
1274 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1275 */
1276 isl_surf_usage_flags_t usage;
1277
1278 /**
1279 * The format to use in the view
1280 *
1281 * This may differ from the format of the actual isl_surf but must have
1282 * the same block size.
1283 */
1284 enum isl_format format;
1285
1286 uint32_t base_level;
1287 uint32_t levels;
1288
1289 /**
1290 * Base array layer
1291 *
1292 * For cube maps, both base_array_layer and array_len should be
1293 * specified in terms of 2-D layers and must be a multiple of 6.
1294 *
1295 * 3-D textures are effectively treated as 2-D arrays when used as a
1296 * storage image or render target. If `usage` contains
1297 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1298 * base_array_layer and array_len are applied. If the surface is only used
1299 * for texturing, they are ignored.
1300 */
1301 uint32_t base_array_layer;
1302
1303 /**
1304 * Array Length
1305 *
1306 * Indicates the number of array elements starting at Base Array Layer.
1307 */
1308 uint32_t array_len;
1309
1310 struct isl_swizzle swizzle;
1311 };
1312
1313 union isl_color_value {
1314 float f32[4];
1315 uint32_t u32[4];
1316 int32_t i32[4];
1317 };
1318
1319 struct isl_surf_fill_state_info {
1320 const struct isl_surf *surf;
1321 const struct isl_view *view;
1322
1323 /**
1324 * The address of the surface in GPU memory.
1325 */
1326 uint64_t address;
1327
1328 /**
1329 * The Memory Object Control state for the filled surface state.
1330 *
1331 * The exact format of this value depends on hardware generation.
1332 */
1333 uint32_t mocs;
1334
1335 /**
1336 * The auxilary surface or NULL if no auxilary surface is to be used.
1337 */
1338 const struct isl_surf *aux_surf;
1339 enum isl_aux_usage aux_usage;
1340 uint64_t aux_address;
1341
1342 /**
1343 * The clear color for this surface
1344 *
1345 * Valid values depend on hardware generation.
1346 */
1347 union isl_color_value clear_color;
1348
1349 /**
1350 * Send only the clear value address
1351 *
1352 * If set, we only pass the clear address to the GPU and it will fetch it
1353 * from wherever it is.
1354 */
1355 bool use_clear_address;
1356 uint64_t clear_address;
1357
1358 /**
1359 * Surface write disables for gen4-5
1360 */
1361 isl_channel_mask_t write_disables;
1362
1363 /* Intra-tile offset */
1364 uint16_t x_offset_sa, y_offset_sa;
1365 };
1366
1367 struct isl_buffer_fill_state_info {
1368 /**
1369 * The address of the surface in GPU memory.
1370 */
1371 uint64_t address;
1372
1373 /**
1374 * The size of the buffer
1375 */
1376 uint64_t size_B;
1377
1378 /**
1379 * The Memory Object Control state for the filled surface state.
1380 *
1381 * The exact format of this value depends on hardware generation.
1382 */
1383 uint32_t mocs;
1384
1385 /**
1386 * The format to use in the surface state
1387 *
1388 * This may differ from the format of the actual isl_surf but have the
1389 * same block size.
1390 */
1391 enum isl_format format;
1392
1393 /**
1394 * The swizzle to use in the surface state
1395 */
1396 struct isl_swizzle swizzle;
1397
1398 uint32_t stride_B;
1399 };
1400
1401 struct isl_depth_stencil_hiz_emit_info {
1402 /**
1403 * The depth surface
1404 */
1405 const struct isl_surf *depth_surf;
1406
1407 /**
1408 * The stencil surface
1409 *
1410 * If separate stencil is not available, this must point to the same
1411 * isl_surf as depth_surf.
1412 */
1413 const struct isl_surf *stencil_surf;
1414
1415 /**
1416 * The view into the depth and stencil surfaces.
1417 *
1418 * This view applies to both surfaces simultaneously.
1419 */
1420 const struct isl_view *view;
1421
1422 /**
1423 * The address of the depth surface in GPU memory
1424 */
1425 uint64_t depth_address;
1426
1427 /**
1428 * The address of the stencil surface in GPU memory
1429 *
1430 * If separate stencil is not available, this must have the same value as
1431 * depth_address.
1432 */
1433 uint64_t stencil_address;
1434
1435 /**
1436 * The Memory Object Control state for depth and stencil buffers
1437 *
1438 * Both depth and stencil will get the same MOCS value. The exact format
1439 * of this value depends on hardware generation.
1440 */
1441 uint32_t mocs;
1442
1443 /**
1444 * The HiZ surface or NULL if HiZ is disabled.
1445 */
1446 const struct isl_surf *hiz_surf;
1447 enum isl_aux_usage hiz_usage;
1448 uint64_t hiz_address;
1449
1450 /**
1451 * The depth clear value
1452 */
1453 float depth_clear_value;
1454
1455 /**
1456 * Track stencil aux usage for Gen >= 12
1457 */
1458 enum isl_aux_usage stencil_aux_usage;
1459 };
1460
1461 extern const struct isl_format_layout isl_format_layouts[];
1462
1463 void
1464 isl_device_init(struct isl_device *dev,
1465 const struct gen_device_info *info,
1466 bool has_bit6_swizzling);
1467
1468 isl_sample_count_mask_t ATTRIBUTE_CONST
1469 isl_device_get_sample_counts(struct isl_device *dev);
1470
1471 static inline const struct isl_format_layout * ATTRIBUTE_CONST
1472 isl_format_get_layout(enum isl_format fmt)
1473 {
1474 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1475 assert(fmt < ISL_NUM_FORMATS);
1476 return &isl_format_layouts[fmt];
1477 }
1478
1479 bool isl_format_is_valid(enum isl_format);
1480
1481 static inline const char * ATTRIBUTE_CONST
1482 isl_format_get_name(enum isl_format fmt)
1483 {
1484 return isl_format_get_layout(fmt)->name;
1485 }
1486
1487 enum isl_format isl_format_for_pipe_format(enum pipe_format pf);
1488
1489 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1490 enum isl_format format);
1491 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1492 enum isl_format format);
1493 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1494 enum isl_format format);
1495 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1496 enum isl_format format);
1497 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1498 enum isl_format format);
1499 bool isl_format_supports_typed_writes(const struct gen_device_info *devinfo,
1500 enum isl_format format);
1501 bool isl_format_supports_typed_reads(const struct gen_device_info *devinfo,
1502 enum isl_format format);
1503 bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
1504 enum isl_format format);
1505 bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
1506 enum isl_format format);
1507 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1508 enum isl_format format);
1509
1510 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
1511 enum isl_format format1,
1512 enum isl_format format2);
1513 uint8_t isl_format_get_aux_map_encoding(enum isl_format format);
1514
1515 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1516 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1517 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1518 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1519 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1520 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1521
1522 static inline bool
1523 isl_format_has_normalized_channel(enum isl_format fmt)
1524 {
1525 return isl_format_has_unorm_channel(fmt) ||
1526 isl_format_has_snorm_channel(fmt);
1527 }
1528
1529 static inline bool
1530 isl_format_has_float_channel(enum isl_format fmt)
1531 {
1532 return isl_format_has_ufloat_channel(fmt) ||
1533 isl_format_has_sfloat_channel(fmt);
1534 }
1535
1536 static inline bool
1537 isl_format_has_int_channel(enum isl_format fmt)
1538 {
1539 return isl_format_has_uint_channel(fmt) ||
1540 isl_format_has_sint_channel(fmt);
1541 }
1542
1543 bool isl_format_has_color_component(enum isl_format fmt,
1544 int component) ATTRIBUTE_CONST;
1545
1546 unsigned isl_format_get_num_channels(enum isl_format fmt);
1547
1548 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1549
1550 static inline bool
1551 isl_format_is_compressed(enum isl_format fmt)
1552 {
1553 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1554
1555 return fmtl->txc != ISL_TXC_NONE;
1556 }
1557
1558 static inline bool
1559 isl_format_has_bc_compression(enum isl_format fmt)
1560 {
1561 switch (isl_format_get_layout(fmt)->txc) {
1562 case ISL_TXC_DXT1:
1563 case ISL_TXC_DXT3:
1564 case ISL_TXC_DXT5:
1565 return true;
1566 case ISL_TXC_NONE:
1567 case ISL_TXC_FXT1:
1568 case ISL_TXC_RGTC1:
1569 case ISL_TXC_RGTC2:
1570 case ISL_TXC_BPTC:
1571 case ISL_TXC_ETC1:
1572 case ISL_TXC_ETC2:
1573 case ISL_TXC_ASTC:
1574 return false;
1575
1576 case ISL_TXC_HIZ:
1577 case ISL_TXC_MCS:
1578 case ISL_TXC_CCS:
1579 unreachable("Should not be called on an aux surface");
1580 }
1581
1582 unreachable("bad texture compression mode");
1583 return false;
1584 }
1585
1586 static inline bool
1587 isl_format_is_yuv(enum isl_format fmt)
1588 {
1589 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1590
1591 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1592 }
1593
1594 static inline bool
1595 isl_format_block_is_1x1x1(enum isl_format fmt)
1596 {
1597 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1598
1599 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1600 }
1601
1602 static inline bool
1603 isl_format_is_srgb(enum isl_format fmt)
1604 {
1605 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
1606 }
1607
1608 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1609
1610 static inline bool
1611 isl_format_is_rgb(enum isl_format fmt)
1612 {
1613 if (isl_format_is_yuv(fmt))
1614 return false;
1615
1616 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1617
1618 return fmtl->channels.r.bits > 0 &&
1619 fmtl->channels.g.bits > 0 &&
1620 fmtl->channels.b.bits > 0 &&
1621 fmtl->channels.a.bits == 0;
1622 }
1623
1624 static inline bool
1625 isl_format_is_rgbx(enum isl_format fmt)
1626 {
1627 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1628
1629 return fmtl->channels.r.bits > 0 &&
1630 fmtl->channels.g.bits > 0 &&
1631 fmtl->channels.b.bits > 0 &&
1632 fmtl->channels.a.bits > 0 &&
1633 fmtl->channels.a.type == ISL_VOID;
1634 }
1635
1636 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1637 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1638 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1639
1640 void isl_color_value_pack(const union isl_color_value *value,
1641 enum isl_format format,
1642 uint32_t *data_out);
1643 void isl_color_value_unpack(union isl_color_value *value,
1644 enum isl_format format,
1645 const uint32_t *data_in);
1646
1647 bool isl_is_storage_image_format(enum isl_format fmt);
1648
1649 enum isl_format
1650 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1651 enum isl_format fmt);
1652
1653 /* Returns true if this hardware supports typed load/store on a format with
1654 * the same size as the given format.
1655 */
1656 bool
1657 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1658 enum isl_format fmt);
1659
1660 static inline enum isl_tiling
1661 isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
1662 {
1663 assert(__builtin_popcount(flag) == 1);
1664 return (enum isl_tiling) (__builtin_ffs(flag) - 1);
1665 }
1666
1667 static inline bool
1668 isl_tiling_is_any_y(enum isl_tiling tiling)
1669 {
1670 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1671 }
1672
1673 static inline bool
1674 isl_tiling_is_std_y(enum isl_tiling tiling)
1675 {
1676 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1677 }
1678
1679 uint32_t
1680 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
1681
1682 enum isl_tiling
1683 isl_tiling_from_i915_tiling(uint32_t tiling);
1684
1685 static inline bool
1686 isl_aux_usage_has_hiz(enum isl_aux_usage usage)
1687 {
1688 return usage == ISL_AUX_USAGE_HIZ ||
1689 usage == ISL_AUX_USAGE_HIZ_CCS;
1690 }
1691
1692 static inline bool
1693 isl_aux_usage_has_mcs(enum isl_aux_usage usage)
1694 {
1695 return usage == ISL_AUX_USAGE_MCS ||
1696 usage == ISL_AUX_USAGE_MCS_CCS;
1697 }
1698
1699 static inline bool
1700 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
1701 {
1702 return usage == ISL_AUX_USAGE_CCS_D ||
1703 usage == ISL_AUX_USAGE_CCS_E ||
1704 usage == ISL_AUX_USAGE_MC ||
1705 usage == ISL_AUX_USAGE_HIZ_CCS ||
1706 usage == ISL_AUX_USAGE_MCS_CCS;
1707 }
1708
1709 static inline bool
1710 isl_aux_state_has_valid_primary(enum isl_aux_state state)
1711 {
1712 return state == ISL_AUX_STATE_RESOLVED ||
1713 state == ISL_AUX_STATE_PASS_THROUGH ||
1714 state == ISL_AUX_STATE_AUX_INVALID;
1715 }
1716
1717 static inline bool
1718 isl_aux_state_has_valid_aux(enum isl_aux_state state)
1719 {
1720 return state != ISL_AUX_STATE_AUX_INVALID;
1721 }
1722
1723 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
1724 isl_drm_modifier_get_info(uint64_t modifier);
1725
1726 static inline bool
1727 isl_drm_modifier_has_aux(uint64_t modifier)
1728 {
1729 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
1730 }
1731
1732 /** Returns the default isl_aux_state for the given modifier.
1733 *
1734 * If we have a modifier which supports compression, then the auxiliary data
1735 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1736 * can be in any of the following:
1737 *
1738 * - ISL_AUX_STATE_CLEAR
1739 * - ISL_AUX_STATE_PARTIAL_CLEAR
1740 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1741 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1742 * - ISL_AUX_STATE_RESOLVED
1743 * - ISL_AUX_STATE_PASS_THROUGH
1744 *
1745 * If the modifier does not support fast-clears, then we are guaranteed
1746 * that the surface is at least partially resolved and the first three not
1747 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1748 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1749 * because they are the least common denominator of the set of possible aux
1750 * states and will yield a valid interpretation of the aux data.
1751 *
1752 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1753 */
1754 static inline enum isl_aux_state
1755 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
1756 {
1757 const struct isl_drm_modifier_info *mod_info =
1758 isl_drm_modifier_get_info(modifier);
1759
1760 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
1761 return ISL_AUX_STATE_AUX_INVALID;
1762
1763 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
1764 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
1765 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1766 }
1767
1768 struct isl_extent2d ATTRIBUTE_CONST
1769 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1770
1771 static inline bool
1772 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1773 {
1774 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1775 }
1776
1777 static inline bool
1778 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1779 {
1780 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1781 }
1782
1783 static inline bool
1784 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1785 {
1786 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1787 }
1788
1789 static inline bool
1790 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1791 {
1792 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1793 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1794 }
1795
1796 static inline bool
1797 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1798 {
1799 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1800 }
1801
1802 static inline bool
1803 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1804 {
1805 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1806 (info->format == ISL_FORMAT_R16_UNORM);
1807 }
1808
1809 static inline bool
1810 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1811 {
1812 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1813 (info->format == ISL_FORMAT_R32_FLOAT);
1814 }
1815
1816 static inline struct isl_extent2d
1817 isl_extent2d(uint32_t width, uint32_t height)
1818 {
1819 struct isl_extent2d e = { { 0 } };
1820
1821 e.width = width;
1822 e.height = height;
1823
1824 return e;
1825 }
1826
1827 static inline struct isl_extent3d
1828 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1829 {
1830 struct isl_extent3d e = { { 0 } };
1831
1832 e.width = width;
1833 e.height = height;
1834 e.depth = depth;
1835
1836 return e;
1837 }
1838
1839 static inline struct isl_extent4d
1840 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1841 uint32_t array_len)
1842 {
1843 struct isl_extent4d e = { { 0 } };
1844
1845 e.width = width;
1846 e.height = height;
1847 e.depth = depth;
1848 e.array_len = array_len;
1849
1850 return e;
1851 }
1852
1853 bool isl_color_value_is_zero(union isl_color_value value,
1854 enum isl_format format);
1855
1856 bool isl_color_value_is_zero_one(union isl_color_value value,
1857 enum isl_format format);
1858
1859 static inline bool
1860 isl_swizzle_is_identity(struct isl_swizzle swizzle)
1861 {
1862 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
1863 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
1864 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
1865 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
1866 }
1867
1868 bool
1869 isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
1870 struct isl_swizzle swizzle);
1871
1872 struct isl_swizzle
1873 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
1874 struct isl_swizzle
1875 isl_swizzle_invert(struct isl_swizzle swizzle);
1876
1877 #define isl_surf_init(dev, surf, ...) \
1878 isl_surf_init_s((dev), (surf), \
1879 &(struct isl_surf_init_info) { __VA_ARGS__ });
1880
1881 bool
1882 isl_surf_init_s(const struct isl_device *dev,
1883 struct isl_surf *surf,
1884 const struct isl_surf_init_info *restrict info);
1885
1886 void
1887 isl_surf_get_tile_info(const struct isl_surf *surf,
1888 struct isl_tile_info *tile_info);
1889
1890 bool
1891 isl_surf_get_hiz_surf(const struct isl_device *dev,
1892 const struct isl_surf *surf,
1893 struct isl_surf *hiz_surf);
1894
1895 bool
1896 isl_surf_get_mcs_surf(const struct isl_device *dev,
1897 const struct isl_surf *surf,
1898 struct isl_surf *mcs_surf);
1899
1900 bool
1901 isl_surf_get_ccs_surf(const struct isl_device *dev,
1902 const struct isl_surf *surf,
1903 struct isl_surf *aux_surf,
1904 struct isl_surf *extra_aux_surf,
1905 uint32_t row_pitch_B /**< Ignored if 0 */);
1906
1907 #define isl_surf_fill_state(dev, state, ...) \
1908 isl_surf_fill_state_s((dev), (state), \
1909 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1910
1911 void
1912 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1913 const struct isl_surf_fill_state_info *restrict info);
1914
1915 #define isl_buffer_fill_state(dev, state, ...) \
1916 isl_buffer_fill_state_s((dev), (state), \
1917 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1918
1919 void
1920 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1921 const struct isl_buffer_fill_state_info *restrict info);
1922
1923 void
1924 isl_null_fill_state(const struct isl_device *dev, void *state,
1925 struct isl_extent3d size);
1926
1927 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1928 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1929 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1930
1931 void
1932 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
1933 const struct isl_depth_stencil_hiz_emit_info *restrict info);
1934
1935 void
1936 isl_surf_fill_image_param(const struct isl_device *dev,
1937 struct brw_image_param *param,
1938 const struct isl_surf *surf,
1939 const struct isl_view *view);
1940
1941 void
1942 isl_buffer_fill_image_param(const struct isl_device *dev,
1943 struct brw_image_param *param,
1944 enum isl_format format,
1945 uint64_t size);
1946
1947 /**
1948 * Alignment of the upper-left sample of each subimage, in units of surface
1949 * elements.
1950 */
1951 static inline struct isl_extent3d
1952 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1953 {
1954 return surf->image_alignment_el;
1955 }
1956
1957 /**
1958 * Alignment of the upper-left sample of each subimage, in units of surface
1959 * samples.
1960 */
1961 static inline struct isl_extent3d
1962 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1963 {
1964 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1965
1966 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1967 fmtl->bh * surf->image_alignment_el.h,
1968 fmtl->bd * surf->image_alignment_el.d);
1969 }
1970
1971 /**
1972 * Logical extent of level 0 in units of surface elements.
1973 */
1974 static inline struct isl_extent4d
1975 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
1976 {
1977 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1978
1979 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
1980 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
1981 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
1982 surf->logical_level0_px.a);
1983 }
1984
1985 /**
1986 * Physical extent of level 0 in units of surface elements.
1987 */
1988 static inline struct isl_extent4d
1989 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
1990 {
1991 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1992
1993 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
1994 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
1995 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
1996 surf->phys_level0_sa.a);
1997 }
1998
1999 /**
2000 * Pitch between vertically adjacent surface elements, in bytes.
2001 */
2002 static inline uint32_t
2003 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
2004 {
2005 return surf->row_pitch_B;
2006 }
2007
2008 /**
2009 * Pitch between vertically adjacent surface elements, in units of surface elements.
2010 */
2011 static inline uint32_t
2012 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
2013 {
2014 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2015
2016 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
2017 return surf->row_pitch_B / (fmtl->bpb / 8);
2018 }
2019
2020 /**
2021 * Pitch between physical array slices, in rows of surface elements.
2022 */
2023 static inline uint32_t
2024 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
2025 {
2026 return surf->array_pitch_el_rows;
2027 }
2028
2029 /**
2030 * Pitch between physical array slices, in units of surface elements.
2031 */
2032 static inline uint32_t
2033 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
2034 {
2035 return isl_surf_get_array_pitch_el_rows(surf) *
2036 isl_surf_get_row_pitch_el(surf);
2037 }
2038
2039 /**
2040 * Pitch between physical array slices, in rows of surface samples.
2041 */
2042 static inline uint32_t
2043 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
2044 {
2045 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2046 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
2047 }
2048
2049 /**
2050 * Pitch between physical array slices, in bytes.
2051 */
2052 static inline uint32_t
2053 isl_surf_get_array_pitch(const struct isl_surf *surf)
2054 {
2055 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
2056 }
2057
2058 /**
2059 * Calculate the offset, in units of surface samples, to a subimage in the
2060 * surface.
2061 *
2062 * @invariant level < surface levels
2063 * @invariant logical_array_layer < logical array length of surface
2064 * @invariant logical_z_offset_px < logical depth of surface at level
2065 */
2066 void
2067 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2068 uint32_t level,
2069 uint32_t logical_array_layer,
2070 uint32_t logical_z_offset_px,
2071 uint32_t *x_offset_sa,
2072 uint32_t *y_offset_sa);
2073
2074 /**
2075 * Calculate the offset, in units of surface elements, to a subimage in the
2076 * surface.
2077 *
2078 * @invariant level < surface levels
2079 * @invariant logical_array_layer < logical array length of surface
2080 * @invariant logical_z_offset_px < logical depth of surface at level
2081 */
2082 void
2083 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2084 uint32_t level,
2085 uint32_t logical_array_layer,
2086 uint32_t logical_z_offset_px,
2087 uint32_t *x_offset_el,
2088 uint32_t *y_offset_el);
2089
2090 /**
2091 * Calculate the offset, in bytes and intratile surface samples, to a
2092 * subimage in the surface.
2093 *
2094 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2095 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2096 * offsets to samples.
2097 *
2098 * @invariant level < surface levels
2099 * @invariant logical_array_layer < logical array length of surface
2100 * @invariant logical_z_offset_px < logical depth of surface at level
2101 */
2102 void
2103 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2104 uint32_t level,
2105 uint32_t logical_array_layer,
2106 uint32_t logical_z_offset_px,
2107 uint32_t *offset_B,
2108 uint32_t *x_offset_sa,
2109 uint32_t *y_offset_sa);
2110
2111 /**
2112 * Calculate the range in bytes occupied by a subimage, to the nearest tile.
2113 *
2114 * The range returned will be the smallest memory range in which the give
2115 * subimage fits, rounded to even tiles. Intel images do not usually have a
2116 * direct subimage -> range mapping so the range returned may contain data
2117 * from other sub-images. The returned range is a half-open interval where
2118 * all of the addresses within the subimage are < end_tile_B.
2119 *
2120 * @invariant level < surface levels
2121 * @invariant logical_array_layer < logical array length of surface
2122 * @invariant logical_z_offset_px < logical depth of surface at level
2123 */
2124 void
2125 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2126 uint32_t level,
2127 uint32_t logical_array_layer,
2128 uint32_t logical_z_offset_px,
2129 uint32_t *start_tile_B,
2130 uint32_t *end_tile_B);
2131
2132 /**
2133 * Create an isl_surf that represents a particular subimage in the surface.
2134 *
2135 * The newly created surface will have a single miplevel and array slice. The
2136 * surface lives at the returned byte and intratile offsets, in samples.
2137 *
2138 * It is safe to call this function with surf == image_surf.
2139 *
2140 * @invariant level < surface levels
2141 * @invariant logical_array_layer < logical array length of surface
2142 * @invariant logical_z_offset_px < logical depth of surface at level
2143 */
2144 void
2145 isl_surf_get_image_surf(const struct isl_device *dev,
2146 const struct isl_surf *surf,
2147 uint32_t level,
2148 uint32_t logical_array_layer,
2149 uint32_t logical_z_offset_px,
2150 struct isl_surf *image_surf,
2151 uint32_t *offset_B,
2152 uint32_t *x_offset_sa,
2153 uint32_t *y_offset_sa);
2154
2155 /**
2156 * @brief Calculate the intratile offsets to a surface.
2157 *
2158 * In @a base_address_offset return the offset from the base of the surface to
2159 * the base address of the first tile of the subimage. In @a x_offset_B and
2160 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2161 * tile's base to the subimage's first surface element. The x and y offsets
2162 * are intratile offsets; that is, they do not exceed the boundary of the
2163 * surface's tiling format.
2164 */
2165 void
2166 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2167 uint32_t bpb,
2168 uint32_t row_pitch_B,
2169 uint32_t total_x_offset_el,
2170 uint32_t total_y_offset_el,
2171 uint32_t *base_address_offset,
2172 uint32_t *x_offset_el,
2173 uint32_t *y_offset_el);
2174
2175 static inline void
2176 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2177 enum isl_format format,
2178 uint32_t row_pitch_B,
2179 uint32_t total_x_offset_sa,
2180 uint32_t total_y_offset_sa,
2181 uint32_t *base_address_offset,
2182 uint32_t *x_offset_sa,
2183 uint32_t *y_offset_sa)
2184 {
2185 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2186
2187 /* For computing the intratile offsets, we actually want a strange unit
2188 * which is samples for multisampled surfaces but elements for compressed
2189 * surfaces.
2190 */
2191 assert(total_x_offset_sa % fmtl->bw == 0);
2192 assert(total_y_offset_sa % fmtl->bh == 0);
2193 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
2194 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
2195
2196 isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
2197 total_x_offset, total_y_offset,
2198 base_address_offset,
2199 x_offset_sa, y_offset_sa);
2200 *x_offset_sa *= fmtl->bw;
2201 *y_offset_sa *= fmtl->bh;
2202 }
2203
2204 /**
2205 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2206 *
2207 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2208 * @pre surf->format must be a valid format for depth surfaces
2209 */
2210 uint32_t
2211 isl_surf_get_depth_format(const struct isl_device *dev,
2212 const struct isl_surf *surf);
2213
2214 /**
2215 * @brief determines if a surface supports writing through HIZ to the CCS.
2216 */
2217 bool
2218 isl_surf_supports_hiz_ccs_wt(const struct gen_device_info *dev,
2219 const struct isl_surf *surf,
2220 enum isl_aux_usage aux_usage);
2221
2222 /**
2223 * @brief performs a copy from linear to tiled surface
2224 *
2225 */
2226 void
2227 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
2228 uint32_t yt1, uint32_t yt2,
2229 char *dst, const char *src,
2230 uint32_t dst_pitch, int32_t src_pitch,
2231 bool has_swizzling,
2232 enum isl_tiling tiling,
2233 isl_memcpy_type copy_type);
2234
2235 /**
2236 * @brief performs a copy from tiled to linear surface
2237 *
2238 */
2239 void
2240 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
2241 uint32_t yt1, uint32_t yt2,
2242 char *dst, const char *src,
2243 int32_t dst_pitch, uint32_t src_pitch,
2244 bool has_swizzling,
2245 enum isl_tiling tiling,
2246 isl_memcpy_type copy_type);
2247
2248 #ifdef __cplusplus
2249 }
2250 #endif
2251
2252 #endif /* ISL_H */