Merge remote-tracking branch 'origin/master' into vulkan
[mesa.git] / src / intel / isl / isl_gen6.c
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "isl_gen6.h"
25 #include "isl_priv.h"
26
27 bool
28 gen6_choose_msaa_layout(const struct isl_device *dev,
29 const struct isl_surf_init_info *info,
30 enum isl_tiling tiling,
31 enum isl_msaa_layout *msaa_layout)
32 {
33 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
34
35 assert(ISL_DEV_GEN(dev) == 6);
36 assert(info->samples >= 1);
37
38 if (info->samples == 1) {
39 *msaa_layout = ISL_MSAA_LAYOUT_NONE;
40 return false;
41 }
42
43 /* From the Sandybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Surface
44 * Format:
45 *
46 * If Number of Multisamples is set to a value other than
47 * MULTISAMPLECOUNT_1, this field cannot be set to the following
48 * formats:
49 *
50 * - any format with greater than 64 bits per element
51 * - any compressed texture format (BC*)
52 * - any YCRCB* format
53 */
54 if (fmtl->bs > 8)
55 return false;
56 if (isl_format_is_compressed(info->format))
57 return false;
58 if (isl_format_is_yuv(info->format))
59 return false;
60
61 /* From the Sandybridge PRM, Volume 4 Part 1 p85, SURFACE_STATE, Number of
62 * Multisamples:
63 *
64 * If this field is any value other than MULTISAMPLECOUNT_1 the
65 * following restrictions apply:
66 *
67 * - the Surface Type must be SURFTYPE_2D
68 * - [...]
69 */
70 if (info->dim != ISL_SURF_DIM_2D)
71 return false;
72
73 /* More obvious restrictions */
74 if (isl_surf_usage_is_display(info->usage))
75 return false;
76 if (tiling == ISL_TILING_LINEAR)
77 return false;
78 if (info->levels > 1)
79 return false;
80
81 *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
82 return true;
83 }
84
85 void
86 gen6_choose_image_alignment_el(const struct isl_device *dev,
87 const struct isl_surf_init_info *restrict info,
88 enum isl_tiling tiling,
89 enum isl_msaa_layout msaa_layout,
90 struct isl_extent3d *image_align_el)
91 {
92 /* Note that the surface's horizontal image alignment is not programmable
93 * on Sandybridge.
94 *
95 * From the Sandybridge PRM (2011-05), Volume 1, Part 1, Section 7.18.3.4
96 * Alignment Unit Size:
97 *
98 * Note that the compressed formats are padded to a full compression cell.
99 *
100 * +------------------------+--------+--------+
101 * | format | halign | valign |
102 * +------------------------+--------+--------+
103 * | YUV 4:2:2 formats | 4 | * |
104 * | uncompressed formats | 4 | * |
105 * +------------------------+--------+--------+
106 *
107 * * For these formats, the vertical alignment factor ā€œjā€ is determined
108 * as follows:
109 * - j = 4 for any depth buffer
110 * - j = 2 for separate stencil buffer
111 * - j = 4 for any render target surface is multisampled (4x)
112 * - j = 2 for all other render target surface
113 *
114 * From the Sandrybridge PRM (2011-05), Volume 4, Part 1, Section 2.11.2
115 * SURFACE_STATE, Surface Vertical Alignment:
116 *
117 * - This field must be set to VALIGN_2 if the Surface Format is 96 bits
118 * per element (BPE).
119 *
120 * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
121 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
122 * (0x190)
123 */
124
125 if (isl_format_is_compressed(info->format)) {
126 *image_align_el = isl_extent3d(1, 1, 1);
127 return;
128 }
129
130 if (isl_format_is_yuv(info->format)) {
131 *image_align_el = isl_extent3d(4, 2, 1);
132 return;
133 }
134
135 if (info->samples > 1) {
136 *image_align_el = isl_extent3d(4, 4, 1);
137 return;
138 }
139
140 if (isl_surf_usage_is_depth_or_stencil(info->usage) &&
141 !ISL_DEV_USE_SEPARATE_STENCIL(dev)) {
142 /* interleaved depthstencil buffer */
143 *image_align_el = isl_extent3d(4, 4, 1);
144 return;
145 }
146
147 if (isl_surf_usage_is_depth(info->usage)) {
148 /* separate depth buffer */
149 *image_align_el = isl_extent3d(4, 4, 1);
150 return;
151 }
152
153 if (isl_surf_usage_is_stencil(info->usage)) {
154 /* separate stencil buffer */
155 *image_align_el = isl_extent3d(4, 2, 1);
156 return;
157 }
158
159 *image_align_el = isl_extent3d(4, 2, 1);
160 }