src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static uint64_t
  30 __gen_combine_address(__attribute__((unused)) void *data,
  31                       __attribute__((unused)) void *loc, uint64_t addr,
  32                       uint32_t delta)
  33 {
  34    return addr + delta;
  35 }
  36
  37 #include "genxml/gen_macros.h"
  38 #include "genxml/genX_pack.h"
  39
  40 #include "isl_priv.h"
  41
  42 #if GEN_GEN >= 8
  43 static const uint8_t isl_to_gen_halign[] = {
  44     [4] = HALIGN4,
  45     [8] = HALIGN8,
  46     [16] = HALIGN16,
  47 };
  48 #elif GEN_GEN >= 7
  49 static const uint8_t isl_to_gen_halign[] = {
  50     [4] = HALIGN_4,
  51     [8] = HALIGN_8,
  52 };
  53 #endif
  54
  55 #if GEN_GEN >= 8
  56 static const uint8_t isl_to_gen_valign[] = {
  57     [4] = VALIGN4,
  58     [8] = VALIGN8,
  59     [16] = VALIGN16,
  60 };
  61 #elif GEN_GEN >= 6
  62 static const uint8_t isl_to_gen_valign[] = {
  63     [2] = VALIGN_2,
  64     [4] = VALIGN_4,
  65 };
  66 #endif
  67
  68 #if GEN_GEN >= 8
  69 static const uint8_t isl_to_gen_tiling[] = {
  70    [ISL_TILING_LINEAR]  = LINEAR,
  71    [ISL_TILING_X]       = XMAJOR,
  72    [ISL_TILING_Y0]      = YMAJOR,
  73    [ISL_TILING_Yf]      = YMAJOR,
  74    [ISL_TILING_Ys]      = YMAJOR,
  75    [ISL_TILING_W]       = WMAJOR,
  76 };
  77 #endif
  78
  79 #if GEN_GEN >= 7
  80 static const uint32_t isl_to_gen_multisample_layout[] = {
  81    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  82    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  83    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  84 };
  85 #endif
  86
  87 #if GEN_GEN >= 9
  88 static const uint32_t isl_to_gen_aux_mode[] = {
  89    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  90    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  91    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
  92    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
  93    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  94 };
  95 #elif GEN_GEN >= 8
  96 static const uint32_t isl_to_gen_aux_mode[] = {
  97    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  98    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  99    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 100    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 101 };
 102 #endif
 103
 104 static uint8_t
 105 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 106 {
 107    switch (dim) {
 108    default:
 109       unreachable("bad isl_surf_dim");
 110    case ISL_SURF_DIM_1D:
 111       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 112       return SURFTYPE_1D;
 113    case ISL_SURF_DIM_2D:
 114       if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
 115           (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
 116          /* We need SURFTYPE_CUBE to make cube sampling work */
 117          return SURFTYPE_CUBE;
 118       } else {
 119          /* Everything else (render and storage) treat cubes as plain
 120           * 2D array textures
 121           */
 122          return SURFTYPE_2D;
 123       }
 124    case ISL_SURF_DIM_3D:
 125       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 126       return SURFTYPE_3D;
 127    }
 128 }
 129
 130 /**
 131  * Get the horizontal and vertical alignment in the units expected by the
 132  * hardware.  Note that this does NOT give you the actual hardware enum values
 133  * but an index into the isl_to_gen_[hv]align arrays above.
 134  */
 135 UNUSED static struct isl_extent3d
 136 get_image_alignment(const struct isl_surf *surf)
 137 {
 138    if (GEN_GEN >= 9) {
 139       if (isl_tiling_is_std_y(surf->tiling) ||
 140           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 141          /* The hardware ignores the alignment values. Anyway, the surface's
 142           * true alignment is likely outside the enum range of HALIGN* and
 143           * VALIGN*.
 144           */
 145          return isl_extent3d(4, 4, 1);
 146       } else {
 147          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 148           * of surface elements (not pixels nor samples). For compressed formats,
 149           * a "surface element" is defined as a compression block.  For example,
 150           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 151           * format (ETC2 has a block height of 4), then the vertical alignment is
 152           * 4 compression blocks or, equivalently, 16 pixels.
 153           */
 154          return isl_surf_get_image_alignment_el(surf);
 155       }
 156    } else {
 157       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 158        * units of surface samples.  For example, if SurfaceVerticalAlignment
 159        * is VALIGN_4 and the surface is singlesampled, then for any surface
 160        * format (compressed or not) the vertical alignment is
 161        * 4 pixels.
 162        */
 163       return isl_surf_get_image_alignment_sa(surf);
 164    }
 165 }
 166
 167 #if GEN_GEN >= 8
 168 static uint32_t
 169 get_qpitch(const struct isl_surf *surf)
 170 {
 171    switch (surf->dim_layout) {
 172    default:
 173       unreachable("Bad isl_surf_dim");
 174    case ISL_DIM_LAYOUT_GEN4_2D:
 175       if (GEN_GEN >= 9) {
 176          if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
 177             /* This is rather annoying and completely undocumented.  It
 178              * appears that the hardware has a bug (or undocumented feature)
 179              * regarding stencil buffers most likely related to the way
 180              * W-tiling is handled as modified Y-tiling.  If you bind a 3-D
 181              * stencil buffer normally, and use texelFetch on it, the z or
 182              * array index will get implicitly multiplied by 2 for no obvious
 183              * reason.  The fix appears to be to divide qpitch by 2 for
 184              * W-tiled surfaces.
 185              */
 186             return isl_surf_get_array_pitch_el_rows(surf) / 2;
 187          } else {
 188             return isl_surf_get_array_pitch_el_rows(surf);
 189          }
 190       } else {
 191          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 192           *
 193           *    "This field must be set to an integer multiple of the Surface
 194           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 195           *    ETC*, and EAC* Surface Formats), this field is in units of
 196           *    rows in the uncompressed surface, and must be set to an
 197           *    integer multiple of the vertical alignment parameter "j"
 198           *    defined in the Common Surface Formats section."
 199           */
 200          return isl_surf_get_array_pitch_sa_rows(surf);
 201       }
 202    case ISL_DIM_LAYOUT_GEN9_1D:
 203       /* QPitch is usually expressed as rows of surface elements (where
 204        * a surface element is an compression block or a single surface
 205        * sample). Skylake 1D is an outlier.
 206        *
 207        * From the Skylake BSpec >> Memory Views >> Common Surface
 208        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 209        *
 210        *    Surface QPitch specifies the distance in pixels between array
 211        *    slices.
 212        */
 213       return isl_surf_get_array_pitch_el(surf);
 214    case ISL_DIM_LAYOUT_GEN4_3D:
 215       /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
 216        * different pitch at each LOD.  Also, the QPitch field is ignored for
 217        * these surfaces.  From the Broadwell PRM documentation for QPitch:
 218        *
 219        *    This field specifies the distance in rows between array slices. It
 220        *    is used only in the following cases:
 221        *     - Surface Array is enabled OR
 222        *     - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
 223        *       Surface Storage Format set to MSFMT_MSS OR
 224        *     - Surface Type is SURFTYPE_CUBE
 225        *
 226        * None of the three conditions above can possibly apply to a 3D surface
 227        * so it is safe to just set QPitch to 0.
 228        */
 229       return 0;
 230    }
 231 }
 232 #endif /* GEN_GEN >= 8 */
 233
 234 void
 235 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 236                             const struct isl_surf_fill_state_info *restrict info)
 237 {
 238    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 239
 240    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 241
 242    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 243       assert(isl_format_supports_rendering(dev->info, info->view->format));
 244    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 245       assert(isl_format_supports_sampling(dev->info, info->view->format));
 246
 247    /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
 248     *
 249     *    This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
 250     *    format if the Surface Type is SURFTYPE_1D
 251     */
 252    if (info->surf->dim == ISL_SURF_DIM_1D)
 253       assert(!isl_format_is_compressed(info->view->format));
 254
 255    if (isl_format_is_compressed(info->surf->format)) {
 256       /* You're not allowed to make a view of a compressed format with any
 257        * format other than the surface format.  None of the userspace APIs
 258        * allow for this directly and doing so would mess up a number of
 259        * surface parameters such as Width, Height, and alignments.  Ideally,
 260        * we'd like to assert that the two formats match.  However, we have an
 261        * S3TC workaround that requires us to do reinterpretation.  So assert
 262        * that they're at least the same bpb and block size.
 263        */
 264       MAYBE_UNUSED const struct isl_format_layout *surf_fmtl =
 265          isl_format_get_layout(info->surf->format);
 266       MAYBE_UNUSED const struct isl_format_layout *view_fmtl =
 267          isl_format_get_layout(info->surf->format);
 268       assert(surf_fmtl->bpb == view_fmtl->bpb);
 269       assert(surf_fmtl->bw == view_fmtl->bw);
 270       assert(surf_fmtl->bh == view_fmtl->bh);
 271    }
 272
 273    s.SurfaceFormat = info->view->format;
 274
 275 #if GEN_GEN <= 5
 276    s.ColorBufferComponentWriteDisables = info->write_disables;
 277 #else
 278    assert(info->write_disables == 0);
 279 #endif
 280
 281 #if GEN_IS_HASWELL
 282    s.IntegerSurfaceFormat =
 283       isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
 284 #endif
 285
 286    assert(info->surf->logical_level0_px.width > 0 &&
 287           info->surf->logical_level0_px.height > 0);
 288
 289    s.Width = info->surf->logical_level0_px.width - 1;
 290    s.Height = info->surf->logical_level0_px.height - 1;
 291
 292    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 293     * (Surface Arrays For all surfaces other than separate stencil buffer):
 294     *
 295     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 296     *  calculated in the equation above , for every other odd Surface Height
 297     *  starting from 1 i.e. 1,5,9,13"
 298     *
 299     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 300     * input for the rendering surface to achieve the same qpitch. For the
 301     * affected heights, we increment the height by 1 for the rendering
 302     * surface.
 303     */
 304    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 305        info->surf->samples > 1 &&
 306        (info->surf->logical_level0_px.height % 4) == 1)
 307       s.Height++;
 308
 309    switch (s.SurfaceType) {
 310    case SURFTYPE_1D:
 311    case SURFTYPE_2D:
 312       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 313        *
 314        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 315        *    must be set to zero if this surface is used with sampling engine
 316        *    messages."
 317        *
 318        * This restriction appears to exist only on Ivy Bridge.
 319        */
 320       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 321           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 322           info->surf->samples > 1)
 323          assert(info->view->base_array_layer == 0);
 324
 325       s.MinimumArrayElement = info->view->base_array_layer;
 326
 327       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 328        *
 329        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 330        *    by one for each increase from zero of Minimum Array Element. For
 331        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 332        *    the range of this field is reduced to [0,1023].
 333        *
 334        * In other words, 'Depth' is the number of array layers.
 335        */
 336       s.Depth = info->view->array_len - 1;
 337
 338       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 339        *
 340        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 341        *    This field must be set to the same value as the Depth field.
 342        */
 343       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 344                                ISL_SURF_USAGE_STORAGE_BIT))
 345          s.RenderTargetViewExtent = s.Depth;
 346       break;
 347    case SURFTYPE_CUBE:
 348       s.MinimumArrayElement = info->view->base_array_layer;
 349       /* Same as SURFTYPE_2D, but divided by 6 */
 350       s.Depth = info->view->array_len / 6 - 1;
 351       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 352                                ISL_SURF_USAGE_STORAGE_BIT))
 353          s.RenderTargetViewExtent = s.Depth;
 354       break;
 355    case SURFTYPE_3D:
 356       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 357        *
 358        *    If the volume texture is MIP-mapped, this field specifies the
 359        *    depth of the base MIP level.
 360        */
 361       s.Depth = info->surf->logical_level0_px.depth - 1;
 362
 363       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 364        *
 365        *    For Render Target and Typed Dataport 3D Surfaces: This field
 366        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 367        *    the LOD currently being rendered to.
 368        *
 369        * The docs specify that this only matters for render targets and
 370        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 371        * Depth field has more bits than RenderTargetViewExtent so we can have
 372        * textures with more levels than we can render to.  In order to prevent
 373        * assert-failures in the packing function below, we only set the field
 374        * when it's actually going to be used by the hardware.
 375        *
 376        * Similaraly, the MinimumArrayElement field is ignored by all hardware
 377        * prior to Sky Lake when texturing and we want it set to 0 anyway.
 378        * Since it's already initialized to 0, we can just leave it alone for
 379        * texture surfaces.
 380        */
 381       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 382                                ISL_SURF_USAGE_STORAGE_BIT)) {
 383          s.MinimumArrayElement = info->view->base_array_layer;
 384          s.RenderTargetViewExtent = info->view->array_len - 1;
 385       }
 386       break;
 387    default:
 388       unreachable("bad SurfaceType");
 389    }
 390
 391 #if GEN_GEN >= 7
 392    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 393 #endif
 394
 395    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 396       /* For render target surfaces, the hardware interprets field
 397        * MIPCount/LOD as LOD. The Broadwell PRM says:
 398        *
 399        *    MIPCountLOD defines the LOD that will be rendered into.
 400        *    SurfaceMinLOD is ignored.
 401        */
 402       s.MIPCountLOD = info->view->base_level;
 403       s.SurfaceMinLOD = 0;
 404    } else {
 405       /* For non render target surfaces, the hardware interprets field
 406        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 407        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 408        */
 409       s.SurfaceMinLOD = info->view->base_level;
 410       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 411    }
 412
 413 #if GEN_GEN >= 9
 414    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 415     * Start LOD" to 15 to prevent the hardware from trying to use them.
 416     */
 417    s.TiledResourceMode = NONE;
 418    s.MipTailStartLOD = 15;
 419 #endif
 420
 421 #if GEN_GEN >= 6
 422    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 423    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 424 #if GEN_GEN >= 7
 425    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 426 #endif
 427 #endif
 428
 429    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 430       /* For gen9 1-D textures, surface pitch is ignored */
 431       s.SurfacePitch = 0;
 432    } else {
 433       s.SurfacePitch = info->surf->row_pitch - 1;
 434    }
 435
 436 #if GEN_GEN >= 8
 437    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 438 #elif GEN_GEN == 7
 439    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 440                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 441 #endif
 442
 443 #if GEN_GEN >= 8
 444    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 445 #else
 446    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 447    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 448                                                       TILEWALK_XMAJOR,
 449 #endif
 450
 451 #if GEN_GEN >= 8
 452    s.RenderCacheReadWriteMode = WriteOnlyCache;
 453 #else
 454    s.RenderCacheReadWriteMode = 0;
 455 #endif
 456
 457    s.CubeFaceEnablePositiveZ = 1;
 458    s.CubeFaceEnableNegativeZ = 1;
 459    s.CubeFaceEnablePositiveY = 1;
 460    s.CubeFaceEnableNegativeY = 1;
 461    s.CubeFaceEnablePositiveX = 1;
 462    s.CubeFaceEnableNegativeX = 1;
 463
 464 #if GEN_GEN >= 6
 465    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 466 #if GEN_GEN >= 7
 467    s.MultisampledSurfaceStorageFormat =
 468       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 469 #endif
 470 #endif
 471
 472 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 473    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 474       assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
 475
 476    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
 477    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
 478    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
 479    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
 480 #else
 481    assert(isl_swizzle_is_identity(info->view->swizzle));
 482 #endif
 483
 484    s.SurfaceBaseAddress = info->address;
 485
 486 #if GEN_GEN >= 6
 487    s.MOCS = info->mocs;
 488 #endif
 489
 490 #if GEN_GEN > 4 || GEN_IS_G4X
 491    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 492       /* There are fairly strict rules about when the offsets can be used.
 493        * These are mostly taken from the Sky Lake PRM documentation for
 494        * RENDER_SURFACE_STATE.
 495        */
 496       assert(info->surf->tiling != ISL_TILING_LINEAR);
 497       assert(info->surf->dim == ISL_SURF_DIM_2D);
 498       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 499       assert(info->surf->levels == 1);
 500       assert(info->surf->logical_level0_px.array_len == 1);
 501       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 502
 503       if (GEN_GEN >= 8) {
 504          /* Broadwell added more rules. */
 505          assert(info->surf->samples == 1);
 506          if (isl_format_get_layout(info->view->format)->bpb == 8)
 507             assert(info->x_offset_sa % 16 == 0);
 508          if (isl_format_get_layout(info->view->format)->bpb == 16)
 509             assert(info->x_offset_sa % 8 == 0);
 510       }
 511
 512 #if GEN_GEN >= 7
 513       s.SurfaceArray = false;
 514 #endif
 515    }
 516
 517    const unsigned x_div = 4;
 518    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 519    assert(info->x_offset_sa % x_div == 0);
 520    assert(info->y_offset_sa % y_div == 0);
 521    s.XOffset = info->x_offset_sa / x_div;
 522    s.YOffset = info->y_offset_sa / y_div;
 523 #else
 524    assert(info->x_offset_sa == 0);
 525    assert(info->y_offset_sa == 0);
 526 #endif
 527
 528 #if GEN_GEN >= 7
 529    if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
 530       /* The docs don't appear to say anything whatsoever about compression
 531        * and the data port.  Testing seems to indicate that the data port
 532        * completely ignores the AuxiliarySurfaceMode field.
 533        */
 534       assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
 535
 536       struct isl_tile_info tile_info;
 537       isl_surf_get_tile_info(info->aux_surf, &tile_info);
 538       uint32_t pitch_in_tiles =
 539          info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
 540
 541       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 542       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 543
 544 #if GEN_GEN >= 8
 545       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
 546       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 547        * doesn't expect our definition of the compression, it expects qpitch
 548        * in units of samples on the main surface.
 549        */
 550       s.AuxiliarySurfaceQPitch =
 551          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 552
 553       if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
 554          /* The number of samples must be 1 */
 555          assert(info->surf->samples == 1);
 556
 557          /* The dimension must not be 3D */
 558          assert(info->surf->dim != ISL_SURF_DIM_3D);
 559
 560          /* The format must be one of the following: */
 561          switch (info->view->format) {
 562          case ISL_FORMAT_R32_FLOAT:
 563          case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
 564          case ISL_FORMAT_R16_UNORM:
 565             break;
 566          default:
 567             assert(!"Incompatible HiZ Sampling format");
 568             break;
 569          }
 570       }
 571
 572       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 573 #else
 574       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 575              info->aux_usage == ISL_AUX_USAGE_CCS_D);
 576       s.MCSEnable = true;
 577 #endif
 578    }
 579 #endif
 580
 581 #if GEN_GEN >= 8
 582    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 583     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 584     *
 585     *    This bit must be set for the following surface types: BC2_UNORM
 586     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 587     */
 588    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 589       switch (info->view->format) {
 590       case ISL_FORMAT_BC2_UNORM:
 591       case ISL_FORMAT_BC3_UNORM:
 592       case ISL_FORMAT_BC5_UNORM:
 593       case ISL_FORMAT_BC5_SNORM:
 594       case ISL_FORMAT_BC7_UNORM:
 595          s.SamplerL2BypassModeDisable = true;
 596          break;
 597       default:
 598          /* From the SKL PRM, Programming Note under Sampler Output Channel
 599           * Mapping:
 600           *
 601           *    If a surface has an associated HiZ Auxilliary surface, the
 602           *    Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
 603           *    must be set.
 604           */
 605          if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
 606             s.SamplerL2BypassModeDisable = true;
 607          break;
 608       }
 609    }
 610 #endif
 611
 612    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 613       if (info->use_clear_address) {
 614 #if GEN_GEN >= 10
 615          s.ClearValueAddressEnable = true;
 616          s.ClearValueAddress = info->clear_address;
 617 #else
 618          unreachable("Gen9 and earlier do not support indirect clear colors");
 619 #endif
 620       }
 621 #if GEN_GEN >= 9
 622       if (!info->use_clear_address) {
 623          s.RedClearColor = info->clear_color.u32[0];
 624          s.GreenClearColor = info->clear_color.u32[1];
 625          s.BlueClearColor = info->clear_color.u32[2];
 626          s.AlphaClearColor = info->clear_color.u32[3];
 627       }
 628 #elif GEN_GEN >= 7
 629       /* Prior to Sky Lake, we only have one bit for the clear color which
 630        * gives us 0 or 1 in whatever the surface's format happens to be.
 631        */
 632       if (isl_format_has_int_channel(info->view->format)) {
 633          for (unsigned i = 0; i < 4; i++) {
 634             assert(info->clear_color.u32[i] == 0 ||
 635                    info->clear_color.u32[i] == 1);
 636          }
 637          s.RedClearColor = info->clear_color.u32[0] != 0;
 638          s.GreenClearColor = info->clear_color.u32[1] != 0;
 639          s.BlueClearColor = info->clear_color.u32[2] != 0;
 640          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 641       } else {
 642          for (unsigned i = 0; i < 4; i++) {
 643             assert(info->clear_color.f32[i] == 0.0f ||
 644                    info->clear_color.f32[i] == 1.0f);
 645          }
 646          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 647          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 648          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 649          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 650       }
 651 #endif
 652    }
 653
 654    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 655 }
 656
 657 void
 658 isl_genX(buffer_fill_state_s)(void *state,
 659                               const struct isl_buffer_fill_state_info *restrict info)
 660 {
 661    uint64_t buffer_size = info->size;
 662
 663    /* Uniform and Storage buffers need to have surface size not less that the
 664     * aligned 32-bit size of the buffer. To calculate the array lenght on
 665     * unsized arrays in StorageBuffer the last 2 bits store the padding size
 666     * added to the surface, so we can calculate latter the original buffer
 667     * size to know the number of elements.
 668     *
 669     *  surface_size = isl_align(buffer_size, 4) +
 670     *                 (isl_align(buffer_size) - buffer_size)
 671     *
 672     *  buffer_size = (surface_size & ~3) - (surface_size & 3)
 673     */
 674    if (info->format == ISL_FORMAT_RAW  ||
 675        info->stride < isl_format_get_layout(info->format)->bpb / 8) {
 676       assert(info->stride == 1);
 677       uint64_t aligned_size = isl_align(buffer_size, 4);
 678       buffer_size = aligned_size + (aligned_size - buffer_size);
 679    }
 680
 681    uint32_t num_elements = buffer_size / info->stride;
 682
 683    if (GEN_GEN >= 7) {
 684       /* From the IVB PRM, SURFACE_STATE::Height,
 685        *
 686        *    For typed buffer and structured buffer surfaces, the number
 687        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 688        *    surfaces, the number of entries in the buffer is the number of bytes
 689        *    which can range from 1 to 2^30.
 690        */
 691       if (info->format == ISL_FORMAT_RAW) {
 692          assert(num_elements <= (1ull << 30));
 693          assert(num_elements > 0);
 694       } else {
 695          assert(num_elements <= (1ull << 27));
 696       }
 697    } else {
 698       assert(num_elements <= (1ull << 27));
 699    }
 700
 701    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 702
 703    s.SurfaceType = SURFTYPE_BUFFER;
 704    s.SurfaceFormat = info->format;
 705
 706 #if GEN_GEN >= 6
 707    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 708 #if GEN_GEN >= 7
 709    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 710    s.SurfaceArray = false;
 711 #endif
 712 #endif
 713
 714 #if GEN_GEN >= 7
 715    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 716    s.Width = (num_elements - 1) & 0x7f;
 717    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 718 #else
 719    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 720    s.Width = (num_elements - 1) & 0x7f;
 721    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 722 #endif
 723
 724    s.SurfacePitch = info->stride - 1;
 725
 726 #if GEN_GEN >= 6
 727    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 728 #endif
 729
 730 #if (GEN_GEN >= 8)
 731    s.TileMode = LINEAR;
 732 #else
 733    s.TiledSurface = false;
 734 #endif
 735
 736 #if (GEN_GEN >= 8)
 737    s.RenderCacheReadWriteMode = WriteOnlyCache;
 738 #else
 739    s.RenderCacheReadWriteMode = 0;
 740 #endif
 741
 742    s.SurfaceBaseAddress = info->address;
 743 #if GEN_GEN >= 6
 744    s.MOCS = info->mocs;
 745 #endif
 746
 747 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 748    s.ShaderChannelSelectRed = SCS_RED;
 749    s.ShaderChannelSelectGreen = SCS_GREEN;
 750    s.ShaderChannelSelectBlue = SCS_BLUE;
 751    s.ShaderChannelSelectAlpha = SCS_ALPHA;
 752 #endif
 753
 754    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 755 }
 756
 757 void
 758 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
 759 {
 760    struct GENX(RENDER_SURFACE_STATE) s = {
 761       .SurfaceType = SURFTYPE_NULL,
 762       .SurfaceFormat = ISL_FORMAT_B8G8R8A8_UNORM,
 763 #if GEN_GEN >= 7
 764       .SurfaceArray = size.depth > 0,
 765 #endif
 766 #if GEN_GEN >= 8
 767       .TileMode = YMAJOR,
 768 #else
 769       .TiledSurface = true,
 770       .TileWalk = TILEWALK_YMAJOR,
 771 #endif
 772       .Width = size.width - 1,
 773       .Height = size.height - 1,
 774       .Depth = size.depth - 1,
 775       .RenderTargetViewExtent = size.depth - 1,
 776 #if GEN_GEN <= 5
 777       .ColorBufferComponentWriteDisables = 0xf,
 778 #endif
 779    };
 780    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 781 }