src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static uint64_t
  30 __gen_combine_address(__attribute__((unused)) void *data,
  31                       __attribute__((unused)) void *loc, uint64_t addr,
  32                       uint32_t delta)
  33 {
  34    return addr + delta;
  35 }
  36
  37 #include "genxml/gen_macros.h"
  38 #include "genxml/genX_pack.h"
  39
  40 #include "isl_priv.h"
  41
  42 #if GEN_GEN >= 8
  43 static const uint8_t isl_to_gen_halign[] = {
  44     [4] = HALIGN4,
  45     [8] = HALIGN8,
  46     [16] = HALIGN16,
  47 };
  48 #elif GEN_GEN >= 7
  49 static const uint8_t isl_to_gen_halign[] = {
  50     [4] = HALIGN_4,
  51     [8] = HALIGN_8,
  52 };
  53 #endif
  54
  55 #if GEN_GEN >= 8
  56 static const uint8_t isl_to_gen_valign[] = {
  57     [4] = VALIGN4,
  58     [8] = VALIGN8,
  59     [16] = VALIGN16,
  60 };
  61 #elif GEN_GEN >= 6
  62 static const uint8_t isl_to_gen_valign[] = {
  63     [2] = VALIGN_2,
  64     [4] = VALIGN_4,
  65 };
  66 #endif
  67
  68 #if GEN_GEN >= 8
  69 static const uint8_t isl_to_gen_tiling[] = {
  70    [ISL_TILING_LINEAR]  = LINEAR,
  71    [ISL_TILING_X]       = XMAJOR,
  72    [ISL_TILING_Y0]      = YMAJOR,
  73    [ISL_TILING_Yf]      = YMAJOR,
  74    [ISL_TILING_Ys]      = YMAJOR,
  75 #if GEN_GEN <= 11
  76    [ISL_TILING_W]       = WMAJOR,
  77 #endif
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 12
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
  93    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  94    [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
  95    [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
  96    [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E,
  97 };
  98 #elif GEN_GEN >= 9
  99 static const uint32_t isl_to_gen_aux_mode[] = {
 100    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 101    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 102    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
 103    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
 104    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
 105 };
 106 #elif GEN_GEN >= 8
 107 static const uint32_t isl_to_gen_aux_mode[] = {
 108    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 109    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 110    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 111    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 112 };
 113 #endif
 114
 115 static uint8_t
 116 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 117 {
 118    switch (dim) {
 119    default:
 120       unreachable("bad isl_surf_dim");
 121    case ISL_SURF_DIM_1D:
 122       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 123       return SURFTYPE_1D;
 124    case ISL_SURF_DIM_2D:
 125       if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
 126           (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
 127          /* We need SURFTYPE_CUBE to make cube sampling work */
 128          return SURFTYPE_CUBE;
 129       } else {
 130          /* Everything else (render and storage) treat cubes as plain
 131           * 2D array textures
 132           */
 133          return SURFTYPE_2D;
 134       }
 135    case ISL_SURF_DIM_3D:
 136       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 137       return SURFTYPE_3D;
 138    }
 139 }
 140
 141 /**
 142  * Get the horizontal and vertical alignment in the units expected by the
 143  * hardware.  Note that this does NOT give you the actual hardware enum values
 144  * but an index into the isl_to_gen_[hv]align arrays above.
 145  */
 146 UNUSED static struct isl_extent3d
 147 get_image_alignment(const struct isl_surf *surf)
 148 {
 149    if (GEN_GEN >= 9) {
 150       if (isl_tiling_is_std_y(surf->tiling) ||
 151           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 152          /* The hardware ignores the alignment values. Anyway, the surface's
 153           * true alignment is likely outside the enum range of HALIGN* and
 154           * VALIGN*.
 155           */
 156          return isl_extent3d(4, 4, 1);
 157       } else {
 158          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 159           * of surface elements (not pixels nor samples). For compressed formats,
 160           * a "surface element" is defined as a compression block.  For example,
 161           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 162           * format (ETC2 has a block height of 4), then the vertical alignment is
 163           * 4 compression blocks or, equivalently, 16 pixels.
 164           */
 165          return isl_surf_get_image_alignment_el(surf);
 166       }
 167    } else {
 168       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 169        * units of surface samples.  For example, if SurfaceVerticalAlignment
 170        * is VALIGN_4 and the surface is singlesampled, then for any surface
 171        * format (compressed or not) the vertical alignment is
 172        * 4 pixels.
 173        */
 174       return isl_surf_get_image_alignment_sa(surf);
 175    }
 176 }
 177
 178 #if GEN_GEN >= 8
 179 static uint32_t
 180 get_qpitch(const struct isl_surf *surf)
 181 {
 182    switch (surf->dim_layout) {
 183    default:
 184       unreachable("Bad isl_surf_dim");
 185    case ISL_DIM_LAYOUT_GEN4_2D:
 186       if (GEN_GEN >= 9) {
 187          if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
 188             /* This is rather annoying and completely undocumented.  It
 189              * appears that the hardware has a bug (or undocumented feature)
 190              * regarding stencil buffers most likely related to the way
 191              * W-tiling is handled as modified Y-tiling.  If you bind a 3-D
 192              * stencil buffer normally, and use texelFetch on it, the z or
 193              * array index will get implicitly multiplied by 2 for no obvious
 194              * reason.  The fix appears to be to divide qpitch by 2 for
 195              * W-tiled surfaces.
 196              */
 197             return isl_surf_get_array_pitch_el_rows(surf) / 2;
 198          } else {
 199             return isl_surf_get_array_pitch_el_rows(surf);
 200          }
 201       } else {
 202          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 203           *
 204           *    "This field must be set to an integer multiple of the Surface
 205           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 206           *    ETC*, and EAC* Surface Formats), this field is in units of
 207           *    rows in the uncompressed surface, and must be set to an
 208           *    integer multiple of the vertical alignment parameter "j"
 209           *    defined in the Common Surface Formats section."
 210           */
 211          return isl_surf_get_array_pitch_sa_rows(surf);
 212       }
 213    case ISL_DIM_LAYOUT_GEN9_1D:
 214       /* QPitch is usually expressed as rows of surface elements (where
 215        * a surface element is an compression block or a single surface
 216        * sample). Skylake 1D is an outlier.
 217        *
 218        * From the Skylake BSpec >> Memory Views >> Common Surface
 219        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 220        *
 221        *    Surface QPitch specifies the distance in pixels between array
 222        *    slices.
 223        */
 224       return isl_surf_get_array_pitch_el(surf);
 225    case ISL_DIM_LAYOUT_GEN4_3D:
 226       /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
 227        * different pitch at each LOD.  Also, the QPitch field is ignored for
 228        * these surfaces.  From the Broadwell PRM documentation for QPitch:
 229        *
 230        *    This field specifies the distance in rows between array slices. It
 231        *    is used only in the following cases:
 232        *     - Surface Array is enabled OR
 233        *     - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
 234        *       Surface Storage Format set to MSFMT_MSS OR
 235        *     - Surface Type is SURFTYPE_CUBE
 236        *
 237        * None of the three conditions above can possibly apply to a 3D surface
 238        * so it is safe to just set QPitch to 0.
 239        */
 240       return 0;
 241    }
 242 }
 243 #endif /* GEN_GEN >= 8 */
 244
 245 void
 246 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 247                             const struct isl_surf_fill_state_info *restrict info)
 248 {
 249    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 250
 251    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 252
 253    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 254       assert(isl_format_supports_rendering(dev->info, info->view->format));
 255    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 256       assert(isl_format_supports_sampling(dev->info, info->view->format));
 257
 258    /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
 259     *
 260     *    This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
 261     *    format if the Surface Type is SURFTYPE_1D
 262     */
 263    if (info->surf->dim == ISL_SURF_DIM_1D)
 264       assert(!isl_format_is_compressed(info->view->format));
 265
 266    if (isl_format_is_compressed(info->surf->format)) {
 267       /* You're not allowed to make a view of a compressed format with any
 268        * format other than the surface format.  None of the userspace APIs
 269        * allow for this directly and doing so would mess up a number of
 270        * surface parameters such as Width, Height, and alignments.  Ideally,
 271        * we'd like to assert that the two formats match.  However, we have an
 272        * S3TC workaround that requires us to do reinterpretation.  So assert
 273        * that they're at least the same bpb and block size.
 274        */
 275       ASSERTED const struct isl_format_layout *surf_fmtl =
 276          isl_format_get_layout(info->surf->format);
 277       ASSERTED const struct isl_format_layout *view_fmtl =
 278          isl_format_get_layout(info->surf->format);
 279       assert(surf_fmtl->bpb == view_fmtl->bpb);
 280       assert(surf_fmtl->bw == view_fmtl->bw);
 281       assert(surf_fmtl->bh == view_fmtl->bh);
 282    }
 283
 284    s.SurfaceFormat = info->view->format;
 285
 286 #if GEN_GEN >= 12
 287    /* The BSpec description of this field says:
 288     *
 289     *    "This bit field, when set, indicates if the resource is created as
 290     *    Depth/Stencil resource."
 291     *
 292     *    "SW must set this bit for any resource that was created with
 293     *    Depth/Stencil resource flag. Setting this bit allows HW to properly
 294     *    interpret the data-layout for various cases. For any resource that's
 295     *    created without Depth/Stencil resource flag, it must be reset."
 296     *
 297     * Even though the docs for this bit seem to imply that it's required for
 298     * anything which might have been used for depth/stencil, empirical
 299     * evidence suggests that it only affects CCS compression usage.  There are
 300     * a few things which back this up:
 301     *
 302     *  1. The docs are also pretty clear that this bit was added as part
 303     *     of enabling Gen12 depth/stencil lossless compression.
 304     *
 305     *  2. The only new difference between depth/stencil and color images on
 306     *     Gen12 (where the bit was added) is how they treat CCS compression.
 307     *     All other differences such as alignment requirements and MSAA layout
 308     *     are already covered by other bits.
 309     *
 310     * Under these assumptions, it makes sense for ISL to model this bit as
 311     * being an extension of AuxiliarySurfaceMode where STC_CCS and HIZ_CCS_WT
 312     * are indicated by AuxiliarySurfaceMode == CCS_E and DepthStencilResource
 313     * == true.
 314     */
 315    s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
 316                             info->aux_usage == ISL_AUX_USAGE_STC_CCS;
 317 #endif
 318
 319 #if GEN_GEN <= 5
 320    s.ColorBufferComponentWriteDisables = info->write_disables;
 321 #else
 322    assert(info->write_disables == 0);
 323 #endif
 324
 325 #if GEN_IS_HASWELL
 326    s.IntegerSurfaceFormat =
 327       isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
 328 #endif
 329
 330    assert(info->surf->logical_level0_px.width > 0 &&
 331           info->surf->logical_level0_px.height > 0);
 332
 333    s.Width = info->surf->logical_level0_px.width - 1;
 334    s.Height = info->surf->logical_level0_px.height - 1;
 335
 336    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 337     * (Surface Arrays For all surfaces other than separate stencil buffer):
 338     *
 339     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 340     *  calculated in the equation above , for every other odd Surface Height
 341     *  starting from 1 i.e. 1,5,9,13"
 342     *
 343     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 344     * input for the rendering surface to achieve the same qpitch. For the
 345     * affected heights, we increment the height by 1 for the rendering
 346     * surface.
 347     */
 348    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 349        info->surf->samples > 1 &&
 350        (info->surf->logical_level0_px.height % 4) == 1)
 351       s.Height++;
 352
 353    switch (s.SurfaceType) {
 354    case SURFTYPE_1D:
 355    case SURFTYPE_2D:
 356       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 357        *
 358        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 359        *    must be set to zero if this surface is used with sampling engine
 360        *    messages."
 361        *
 362        * This restriction appears to exist only on Ivy Bridge.
 363        */
 364       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 365           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 366           info->surf->samples > 1)
 367          assert(info->view->base_array_layer == 0);
 368
 369       s.MinimumArrayElement = info->view->base_array_layer;
 370
 371       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 372        *
 373        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 374        *    by one for each increase from zero of Minimum Array Element. For
 375        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 376        *    the range of this field is reduced to [0,1023].
 377        *
 378        * In other words, 'Depth' is the number of array layers.
 379        */
 380       s.Depth = info->view->array_len - 1;
 381
 382       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 383        *
 384        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 385        *    This field must be set to the same value as the Depth field.
 386        */
 387       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 388                                ISL_SURF_USAGE_STORAGE_BIT))
 389          s.RenderTargetViewExtent = s.Depth;
 390       break;
 391    case SURFTYPE_CUBE:
 392       s.MinimumArrayElement = info->view->base_array_layer;
 393       /* Same as SURFTYPE_2D, but divided by 6 */
 394       s.Depth = info->view->array_len / 6 - 1;
 395       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 396                                ISL_SURF_USAGE_STORAGE_BIT))
 397          s.RenderTargetViewExtent = s.Depth;
 398       break;
 399    case SURFTYPE_3D:
 400       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 401        *
 402        *    If the volume texture is MIP-mapped, this field specifies the
 403        *    depth of the base MIP level.
 404        */
 405       s.Depth = info->surf->logical_level0_px.depth - 1;
 406
 407       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 408        *
 409        *    For Render Target and Typed Dataport 3D Surfaces: This field
 410        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 411        *    the LOD currently being rendered to.
 412        *
 413        * The docs specify that this only matters for render targets and
 414        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 415        * Depth field has more bits than RenderTargetViewExtent so we can have
 416        * textures with more levels than we can render to.  In order to prevent
 417        * assert-failures in the packing function below, we only set the field
 418        * when it's actually going to be used by the hardware.
 419        *
 420        * Similaraly, the MinimumArrayElement field is ignored by all hardware
 421        * prior to Sky Lake when texturing and we want it set to 0 anyway.
 422        * Since it's already initialized to 0, we can just leave it alone for
 423        * texture surfaces.
 424        */
 425       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 426                                ISL_SURF_USAGE_STORAGE_BIT)) {
 427          s.MinimumArrayElement = info->view->base_array_layer;
 428          s.RenderTargetViewExtent = info->view->array_len - 1;
 429       }
 430       break;
 431    default:
 432       unreachable("bad SurfaceType");
 433    }
 434
 435 #if GEN_GEN >= 12
 436    /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
 437    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
 438       info->view->array_len > 1;
 439 #elif GEN_GEN >= 7
 440    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 441 #endif
 442
 443    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 444       /* For render target surfaces, the hardware interprets field
 445        * MIPCount/LOD as LOD. The Broadwell PRM says:
 446        *
 447        *    MIPCountLOD defines the LOD that will be rendered into.
 448        *    SurfaceMinLOD is ignored.
 449        */
 450       s.MIPCountLOD = info->view->base_level;
 451       s.SurfaceMinLOD = 0;
 452    } else {
 453       /* For non render target surfaces, the hardware interprets field
 454        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 455        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 456        */
 457       s.SurfaceMinLOD = info->view->base_level;
 458       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 459    }
 460
 461 #if GEN_GEN >= 9
 462    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 463     * Start LOD" to 15 to prevent the hardware from trying to use them.
 464     */
 465    s.TiledResourceMode = NONE;
 466    s.MipTailStartLOD = 15;
 467 #endif
 468
 469 #if GEN_GEN >= 6
 470    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 471    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 472 #if GEN_GEN >= 7
 473    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 474 #endif
 475 #endif
 476
 477    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 478       /* For gen9 1-D textures, surface pitch is ignored */
 479       s.SurfacePitch = 0;
 480    } else {
 481       s.SurfacePitch = info->surf->row_pitch_B - 1;
 482    }
 483
 484 #if GEN_GEN >= 8
 485    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 486 #elif GEN_GEN == 7
 487    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 488                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 489 #endif
 490
 491 #if GEN_GEN >= 8
 492    assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W);
 493    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 494 #else
 495    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 496    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 497                                                       TILEWALK_XMAJOR,
 498 #endif
 499
 500 #if GEN_GEN >= 8
 501    s.RenderCacheReadWriteMode = WriteOnlyCache;
 502 #else
 503    s.RenderCacheReadWriteMode = 0;
 504 #endif
 505
 506 #if GEN_GEN >= 11
 507    /* We've seen dEQP failures when enabling this bit with UINT formats,
 508     * which particularly affects blorp_copy() operations.  It shouldn't
 509     * have any effect on UINT textures anyway, so disable it for them.
 510     */
 511    s.EnableUnormPathInColorPipe =
 512       !isl_format_has_int_channel(info->view->format);
 513 #endif
 514
 515    s.CubeFaceEnablePositiveZ = 1;
 516    s.CubeFaceEnableNegativeZ = 1;
 517    s.CubeFaceEnablePositiveY = 1;
 518    s.CubeFaceEnableNegativeY = 1;
 519    s.CubeFaceEnablePositiveX = 1;
 520    s.CubeFaceEnableNegativeX = 1;
 521
 522 #if GEN_GEN >= 6
 523    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 524 #if GEN_GEN >= 7
 525    s.MultisampledSurfaceStorageFormat =
 526       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 527 #endif
 528 #endif
 529
 530 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 531    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 532       assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
 533
 534    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
 535    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
 536    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
 537    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
 538 #else
 539    assert(isl_swizzle_is_identity(info->view->swizzle));
 540 #endif
 541
 542    s.SurfaceBaseAddress = info->address;
 543
 544 #if GEN_GEN >= 6
 545    s.MOCS = info->mocs;
 546 #endif
 547
 548 #if GEN_GEN > 4 || GEN_IS_G4X
 549    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 550       /* There are fairly strict rules about when the offsets can be used.
 551        * These are mostly taken from the Sky Lake PRM documentation for
 552        * RENDER_SURFACE_STATE.
 553        */
 554       assert(info->surf->tiling != ISL_TILING_LINEAR);
 555       assert(info->surf->dim == ISL_SURF_DIM_2D);
 556       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 557       assert(info->surf->levels == 1);
 558       assert(info->surf->logical_level0_px.array_len == 1);
 559       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 560
 561       if (GEN_GEN >= 8) {
 562          /* Broadwell added more rules. */
 563          assert(info->surf->samples == 1);
 564          if (isl_format_get_layout(info->view->format)->bpb == 8)
 565             assert(info->x_offset_sa % 16 == 0);
 566          if (isl_format_get_layout(info->view->format)->bpb == 16)
 567             assert(info->x_offset_sa % 8 == 0);
 568       }
 569
 570 #if GEN_GEN >= 7
 571       s.SurfaceArray = false;
 572 #endif
 573    }
 574
 575    const unsigned x_div = 4;
 576    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 577    assert(info->x_offset_sa % x_div == 0);
 578    assert(info->y_offset_sa % y_div == 0);
 579    s.XOffset = info->x_offset_sa / x_div;
 580    s.YOffset = info->y_offset_sa / y_div;
 581 #else
 582    assert(info->x_offset_sa == 0);
 583    assert(info->y_offset_sa == 0);
 584 #endif
 585
 586 #if GEN_GEN >= 7
 587    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 588       /* Check valid aux usages per-gen */
 589       if (GEN_GEN >= 12) {
 590          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 591                 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
 592                 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
 593                 info->aux_usage == ISL_AUX_USAGE_MCS_CCS ||
 594                 info->aux_usage == ISL_AUX_USAGE_STC_CCS);
 595       } else if (GEN_GEN >= 9) {
 596          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
 597                 info->aux_usage == ISL_AUX_USAGE_MCS ||
 598                 info->aux_usage == ISL_AUX_USAGE_CCS_D ||
 599                 info->aux_usage == ISL_AUX_USAGE_CCS_E);
 600       } else if (GEN_GEN >= 8) {
 601          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
 602                 info->aux_usage == ISL_AUX_USAGE_MCS ||
 603                 info->aux_usage == ISL_AUX_USAGE_CCS_D);
 604       } else if (GEN_GEN >= 7) {
 605          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 606                 info->aux_usage == ISL_AUX_USAGE_CCS_D);
 607       }
 608
 609       /* The docs don't appear to say anything whatsoever about compression
 610        * and the data port.  Testing seems to indicate that the data port
 611        * completely ignores the AuxiliarySurfaceMode field.
 612        */
 613       assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
 614
 615       if (isl_surf_usage_is_depth(info->surf->usage))
 616          assert(isl_aux_usage_has_hiz(info->aux_usage));
 617
 618       if (isl_surf_usage_is_stencil(info->surf->usage))
 619          assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS);
 620
 621       if (isl_aux_usage_has_hiz(info->aux_usage)) {
 622          /* For Gen8-10, there are some restrictions around sampling from HiZ.
 623           * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
 624           * say:
 625           *
 626           *    "If this field is set to AUX_HIZ, Number of Multisamples must
 627           *    be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
 628           *
 629           * On Gen12, the docs are a bit less obvious but the restriction is
 630           * the same.  The limitation isn't called out explicitly but the docs
 631           * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode
 632           * say:
 633           *
 634           *    "If Number of multisamples > 1, programming this value means
 635           *    MSAA compression is enabled for that surface. Auxillary surface
 636           *    is MSC with tile y."
 637           *
 638           * Since this interpretation ignores whether the surface is
 639           * depth/stencil or not and since multisampled depth buffers use
 640           * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
 641           * compression, this means that we can't even specify MSAA depth CCS
 642           * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
 643           */
 644          assert(info->surf->samples == 1);
 645
 646          /* The dimension must not be 3D */
 647          assert(info->surf->dim != ISL_SURF_DIM_3D);
 648
 649          /* The format must be one of the following: */
 650          switch (info->view->format) {
 651          case ISL_FORMAT_R32_FLOAT:
 652          case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
 653          case ISL_FORMAT_R16_UNORM:
 654             break;
 655          default:
 656             assert(!"Incompatible HiZ Sampling format");
 657             break;
 658          }
 659       }
 660
 661 #if GEN_GEN >= 8
 662       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 663 #else
 664       s.MCSEnable = true;
 665 #endif
 666    }
 667
 668    /* The auxiliary buffer info is filled when it's useable by the HW.
 669     *
 670     * Starting with Gen12, the only form of compression that can be used
 671     * with RENDER_SURFACE_STATE which requires an aux surface is MCS.
 672     * HiZ still requires a surface but the HiZ surface can only be
 673     * accessed through 3DSTATE_HIER_DEPTH_BUFFER.
 674     *
 675     * On all earlier hardware, an aux surface is required for all forms
 676     * of compression.
 677     */
 678    if ((GEN_GEN < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) ||
 679        (GEN_GEN >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) {
 680
 681       assert(info->aux_surf != NULL);
 682
 683       struct isl_tile_info tile_info;
 684       isl_surf_get_tile_info(info->aux_surf, &tile_info);
 685       uint32_t pitch_in_tiles =
 686          info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
 687
 688       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 689       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 690
 691 #if GEN_GEN >= 8
 692       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 693        * doesn't expect our definition of the compression, it expects qpitch
 694        * in units of samples on the main surface.
 695        */
 696       s.AuxiliarySurfaceQPitch =
 697          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 698 #endif
 699    }
 700 #endif
 701
 702 #if GEN_GEN >= 8 && GEN_GEN < 11
 703    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 704     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 705     *
 706     *    This bit must be set for the following surface types: BC2_UNORM
 707     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 708     */
 709    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 710       switch (info->view->format) {
 711       case ISL_FORMAT_BC2_UNORM:
 712       case ISL_FORMAT_BC3_UNORM:
 713       case ISL_FORMAT_BC5_UNORM:
 714       case ISL_FORMAT_BC5_SNORM:
 715       case ISL_FORMAT_BC7_UNORM:
 716          s.SamplerL2BypassModeDisable = true;
 717          break;
 718       default:
 719          /* From the SKL PRM, Programming Note under Sampler Output Channel
 720           * Mapping:
 721           *
 722           *    If a surface has an associated HiZ Auxilliary surface, the
 723           *    Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
 724           *    must be set.
 725           */
 726          if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
 727             s.SamplerL2BypassModeDisable = true;
 728          break;
 729       }
 730    }
 731 #endif
 732
 733    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 734       if (info->use_clear_address) {
 735 #if GEN_GEN >= 10
 736          s.ClearValueAddressEnable = true;
 737          s.ClearValueAddress = info->clear_address;
 738 #else
 739          unreachable("Gen9 and earlier do not support indirect clear colors");
 740 #endif
 741       }
 742
 743 #if GEN_GEN == 11
 744       /*
 745        * From BXML > GT > Shared Functions > vol5c Shared Functions >
 746        * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
 747        *
 748        *   Project: Gen11
 749        *
 750        *   "Enables Pixel backend hw to convert clear values into native format
 751        *    and write back to clear address, so that display and sampler can use
 752        *    the converted value for resolving fast cleared RTs."
 753        *
 754        * Summary:
 755        *   Clear color conversion must be enabled if the clear color is stored
 756        *   indirectly and fast color clears are enabled.
 757        */
 758       if (info->use_clear_address) {
 759          s.ClearColorConversionEnable = true;
 760       }
 761 #endif
 762
 763 #if GEN_GEN >= 12
 764       assert(info->use_clear_address);
 765 #elif GEN_GEN >= 9
 766       if (!info->use_clear_address) {
 767          s.RedClearColor = info->clear_color.u32[0];
 768          s.GreenClearColor = info->clear_color.u32[1];
 769          s.BlueClearColor = info->clear_color.u32[2];
 770          s.AlphaClearColor = info->clear_color.u32[3];
 771       }
 772 #elif GEN_GEN >= 7
 773       /* Prior to Sky Lake, we only have one bit for the clear color which
 774        * gives us 0 or 1 in whatever the surface's format happens to be.
 775        */
 776       if (isl_format_has_int_channel(info->view->format)) {
 777          for (unsigned i = 0; i < 4; i++) {
 778             assert(info->clear_color.u32[i] == 0 ||
 779                    info->clear_color.u32[i] == 1);
 780          }
 781          s.RedClearColor = info->clear_color.u32[0] != 0;
 782          s.GreenClearColor = info->clear_color.u32[1] != 0;
 783          s.BlueClearColor = info->clear_color.u32[2] != 0;
 784          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 785       } else {
 786          for (unsigned i = 0; i < 4; i++) {
 787             assert(info->clear_color.f32[i] == 0.0f ||
 788                    info->clear_color.f32[i] == 1.0f);
 789          }
 790          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 791          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 792          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 793          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 794       }
 795 #endif
 796    }
 797
 798    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 799 }
 800
 801 void
 802 isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
 803                               const struct isl_buffer_fill_state_info *restrict info)
 804 {
 805    uint64_t buffer_size = info->size_B;
 806
 807    /* Uniform and Storage buffers need to have surface size not less that the
 808     * aligned 32-bit size of the buffer. To calculate the array lenght on
 809     * unsized arrays in StorageBuffer the last 2 bits store the padding size
 810     * added to the surface, so we can calculate latter the original buffer
 811     * size to know the number of elements.
 812     *
 813     *  surface_size = isl_align(buffer_size, 4) +
 814     *                 (isl_align(buffer_size) - buffer_size)
 815     *
 816     *  buffer_size = (surface_size & ~3) - (surface_size & 3)
 817     */
 818    if (info->format == ISL_FORMAT_RAW  ||
 819        info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
 820       assert(info->stride_B == 1);
 821       uint64_t aligned_size = isl_align(buffer_size, 4);
 822       buffer_size = aligned_size + (aligned_size - buffer_size);
 823    }
 824
 825    uint32_t num_elements = buffer_size / info->stride_B;
 826
 827    if (GEN_GEN >= 7) {
 828       /* From the IVB PRM, SURFACE_STATE::Height,
 829        *
 830        *    For typed buffer and structured buffer surfaces, the number
 831        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 832        *    surfaces, the number of entries in the buffer is the number of bytes
 833        *    which can range from 1 to 2^30.
 834        */
 835       if (info->format == ISL_FORMAT_RAW) {
 836          assert(num_elements <= (1ull << 30));
 837          assert(num_elements > 0);
 838       } else {
 839          assert(num_elements <= (1ull << 27));
 840       }
 841    } else {
 842       assert(num_elements <= (1ull << 27));
 843    }
 844
 845    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 846
 847    s.SurfaceType = SURFTYPE_BUFFER;
 848    s.SurfaceFormat = info->format;
 849
 850 #if GEN_GEN >= 6
 851    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 852 #if GEN_GEN >= 7
 853    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 854    s.SurfaceArray = false;
 855 #endif
 856 #endif
 857
 858 #if GEN_GEN >= 7
 859    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 860    s.Width = (num_elements - 1) & 0x7f;
 861    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 862 #else
 863    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 864    s.Width = (num_elements - 1) & 0x7f;
 865    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 866 #endif
 867
 868    if (GEN_GEN == 12 && dev->info->revision == 0) {
 869       /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer
 870        * textures with very close base addresses (delta < 64B) to corrupt each
 871        * other.  We can sort-of work around this by making small buffer
 872        * textures 1D textures instead.  This doesn't fix the problem for large
 873        * buffer textures but the liklihood of large, overlapping, and very
 874        * close buffer textures is fairly low and the point is to hack around
 875        * the bug so we can run apps and tests.
 876        */
 877        if (info->format != ISL_FORMAT_RAW &&
 878            info->stride_B == isl_format_get_layout(info->format)->bpb / 8 &&
 879            num_elements <= (1 << 14)) {
 880          s.SurfaceType = SURFTYPE_1D;
 881          s.Width = num_elements - 1;
 882          s.Height = 0;
 883          s.Depth = 0;
 884       }
 885    }
 886
 887    s.SurfacePitch = info->stride_B - 1;
 888
 889 #if GEN_GEN >= 6
 890    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 891 #endif
 892
 893 #if (GEN_GEN >= 8)
 894    s.TileMode = LINEAR;
 895 #else
 896    s.TiledSurface = false;
 897 #endif
 898
 899 #if (GEN_GEN >= 8)
 900    s.RenderCacheReadWriteMode = WriteOnlyCache;
 901 #else
 902    s.RenderCacheReadWriteMode = 0;
 903 #endif
 904
 905    s.SurfaceBaseAddress = info->address;
 906 #if GEN_GEN >= 6
 907    s.MOCS = info->mocs;
 908 #endif
 909
 910 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 911    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
 912    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
 913    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
 914    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
 915 #endif
 916
 917    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 918 }
 919
 920 void
 921 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
 922 {
 923    struct GENX(RENDER_SURFACE_STATE) s = {
 924       .SurfaceType = SURFTYPE_NULL,
 925       /* We previously had this format set to B8G8R8A8_UNORM but ran into
 926        * hangs on IVB. R32_UINT seems to work for everybody.
 927        *
 928        * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
 929        */
 930       .SurfaceFormat = ISL_FORMAT_R32_UINT,
 931 #if GEN_GEN >= 7
 932       .SurfaceArray = size.depth > 1,
 933 #endif
 934 #if GEN_GEN >= 8
 935       .TileMode = YMAJOR,
 936 #else
 937       .TiledSurface = true,
 938       .TileWalk = TILEWALK_YMAJOR,
 939 #endif
 940 #if GEN_GEN == 7
 941       /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
 942        * Functions"
 943        *
 944        * RENDER_SURFACE_STATE::Surface Vertical Alignment
 945        *
 946        *    "This field must be set to VALIGN_4 for all tiled Y Render Target
 947        *     surfaces."
 948        *
 949        * Affect IVB, HSW.
 950        */
 951       .SurfaceVerticalAlignment = VALIGN_4,
 952 #endif
 953       .Width = size.width - 1,
 954       .Height = size.height - 1,
 955       .Depth = size.depth - 1,
 956       .RenderTargetViewExtent = size.depth - 1,
 957 #if GEN_GEN <= 5
 958       .ColorBufferComponentWriteDisables = 0xf,
 959 #endif
 960    };
 961    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 962 }