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1224e8f6b7f15a36b394c2f4cb7d327e5e8c1060
[mesa.git] / src / intel / tools / aub_write.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "aub_write.h"
25
26 #include <inttypes.h>
27 #include <signal.h>
28 #include <stdarg.h>
29 #include <stdlib.h>
30 #include <string.h>
31
32 #include "i915_drm.h"
33 #include "intel_aub.h"
34
35 #ifndef ALIGN
36 #define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
37 #endif
38
39 #define MI_LOAD_REGISTER_IMM_n(n) ((0x22 << 23) | (2 * (n) - 1))
40 #define MI_LRI_FORCE_POSTED (1<<12)
41
42 #define MI_BATCH_NON_SECURE_I965 (1 << 8)
43
44 #define MI_BATCH_BUFFER_END (0xA << 23)
45
46 #define min(a, b) ({ \
47 __typeof(a) _a = (a); \
48 __typeof(b) _b = (b); \
49 _a < _b ? _a : _b; \
50 })
51
52 #define max(a, b) ({ \
53 __typeof(a) _a = (a); \
54 __typeof(b) _b = (b); \
55 _a > _b ? _a : _b; \
56 })
57
58 #define HWS_PGA_RCSUNIT 0x02080
59 #define HWS_PGA_VCSUNIT0 0x12080
60 #define HWS_PGA_BCSUNIT 0x22080
61
62 #define GFX_MODE_RCSUNIT 0x0229c
63 #define GFX_MODE_VCSUNIT0 0x1229c
64 #define GFX_MODE_BCSUNIT 0x2229c
65
66 #define EXECLIST_SUBMITPORT_RCSUNIT 0x02230
67 #define EXECLIST_SUBMITPORT_VCSUNIT0 0x12230
68 #define EXECLIST_SUBMITPORT_BCSUNIT 0x22230
69
70 #define EXECLIST_STATUS_RCSUNIT 0x02234
71 #define EXECLIST_STATUS_VCSUNIT0 0x12234
72 #define EXECLIST_STATUS_BCSUNIT 0x22234
73
74 #define EXECLIST_SQ_CONTENTS0_RCSUNIT 0x02510
75 #define EXECLIST_SQ_CONTENTS0_VCSUNIT0 0x12510
76 #define EXECLIST_SQ_CONTENTS0_BCSUNIT 0x22510
77
78 #define EXECLIST_CONTROL_RCSUNIT 0x02550
79 #define EXECLIST_CONTROL_VCSUNIT0 0x12550
80 #define EXECLIST_CONTROL_BCSUNIT 0x22550
81
82 #define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024)
83
84 #define PTE_SIZE 4
85 #define GEN8_PTE_SIZE 8
86
87 #define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)
88 #define PT_SIZE ALIGN(NUM_PT_ENTRIES * GEN8_PTE_SIZE, 4096)
89
90 #define RING_SIZE (1 * 4096)
91 #define PPHWSP_SIZE (1 * 4096)
92 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * 4096)
93 #define GEN10_LR_CONTEXT_RENDER_SIZE (19 * 4096)
94 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * 4096)
95 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * 4096)
96 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * 4096)
97
98
99 #define STATIC_GGTT_MAP_START 0
100
101 #define RENDER_RING_ADDR STATIC_GGTT_MAP_START
102 #define RENDER_CONTEXT_ADDR (RENDER_RING_ADDR + RING_SIZE)
103
104 #define BLITTER_RING_ADDR (RENDER_CONTEXT_ADDR + PPHWSP_SIZE + GEN10_LR_CONTEXT_RENDER_SIZE)
105 #define BLITTER_CONTEXT_ADDR (BLITTER_RING_ADDR + RING_SIZE)
106
107 #define VIDEO_RING_ADDR (BLITTER_CONTEXT_ADDR + PPHWSP_SIZE + GEN8_LR_CONTEXT_OTHER_SIZE)
108 #define VIDEO_CONTEXT_ADDR (VIDEO_RING_ADDR + RING_SIZE)
109
110 #define STATIC_GGTT_MAP_END (VIDEO_CONTEXT_ADDR + PPHWSP_SIZE + GEN8_LR_CONTEXT_OTHER_SIZE)
111 #define STATIC_GGTT_MAP_SIZE (STATIC_GGTT_MAP_END - STATIC_GGTT_MAP_START)
112
113 #define PML4_PHYS_ADDR ((uint64_t)(STATIC_GGTT_MAP_END))
114
115 #define CONTEXT_FLAGS (0x339) /* Normal Priority | L3-LLC Coherency |
116 * PPGTT Enabled |
117 * Legacy Context with 64 bit VA support |
118 * Valid
119 */
120
121 #define RENDER_CONTEXT_DESCRIPTOR ((uint64_t)1 << 62 | RENDER_CONTEXT_ADDR | CONTEXT_FLAGS)
122 #define BLITTER_CONTEXT_DESCRIPTOR ((uint64_t)2 << 62 | BLITTER_CONTEXT_ADDR | CONTEXT_FLAGS)
123 #define VIDEO_CONTEXT_DESCRIPTOR ((uint64_t)3 << 62 | VIDEO_CONTEXT_ADDR | CONTEXT_FLAGS)
124
125 static const uint32_t render_context_init[GEN9_LR_CONTEXT_RENDER_SIZE / /* Choose the largest */
126 sizeof(uint32_t)] = {
127 0 /* MI_NOOP */,
128 MI_LOAD_REGISTER_IMM_n(14) | MI_LRI_FORCE_POSTED,
129 0x2244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
130 0x2034 /* RING_HEAD */, 0,
131 0x2030 /* RING_TAIL */, 0,
132 0x2038 /* RING_BUFFER_START */, RENDER_RING_ADDR,
133 0x203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
134 0x2168 /* BB_HEAD_U */, 0,
135 0x2140 /* BB_HEAD_L */, 0,
136 0x2110 /* BB_STATE */, 0,
137 0x211C /* SECOND_BB_HEAD_U */, 0,
138 0x2114 /* SECOND_BB_HEAD_L */, 0,
139 0x2118 /* SECOND_BB_STATE */, 0,
140 0x21C0 /* BB_PER_CTX_PTR */, 0,
141 0x21C4 /* RCS_INDIRECT_CTX */, 0,
142 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0,
143 /* MI_NOOP */
144 0, 0,
145
146 0 /* MI_NOOP */,
147 MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
148 0x23A8 /* CTX_TIMESTAMP */, 0,
149 0x228C /* PDP3_UDW */, 0,
150 0x2288 /* PDP3_LDW */, 0,
151 0x2284 /* PDP2_UDW */, 0,
152 0x2280 /* PDP2_LDW */, 0,
153 0x227C /* PDP1_UDW */, 0,
154 0x2278 /* PDP1_LDW */, 0,
155 0x2274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
156 0x2270 /* PDP0_LDW */, PML4_PHYS_ADDR,
157 /* MI_NOOP */
158 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
159
160 0 /* MI_NOOP */,
161 MI_LOAD_REGISTER_IMM_n(1),
162 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF,
163 MI_BATCH_BUFFER_END
164 };
165
166 static const uint32_t blitter_context_init[GEN8_LR_CONTEXT_OTHER_SIZE /
167 sizeof(uint32_t)] = {
168 0 /* MI_NOOP */,
169 MI_LOAD_REGISTER_IMM_n(11) | MI_LRI_FORCE_POSTED,
170 0x22244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
171 0x22034 /* RING_HEAD */, 0,
172 0x22030 /* RING_TAIL */, 0,
173 0x22038 /* RING_BUFFER_START */, BLITTER_RING_ADDR,
174 0x2203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
175 0x22168 /* BB_HEAD_U */, 0,
176 0x22140 /* BB_HEAD_L */, 0,
177 0x22110 /* BB_STATE */, 0,
178 0x2211C /* SECOND_BB_HEAD_U */, 0,
179 0x22114 /* SECOND_BB_HEAD_L */, 0,
180 0x22118 /* SECOND_BB_STATE */, 0,
181 /* MI_NOOP */
182 0, 0, 0, 0, 0, 0, 0, 0,
183
184 0 /* MI_NOOP */,
185 MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
186 0x223A8 /* CTX_TIMESTAMP */, 0,
187 0x2228C /* PDP3_UDW */, 0,
188 0x22288 /* PDP3_LDW */, 0,
189 0x22284 /* PDP2_UDW */, 0,
190 0x22280 /* PDP2_LDW */, 0,
191 0x2227C /* PDP1_UDW */, 0,
192 0x22278 /* PDP1_LDW */, 0,
193 0x22274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
194 0x22270 /* PDP0_LDW */, PML4_PHYS_ADDR,
195 /* MI_NOOP */
196 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
197
198 MI_BATCH_BUFFER_END
199 };
200
201 static const uint32_t video_context_init[GEN8_LR_CONTEXT_OTHER_SIZE /
202 sizeof(uint32_t)] = {
203 0 /* MI_NOOP */,
204 MI_LOAD_REGISTER_IMM_n(11) | MI_LRI_FORCE_POSTED,
205 0x1C244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
206 0x1C034 /* RING_HEAD */, 0,
207 0x1C030 /* RING_TAIL */, 0,
208 0x1C038 /* RING_BUFFER_START */, VIDEO_RING_ADDR,
209 0x1C03C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
210 0x1C168 /* BB_HEAD_U */, 0,
211 0x1C140 /* BB_HEAD_L */, 0,
212 0x1C110 /* BB_STATE */, 0,
213 0x1C11C /* SECOND_BB_HEAD_U */, 0,
214 0x1C114 /* SECOND_BB_HEAD_L */, 0,
215 0x1C118 /* SECOND_BB_STATE */, 0,
216 /* MI_NOOP */
217 0, 0, 0, 0, 0, 0, 0, 0,
218
219 0 /* MI_NOOP */,
220 MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
221 0x1C3A8 /* CTX_TIMESTAMP */, 0,
222 0x1C28C /* PDP3_UDW */, 0,
223 0x1C288 /* PDP3_LDW */, 0,
224 0x1C284 /* PDP2_UDW */, 0,
225 0x1C280 /* PDP2_LDW */, 0,
226 0x1C27C /* PDP1_UDW */, 0,
227 0x1C278 /* PDP1_LDW */, 0,
228 0x1C274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
229 0x1C270 /* PDP0_LDW */, PML4_PHYS_ADDR,
230 /* MI_NOOP */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232
233 MI_BATCH_BUFFER_END
234 };
235
236 static void __attribute__ ((format(__printf__, 2, 3)))
237 fail_if(int cond, const char *format, ...)
238 {
239 va_list args;
240
241 if (!cond)
242 return;
243
244 va_start(args, format);
245 vfprintf(stderr, format, args);
246 va_end(args);
247
248 raise(SIGTRAP);
249 }
250
251 static inline uint32_t
252 align_u32(uint32_t v, uint32_t a)
253 {
254 return (v + a - 1) & ~(a - 1);
255 }
256
257 static void
258 aub_ppgtt_table_finish(struct aub_ppgtt_table *table)
259 {
260 for (unsigned i = 0; i < ARRAY_SIZE(table->subtables); i++) {
261 aub_ppgtt_table_finish(table->subtables[i]);
262 free(table->subtables[i]);
263 }
264 }
265
266 void
267 aub_file_init(struct aub_file *aub, FILE *file, uint16_t pci_id)
268 {
269 memset(aub, 0, sizeof(*aub));
270
271 aub->file = file;
272 aub->pci_id = pci_id;
273 fail_if(!gen_get_device_info(pci_id, &aub->devinfo),
274 "failed to identify chipset=0x%x\n", pci_id);
275 aub->addr_bits = aub->devinfo.gen >= 8 ? 48 : 32;
276
277 aub->pml4.phys_addr = PML4_PHYS_ADDR;
278 }
279
280 void
281 aub_file_finish(struct aub_file *aub)
282 {
283 aub_ppgtt_table_finish(&aub->pml4);
284 fclose(aub->file);
285 }
286
287 uint32_t
288 aub_gtt_size(struct aub_file *aub)
289 {
290 return NUM_PT_ENTRIES * (aub->addr_bits > 32 ? GEN8_PTE_SIZE : PTE_SIZE);
291 }
292
293 static void
294 data_out(struct aub_file *aub, const void *data, size_t size)
295 {
296 if (size == 0)
297 return;
298
299 fail_if(fwrite(data, 1, size, aub->file) == 0,
300 "Writing to output failed\n");
301 }
302
303 static void
304 dword_out(struct aub_file *aub, uint32_t data)
305 {
306 data_out(aub, &data, sizeof(data));
307 }
308
309 static void
310 mem_trace_memory_write_header_out(struct aub_file *aub, uint64_t addr,
311 uint32_t len, uint32_t addr_space)
312 {
313 uint32_t dwords = ALIGN(len, sizeof(uint32_t)) / sizeof(uint32_t);
314
315 dword_out(aub, CMD_MEM_TRACE_MEMORY_WRITE | (5 + dwords - 1));
316 dword_out(aub, addr & 0xFFFFFFFF); /* addr lo */
317 dword_out(aub, addr >> 32); /* addr hi */
318 dword_out(aub, addr_space); /* gtt */
319 dword_out(aub, len);
320 }
321
322 static void
323 register_write_out(struct aub_file *aub, uint32_t addr, uint32_t value)
324 {
325 uint32_t dwords = 1;
326
327 dword_out(aub, CMD_MEM_TRACE_REGISTER_WRITE | (5 + dwords - 1));
328 dword_out(aub, addr);
329 dword_out(aub, AUB_MEM_TRACE_REGISTER_SIZE_DWORD |
330 AUB_MEM_TRACE_REGISTER_SPACE_MMIO);
331 dword_out(aub, 0xFFFFFFFF); /* mask lo */
332 dword_out(aub, 0x00000000); /* mask hi */
333 dword_out(aub, value);
334 }
335
336 static void
337 populate_ppgtt_table(struct aub_file *aub, struct aub_ppgtt_table *table,
338 int start, int end, int level)
339 {
340 static uint64_t phys_addrs_allocator = (PML4_PHYS_ADDR >> 12) + 1;
341 uint64_t entries[512] = {0};
342 int dirty_start = 512, dirty_end = 0;
343
344 if (aub->verbose_log_file) {
345 fprintf(aub->verbose_log_file,
346 " PPGTT (0x%016" PRIx64 "), lvl %d, start: %x, end: %x\n",
347 table->phys_addr, level, start, end);
348 }
349
350 for (int i = start; i <= end; i++) {
351 if (!table->subtables[i]) {
352 dirty_start = min(dirty_start, i);
353 dirty_end = max(dirty_end, i);
354 if (level == 1) {
355 table->subtables[i] =
356 (void *)(phys_addrs_allocator++ << 12);
357 if (aub->verbose_log_file) {
358 fprintf(aub->verbose_log_file,
359 " Adding entry: %x, phys_addr: 0x%016" PRIx64 "\n",
360 i, (uint64_t)table->subtables[i]);
361 }
362 } else {
363 table->subtables[i] =
364 calloc(1, sizeof(struct aub_ppgtt_table));
365 table->subtables[i]->phys_addr =
366 phys_addrs_allocator++ << 12;
367 if (aub->verbose_log_file) {
368 fprintf(aub->verbose_log_file,
369 " Adding entry: %x, phys_addr: 0x%016" PRIx64 "\n",
370 i, table->subtables[i]->phys_addr);
371 }
372 }
373 }
374 entries[i] = 3 /* read/write | present */ |
375 (level == 1 ? (uint64_t)table->subtables[i] :
376 table->subtables[i]->phys_addr);
377 }
378
379 if (dirty_start <= dirty_end) {
380 uint64_t write_addr = table->phys_addr + dirty_start *
381 sizeof(uint64_t);
382 uint64_t write_size = (dirty_end - dirty_start + 1) *
383 sizeof(uint64_t);
384 mem_trace_memory_write_header_out(aub, write_addr, write_size,
385 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_PHYSICAL);
386 data_out(aub, entries + dirty_start, write_size);
387 }
388 }
389
390 void
391 aub_map_ppgtt(struct aub_file *aub, uint64_t start, uint64_t size)
392 {
393 uint64_t l4_start = start & 0xff8000000000;
394 uint64_t l4_end = ((start + size - 1) | 0x007fffffffff) & 0xffffffffffff;
395
396 #define L4_index(addr) (((addr) >> 39) & 0x1ff)
397 #define L3_index(addr) (((addr) >> 30) & 0x1ff)
398 #define L2_index(addr) (((addr) >> 21) & 0x1ff)
399 #define L1_index(addr) (((addr) >> 12) & 0x1ff)
400
401 #define L3_table(addr) (aub->pml4.subtables[L4_index(addr)])
402 #define L2_table(addr) (L3_table(addr)->subtables[L3_index(addr)])
403 #define L1_table(addr) (L2_table(addr)->subtables[L2_index(addr)])
404
405 if (aub->verbose_log_file) {
406 fprintf(aub->verbose_log_file,
407 " Mapping PPGTT address: 0x%" PRIx64 ", size: %" PRIu64"\n",
408 start, size);
409 }
410
411 populate_ppgtt_table(aub, &aub->pml4, L4_index(l4_start), L4_index(l4_end), 4);
412
413 for (uint64_t l4 = l4_start; l4 < l4_end; l4 += (1ULL << 39)) {
414 uint64_t l3_start = max(l4, start & 0xffffc0000000);
415 uint64_t l3_end = min(l4 + (1ULL << 39) - 1,
416 ((start + size - 1) | 0x00003fffffff) & 0xffffffffffff);
417 uint64_t l3_start_idx = L3_index(l3_start);
418 uint64_t l3_end_idx = L3_index(l3_end);
419
420 populate_ppgtt_table(aub, L3_table(l4), l3_start_idx, l3_end_idx, 3);
421
422 for (uint64_t l3 = l3_start; l3 < l3_end; l3 += (1ULL << 30)) {
423 uint64_t l2_start = max(l3, start & 0xffffffe00000);
424 uint64_t l2_end = min(l3 + (1ULL << 30) - 1,
425 ((start + size - 1) | 0x0000001fffff) & 0xffffffffffff);
426 uint64_t l2_start_idx = L2_index(l2_start);
427 uint64_t l2_end_idx = L2_index(l2_end);
428
429 populate_ppgtt_table(aub, L2_table(l3), l2_start_idx, l2_end_idx, 2);
430
431 for (uint64_t l2 = l2_start; l2 < l2_end; l2 += (1ULL << 21)) {
432 uint64_t l1_start = max(l2, start & 0xfffffffff000);
433 uint64_t l1_end = min(l2 + (1ULL << 21) - 1,
434 ((start + size - 1) | 0x000000000fff) & 0xffffffffffff);
435 uint64_t l1_start_idx = L1_index(l1_start);
436 uint64_t l1_end_idx = L1_index(l1_end);
437
438 populate_ppgtt_table(aub, L1_table(l2), l1_start_idx, l1_end_idx, 1);
439 }
440 }
441 }
442 }
443
444 static uint64_t
445 ppgtt_lookup(struct aub_file *aub, uint64_t ppgtt_addr)
446 {
447 return (uint64_t)L1_table(ppgtt_addr)->subtables[L1_index(ppgtt_addr)];
448 }
449
450 static void
451 write_execlists_header(struct aub_file *aub, const char *name)
452 {
453 char app_name[8 * 4];
454 int app_name_len, dwords;
455
456 app_name_len =
457 snprintf(app_name, sizeof(app_name), "PCI-ID=0x%X %s",
458 aub->pci_id, name);
459 app_name_len = ALIGN(app_name_len, sizeof(uint32_t));
460
461 dwords = 5 + app_name_len / sizeof(uint32_t);
462 dword_out(aub, CMD_MEM_TRACE_VERSION | (dwords - 1));
463 dword_out(aub, AUB_MEM_TRACE_VERSION_FILE_VERSION);
464 dword_out(aub, aub->devinfo.simulator_id << AUB_MEM_TRACE_VERSION_DEVICE_SHIFT);
465 dword_out(aub, 0); /* version */
466 dword_out(aub, 0); /* version */
467 data_out(aub, app_name, app_name_len);
468
469 /* GGTT PT */
470 uint32_t ggtt_ptes = STATIC_GGTT_MAP_SIZE >> 12;
471
472 mem_trace_memory_write_header_out(aub, STATIC_GGTT_MAP_START >> 12,
473 ggtt_ptes * GEN8_PTE_SIZE,
474 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY);
475 for (uint32_t i = 0; i < ggtt_ptes; i++) {
476 dword_out(aub, 1 + 0x1000 * i + STATIC_GGTT_MAP_START);
477 dword_out(aub, 0);
478 }
479
480 /* RENDER_RING */
481 mem_trace_memory_write_header_out(aub, RENDER_RING_ADDR, RING_SIZE,
482 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
483 for (uint32_t i = 0; i < RING_SIZE; i += sizeof(uint32_t))
484 dword_out(aub, 0);
485
486 /* RENDER_PPHWSP */
487 mem_trace_memory_write_header_out(aub, RENDER_CONTEXT_ADDR,
488 PPHWSP_SIZE +
489 sizeof(render_context_init),
490 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
491 for (uint32_t i = 0; i < PPHWSP_SIZE; i += sizeof(uint32_t))
492 dword_out(aub, 0);
493
494 /* RENDER_CONTEXT */
495 data_out(aub, render_context_init, sizeof(render_context_init));
496
497 /* BLITTER_RING */
498 mem_trace_memory_write_header_out(aub, BLITTER_RING_ADDR, RING_SIZE,
499 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
500 for (uint32_t i = 0; i < RING_SIZE; i += sizeof(uint32_t))
501 dword_out(aub, 0);
502
503 /* BLITTER_PPHWSP */
504 mem_trace_memory_write_header_out(aub, BLITTER_CONTEXT_ADDR,
505 PPHWSP_SIZE +
506 sizeof(blitter_context_init),
507 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
508 for (uint32_t i = 0; i < PPHWSP_SIZE; i += sizeof(uint32_t))
509 dword_out(aub, 0);
510
511 /* BLITTER_CONTEXT */
512 data_out(aub, blitter_context_init, sizeof(blitter_context_init));
513
514 /* VIDEO_RING */
515 mem_trace_memory_write_header_out(aub, VIDEO_RING_ADDR, RING_SIZE,
516 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
517 for (uint32_t i = 0; i < RING_SIZE; i += sizeof(uint32_t))
518 dword_out(aub, 0);
519
520 /* VIDEO_PPHWSP */
521 mem_trace_memory_write_header_out(aub, VIDEO_CONTEXT_ADDR,
522 PPHWSP_SIZE +
523 sizeof(video_context_init),
524 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
525 for (uint32_t i = 0; i < PPHWSP_SIZE; i += sizeof(uint32_t))
526 dword_out(aub, 0);
527
528 /* VIDEO_CONTEXT */
529 data_out(aub, video_context_init, sizeof(video_context_init));
530
531 register_write_out(aub, HWS_PGA_RCSUNIT, RENDER_CONTEXT_ADDR);
532 register_write_out(aub, HWS_PGA_VCSUNIT0, VIDEO_CONTEXT_ADDR);
533 register_write_out(aub, HWS_PGA_BCSUNIT, BLITTER_CONTEXT_ADDR);
534
535 register_write_out(aub, GFX_MODE_RCSUNIT, 0x80008000 /* execlist enable */);
536 register_write_out(aub, GFX_MODE_VCSUNIT0, 0x80008000 /* execlist enable */);
537 register_write_out(aub, GFX_MODE_BCSUNIT, 0x80008000 /* execlist enable */);
538 }
539
540 static void write_legacy_header(struct aub_file *aub, const char *name)
541 {
542 char app_name[8 * 4];
543 char comment[16];
544 int comment_len, comment_dwords, dwords;
545 uint32_t entry = 0x200003;
546
547 comment_len = snprintf(comment, sizeof(comment), "PCI-ID=0x%x", aub->pci_id);
548 comment_dwords = ((comment_len + 3) / 4);
549
550 /* Start with a (required) version packet. */
551 dwords = 13 + comment_dwords;
552 dword_out(aub, CMD_AUB_HEADER | (dwords - 2));
553 dword_out(aub, (4 << AUB_HEADER_MAJOR_SHIFT) |
554 (0 << AUB_HEADER_MINOR_SHIFT));
555
556 /* Next comes a 32-byte application name. */
557 strncpy(app_name, name, sizeof(app_name));
558 app_name[sizeof(app_name) - 1] = 0;
559 data_out(aub, app_name, sizeof(app_name));
560
561 dword_out(aub, 0); /* timestamp */
562 dword_out(aub, 0); /* timestamp */
563 dword_out(aub, comment_len);
564 data_out(aub, comment, comment_dwords * 4);
565
566 /* Set up the GTT. The max we can handle is 64M */
567 dword_out(aub, CMD_AUB_TRACE_HEADER_BLOCK |
568 ((aub->addr_bits > 32 ? 6 : 5) - 2));
569 dword_out(aub, AUB_TRACE_MEMTYPE_GTT_ENTRY |
570 AUB_TRACE_TYPE_NOTYPE | AUB_TRACE_OP_DATA_WRITE);
571 dword_out(aub, 0); /* subtype */
572 dword_out(aub, 0); /* offset */
573 dword_out(aub, aub_gtt_size(aub)); /* size */
574 if (aub->addr_bits > 32)
575 dword_out(aub, 0);
576 for (uint32_t i = 0; i < NUM_PT_ENTRIES; i++) {
577 dword_out(aub, entry + 0x1000 * i);
578 if (aub->addr_bits > 32)
579 dword_out(aub, 0);
580 }
581 }
582
583 void
584 aub_write_header(struct aub_file *aub, const char *app_name)
585 {
586 if (aub_use_execlists(aub))
587 write_execlists_header(aub, app_name);
588 else
589 write_legacy_header(aub, app_name);
590 }
591
592 /**
593 * Break up large objects into multiple writes. Otherwise a 128kb VBO
594 * would overflow the 16 bits of size field in the packet header and
595 * everything goes badly after that.
596 */
597 void
598 aub_write_trace_block(struct aub_file *aub,
599 uint32_t type, void *virtual,
600 uint32_t size, uint64_t gtt_offset)
601 {
602 uint32_t block_size;
603 uint32_t subtype = 0;
604 static const char null_block[8 * 4096];
605
606 for (uint32_t offset = 0; offset < size; offset += block_size) {
607 block_size = min(8 * 4096, size - offset);
608
609 if (aub_use_execlists(aub)) {
610 block_size = min(4096, block_size);
611 mem_trace_memory_write_header_out(aub,
612 ppgtt_lookup(aub, gtt_offset + offset),
613 block_size,
614 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_PHYSICAL);
615 } else {
616 dword_out(aub, CMD_AUB_TRACE_HEADER_BLOCK |
617 ((aub->addr_bits > 32 ? 6 : 5) - 2));
618 dword_out(aub, AUB_TRACE_MEMTYPE_GTT |
619 type | AUB_TRACE_OP_DATA_WRITE);
620 dword_out(aub, subtype);
621 dword_out(aub, gtt_offset + offset);
622 dword_out(aub, align_u32(block_size, 4));
623 if (aub->addr_bits > 32)
624 dword_out(aub, (gtt_offset + offset) >> 32);
625 }
626
627 if (virtual)
628 data_out(aub, ((char *) virtual) + offset, block_size);
629 else
630 data_out(aub, null_block, block_size);
631
632 /* Pad to a multiple of 4 bytes. */
633 data_out(aub, null_block, -block_size & 3);
634 }
635 }
636
637 static void
638 aub_dump_execlist(struct aub_file *aub, uint64_t batch_offset, int ring_flag)
639 {
640 uint32_t ring_addr;
641 uint64_t descriptor;
642 uint32_t elsp_reg;
643 uint32_t elsq_reg;
644 uint32_t status_reg;
645 uint32_t control_reg;
646
647 switch (ring_flag) {
648 case I915_EXEC_DEFAULT:
649 case I915_EXEC_RENDER:
650 ring_addr = RENDER_RING_ADDR;
651 descriptor = RENDER_CONTEXT_DESCRIPTOR;
652 elsp_reg = EXECLIST_SUBMITPORT_RCSUNIT;
653 elsq_reg = EXECLIST_SQ_CONTENTS0_RCSUNIT;
654 status_reg = EXECLIST_STATUS_RCSUNIT;
655 control_reg = EXECLIST_CONTROL_RCSUNIT;
656 break;
657 case I915_EXEC_BSD:
658 ring_addr = VIDEO_RING_ADDR;
659 descriptor = VIDEO_CONTEXT_DESCRIPTOR;
660 elsp_reg = EXECLIST_SUBMITPORT_VCSUNIT0;
661 elsq_reg = EXECLIST_SQ_CONTENTS0_VCSUNIT0;
662 status_reg = EXECLIST_STATUS_VCSUNIT0;
663 control_reg = EXECLIST_CONTROL_VCSUNIT0;
664 break;
665 case I915_EXEC_BLT:
666 ring_addr = BLITTER_RING_ADDR;
667 descriptor = BLITTER_CONTEXT_DESCRIPTOR;
668 elsp_reg = EXECLIST_SUBMITPORT_BCSUNIT;
669 elsq_reg = EXECLIST_SQ_CONTENTS0_BCSUNIT;
670 status_reg = EXECLIST_STATUS_BCSUNIT;
671 control_reg = EXECLIST_CONTROL_BCSUNIT;
672 break;
673 default:
674 unreachable("unknown ring");
675 }
676
677 mem_trace_memory_write_header_out(aub, ring_addr, 16,
678 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
679 dword_out(aub, AUB_MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965 | (3 - 2));
680 dword_out(aub, batch_offset & 0xFFFFFFFF);
681 dword_out(aub, batch_offset >> 32);
682 dword_out(aub, 0 /* MI_NOOP */);
683
684 mem_trace_memory_write_header_out(aub, ring_addr + 8192 + 20, 4,
685 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
686 dword_out(aub, 0); /* RING_BUFFER_HEAD */
687 mem_trace_memory_write_header_out(aub, ring_addr + 8192 + 28, 4,
688 AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT);
689 dword_out(aub, 16); /* RING_BUFFER_TAIL */
690
691 if (aub->devinfo.gen >= 11) {
692 register_write_out(aub, elsq_reg, descriptor & 0xFFFFFFFF);
693 register_write_out(aub, elsq_reg + sizeof(uint32_t), descriptor >> 32);
694 register_write_out(aub, control_reg, 1);
695 } else {
696 register_write_out(aub, elsp_reg, 0);
697 register_write_out(aub, elsp_reg, 0);
698 register_write_out(aub, elsp_reg, descriptor >> 32);
699 register_write_out(aub, elsp_reg, descriptor & 0xFFFFFFFF);
700 }
701
702 dword_out(aub, CMD_MEM_TRACE_REGISTER_POLL | (5 + 1 - 1));
703 dword_out(aub, status_reg);
704 dword_out(aub, AUB_MEM_TRACE_REGISTER_SIZE_DWORD |
705 AUB_MEM_TRACE_REGISTER_SPACE_MMIO);
706 if (aub->devinfo.gen >= 11) {
707 dword_out(aub, 0x00000001); /* mask lo */
708 dword_out(aub, 0x00000000); /* mask hi */
709 dword_out(aub, 0x00000001);
710 } else {
711 dword_out(aub, 0x00000010); /* mask lo */
712 dword_out(aub, 0x00000000); /* mask hi */
713 dword_out(aub, 0x00000000);
714 }
715 }
716
717 static void
718 aub_dump_ringbuffer(struct aub_file *aub, uint64_t batch_offset,
719 uint64_t offset, int ring_flag)
720 {
721 uint32_t ringbuffer[4096];
722 unsigned aub_mi_bbs_len;
723 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
724 int ring_count = 0;
725
726 if (ring_flag == I915_EXEC_BSD)
727 ring = AUB_TRACE_TYPE_RING_PRB1;
728 else if (ring_flag == I915_EXEC_BLT)
729 ring = AUB_TRACE_TYPE_RING_PRB2;
730
731 /* Make a ring buffer to execute our batchbuffer. */
732 memset(ringbuffer, 0, sizeof(ringbuffer));
733
734 aub_mi_bbs_len = aub->addr_bits > 32 ? 3 : 2;
735 ringbuffer[ring_count] = AUB_MI_BATCH_BUFFER_START | (aub_mi_bbs_len - 2);
736 aub_write_reloc(&aub->devinfo, &ringbuffer[ring_count + 1], batch_offset);
737 ring_count += aub_mi_bbs_len;
738
739 /* Write out the ring. This appears to trigger execution of
740 * the ring in the simulator.
741 */
742 dword_out(aub, CMD_AUB_TRACE_HEADER_BLOCK |
743 ((aub->addr_bits > 32 ? 6 : 5) - 2));
744 dword_out(aub, AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
745 dword_out(aub, 0); /* general/surface subtype */
746 dword_out(aub, offset);
747 dword_out(aub, ring_count * 4);
748 if (aub->addr_bits > 32)
749 dword_out(aub, offset >> 32);
750
751 data_out(aub, ringbuffer, ring_count * 4);
752 }
753
754 void
755 aub_write_exec(struct aub_file *aub, uint64_t batch_addr,
756 uint64_t offset, int ring_flag)
757 {
758 if (aub_use_execlists(aub)) {
759 aub_dump_execlist(aub, batch_addr, ring_flag);
760 } else {
761 /* Dump ring buffer */
762 aub_dump_ringbuffer(aub, batch_addr, offset, ring_flag);
763 }
764 fflush(aub->file);
765 }