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anv/allocator: Drop the block_size field from block_pool
[mesa.git] / src / intel / vulkan / anv_blorp.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_private.h"
25
26 static bool
27 lookup_blorp_shader(struct blorp_context *blorp,
28 const void *key, uint32_t key_size,
29 uint32_t *kernel_out, void *prog_data_out)
30 {
31 struct anv_device *device = blorp->driver_ctx;
32
33 /* The blorp cache must be a real cache */
34 assert(device->blorp_shader_cache.cache);
35
36 struct anv_shader_bin *bin =
37 anv_pipeline_cache_search(&device->blorp_shader_cache, key, key_size);
38 if (!bin)
39 return false;
40
41 /* The cache already has a reference and it's not going anywhere so there
42 * is no need to hold a second reference.
43 */
44 anv_shader_bin_unref(device, bin);
45
46 *kernel_out = bin->kernel.offset;
47 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
48
49 return true;
50 }
51
52 static bool
53 upload_blorp_shader(struct blorp_context *blorp,
54 const void *key, uint32_t key_size,
55 const void *kernel, uint32_t kernel_size,
56 const struct brw_stage_prog_data *prog_data,
57 uint32_t prog_data_size,
58 uint32_t *kernel_out, void *prog_data_out)
59 {
60 struct anv_device *device = blorp->driver_ctx;
61
62 /* The blorp cache must be a real cache */
63 assert(device->blorp_shader_cache.cache);
64
65 struct anv_pipeline_bind_map bind_map = {
66 .surface_count = 0,
67 .sampler_count = 0,
68 };
69
70 struct anv_shader_bin *bin =
71 anv_pipeline_cache_upload_kernel(&device->blorp_shader_cache,
72 key, key_size, kernel, kernel_size,
73 prog_data, prog_data_size, &bind_map);
74
75 if (!bin)
76 return false;
77
78 /* The cache already has a reference and it's not going anywhere so there
79 * is no need to hold a second reference.
80 */
81 anv_shader_bin_unref(device, bin);
82
83 *kernel_out = bin->kernel.offset;
84 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
85
86 return true;
87 }
88
89 void
90 anv_device_init_blorp(struct anv_device *device)
91 {
92 anv_pipeline_cache_init(&device->blorp_shader_cache, device, true);
93 blorp_init(&device->blorp, device, &device->isl_dev);
94 device->blorp.compiler = device->instance->physicalDevice.compiler;
95 device->blorp.mocs.tex = device->default_mocs;
96 device->blorp.mocs.rb = device->default_mocs;
97 device->blorp.mocs.vb = device->default_mocs;
98 device->blorp.lookup_shader = lookup_blorp_shader;
99 device->blorp.upload_shader = upload_blorp_shader;
100 switch (device->info.gen) {
101 case 7:
102 if (device->info.is_haswell) {
103 device->blorp.exec = gen75_blorp_exec;
104 } else {
105 device->blorp.exec = gen7_blorp_exec;
106 }
107 break;
108 case 8:
109 device->blorp.exec = gen8_blorp_exec;
110 break;
111 case 9:
112 device->blorp.exec = gen9_blorp_exec;
113 break;
114 default:
115 unreachable("Unknown hardware generation");
116 }
117 }
118
119 void
120 anv_device_finish_blorp(struct anv_device *device)
121 {
122 blorp_finish(&device->blorp);
123 anv_pipeline_cache_finish(&device->blorp_shader_cache);
124 }
125
126 static void
127 get_blorp_surf_for_anv_buffer(struct anv_device *device,
128 struct anv_buffer *buffer, uint64_t offset,
129 uint32_t width, uint32_t height,
130 uint32_t row_pitch, enum isl_format format,
131 struct blorp_surf *blorp_surf,
132 struct isl_surf *isl_surf)
133 {
134 const struct isl_format_layout *fmtl =
135 isl_format_get_layout(format);
136 bool ok UNUSED;
137
138 /* ASTC is the only format which doesn't support linear layouts.
139 * Create an equivalently sized surface with ISL to get around this.
140 */
141 if (fmtl->txc == ISL_TXC_ASTC) {
142 /* Use an equivalently sized format */
143 format = ISL_FORMAT_R32G32B32A32_UINT;
144 assert(fmtl->bpb == isl_format_get_layout(format)->bpb);
145
146 /* Shrink the dimensions for the new format */
147 width = DIV_ROUND_UP(width, fmtl->bw);
148 height = DIV_ROUND_UP(height, fmtl->bh);
149 }
150
151 *blorp_surf = (struct blorp_surf) {
152 .surf = isl_surf,
153 .addr = {
154 .buffer = buffer->bo,
155 .offset = buffer->offset + offset,
156 },
157 };
158
159 ok = isl_surf_init(&device->isl_dev, isl_surf,
160 .dim = ISL_SURF_DIM_2D,
161 .format = format,
162 .width = width,
163 .height = height,
164 .depth = 1,
165 .levels = 1,
166 .array_len = 1,
167 .samples = 1,
168 .row_pitch = row_pitch,
169 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
170 ISL_SURF_USAGE_RENDER_TARGET_BIT,
171 .tiling_flags = ISL_TILING_LINEAR_BIT);
172 assert(ok);
173 }
174
175 static void
176 get_blorp_surf_for_anv_image(const struct anv_image *image,
177 VkImageAspectFlags aspect,
178 enum isl_aux_usage aux_usage,
179 struct blorp_surf *blorp_surf)
180 {
181 if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT ||
182 aux_usage == ISL_AUX_USAGE_HIZ)
183 aux_usage = ISL_AUX_USAGE_NONE;
184
185 const struct anv_surface *surface =
186 anv_image_get_surface_for_aspect_mask(image, aspect);
187
188 *blorp_surf = (struct blorp_surf) {
189 .surf = &surface->isl,
190 .addr = {
191 .buffer = image->bo,
192 .offset = image->offset + surface->offset,
193 },
194 };
195
196 if (aux_usage != ISL_AUX_USAGE_NONE) {
197 blorp_surf->aux_surf = &image->aux_surface.isl,
198 blorp_surf->aux_addr = (struct blorp_address) {
199 .buffer = image->bo,
200 .offset = image->offset + image->aux_surface.offset,
201 };
202 blorp_surf->aux_usage = aux_usage;
203 }
204 }
205
206 void anv_CmdCopyImage(
207 VkCommandBuffer commandBuffer,
208 VkImage srcImage,
209 VkImageLayout srcImageLayout,
210 VkImage dstImage,
211 VkImageLayout dstImageLayout,
212 uint32_t regionCount,
213 const VkImageCopy* pRegions)
214 {
215 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
216 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
217 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
218
219 struct blorp_batch batch;
220 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
221
222 for (unsigned r = 0; r < regionCount; r++) {
223 VkOffset3D srcOffset =
224 anv_sanitize_image_offset(src_image->type, pRegions[r].srcOffset);
225 VkOffset3D dstOffset =
226 anv_sanitize_image_offset(dst_image->type, pRegions[r].dstOffset);
227 VkExtent3D extent =
228 anv_sanitize_image_extent(src_image->type, pRegions[r].extent);
229
230 unsigned dst_base_layer, layer_count;
231 if (dst_image->type == VK_IMAGE_TYPE_3D) {
232 dst_base_layer = pRegions[r].dstOffset.z;
233 layer_count = pRegions[r].extent.depth;
234 } else {
235 dst_base_layer = pRegions[r].dstSubresource.baseArrayLayer;
236 layer_count =
237 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
238 }
239
240 unsigned src_base_layer;
241 if (src_image->type == VK_IMAGE_TYPE_3D) {
242 src_base_layer = pRegions[r].srcOffset.z;
243 } else {
244 src_base_layer = pRegions[r].srcSubresource.baseArrayLayer;
245 assert(layer_count ==
246 anv_get_layerCount(src_image, &pRegions[r].srcSubresource));
247 }
248
249 assert(pRegions[r].srcSubresource.aspectMask ==
250 pRegions[r].dstSubresource.aspectMask);
251
252 uint32_t a;
253 for_each_bit(a, pRegions[r].dstSubresource.aspectMask) {
254 VkImageAspectFlagBits aspect = (1 << a);
255
256 struct blorp_surf src_surf, dst_surf;
257 get_blorp_surf_for_anv_image(src_image, aspect, src_image->aux_usage,
258 &src_surf);
259 get_blorp_surf_for_anv_image(dst_image, aspect, dst_image->aux_usage,
260 &dst_surf);
261
262 for (unsigned i = 0; i < layer_count; i++) {
263 blorp_copy(&batch, &src_surf, pRegions[r].srcSubresource.mipLevel,
264 src_base_layer + i,
265 &dst_surf, pRegions[r].dstSubresource.mipLevel,
266 dst_base_layer + i,
267 srcOffset.x, srcOffset.y,
268 dstOffset.x, dstOffset.y,
269 extent.width, extent.height);
270 }
271 }
272 }
273
274 blorp_batch_finish(&batch);
275 }
276
277 static void
278 copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
279 struct anv_buffer *anv_buffer,
280 struct anv_image *anv_image,
281 uint32_t regionCount,
282 const VkBufferImageCopy* pRegions,
283 bool buffer_to_image)
284 {
285 struct blorp_batch batch;
286 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
287
288 struct {
289 struct blorp_surf surf;
290 uint32_t level;
291 VkOffset3D offset;
292 } image, buffer, *src, *dst;
293
294 buffer.level = 0;
295 buffer.offset = (VkOffset3D) { 0, 0, 0 };
296
297 if (buffer_to_image) {
298 src = &buffer;
299 dst = &image;
300 } else {
301 src = &image;
302 dst = &buffer;
303 }
304
305 for (unsigned r = 0; r < regionCount; r++) {
306 const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
307
308 get_blorp_surf_for_anv_image(anv_image, aspect, anv_image->aux_usage,
309 &image.surf);
310 image.offset =
311 anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
312 image.level = pRegions[r].imageSubresource.mipLevel;
313
314 VkExtent3D extent =
315 anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
316 if (anv_image->type != VK_IMAGE_TYPE_3D) {
317 image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
318 extent.depth =
319 anv_get_layerCount(anv_image, &pRegions[r].imageSubresource);
320 }
321
322 const enum isl_format buffer_format =
323 anv_get_isl_format(&cmd_buffer->device->info, anv_image->vk_format,
324 aspect, VK_IMAGE_TILING_LINEAR);
325
326 const VkExtent3D bufferImageExtent = {
327 .width = pRegions[r].bufferRowLength ?
328 pRegions[r].bufferRowLength : extent.width,
329 .height = pRegions[r].bufferImageHeight ?
330 pRegions[r].bufferImageHeight : extent.height,
331 };
332
333 const struct isl_format_layout *buffer_fmtl =
334 isl_format_get_layout(buffer_format);
335
336 const uint32_t buffer_row_pitch =
337 DIV_ROUND_UP(bufferImageExtent.width, buffer_fmtl->bw) *
338 (buffer_fmtl->bpb / 8);
339
340 const uint32_t buffer_layer_stride =
341 DIV_ROUND_UP(bufferImageExtent.height, buffer_fmtl->bh) *
342 buffer_row_pitch;
343
344 struct isl_surf buffer_isl_surf;
345 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
346 anv_buffer, pRegions[r].bufferOffset,
347 extent.width, extent.height,
348 buffer_row_pitch, buffer_format,
349 &buffer.surf, &buffer_isl_surf);
350
351 for (unsigned z = 0; z < extent.depth; z++) {
352 blorp_copy(&batch, &src->surf, src->level, src->offset.z,
353 &dst->surf, dst->level, dst->offset.z,
354 src->offset.x, src->offset.y, dst->offset.x, dst->offset.y,
355 extent.width, extent.height);
356
357 image.offset.z++;
358 buffer.surf.addr.offset += buffer_layer_stride;
359 }
360 }
361
362 blorp_batch_finish(&batch);
363 }
364
365 void anv_CmdCopyBufferToImage(
366 VkCommandBuffer commandBuffer,
367 VkBuffer srcBuffer,
368 VkImage dstImage,
369 VkImageLayout dstImageLayout,
370 uint32_t regionCount,
371 const VkBufferImageCopy* pRegions)
372 {
373 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
374 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
375 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
376
377 copy_buffer_to_image(cmd_buffer, src_buffer, dst_image,
378 regionCount, pRegions, true);
379 }
380
381 void anv_CmdCopyImageToBuffer(
382 VkCommandBuffer commandBuffer,
383 VkImage srcImage,
384 VkImageLayout srcImageLayout,
385 VkBuffer dstBuffer,
386 uint32_t regionCount,
387 const VkBufferImageCopy* pRegions)
388 {
389 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
390 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
391 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
392
393 copy_buffer_to_image(cmd_buffer, dst_buffer, src_image,
394 regionCount, pRegions, false);
395 }
396
397 static bool
398 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
399 {
400 bool flip = false;
401 if (*src0 > *src1) {
402 unsigned tmp = *src0;
403 *src0 = *src1;
404 *src1 = tmp;
405 flip = !flip;
406 }
407
408 if (*dst0 > *dst1) {
409 unsigned tmp = *dst0;
410 *dst0 = *dst1;
411 *dst1 = tmp;
412 flip = !flip;
413 }
414
415 return flip;
416 }
417
418 void anv_CmdBlitImage(
419 VkCommandBuffer commandBuffer,
420 VkImage srcImage,
421 VkImageLayout srcImageLayout,
422 VkImage dstImage,
423 VkImageLayout dstImageLayout,
424 uint32_t regionCount,
425 const VkImageBlit* pRegions,
426 VkFilter filter)
427
428 {
429 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
430 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
431 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
432
433 struct blorp_surf src, dst;
434
435 uint32_t gl_filter;
436 switch (filter) {
437 case VK_FILTER_NEAREST:
438 gl_filter = 0x2600; /* GL_NEAREST */
439 break;
440 case VK_FILTER_LINEAR:
441 gl_filter = 0x2601; /* GL_LINEAR */
442 break;
443 default:
444 unreachable("Invalid filter");
445 }
446
447 struct blorp_batch batch;
448 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
449
450 for (unsigned r = 0; r < regionCount; r++) {
451 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
452 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
453
454 get_blorp_surf_for_anv_image(src_image, src_res->aspectMask,
455 src_image->aux_usage, &src);
456 get_blorp_surf_for_anv_image(dst_image, dst_res->aspectMask,
457 dst_image->aux_usage, &dst);
458
459 struct anv_format src_format =
460 anv_get_format(&cmd_buffer->device->info, src_image->vk_format,
461 src_res->aspectMask, src_image->tiling);
462 struct anv_format dst_format =
463 anv_get_format(&cmd_buffer->device->info, dst_image->vk_format,
464 dst_res->aspectMask, dst_image->tiling);
465
466 unsigned dst_start, dst_end;
467 if (dst_image->type == VK_IMAGE_TYPE_3D) {
468 assert(dst_res->baseArrayLayer == 0);
469 dst_start = pRegions[r].dstOffsets[0].z;
470 dst_end = pRegions[r].dstOffsets[1].z;
471 } else {
472 dst_start = dst_res->baseArrayLayer;
473 dst_end = dst_start + anv_get_layerCount(dst_image, dst_res);
474 }
475
476 unsigned src_start, src_end;
477 if (src_image->type == VK_IMAGE_TYPE_3D) {
478 assert(src_res->baseArrayLayer == 0);
479 src_start = pRegions[r].srcOffsets[0].z;
480 src_end = pRegions[r].srcOffsets[1].z;
481 } else {
482 src_start = src_res->baseArrayLayer;
483 src_end = src_start + anv_get_layerCount(src_image, src_res);
484 }
485
486 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
487 float src_z_step = (float)(src_end + 1 - src_start) /
488 (float)(dst_end + 1 - dst_start);
489
490 if (flip_z) {
491 src_start = src_end;
492 src_z_step *= -1;
493 }
494
495 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
496 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
497 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
498 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
499 bool flip_x = flip_coords(&src_x0, &src_x1, &dst_x0, &dst_x1);
500
501 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
502 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
503 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
504 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
505 bool flip_y = flip_coords(&src_y0, &src_y1, &dst_y0, &dst_y1);
506
507 const unsigned num_layers = dst_end - dst_start;
508 for (unsigned i = 0; i < num_layers; i++) {
509 unsigned dst_z = dst_start + i;
510 unsigned src_z = src_start + i * src_z_step;
511
512 blorp_blit(&batch, &src, src_res->mipLevel, src_z,
513 src_format.isl_format, src_format.swizzle,
514 &dst, dst_res->mipLevel, dst_z,
515 dst_format.isl_format,
516 anv_swizzle_for_render(dst_format.swizzle),
517 src_x0, src_y0, src_x1, src_y1,
518 dst_x0, dst_y0, dst_x1, dst_y1,
519 gl_filter, flip_x, flip_y);
520 }
521
522 }
523
524 blorp_batch_finish(&batch);
525 }
526
527 static enum isl_format
528 isl_format_for_size(unsigned size_B)
529 {
530 switch (size_B) {
531 case 1: return ISL_FORMAT_R8_UINT;
532 case 2: return ISL_FORMAT_R8G8_UINT;
533 case 4: return ISL_FORMAT_R8G8B8A8_UINT;
534 case 8: return ISL_FORMAT_R16G16B16A16_UINT;
535 case 16: return ISL_FORMAT_R32G32B32A32_UINT;
536 default:
537 unreachable("Not a power-of-two format size");
538 }
539 }
540
541 static void
542 do_buffer_copy(struct blorp_batch *batch,
543 struct anv_bo *src, uint64_t src_offset,
544 struct anv_bo *dst, uint64_t dst_offset,
545 int width, int height, int block_size)
546 {
547 struct anv_device *device = batch->blorp->driver_ctx;
548
549 /* The actual format we pick doesn't matter as blorp will throw it away.
550 * The only thing that actually matters is the size.
551 */
552 enum isl_format format = isl_format_for_size(block_size);
553
554 struct isl_surf surf;
555 isl_surf_init(&device->isl_dev, &surf,
556 .dim = ISL_SURF_DIM_2D,
557 .format = format,
558 .width = width,
559 .height = height,
560 .depth = 1,
561 .levels = 1,
562 .array_len = 1,
563 .samples = 1,
564 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
565 ISL_SURF_USAGE_RENDER_TARGET_BIT,
566 .tiling_flags = ISL_TILING_LINEAR_BIT);
567 assert(surf.row_pitch == width * block_size);
568
569 struct blorp_surf src_blorp_surf = {
570 .surf = &surf,
571 .addr = {
572 .buffer = src,
573 .offset = src_offset,
574 },
575 };
576
577 struct blorp_surf dst_blorp_surf = {
578 .surf = &surf,
579 .addr = {
580 .buffer = dst,
581 .offset = dst_offset,
582 },
583 };
584
585 blorp_copy(batch, &src_blorp_surf, 0, 0, &dst_blorp_surf, 0, 0,
586 0, 0, 0, 0, width, height);
587 }
588
589 /**
590 * Returns the greatest common divisor of a and b that is a power of two.
591 */
592 static inline uint64_t
593 gcd_pow2_u64(uint64_t a, uint64_t b)
594 {
595 assert(a > 0 || b > 0);
596
597 unsigned a_log2 = ffsll(a) - 1;
598 unsigned b_log2 = ffsll(b) - 1;
599
600 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
601 * case, the MIN2() will take the other one. If both are 0 then we will
602 * hit the assert above.
603 */
604 return 1 << MIN2(a_log2, b_log2);
605 }
606
607 /* This is maximum possible width/height our HW can handle */
608 #define MAX_SURFACE_DIM (1ull << 14)
609
610 void anv_CmdCopyBuffer(
611 VkCommandBuffer commandBuffer,
612 VkBuffer srcBuffer,
613 VkBuffer dstBuffer,
614 uint32_t regionCount,
615 const VkBufferCopy* pRegions)
616 {
617 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
618 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
619 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
620
621 struct blorp_batch batch;
622 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
623
624 for (unsigned r = 0; r < regionCount; r++) {
625 uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
626 uint64_t dst_offset = dst_buffer->offset + pRegions[r].dstOffset;
627 uint64_t copy_size = pRegions[r].size;
628
629 /* First, we compute the biggest format that can be used with the
630 * given offsets and size.
631 */
632 int bs = 16;
633 bs = gcd_pow2_u64(bs, src_offset);
634 bs = gcd_pow2_u64(bs, dst_offset);
635 bs = gcd_pow2_u64(bs, pRegions[r].size);
636
637 /* First, we make a bunch of max-sized copies */
638 uint64_t max_copy_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
639 while (copy_size >= max_copy_size) {
640 do_buffer_copy(&batch, src_buffer->bo, src_offset,
641 dst_buffer->bo, dst_offset,
642 MAX_SURFACE_DIM, MAX_SURFACE_DIM, bs);
643 copy_size -= max_copy_size;
644 src_offset += max_copy_size;
645 dst_offset += max_copy_size;
646 }
647
648 /* Now make a max-width copy */
649 uint64_t height = copy_size / (MAX_SURFACE_DIM * bs);
650 assert(height < MAX_SURFACE_DIM);
651 if (height != 0) {
652 uint64_t rect_copy_size = height * MAX_SURFACE_DIM * bs;
653 do_buffer_copy(&batch, src_buffer->bo, src_offset,
654 dst_buffer->bo, dst_offset,
655 MAX_SURFACE_DIM, height, bs);
656 copy_size -= rect_copy_size;
657 src_offset += rect_copy_size;
658 dst_offset += rect_copy_size;
659 }
660
661 /* Finally, make a small copy to finish it off */
662 if (copy_size != 0) {
663 do_buffer_copy(&batch, src_buffer->bo, src_offset,
664 dst_buffer->bo, dst_offset,
665 copy_size / bs, 1, bs);
666 }
667 }
668
669 blorp_batch_finish(&batch);
670 }
671
672 void anv_CmdUpdateBuffer(
673 VkCommandBuffer commandBuffer,
674 VkBuffer dstBuffer,
675 VkDeviceSize dstOffset,
676 VkDeviceSize dataSize,
677 const void* pData)
678 {
679 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
680 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
681
682 struct blorp_batch batch;
683 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
684
685 /* We can't quite grab a full block because the state stream needs a
686 * little data at the top to build its linked list.
687 */
688 const uint32_t max_update_size =
689 cmd_buffer->device->dynamic_state_pool.block_size - 64;
690
691 assert(max_update_size < MAX_SURFACE_DIM * 4);
692
693 /* We're about to read data that was written from the CPU. Flush the
694 * texture cache so we don't get anything stale.
695 */
696 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
697
698 while (dataSize) {
699 const uint32_t copy_size = MIN2(dataSize, max_update_size);
700
701 struct anv_state tmp_data =
702 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, copy_size, 64);
703
704 memcpy(tmp_data.map, pData, copy_size);
705
706 anv_state_flush(cmd_buffer->device, tmp_data);
707
708 int bs = 16;
709 bs = gcd_pow2_u64(bs, dstOffset);
710 bs = gcd_pow2_u64(bs, copy_size);
711
712 do_buffer_copy(&batch,
713 &cmd_buffer->device->dynamic_state_block_pool.bo,
714 tmp_data.offset,
715 dst_buffer->bo, dst_buffer->offset + dstOffset,
716 copy_size / bs, 1, bs);
717
718 dataSize -= copy_size;
719 dstOffset += copy_size;
720 pData = (void *)pData + copy_size;
721 }
722
723 blorp_batch_finish(&batch);
724 }
725
726 void anv_CmdFillBuffer(
727 VkCommandBuffer commandBuffer,
728 VkBuffer dstBuffer,
729 VkDeviceSize dstOffset,
730 VkDeviceSize fillSize,
731 uint32_t data)
732 {
733 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
734 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
735 struct blorp_surf surf;
736 struct isl_surf isl_surf;
737
738 struct blorp_batch batch;
739 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
740
741 fillSize = anv_buffer_get_range(dst_buffer, dstOffset, fillSize);
742
743 /* From the Vulkan spec:
744 *
745 * "size is the number of bytes to fill, and must be either a multiple
746 * of 4, or VK_WHOLE_SIZE to fill the range from offset to the end of
747 * the buffer. If VK_WHOLE_SIZE is used and the remaining size of the
748 * buffer is not a multiple of 4, then the nearest smaller multiple is
749 * used."
750 */
751 fillSize &= ~3ull;
752
753 /* First, we compute the biggest format that can be used with the
754 * given offsets and size.
755 */
756 int bs = 16;
757 bs = gcd_pow2_u64(bs, dstOffset);
758 bs = gcd_pow2_u64(bs, fillSize);
759 enum isl_format isl_format = isl_format_for_size(bs);
760
761 union isl_color_value color = {
762 .u32 = { data, data, data, data },
763 };
764
765 const uint64_t max_fill_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
766 while (fillSize >= max_fill_size) {
767 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
768 dst_buffer, dstOffset,
769 MAX_SURFACE_DIM, MAX_SURFACE_DIM,
770 MAX_SURFACE_DIM * bs, isl_format,
771 &surf, &isl_surf);
772
773 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
774 0, 0, 1, 0, 0, MAX_SURFACE_DIM, MAX_SURFACE_DIM,
775 color, NULL);
776 fillSize -= max_fill_size;
777 dstOffset += max_fill_size;
778 }
779
780 uint64_t height = fillSize / (MAX_SURFACE_DIM * bs);
781 assert(height < MAX_SURFACE_DIM);
782 if (height != 0) {
783 const uint64_t rect_fill_size = height * MAX_SURFACE_DIM * bs;
784 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
785 dst_buffer, dstOffset,
786 MAX_SURFACE_DIM, height,
787 MAX_SURFACE_DIM * bs, isl_format,
788 &surf, &isl_surf);
789
790 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
791 0, 0, 1, 0, 0, MAX_SURFACE_DIM, height,
792 color, NULL);
793 fillSize -= rect_fill_size;
794 dstOffset += rect_fill_size;
795 }
796
797 if (fillSize != 0) {
798 const uint32_t width = fillSize / bs;
799 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
800 dst_buffer, dstOffset,
801 width, 1,
802 width * bs, isl_format,
803 &surf, &isl_surf);
804
805 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
806 0, 0, 1, 0, 0, width, 1,
807 color, NULL);
808 }
809
810 blorp_batch_finish(&batch);
811 }
812
813 void anv_CmdClearColorImage(
814 VkCommandBuffer commandBuffer,
815 VkImage _image,
816 VkImageLayout imageLayout,
817 const VkClearColorValue* pColor,
818 uint32_t rangeCount,
819 const VkImageSubresourceRange* pRanges)
820 {
821 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
822 ANV_FROM_HANDLE(anv_image, image, _image);
823
824 static const bool color_write_disable[4] = { false, false, false, false };
825
826 struct blorp_batch batch;
827 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
828
829 struct blorp_surf surf;
830 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
831 image->aux_usage, &surf);
832
833 for (unsigned r = 0; r < rangeCount; r++) {
834 if (pRanges[r].aspectMask == 0)
835 continue;
836
837 assert(pRanges[r].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
838
839 struct anv_format src_format =
840 anv_get_format(&cmd_buffer->device->info, image->vk_format,
841 VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
842
843 unsigned base_layer = pRanges[r].baseArrayLayer;
844 unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
845
846 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
847 const unsigned level = pRanges[r].baseMipLevel + i;
848 const unsigned level_width = anv_minify(image->extent.width, level);
849 const unsigned level_height = anv_minify(image->extent.height, level);
850
851 if (image->type == VK_IMAGE_TYPE_3D) {
852 base_layer = 0;
853 layer_count = anv_minify(image->extent.depth, level);
854 }
855
856 blorp_clear(&batch, &surf,
857 src_format.isl_format, src_format.swizzle,
858 level, base_layer, layer_count,
859 0, 0, level_width, level_height,
860 vk_to_isl_color(*pColor), color_write_disable);
861 }
862 }
863
864 blorp_batch_finish(&batch);
865 }
866
867 void anv_CmdClearDepthStencilImage(
868 VkCommandBuffer commandBuffer,
869 VkImage image_h,
870 VkImageLayout imageLayout,
871 const VkClearDepthStencilValue* pDepthStencil,
872 uint32_t rangeCount,
873 const VkImageSubresourceRange* pRanges)
874 {
875 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
876 ANV_FROM_HANDLE(anv_image, image, image_h);
877
878 struct blorp_batch batch;
879 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
880
881 struct blorp_surf depth, stencil;
882 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
883 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
884 ISL_AUX_USAGE_NONE, &depth);
885 } else {
886 memset(&depth, 0, sizeof(depth));
887 }
888
889 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
890 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_STENCIL_BIT,
891 ISL_AUX_USAGE_NONE, &stencil);
892 } else {
893 memset(&stencil, 0, sizeof(stencil));
894 }
895
896 for (unsigned r = 0; r < rangeCount; r++) {
897 if (pRanges[r].aspectMask == 0)
898 continue;
899
900 bool clear_depth = pRanges[r].aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
901 bool clear_stencil = pRanges[r].aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
902
903 unsigned base_layer = pRanges[r].baseArrayLayer;
904 unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
905
906 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
907 const unsigned level = pRanges[r].baseMipLevel + i;
908 const unsigned level_width = anv_minify(image->extent.width, level);
909 const unsigned level_height = anv_minify(image->extent.height, level);
910
911 if (image->type == VK_IMAGE_TYPE_3D)
912 layer_count = anv_minify(image->extent.depth, level);
913
914 blorp_clear_depth_stencil(&batch, &depth, &stencil,
915 level, base_layer, layer_count,
916 0, 0, level_width, level_height,
917 clear_depth, pDepthStencil->depth,
918 clear_stencil ? 0xff : 0,
919 pDepthStencil->stencil);
920 }
921 }
922
923 blorp_batch_finish(&batch);
924 }
925
926 VkResult
927 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
928 uint32_t num_entries,
929 uint32_t *state_offset,
930 struct anv_state *bt_state)
931 {
932 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
933 state_offset);
934 if (bt_state->map == NULL) {
935 /* We ran out of space. Grab a new binding table block. */
936 VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
937 if (result != VK_SUCCESS)
938 return result;
939
940 /* Re-emit state base addresses so we get the new surface state base
941 * address before we start emitting binding tables etc.
942 */
943 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
944
945 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
946 state_offset);
947 assert(bt_state->map != NULL);
948 }
949
950 return VK_SUCCESS;
951 }
952
953 static VkResult
954 binding_table_for_surface_state(struct anv_cmd_buffer *cmd_buffer,
955 struct anv_state surface_state,
956 uint32_t *bt_offset)
957 {
958 uint32_t state_offset;
959 struct anv_state bt_state;
960
961 VkResult result =
962 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset,
963 &bt_state);
964 if (result != VK_SUCCESS)
965 return result;
966
967 uint32_t *bt_map = bt_state.map;
968 bt_map[0] = surface_state.offset + state_offset;
969
970 *bt_offset = bt_state.offset;
971 return VK_SUCCESS;
972 }
973
974 static void
975 clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
976 struct blorp_batch *batch,
977 const VkClearAttachment *attachment,
978 uint32_t rectCount, const VkClearRect *pRects)
979 {
980 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
981 const uint32_t color_att = attachment->colorAttachment;
982 const uint32_t att_idx = subpass->color_attachments[color_att].attachment;
983
984 if (att_idx == VK_ATTACHMENT_UNUSED)
985 return;
986
987 struct anv_render_pass_attachment *pass_att =
988 &cmd_buffer->state.pass->attachments[att_idx];
989 struct anv_attachment_state *att_state =
990 &cmd_buffer->state.attachments[att_idx];
991
992 uint32_t binding_table;
993 VkResult result =
994 binding_table_for_surface_state(cmd_buffer, att_state->color_rt_state,
995 &binding_table);
996 if (result != VK_SUCCESS)
997 return;
998
999 union isl_color_value clear_color =
1000 vk_to_isl_color(attachment->clearValue.color);
1001
1002 for (uint32_t r = 0; r < rectCount; ++r) {
1003 const VkOffset2D offset = pRects[r].rect.offset;
1004 const VkExtent2D extent = pRects[r].rect.extent;
1005 blorp_clear_attachments(batch, binding_table,
1006 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
1007 pRects[r].baseArrayLayer,
1008 pRects[r].layerCount,
1009 offset.x, offset.y,
1010 offset.x + extent.width, offset.y + extent.height,
1011 true, clear_color, false, 0.0f, 0, 0);
1012 }
1013 }
1014
1015 static void
1016 clear_depth_stencil_attachment(struct anv_cmd_buffer *cmd_buffer,
1017 struct blorp_batch *batch,
1018 const VkClearAttachment *attachment,
1019 uint32_t rectCount, const VkClearRect *pRects)
1020 {
1021 static const union isl_color_value color_value = { .u32 = { 0, } };
1022 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
1023 const uint32_t att_idx = subpass->depth_stencil_attachment.attachment;
1024
1025 if (att_idx == VK_ATTACHMENT_UNUSED)
1026 return;
1027
1028 struct anv_render_pass_attachment *pass_att =
1029 &cmd_buffer->state.pass->attachments[att_idx];
1030
1031 bool clear_depth = attachment->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
1032 bool clear_stencil = attachment->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
1033
1034 enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
1035 if (clear_depth) {
1036 depth_format = anv_get_isl_format(&cmd_buffer->device->info,
1037 pass_att->format,
1038 VK_IMAGE_ASPECT_DEPTH_BIT,
1039 VK_IMAGE_TILING_OPTIMAL);
1040 }
1041
1042 uint32_t binding_table;
1043 VkResult result =
1044 binding_table_for_surface_state(cmd_buffer,
1045 cmd_buffer->state.null_surface_state,
1046 &binding_table);
1047 if (result != VK_SUCCESS)
1048 return;
1049
1050 for (uint32_t r = 0; r < rectCount; ++r) {
1051 const VkOffset2D offset = pRects[r].rect.offset;
1052 const VkExtent2D extent = pRects[r].rect.extent;
1053 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1054 blorp_clear_attachments(batch, binding_table,
1055 depth_format, pass_att->samples,
1056 pRects[r].baseArrayLayer,
1057 pRects[r].layerCount,
1058 offset.x, offset.y,
1059 offset.x + extent.width, offset.y + extent.height,
1060 false, color_value,
1061 clear_depth, value.depth,
1062 clear_stencil ? 0xff : 0, value.stencil);
1063 }
1064 }
1065
1066 void anv_CmdClearAttachments(
1067 VkCommandBuffer commandBuffer,
1068 uint32_t attachmentCount,
1069 const VkClearAttachment* pAttachments,
1070 uint32_t rectCount,
1071 const VkClearRect* pRects)
1072 {
1073 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1074
1075 /* Because this gets called within a render pass, we tell blorp not to
1076 * trash our depth and stencil buffers.
1077 */
1078 struct blorp_batch batch;
1079 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1080 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1081
1082 for (uint32_t a = 0; a < attachmentCount; ++a) {
1083 if (pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
1084 clear_color_attachment(cmd_buffer, &batch,
1085 &pAttachments[a],
1086 rectCount, pRects);
1087 } else {
1088 clear_depth_stencil_attachment(cmd_buffer, &batch,
1089 &pAttachments[a],
1090 rectCount, pRects);
1091 }
1092 }
1093
1094 blorp_batch_finish(&batch);
1095 }
1096
1097 enum subpass_stage {
1098 SUBPASS_STAGE_LOAD,
1099 SUBPASS_STAGE_DRAW,
1100 SUBPASS_STAGE_RESOLVE,
1101 };
1102
1103 static bool
1104 subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer)
1105 {
1106 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1107 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1108
1109 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1110 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1111 if (a == VK_ATTACHMENT_UNUSED)
1112 continue;
1113
1114 assert(a < cmd_state->pass->attachment_count);
1115 if (cmd_state->attachments[a].pending_clear_aspects) {
1116 return true;
1117 }
1118 }
1119
1120 if (ds != VK_ATTACHMENT_UNUSED) {
1121 assert(ds < cmd_state->pass->attachment_count);
1122 if (cmd_state->attachments[ds].pending_clear_aspects)
1123 return true;
1124 }
1125
1126 return false;
1127 }
1128
1129 void
1130 anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
1131 {
1132 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1133 const VkRect2D render_area = cmd_buffer->state.render_area;
1134
1135
1136 if (!subpass_needs_clear(cmd_buffer))
1137 return;
1138
1139 /* Because this gets called within a render pass, we tell blorp not to
1140 * trash our depth and stencil buffers.
1141 */
1142 struct blorp_batch batch;
1143 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1144 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1145
1146 VkClearRect clear_rect = {
1147 .rect = cmd_buffer->state.render_area,
1148 .baseArrayLayer = 0,
1149 .layerCount = cmd_buffer->state.framebuffer->layers,
1150 };
1151
1152 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1153 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1154 const uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1155 if (a == VK_ATTACHMENT_UNUSED)
1156 continue;
1157
1158 assert(a < cmd_state->pass->attachment_count);
1159 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
1160
1161 if (!att_state->pending_clear_aspects)
1162 continue;
1163
1164 assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1165
1166 struct anv_image_view *iview = fb->attachments[a];
1167 const struct anv_image *image = iview->image;
1168 struct blorp_surf surf;
1169 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1170 att_state->aux_usage, &surf);
1171
1172 if (att_state->fast_clear) {
1173 surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
1174
1175 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1176 *
1177 * "After Render target fast clear, pipe-control with color cache
1178 * write-flush must be issued before sending any DRAW commands on
1179 * that render target."
1180 *
1181 * This comment is a bit cryptic and doesn't really tell you what's
1182 * going or what's really needed. It appears that fast clear ops are
1183 * not properly synchronized with other drawing. This means that we
1184 * cannot have a fast clear operation in the pipe at the same time as
1185 * other regular drawing operations. We need to use a PIPE_CONTROL
1186 * to ensure that the contents of the previous draw hit the render
1187 * target before we resolve and then use a second PIPE_CONTROL after
1188 * the resolve to ensure that it is completed before any additional
1189 * drawing occurs.
1190 */
1191 cmd_buffer->state.pending_pipe_bits |=
1192 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1193
1194 blorp_fast_clear(&batch, &surf, iview->isl.format,
1195 iview->isl.base_level,
1196 iview->isl.base_array_layer, fb->layers,
1197 render_area.offset.x, render_area.offset.y,
1198 render_area.offset.x + render_area.extent.width,
1199 render_area.offset.y + render_area.extent.height);
1200
1201 cmd_buffer->state.pending_pipe_bits |=
1202 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1203 } else {
1204 blorp_clear(&batch, &surf, iview->isl.format,
1205 anv_swizzle_for_render(iview->isl.swizzle),
1206 iview->isl.base_level,
1207 iview->isl.base_array_layer, fb->layers,
1208 render_area.offset.x, render_area.offset.y,
1209 render_area.offset.x + render_area.extent.width,
1210 render_area.offset.y + render_area.extent.height,
1211 vk_to_isl_color(att_state->clear_value.color), NULL);
1212 }
1213
1214 att_state->pending_clear_aspects = 0;
1215 }
1216
1217 const uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1218 assert(ds == VK_ATTACHMENT_UNUSED || ds < cmd_state->pass->attachment_count);
1219
1220 if (ds != VK_ATTACHMENT_UNUSED &&
1221 cmd_state->attachments[ds].pending_clear_aspects) {
1222
1223 VkClearAttachment clear_att = {
1224 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1225 .clearValue = cmd_state->attachments[ds].clear_value,
1226 };
1227
1228
1229 const uint8_t gen = cmd_buffer->device->info.gen;
1230 bool clear_with_hiz = gen >= 8 && cmd_state->attachments[ds].aux_usage ==
1231 ISL_AUX_USAGE_HIZ;
1232 const struct anv_image_view *iview = fb->attachments[ds];
1233
1234 if (clear_with_hiz) {
1235 const bool clear_depth = clear_att.aspectMask &
1236 VK_IMAGE_ASPECT_DEPTH_BIT;
1237 const bool clear_stencil = clear_att.aspectMask &
1238 VK_IMAGE_ASPECT_STENCIL_BIT;
1239
1240 /* Check against restrictions for depth buffer clearing. A great GPU
1241 * performance benefit isn't expected when using the HZ sequence for
1242 * stencil-only clears. Therefore, we don't emit a HZ op sequence for
1243 * a stencil clear in addition to using the BLORP-fallback for depth.
1244 */
1245 if (clear_depth) {
1246 if (!blorp_can_hiz_clear_depth(gen, iview->isl.format,
1247 iview->image->samples,
1248 render_area.offset.x,
1249 render_area.offset.y,
1250 render_area.offset.x +
1251 render_area.extent.width,
1252 render_area.offset.y +
1253 render_area.extent.height)) {
1254 clear_with_hiz = false;
1255 } else if (clear_att.clearValue.depthStencil.depth !=
1256 ANV_HZ_FC_VAL) {
1257 /* Don't enable fast depth clears for any color not equal to
1258 * ANV_HZ_FC_VAL.
1259 */
1260 clear_with_hiz = false;
1261 } else if (gen == 8 &&
1262 anv_can_sample_with_hiz(&cmd_buffer->device->info,
1263 iview->aspect_mask,
1264 iview->image->samples)) {
1265 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
1266 * fast-cleared portion of a HiZ buffer. Testing has revealed
1267 * that Gen8 only supports returning 0.0f. Gens prior to gen8 do
1268 * not support this feature at all.
1269 */
1270 clear_with_hiz = false;
1271 }
1272 }
1273
1274 if (clear_with_hiz) {
1275 blorp_gen8_hiz_clear_attachments(&batch, iview->image->samples,
1276 render_area.offset.x,
1277 render_area.offset.y,
1278 render_area.offset.x +
1279 render_area.extent.width,
1280 render_area.offset.y +
1281 render_area.extent.height,
1282 clear_depth, clear_stencil,
1283 clear_att.clearValue.
1284 depthStencil.stencil);
1285 }
1286 }
1287
1288 if (!clear_with_hiz) {
1289 clear_depth_stencil_attachment(cmd_buffer, &batch,
1290 &clear_att, 1, &clear_rect);
1291 }
1292
1293 cmd_state->attachments[ds].pending_clear_aspects = 0;
1294 }
1295
1296 blorp_batch_finish(&batch);
1297 }
1298
1299 static void
1300 resolve_image(struct blorp_batch *batch,
1301 const struct anv_image *src_image,
1302 uint32_t src_level, uint32_t src_layer,
1303 const struct anv_image *dst_image,
1304 uint32_t dst_level, uint32_t dst_layer,
1305 VkImageAspectFlags aspect_mask,
1306 uint32_t src_x, uint32_t src_y, uint32_t dst_x, uint32_t dst_y,
1307 uint32_t width, uint32_t height)
1308 {
1309 assert(src_image->type == VK_IMAGE_TYPE_2D);
1310 assert(src_image->samples > 1);
1311 assert(dst_image->type == VK_IMAGE_TYPE_2D);
1312 assert(dst_image->samples == 1);
1313
1314 uint32_t a;
1315 for_each_bit(a, aspect_mask) {
1316 VkImageAspectFlagBits aspect = 1 << a;
1317
1318 struct blorp_surf src_surf, dst_surf;
1319 get_blorp_surf_for_anv_image(src_image, aspect,
1320 src_image->aux_usage, &src_surf);
1321 get_blorp_surf_for_anv_image(dst_image, aspect,
1322 dst_image->aux_usage, &dst_surf);
1323
1324 blorp_blit(batch,
1325 &src_surf, src_level, src_layer,
1326 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1327 &dst_surf, dst_level, dst_layer,
1328 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1329 src_x, src_y, src_x + width, src_y + height,
1330 dst_x, dst_y, dst_x + width, dst_y + height,
1331 0x2600 /* GL_NEAREST */, false, false);
1332 }
1333 }
1334
1335 void anv_CmdResolveImage(
1336 VkCommandBuffer commandBuffer,
1337 VkImage srcImage,
1338 VkImageLayout srcImageLayout,
1339 VkImage dstImage,
1340 VkImageLayout dstImageLayout,
1341 uint32_t regionCount,
1342 const VkImageResolve* pRegions)
1343 {
1344 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1345 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
1346 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
1347
1348 struct blorp_batch batch;
1349 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1350
1351 for (uint32_t r = 0; r < regionCount; r++) {
1352 assert(pRegions[r].srcSubresource.aspectMask ==
1353 pRegions[r].dstSubresource.aspectMask);
1354 assert(anv_get_layerCount(src_image, &pRegions[r].srcSubresource) ==
1355 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource));
1356
1357 const uint32_t layer_count =
1358 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
1359
1360 for (uint32_t layer = 0; layer < layer_count; layer++) {
1361 resolve_image(&batch,
1362 src_image, pRegions[r].srcSubresource.mipLevel,
1363 pRegions[r].srcSubresource.baseArrayLayer + layer,
1364 dst_image, pRegions[r].dstSubresource.mipLevel,
1365 pRegions[r].dstSubresource.baseArrayLayer + layer,
1366 pRegions[r].dstSubresource.aspectMask,
1367 pRegions[r].srcOffset.x, pRegions[r].srcOffset.y,
1368 pRegions[r].dstOffset.x, pRegions[r].dstOffset.y,
1369 pRegions[r].extent.width, pRegions[r].extent.height);
1370 }
1371 }
1372
1373 blorp_batch_finish(&batch);
1374 }
1375
1376 static void
1377 ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
1378 struct blorp_batch *batch,
1379 uint32_t att)
1380 {
1381 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1382 struct anv_attachment_state *att_state =
1383 &cmd_buffer->state.attachments[att];
1384
1385 if (att_state->aux_usage == ISL_AUX_USAGE_NONE ||
1386 att_state->aux_usage == ISL_AUX_USAGE_MCS)
1387 return; /* Nothing to resolve */
1388
1389 assert(att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
1390 att_state->aux_usage == ISL_AUX_USAGE_CCS_D);
1391
1392 struct anv_render_pass *pass = cmd_buffer->state.pass;
1393 const uint32_t subpass_idx = anv_get_subpass_id(&cmd_buffer->state);
1394
1395 /* Scan forward to see what all ways this attachment will be used.
1396 * Ideally, we would like to resolve in the same subpass as the last write
1397 * of a particular attachment. That way we only resolve once but it's
1398 * still hot in the cache.
1399 */
1400 bool found_draw = false;
1401 enum anv_subpass_usage usage = 0;
1402 for (uint32_t s = subpass_idx + 1; s < pass->subpass_count; s++) {
1403 usage |= pass->attachments[att].subpass_usage[s];
1404
1405 if (usage & (ANV_SUBPASS_USAGE_DRAW | ANV_SUBPASS_USAGE_RESOLVE_DST)) {
1406 /* We found another subpass that draws to this attachment. We'll
1407 * wait to resolve until then.
1408 */
1409 found_draw = true;
1410 break;
1411 }
1412 }
1413
1414 struct anv_image_view *iview = fb->attachments[att];
1415 const struct anv_image *image = iview->image;
1416 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1417
1418 enum blorp_fast_clear_op resolve_op = BLORP_FAST_CLEAR_OP_NONE;
1419 if (!found_draw) {
1420 /* This is the last subpass that writes to this attachment so we need to
1421 * resolve here. Ideally, we would like to only resolve if the storeOp
1422 * is set to VK_ATTACHMENT_STORE_OP_STORE. However, we need to ensure
1423 * that the CCS bits are set to "resolved" because there may be copy or
1424 * blit operations (which may ignore CCS) between now and the next time
1425 * we render and we need to ensure that anything they write will be
1426 * respected in the next render. Unfortunately, the hardware does not
1427 * provide us with any sort of "invalidate" pass that sets the CCS to
1428 * "resolved" without writing to the render target.
1429 */
1430 if (iview->image->aux_usage != ISL_AUX_USAGE_CCS_E) {
1431 /* The image destination surface doesn't support compression outside
1432 * the render pass. We need a full resolve.
1433 */
1434 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
1435 } else if (att_state->fast_clear) {
1436 /* We don't know what to do with clear colors outside the render
1437 * pass. We need a partial resolve. Only transparent black is
1438 * built into the surface state object and thus no resolve is
1439 * required for this case.
1440 */
1441 if (att_state->clear_value.color.uint32[0] ||
1442 att_state->clear_value.color.uint32[1] ||
1443 att_state->clear_value.color.uint32[2] ||
1444 att_state->clear_value.color.uint32[3])
1445 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
1446 } else {
1447 /* The image "natively" supports all the compression we care about
1448 * and we don't need to resolve at all. If this is the case, we also
1449 * don't need to resolve for any of the input attachment cases below.
1450 */
1451 }
1452 } else if (usage & ANV_SUBPASS_USAGE_INPUT) {
1453 /* Input attachments are clear-color aware so, at least on Sky Lake, we
1454 * can frequently sample from them with no resolves at all.
1455 */
1456 if (att_state->aux_usage != att_state->input_aux_usage) {
1457 assert(att_state->input_aux_usage == ISL_AUX_USAGE_NONE);
1458 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
1459 } else if (!att_state->clear_color_is_zero_one) {
1460 /* Sky Lake PRM, Vol. 2d, RENDER_SURFACE_STATE::Red Clear Color:
1461 *
1462 * "If Number of Multisamples is MULTISAMPLECOUNT_1 AND if this RT
1463 * is fast cleared with non-0/1 clear value, this RT must be
1464 * partially resolved (refer to Partial Resolve operation) before
1465 * binding this surface to Sampler."
1466 */
1467 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
1468 }
1469 }
1470
1471 if (resolve_op == BLORP_FAST_CLEAR_OP_NONE)
1472 return;
1473
1474 struct blorp_surf surf;
1475 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1476 att_state->aux_usage, &surf);
1477 if (att_state->fast_clear)
1478 surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
1479
1480 /* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
1481 *
1482 * "When performing a render target resolve, PIPE_CONTROL with end of
1483 * pipe sync must be delivered."
1484 *
1485 * This comment is a bit cryptic and doesn't really tell you what's going
1486 * or what's really needed. It appears that fast clear ops are not
1487 * properly synchronized with other drawing. We need to use a PIPE_CONTROL
1488 * to ensure that the contents of the previous draw hit the render target
1489 * before we resolve and then use a second PIPE_CONTROL after the resolve
1490 * to ensure that it is completed before any additional drawing occurs.
1491 */
1492 cmd_buffer->state.pending_pipe_bits |=
1493 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1494
1495 for (uint32_t layer = 0; layer < fb->layers; layer++) {
1496 blorp_ccs_resolve(batch, &surf,
1497 iview->isl.base_level,
1498 iview->isl.base_array_layer + layer,
1499 iview->isl.format, resolve_op);
1500 }
1501
1502 cmd_buffer->state.pending_pipe_bits |=
1503 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1504
1505 /* Once we've done any sort of resolve, we're no longer fast-cleared */
1506 att_state->fast_clear = false;
1507 if (att_state->aux_usage == ISL_AUX_USAGE_CCS_D)
1508 att_state->aux_usage = ISL_AUX_USAGE_NONE;
1509 }
1510
1511 void
1512 anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer)
1513 {
1514 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1515 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1516
1517
1518 struct blorp_batch batch;
1519 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1520
1521 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1522 const uint32_t att = subpass->color_attachments[i].attachment;
1523 if (att == VK_ATTACHMENT_UNUSED)
1524 continue;
1525
1526 assert(att < cmd_buffer->state.pass->attachment_count);
1527 ccs_resolve_attachment(cmd_buffer, &batch, att);
1528 }
1529
1530 if (subpass->has_resolve) {
1531 /* We are about to do some MSAA resolves. We need to flush so that the
1532 * result of writes to the MSAA color attachments show up in the sampler
1533 * when we blit to the single-sampled resolve target.
1534 */
1535 cmd_buffer->state.pending_pipe_bits |=
1536 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
1537 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1538
1539 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1540 uint32_t src_att = subpass->color_attachments[i].attachment;
1541 uint32_t dst_att = subpass->resolve_attachments[i].attachment;
1542
1543 if (dst_att == VK_ATTACHMENT_UNUSED)
1544 continue;
1545
1546 assert(src_att < cmd_buffer->state.pass->attachment_count);
1547 assert(dst_att < cmd_buffer->state.pass->attachment_count);
1548
1549 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
1550 /* From the Vulkan 1.0 spec:
1551 *
1552 * If the first use of an attachment in a render pass is as a
1553 * resolve attachment, then the loadOp is effectively ignored
1554 * as the resolve is guaranteed to overwrite all pixels in the
1555 * render area.
1556 */
1557 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
1558 }
1559
1560 struct anv_image_view *src_iview = fb->attachments[src_att];
1561 struct anv_image_view *dst_iview = fb->attachments[dst_att];
1562
1563 const VkRect2D render_area = cmd_buffer->state.render_area;
1564
1565 assert(src_iview->aspect_mask == dst_iview->aspect_mask);
1566 resolve_image(&batch, src_iview->image,
1567 src_iview->isl.base_level,
1568 src_iview->isl.base_array_layer,
1569 dst_iview->image,
1570 dst_iview->isl.base_level,
1571 dst_iview->isl.base_array_layer,
1572 src_iview->aspect_mask,
1573 render_area.offset.x, render_area.offset.y,
1574 render_area.offset.x, render_area.offset.y,
1575 render_area.extent.width, render_area.extent.height);
1576
1577 ccs_resolve_attachment(cmd_buffer, &batch, dst_att);
1578 }
1579 }
1580
1581 blorp_batch_finish(&batch);
1582 }
1583
1584 void
1585 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
1586 const struct anv_image *image,
1587 enum blorp_hiz_op op)
1588 {
1589 assert(image);
1590
1591 /* Don't resolve depth buffers without an auxiliary HiZ buffer and
1592 * don't perform such a resolve on gens that don't support it.
1593 */
1594 if (cmd_buffer->device->info.gen < 8 ||
1595 image->aux_usage != ISL_AUX_USAGE_HIZ)
1596 return;
1597
1598 assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
1599 op == BLORP_HIZ_OP_DEPTH_RESOLVE);
1600
1601 struct blorp_batch batch;
1602 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1603
1604 struct blorp_surf surf;
1605 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
1606 ISL_AUX_USAGE_NONE, &surf);
1607
1608 /* Manually add the aux HiZ surf */
1609 surf.aux_surf = &image->aux_surface.isl,
1610 surf.aux_addr = (struct blorp_address) {
1611 .buffer = image->bo,
1612 .offset = image->offset + image->aux_surface.offset,
1613 };
1614 surf.aux_usage = ISL_AUX_USAGE_HIZ;
1615
1616 surf.clear_color.u32[0] = (uint32_t) ANV_HZ_FC_VAL;
1617
1618 blorp_gen6_hiz_op(&batch, &surf, 0, 0, op);
1619 blorp_batch_finish(&batch);
1620 }