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blorp: Turn anv_CmdCopyBuffer into a blorp_buffer_copy() helper.
[mesa.git] / src / intel / vulkan / anv_blorp.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_private.h"
25
26 static bool
27 lookup_blorp_shader(struct blorp_context *blorp,
28 const void *key, uint32_t key_size,
29 uint32_t *kernel_out, void *prog_data_out)
30 {
31 struct anv_device *device = blorp->driver_ctx;
32
33 /* The blorp cache must be a real cache */
34 assert(device->blorp_shader_cache.cache);
35
36 struct anv_shader_bin *bin =
37 anv_pipeline_cache_search(&device->blorp_shader_cache, key, key_size);
38 if (!bin)
39 return false;
40
41 /* The cache already has a reference and it's not going anywhere so there
42 * is no need to hold a second reference.
43 */
44 anv_shader_bin_unref(device, bin);
45
46 *kernel_out = bin->kernel.offset;
47 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
48
49 return true;
50 }
51
52 static bool
53 upload_blorp_shader(struct blorp_context *blorp,
54 const void *key, uint32_t key_size,
55 const void *kernel, uint32_t kernel_size,
56 const struct brw_stage_prog_data *prog_data,
57 uint32_t prog_data_size,
58 uint32_t *kernel_out, void *prog_data_out)
59 {
60 struct anv_device *device = blorp->driver_ctx;
61
62 /* The blorp cache must be a real cache */
63 assert(device->blorp_shader_cache.cache);
64
65 struct anv_pipeline_bind_map bind_map = {
66 .surface_count = 0,
67 .sampler_count = 0,
68 };
69
70 struct anv_shader_bin *bin =
71 anv_pipeline_cache_upload_kernel(&device->blorp_shader_cache,
72 key, key_size, kernel, kernel_size,
73 prog_data, prog_data_size, &bind_map);
74
75 if (!bin)
76 return false;
77
78 /* The cache already has a reference and it's not going anywhere so there
79 * is no need to hold a second reference.
80 */
81 anv_shader_bin_unref(device, bin);
82
83 *kernel_out = bin->kernel.offset;
84 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
85
86 return true;
87 }
88
89 void
90 anv_device_init_blorp(struct anv_device *device)
91 {
92 anv_pipeline_cache_init(&device->blorp_shader_cache, device, true);
93 blorp_init(&device->blorp, device, &device->isl_dev);
94 device->blorp.compiler = device->instance->physicalDevice.compiler;
95 device->blorp.mocs.tex = device->default_mocs;
96 device->blorp.mocs.rb = device->default_mocs;
97 device->blorp.mocs.vb = device->default_mocs;
98 device->blorp.lookup_shader = lookup_blorp_shader;
99 device->blorp.upload_shader = upload_blorp_shader;
100 switch (device->info.gen) {
101 case 7:
102 if (device->info.is_haswell) {
103 device->blorp.exec = gen75_blorp_exec;
104 } else {
105 device->blorp.exec = gen7_blorp_exec;
106 }
107 break;
108 case 8:
109 device->blorp.exec = gen8_blorp_exec;
110 break;
111 case 9:
112 device->blorp.exec = gen9_blorp_exec;
113 break;
114 case 10:
115 device->blorp.exec = gen10_blorp_exec;
116 break;
117 default:
118 unreachable("Unknown hardware generation");
119 }
120 }
121
122 void
123 anv_device_finish_blorp(struct anv_device *device)
124 {
125 blorp_finish(&device->blorp);
126 anv_pipeline_cache_finish(&device->blorp_shader_cache);
127 }
128
129 static void
130 get_blorp_surf_for_anv_buffer(struct anv_device *device,
131 struct anv_buffer *buffer, uint64_t offset,
132 uint32_t width, uint32_t height,
133 uint32_t row_pitch, enum isl_format format,
134 struct blorp_surf *blorp_surf,
135 struct isl_surf *isl_surf)
136 {
137 const struct isl_format_layout *fmtl =
138 isl_format_get_layout(format);
139 bool ok UNUSED;
140
141 /* ASTC is the only format which doesn't support linear layouts.
142 * Create an equivalently sized surface with ISL to get around this.
143 */
144 if (fmtl->txc == ISL_TXC_ASTC) {
145 /* Use an equivalently sized format */
146 format = ISL_FORMAT_R32G32B32A32_UINT;
147 assert(fmtl->bpb == isl_format_get_layout(format)->bpb);
148
149 /* Shrink the dimensions for the new format */
150 width = DIV_ROUND_UP(width, fmtl->bw);
151 height = DIV_ROUND_UP(height, fmtl->bh);
152 }
153
154 *blorp_surf = (struct blorp_surf) {
155 .surf = isl_surf,
156 .addr = {
157 .buffer = buffer->bo,
158 .offset = buffer->offset + offset,
159 },
160 };
161
162 ok = isl_surf_init(&device->isl_dev, isl_surf,
163 .dim = ISL_SURF_DIM_2D,
164 .format = format,
165 .width = width,
166 .height = height,
167 .depth = 1,
168 .levels = 1,
169 .array_len = 1,
170 .samples = 1,
171 .row_pitch = row_pitch,
172 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
173 ISL_SURF_USAGE_RENDER_TARGET_BIT,
174 .tiling_flags = ISL_TILING_LINEAR_BIT);
175 assert(ok);
176 }
177
178 static void
179 get_blorp_surf_for_anv_image(const struct anv_image *image,
180 VkImageAspectFlags aspect,
181 enum isl_aux_usage aux_usage,
182 struct blorp_surf *blorp_surf)
183 {
184 if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT ||
185 aux_usage == ISL_AUX_USAGE_HIZ)
186 aux_usage = ISL_AUX_USAGE_NONE;
187
188 const struct anv_surface *surface =
189 anv_image_get_surface_for_aspect_mask(image, aspect);
190
191 *blorp_surf = (struct blorp_surf) {
192 .surf = &surface->isl,
193 .addr = {
194 .buffer = image->bo,
195 .offset = image->offset + surface->offset,
196 },
197 };
198
199 if (aux_usage != ISL_AUX_USAGE_NONE) {
200 blorp_surf->aux_surf = &image->aux_surface.isl,
201 blorp_surf->aux_addr = (struct blorp_address) {
202 .buffer = image->bo,
203 .offset = image->offset + image->aux_surface.offset,
204 };
205 blorp_surf->aux_usage = aux_usage;
206 }
207 }
208
209 void anv_CmdCopyImage(
210 VkCommandBuffer commandBuffer,
211 VkImage srcImage,
212 VkImageLayout srcImageLayout,
213 VkImage dstImage,
214 VkImageLayout dstImageLayout,
215 uint32_t regionCount,
216 const VkImageCopy* pRegions)
217 {
218 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
219 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
220 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
221
222 struct blorp_batch batch;
223 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
224
225 for (unsigned r = 0; r < regionCount; r++) {
226 VkOffset3D srcOffset =
227 anv_sanitize_image_offset(src_image->type, pRegions[r].srcOffset);
228 VkOffset3D dstOffset =
229 anv_sanitize_image_offset(dst_image->type, pRegions[r].dstOffset);
230 VkExtent3D extent =
231 anv_sanitize_image_extent(src_image->type, pRegions[r].extent);
232
233 unsigned dst_base_layer, layer_count;
234 if (dst_image->type == VK_IMAGE_TYPE_3D) {
235 dst_base_layer = pRegions[r].dstOffset.z;
236 layer_count = pRegions[r].extent.depth;
237 } else {
238 dst_base_layer = pRegions[r].dstSubresource.baseArrayLayer;
239 layer_count =
240 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
241 }
242
243 unsigned src_base_layer;
244 if (src_image->type == VK_IMAGE_TYPE_3D) {
245 src_base_layer = pRegions[r].srcOffset.z;
246 } else {
247 src_base_layer = pRegions[r].srcSubresource.baseArrayLayer;
248 assert(layer_count ==
249 anv_get_layerCount(src_image, &pRegions[r].srcSubresource));
250 }
251
252 assert(pRegions[r].srcSubresource.aspectMask ==
253 pRegions[r].dstSubresource.aspectMask);
254
255 uint32_t a;
256 for_each_bit(a, pRegions[r].dstSubresource.aspectMask) {
257 VkImageAspectFlagBits aspect = (1 << a);
258
259 struct blorp_surf src_surf, dst_surf;
260 get_blorp_surf_for_anv_image(src_image, aspect, src_image->aux_usage,
261 &src_surf);
262 get_blorp_surf_for_anv_image(dst_image, aspect, dst_image->aux_usage,
263 &dst_surf);
264
265 for (unsigned i = 0; i < layer_count; i++) {
266 blorp_copy(&batch, &src_surf, pRegions[r].srcSubresource.mipLevel,
267 src_base_layer + i,
268 &dst_surf, pRegions[r].dstSubresource.mipLevel,
269 dst_base_layer + i,
270 srcOffset.x, srcOffset.y,
271 dstOffset.x, dstOffset.y,
272 extent.width, extent.height);
273 }
274 }
275 }
276
277 blorp_batch_finish(&batch);
278 }
279
280 static void
281 copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
282 struct anv_buffer *anv_buffer,
283 struct anv_image *anv_image,
284 uint32_t regionCount,
285 const VkBufferImageCopy* pRegions,
286 bool buffer_to_image)
287 {
288 struct blorp_batch batch;
289 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
290
291 struct {
292 struct blorp_surf surf;
293 uint32_t level;
294 VkOffset3D offset;
295 } image, buffer, *src, *dst;
296
297 buffer.level = 0;
298 buffer.offset = (VkOffset3D) { 0, 0, 0 };
299
300 if (buffer_to_image) {
301 src = &buffer;
302 dst = &image;
303 } else {
304 src = &image;
305 dst = &buffer;
306 }
307
308 for (unsigned r = 0; r < regionCount; r++) {
309 const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
310
311 get_blorp_surf_for_anv_image(anv_image, aspect, anv_image->aux_usage,
312 &image.surf);
313 image.offset =
314 anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
315 image.level = pRegions[r].imageSubresource.mipLevel;
316
317 VkExtent3D extent =
318 anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
319 if (anv_image->type != VK_IMAGE_TYPE_3D) {
320 image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
321 extent.depth =
322 anv_get_layerCount(anv_image, &pRegions[r].imageSubresource);
323 }
324
325 const enum isl_format buffer_format =
326 anv_get_isl_format(&cmd_buffer->device->info, anv_image->vk_format,
327 aspect, VK_IMAGE_TILING_LINEAR);
328
329 const VkExtent3D bufferImageExtent = {
330 .width = pRegions[r].bufferRowLength ?
331 pRegions[r].bufferRowLength : extent.width,
332 .height = pRegions[r].bufferImageHeight ?
333 pRegions[r].bufferImageHeight : extent.height,
334 };
335
336 const struct isl_format_layout *buffer_fmtl =
337 isl_format_get_layout(buffer_format);
338
339 const uint32_t buffer_row_pitch =
340 DIV_ROUND_UP(bufferImageExtent.width, buffer_fmtl->bw) *
341 (buffer_fmtl->bpb / 8);
342
343 const uint32_t buffer_layer_stride =
344 DIV_ROUND_UP(bufferImageExtent.height, buffer_fmtl->bh) *
345 buffer_row_pitch;
346
347 struct isl_surf buffer_isl_surf;
348 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
349 anv_buffer, pRegions[r].bufferOffset,
350 extent.width, extent.height,
351 buffer_row_pitch, buffer_format,
352 &buffer.surf, &buffer_isl_surf);
353
354 for (unsigned z = 0; z < extent.depth; z++) {
355 blorp_copy(&batch, &src->surf, src->level, src->offset.z,
356 &dst->surf, dst->level, dst->offset.z,
357 src->offset.x, src->offset.y, dst->offset.x, dst->offset.y,
358 extent.width, extent.height);
359
360 image.offset.z++;
361 buffer.surf.addr.offset += buffer_layer_stride;
362 }
363 }
364
365 blorp_batch_finish(&batch);
366 }
367
368 void anv_CmdCopyBufferToImage(
369 VkCommandBuffer commandBuffer,
370 VkBuffer srcBuffer,
371 VkImage dstImage,
372 VkImageLayout dstImageLayout,
373 uint32_t regionCount,
374 const VkBufferImageCopy* pRegions)
375 {
376 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
377 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
378 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
379
380 copy_buffer_to_image(cmd_buffer, src_buffer, dst_image,
381 regionCount, pRegions, true);
382 }
383
384 void anv_CmdCopyImageToBuffer(
385 VkCommandBuffer commandBuffer,
386 VkImage srcImage,
387 VkImageLayout srcImageLayout,
388 VkBuffer dstBuffer,
389 uint32_t regionCount,
390 const VkBufferImageCopy* pRegions)
391 {
392 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
393 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
394 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
395
396 copy_buffer_to_image(cmd_buffer, dst_buffer, src_image,
397 regionCount, pRegions, false);
398 }
399
400 static bool
401 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
402 {
403 bool flip = false;
404 if (*src0 > *src1) {
405 unsigned tmp = *src0;
406 *src0 = *src1;
407 *src1 = tmp;
408 flip = !flip;
409 }
410
411 if (*dst0 > *dst1) {
412 unsigned tmp = *dst0;
413 *dst0 = *dst1;
414 *dst1 = tmp;
415 flip = !flip;
416 }
417
418 return flip;
419 }
420
421 void anv_CmdBlitImage(
422 VkCommandBuffer commandBuffer,
423 VkImage srcImage,
424 VkImageLayout srcImageLayout,
425 VkImage dstImage,
426 VkImageLayout dstImageLayout,
427 uint32_t regionCount,
428 const VkImageBlit* pRegions,
429 VkFilter filter)
430
431 {
432 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
433 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
434 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
435
436 struct blorp_surf src, dst;
437
438 uint32_t gl_filter;
439 switch (filter) {
440 case VK_FILTER_NEAREST:
441 gl_filter = 0x2600; /* GL_NEAREST */
442 break;
443 case VK_FILTER_LINEAR:
444 gl_filter = 0x2601; /* GL_LINEAR */
445 break;
446 default:
447 unreachable("Invalid filter");
448 }
449
450 struct blorp_batch batch;
451 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
452
453 for (unsigned r = 0; r < regionCount; r++) {
454 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
455 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
456
457 get_blorp_surf_for_anv_image(src_image, src_res->aspectMask,
458 src_image->aux_usage, &src);
459 get_blorp_surf_for_anv_image(dst_image, dst_res->aspectMask,
460 dst_image->aux_usage, &dst);
461
462 struct anv_format src_format =
463 anv_get_format(&cmd_buffer->device->info, src_image->vk_format,
464 src_res->aspectMask, src_image->tiling);
465 struct anv_format dst_format =
466 anv_get_format(&cmd_buffer->device->info, dst_image->vk_format,
467 dst_res->aspectMask, dst_image->tiling);
468
469 unsigned dst_start, dst_end;
470 if (dst_image->type == VK_IMAGE_TYPE_3D) {
471 assert(dst_res->baseArrayLayer == 0);
472 dst_start = pRegions[r].dstOffsets[0].z;
473 dst_end = pRegions[r].dstOffsets[1].z;
474 } else {
475 dst_start = dst_res->baseArrayLayer;
476 dst_end = dst_start + anv_get_layerCount(dst_image, dst_res);
477 }
478
479 unsigned src_start, src_end;
480 if (src_image->type == VK_IMAGE_TYPE_3D) {
481 assert(src_res->baseArrayLayer == 0);
482 src_start = pRegions[r].srcOffsets[0].z;
483 src_end = pRegions[r].srcOffsets[1].z;
484 } else {
485 src_start = src_res->baseArrayLayer;
486 src_end = src_start + anv_get_layerCount(src_image, src_res);
487 }
488
489 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
490 float src_z_step = (float)(src_end + 1 - src_start) /
491 (float)(dst_end + 1 - dst_start);
492
493 if (flip_z) {
494 src_start = src_end;
495 src_z_step *= -1;
496 }
497
498 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
499 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
500 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
501 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
502 bool flip_x = flip_coords(&src_x0, &src_x1, &dst_x0, &dst_x1);
503
504 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
505 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
506 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
507 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
508 bool flip_y = flip_coords(&src_y0, &src_y1, &dst_y0, &dst_y1);
509
510 const unsigned num_layers = dst_end - dst_start;
511 for (unsigned i = 0; i < num_layers; i++) {
512 unsigned dst_z = dst_start + i;
513 unsigned src_z = src_start + i * src_z_step;
514
515 blorp_blit(&batch, &src, src_res->mipLevel, src_z,
516 src_format.isl_format, src_format.swizzle,
517 &dst, dst_res->mipLevel, dst_z,
518 dst_format.isl_format,
519 anv_swizzle_for_render(dst_format.swizzle),
520 src_x0, src_y0, src_x1, src_y1,
521 dst_x0, dst_y0, dst_x1, dst_y1,
522 gl_filter, flip_x, flip_y);
523 }
524
525 }
526
527 blorp_batch_finish(&batch);
528 }
529
530 static enum isl_format
531 isl_format_for_size(unsigned size_B)
532 {
533 switch (size_B) {
534 case 1: return ISL_FORMAT_R8_UINT;
535 case 2: return ISL_FORMAT_R8G8_UINT;
536 case 4: return ISL_FORMAT_R8G8B8A8_UINT;
537 case 8: return ISL_FORMAT_R16G16B16A16_UINT;
538 case 16: return ISL_FORMAT_R32G32B32A32_UINT;
539 default:
540 unreachable("Not a power-of-two format size");
541 }
542 }
543
544 /**
545 * Returns the greatest common divisor of a and b that is a power of two.
546 */
547 static uint64_t
548 gcd_pow2_u64(uint64_t a, uint64_t b)
549 {
550 assert(a > 0 || b > 0);
551
552 unsigned a_log2 = ffsll(a) - 1;
553 unsigned b_log2 = ffsll(b) - 1;
554
555 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
556 * case, the MIN2() will take the other one. If both are 0 then we will
557 * hit the assert above.
558 */
559 return 1 << MIN2(a_log2, b_log2);
560 }
561
562 /* This is maximum possible width/height our HW can handle */
563 #define MAX_SURFACE_DIM (1ull << 14)
564
565 void anv_CmdCopyBuffer(
566 VkCommandBuffer commandBuffer,
567 VkBuffer srcBuffer,
568 VkBuffer dstBuffer,
569 uint32_t regionCount,
570 const VkBufferCopy* pRegions)
571 {
572 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
573 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
574 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
575
576 struct blorp_batch batch;
577 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
578
579 for (unsigned r = 0; r < regionCount; r++) {
580 struct blorp_address src = {
581 .buffer = src_buffer->bo,
582 .offset = src_buffer->offset + pRegions[r].srcOffset,
583 };
584 struct blorp_address dst = {
585 .buffer = dst_buffer->bo,
586 .offset = dst_buffer->offset + pRegions[r].dstOffset,
587 };
588
589 blorp_buffer_copy(&batch, src, dst, pRegions[r].size);
590 }
591
592 blorp_batch_finish(&batch);
593 }
594
595 void anv_CmdUpdateBuffer(
596 VkCommandBuffer commandBuffer,
597 VkBuffer dstBuffer,
598 VkDeviceSize dstOffset,
599 VkDeviceSize dataSize,
600 const void* pData)
601 {
602 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
603 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
604
605 struct blorp_batch batch;
606 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
607
608 /* We can't quite grab a full block because the state stream needs a
609 * little data at the top to build its linked list.
610 */
611 const uint32_t max_update_size =
612 cmd_buffer->device->dynamic_state_pool.block_size - 64;
613
614 assert(max_update_size < MAX_SURFACE_DIM * 4);
615
616 /* We're about to read data that was written from the CPU. Flush the
617 * texture cache so we don't get anything stale.
618 */
619 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
620
621 while (dataSize) {
622 const uint32_t copy_size = MIN2(dataSize, max_update_size);
623
624 struct anv_state tmp_data =
625 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, copy_size, 64);
626
627 memcpy(tmp_data.map, pData, copy_size);
628
629 anv_state_flush(cmd_buffer->device, tmp_data);
630
631 struct blorp_address src = {
632 .buffer = &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
633 .offset = tmp_data.offset,
634 };
635 struct blorp_address dst = {
636 .buffer = dst_buffer->bo,
637 .offset = dst_buffer->offset + dstOffset,
638 };
639
640 blorp_buffer_copy(&batch, src, dst, copy_size);
641
642 dataSize -= copy_size;
643 dstOffset += copy_size;
644 pData = (void *)pData + copy_size;
645 }
646
647 blorp_batch_finish(&batch);
648 }
649
650 void anv_CmdFillBuffer(
651 VkCommandBuffer commandBuffer,
652 VkBuffer dstBuffer,
653 VkDeviceSize dstOffset,
654 VkDeviceSize fillSize,
655 uint32_t data)
656 {
657 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
658 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
659 struct blorp_surf surf;
660 struct isl_surf isl_surf;
661
662 struct blorp_batch batch;
663 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
664
665 fillSize = anv_buffer_get_range(dst_buffer, dstOffset, fillSize);
666
667 /* From the Vulkan spec:
668 *
669 * "size is the number of bytes to fill, and must be either a multiple
670 * of 4, or VK_WHOLE_SIZE to fill the range from offset to the end of
671 * the buffer. If VK_WHOLE_SIZE is used and the remaining size of the
672 * buffer is not a multiple of 4, then the nearest smaller multiple is
673 * used."
674 */
675 fillSize &= ~3ull;
676
677 /* First, we compute the biggest format that can be used with the
678 * given offsets and size.
679 */
680 int bs = 16;
681 bs = gcd_pow2_u64(bs, dstOffset);
682 bs = gcd_pow2_u64(bs, fillSize);
683 enum isl_format isl_format = isl_format_for_size(bs);
684
685 union isl_color_value color = {
686 .u32 = { data, data, data, data },
687 };
688
689 const uint64_t max_fill_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
690 while (fillSize >= max_fill_size) {
691 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
692 dst_buffer, dstOffset,
693 MAX_SURFACE_DIM, MAX_SURFACE_DIM,
694 MAX_SURFACE_DIM * bs, isl_format,
695 &surf, &isl_surf);
696
697 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
698 0, 0, 1, 0, 0, MAX_SURFACE_DIM, MAX_SURFACE_DIM,
699 color, NULL);
700 fillSize -= max_fill_size;
701 dstOffset += max_fill_size;
702 }
703
704 uint64_t height = fillSize / (MAX_SURFACE_DIM * bs);
705 assert(height < MAX_SURFACE_DIM);
706 if (height != 0) {
707 const uint64_t rect_fill_size = height * MAX_SURFACE_DIM * bs;
708 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
709 dst_buffer, dstOffset,
710 MAX_SURFACE_DIM, height,
711 MAX_SURFACE_DIM * bs, isl_format,
712 &surf, &isl_surf);
713
714 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
715 0, 0, 1, 0, 0, MAX_SURFACE_DIM, height,
716 color, NULL);
717 fillSize -= rect_fill_size;
718 dstOffset += rect_fill_size;
719 }
720
721 if (fillSize != 0) {
722 const uint32_t width = fillSize / bs;
723 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
724 dst_buffer, dstOffset,
725 width, 1,
726 width * bs, isl_format,
727 &surf, &isl_surf);
728
729 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
730 0, 0, 1, 0, 0, width, 1,
731 color, NULL);
732 }
733
734 blorp_batch_finish(&batch);
735 }
736
737 void anv_CmdClearColorImage(
738 VkCommandBuffer commandBuffer,
739 VkImage _image,
740 VkImageLayout imageLayout,
741 const VkClearColorValue* pColor,
742 uint32_t rangeCount,
743 const VkImageSubresourceRange* pRanges)
744 {
745 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
746 ANV_FROM_HANDLE(anv_image, image, _image);
747
748 static const bool color_write_disable[4] = { false, false, false, false };
749
750 struct blorp_batch batch;
751 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
752
753 struct blorp_surf surf;
754 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
755 image->aux_usage, &surf);
756
757 for (unsigned r = 0; r < rangeCount; r++) {
758 if (pRanges[r].aspectMask == 0)
759 continue;
760
761 assert(pRanges[r].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
762
763 struct anv_format src_format =
764 anv_get_format(&cmd_buffer->device->info, image->vk_format,
765 VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
766
767 unsigned base_layer = pRanges[r].baseArrayLayer;
768 unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
769
770 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
771 const unsigned level = pRanges[r].baseMipLevel + i;
772 const unsigned level_width = anv_minify(image->extent.width, level);
773 const unsigned level_height = anv_minify(image->extent.height, level);
774
775 if (image->type == VK_IMAGE_TYPE_3D) {
776 base_layer = 0;
777 layer_count = anv_minify(image->extent.depth, level);
778 }
779
780 blorp_clear(&batch, &surf,
781 src_format.isl_format, src_format.swizzle,
782 level, base_layer, layer_count,
783 0, 0, level_width, level_height,
784 vk_to_isl_color(*pColor), color_write_disable);
785 }
786 }
787
788 blorp_batch_finish(&batch);
789 }
790
791 void anv_CmdClearDepthStencilImage(
792 VkCommandBuffer commandBuffer,
793 VkImage image_h,
794 VkImageLayout imageLayout,
795 const VkClearDepthStencilValue* pDepthStencil,
796 uint32_t rangeCount,
797 const VkImageSubresourceRange* pRanges)
798 {
799 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
800 ANV_FROM_HANDLE(anv_image, image, image_h);
801
802 struct blorp_batch batch;
803 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
804
805 struct blorp_surf depth, stencil;
806 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
807 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
808 ISL_AUX_USAGE_NONE, &depth);
809 } else {
810 memset(&depth, 0, sizeof(depth));
811 }
812
813 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
814 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_STENCIL_BIT,
815 ISL_AUX_USAGE_NONE, &stencil);
816 } else {
817 memset(&stencil, 0, sizeof(stencil));
818 }
819
820 for (unsigned r = 0; r < rangeCount; r++) {
821 if (pRanges[r].aspectMask == 0)
822 continue;
823
824 bool clear_depth = pRanges[r].aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
825 bool clear_stencil = pRanges[r].aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
826
827 unsigned base_layer = pRanges[r].baseArrayLayer;
828 unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
829
830 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
831 const unsigned level = pRanges[r].baseMipLevel + i;
832 const unsigned level_width = anv_minify(image->extent.width, level);
833 const unsigned level_height = anv_minify(image->extent.height, level);
834
835 if (image->type == VK_IMAGE_TYPE_3D)
836 layer_count = anv_minify(image->extent.depth, level);
837
838 blorp_clear_depth_stencil(&batch, &depth, &stencil,
839 level, base_layer, layer_count,
840 0, 0, level_width, level_height,
841 clear_depth, pDepthStencil->depth,
842 clear_stencil ? 0xff : 0,
843 pDepthStencil->stencil);
844 }
845 }
846
847 blorp_batch_finish(&batch);
848 }
849
850 VkResult
851 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
852 uint32_t num_entries,
853 uint32_t *state_offset,
854 struct anv_state *bt_state)
855 {
856 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
857 state_offset);
858 if (bt_state->map == NULL) {
859 /* We ran out of space. Grab a new binding table block. */
860 VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
861 if (result != VK_SUCCESS)
862 return result;
863
864 /* Re-emit state base addresses so we get the new surface state base
865 * address before we start emitting binding tables etc.
866 */
867 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
868
869 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
870 state_offset);
871 assert(bt_state->map != NULL);
872 }
873
874 return VK_SUCCESS;
875 }
876
877 static VkResult
878 binding_table_for_surface_state(struct anv_cmd_buffer *cmd_buffer,
879 struct anv_state surface_state,
880 uint32_t *bt_offset)
881 {
882 uint32_t state_offset;
883 struct anv_state bt_state;
884
885 VkResult result =
886 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset,
887 &bt_state);
888 if (result != VK_SUCCESS)
889 return result;
890
891 uint32_t *bt_map = bt_state.map;
892 bt_map[0] = surface_state.offset + state_offset;
893
894 *bt_offset = bt_state.offset;
895 return VK_SUCCESS;
896 }
897
898 static void
899 clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
900 struct blorp_batch *batch,
901 const VkClearAttachment *attachment,
902 uint32_t rectCount, const VkClearRect *pRects)
903 {
904 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
905 const uint32_t color_att = attachment->colorAttachment;
906 const uint32_t att_idx = subpass->color_attachments[color_att].attachment;
907
908 if (att_idx == VK_ATTACHMENT_UNUSED)
909 return;
910
911 struct anv_render_pass_attachment *pass_att =
912 &cmd_buffer->state.pass->attachments[att_idx];
913 struct anv_attachment_state *att_state =
914 &cmd_buffer->state.attachments[att_idx];
915
916 uint32_t binding_table;
917 VkResult result =
918 binding_table_for_surface_state(cmd_buffer, att_state->color_rt_state,
919 &binding_table);
920 if (result != VK_SUCCESS)
921 return;
922
923 union isl_color_value clear_color =
924 vk_to_isl_color(attachment->clearValue.color);
925
926 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
927 if (subpass->view_mask) {
928 uint32_t view_idx;
929 for_each_bit(view_idx, subpass->view_mask) {
930 for (uint32_t r = 0; r < rectCount; ++r) {
931 const VkOffset2D offset = pRects[r].rect.offset;
932 const VkExtent2D extent = pRects[r].rect.extent;
933 blorp_clear_attachments(batch, binding_table,
934 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
935 view_idx, 1,
936 offset.x, offset.y,
937 offset.x + extent.width,
938 offset.y + extent.height,
939 true, clear_color, false, 0.0f, 0, 0);
940 }
941 }
942 return;
943 }
944
945 for (uint32_t r = 0; r < rectCount; ++r) {
946 const VkOffset2D offset = pRects[r].rect.offset;
947 const VkExtent2D extent = pRects[r].rect.extent;
948 blorp_clear_attachments(batch, binding_table,
949 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
950 pRects[r].baseArrayLayer,
951 pRects[r].layerCount,
952 offset.x, offset.y,
953 offset.x + extent.width, offset.y + extent.height,
954 true, clear_color, false, 0.0f, 0, 0);
955 }
956 }
957
958 static void
959 clear_depth_stencil_attachment(struct anv_cmd_buffer *cmd_buffer,
960 struct blorp_batch *batch,
961 const VkClearAttachment *attachment,
962 uint32_t rectCount, const VkClearRect *pRects)
963 {
964 static const union isl_color_value color_value = { .u32 = { 0, } };
965 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
966 const uint32_t att_idx = subpass->depth_stencil_attachment.attachment;
967
968 if (att_idx == VK_ATTACHMENT_UNUSED)
969 return;
970
971 struct anv_render_pass_attachment *pass_att =
972 &cmd_buffer->state.pass->attachments[att_idx];
973
974 bool clear_depth = attachment->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
975 bool clear_stencil = attachment->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
976
977 enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
978 if (clear_depth) {
979 depth_format = anv_get_isl_format(&cmd_buffer->device->info,
980 pass_att->format,
981 VK_IMAGE_ASPECT_DEPTH_BIT,
982 VK_IMAGE_TILING_OPTIMAL);
983 }
984
985 uint32_t binding_table;
986 VkResult result =
987 binding_table_for_surface_state(cmd_buffer,
988 cmd_buffer->state.null_surface_state,
989 &binding_table);
990 if (result != VK_SUCCESS)
991 return;
992
993 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
994 if (subpass->view_mask) {
995 uint32_t view_idx;
996 for_each_bit(view_idx, subpass->view_mask) {
997 for (uint32_t r = 0; r < rectCount; ++r) {
998 const VkOffset2D offset = pRects[r].rect.offset;
999 const VkExtent2D extent = pRects[r].rect.extent;
1000 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1001 blorp_clear_attachments(batch, binding_table,
1002 depth_format, pass_att->samples,
1003 view_idx, 1,
1004 offset.x, offset.y,
1005 offset.x + extent.width,
1006 offset.y + extent.height,
1007 false, color_value,
1008 clear_depth, value.depth,
1009 clear_stencil ? 0xff : 0, value.stencil);
1010 }
1011 }
1012 return;
1013 }
1014
1015 for (uint32_t r = 0; r < rectCount; ++r) {
1016 const VkOffset2D offset = pRects[r].rect.offset;
1017 const VkExtent2D extent = pRects[r].rect.extent;
1018 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1019 blorp_clear_attachments(batch, binding_table,
1020 depth_format, pass_att->samples,
1021 pRects[r].baseArrayLayer,
1022 pRects[r].layerCount,
1023 offset.x, offset.y,
1024 offset.x + extent.width, offset.y + extent.height,
1025 false, color_value,
1026 clear_depth, value.depth,
1027 clear_stencil ? 0xff : 0, value.stencil);
1028 }
1029 }
1030
1031 void anv_CmdClearAttachments(
1032 VkCommandBuffer commandBuffer,
1033 uint32_t attachmentCount,
1034 const VkClearAttachment* pAttachments,
1035 uint32_t rectCount,
1036 const VkClearRect* pRects)
1037 {
1038 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1039
1040 /* Because this gets called within a render pass, we tell blorp not to
1041 * trash our depth and stencil buffers.
1042 */
1043 struct blorp_batch batch;
1044 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1045 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1046
1047 for (uint32_t a = 0; a < attachmentCount; ++a) {
1048 if (pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
1049 clear_color_attachment(cmd_buffer, &batch,
1050 &pAttachments[a],
1051 rectCount, pRects);
1052 } else {
1053 clear_depth_stencil_attachment(cmd_buffer, &batch,
1054 &pAttachments[a],
1055 rectCount, pRects);
1056 }
1057 }
1058
1059 blorp_batch_finish(&batch);
1060 }
1061
1062 enum subpass_stage {
1063 SUBPASS_STAGE_LOAD,
1064 SUBPASS_STAGE_DRAW,
1065 SUBPASS_STAGE_RESOLVE,
1066 };
1067
1068 static bool
1069 subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer)
1070 {
1071 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1072 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1073
1074 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1075 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1076 if (a == VK_ATTACHMENT_UNUSED)
1077 continue;
1078
1079 assert(a < cmd_state->pass->attachment_count);
1080 if (cmd_state->attachments[a].pending_clear_aspects) {
1081 return true;
1082 }
1083 }
1084
1085 if (ds != VK_ATTACHMENT_UNUSED) {
1086 assert(ds < cmd_state->pass->attachment_count);
1087 if (cmd_state->attachments[ds].pending_clear_aspects)
1088 return true;
1089 }
1090
1091 return false;
1092 }
1093
1094 void
1095 anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
1096 {
1097 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1098 const VkRect2D render_area = cmd_buffer->state.render_area;
1099
1100
1101 if (!subpass_needs_clear(cmd_buffer))
1102 return;
1103
1104 /* Because this gets called within a render pass, we tell blorp not to
1105 * trash our depth and stencil buffers.
1106 */
1107 struct blorp_batch batch;
1108 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1109 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1110
1111 VkClearRect clear_rect = {
1112 .rect = cmd_buffer->state.render_area,
1113 .baseArrayLayer = 0,
1114 .layerCount = cmd_buffer->state.framebuffer->layers,
1115 };
1116
1117 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1118 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1119 const uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1120 if (a == VK_ATTACHMENT_UNUSED)
1121 continue;
1122
1123 assert(a < cmd_state->pass->attachment_count);
1124 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
1125
1126 if (!att_state->pending_clear_aspects)
1127 continue;
1128
1129 assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1130
1131 struct anv_image_view *iview = fb->attachments[a];
1132 const struct anv_image *image = iview->image;
1133 struct blorp_surf surf;
1134 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1135 att_state->aux_usage, &surf);
1136
1137 if (att_state->fast_clear) {
1138 surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
1139
1140 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1141 *
1142 * "After Render target fast clear, pipe-control with color cache
1143 * write-flush must be issued before sending any DRAW commands on
1144 * that render target."
1145 *
1146 * This comment is a bit cryptic and doesn't really tell you what's
1147 * going or what's really needed. It appears that fast clear ops are
1148 * not properly synchronized with other drawing. This means that we
1149 * cannot have a fast clear operation in the pipe at the same time as
1150 * other regular drawing operations. We need to use a PIPE_CONTROL
1151 * to ensure that the contents of the previous draw hit the render
1152 * target before we resolve and then use a second PIPE_CONTROL after
1153 * the resolve to ensure that it is completed before any additional
1154 * drawing occurs.
1155 */
1156 cmd_buffer->state.pending_pipe_bits |=
1157 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1158
1159 blorp_fast_clear(&batch, &surf, iview->isl.format,
1160 iview->isl.base_level,
1161 iview->isl.base_array_layer, fb->layers,
1162 render_area.offset.x, render_area.offset.y,
1163 render_area.offset.x + render_area.extent.width,
1164 render_area.offset.y + render_area.extent.height);
1165
1166 cmd_buffer->state.pending_pipe_bits |=
1167 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1168 } else {
1169 blorp_clear(&batch, &surf, iview->isl.format,
1170 anv_swizzle_for_render(iview->isl.swizzle),
1171 iview->isl.base_level,
1172 iview->isl.base_array_layer, fb->layers,
1173 render_area.offset.x, render_area.offset.y,
1174 render_area.offset.x + render_area.extent.width,
1175 render_area.offset.y + render_area.extent.height,
1176 vk_to_isl_color(att_state->clear_value.color), NULL);
1177 }
1178
1179 att_state->pending_clear_aspects = 0;
1180 }
1181
1182 const uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1183 assert(ds == VK_ATTACHMENT_UNUSED || ds < cmd_state->pass->attachment_count);
1184
1185 if (ds != VK_ATTACHMENT_UNUSED &&
1186 cmd_state->attachments[ds].pending_clear_aspects) {
1187
1188 VkClearAttachment clear_att = {
1189 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1190 .clearValue = cmd_state->attachments[ds].clear_value,
1191 };
1192
1193
1194 const uint8_t gen = cmd_buffer->device->info.gen;
1195 bool clear_with_hiz = gen >= 8 && cmd_state->attachments[ds].aux_usage ==
1196 ISL_AUX_USAGE_HIZ;
1197 const struct anv_image_view *iview = fb->attachments[ds];
1198
1199 if (clear_with_hiz) {
1200 const bool clear_depth = clear_att.aspectMask &
1201 VK_IMAGE_ASPECT_DEPTH_BIT;
1202 const bool clear_stencil = clear_att.aspectMask &
1203 VK_IMAGE_ASPECT_STENCIL_BIT;
1204
1205 /* Check against restrictions for depth buffer clearing. A great GPU
1206 * performance benefit isn't expected when using the HZ sequence for
1207 * stencil-only clears. Therefore, we don't emit a HZ op sequence for
1208 * a stencil clear in addition to using the BLORP-fallback for depth.
1209 */
1210 if (clear_depth) {
1211 if (!blorp_can_hiz_clear_depth(gen, iview->isl.format,
1212 iview->image->samples,
1213 render_area.offset.x,
1214 render_area.offset.y,
1215 render_area.offset.x +
1216 render_area.extent.width,
1217 render_area.offset.y +
1218 render_area.extent.height)) {
1219 clear_with_hiz = false;
1220 } else if (clear_att.clearValue.depthStencil.depth !=
1221 ANV_HZ_FC_VAL) {
1222 /* Don't enable fast depth clears for any color not equal to
1223 * ANV_HZ_FC_VAL.
1224 */
1225 clear_with_hiz = false;
1226 } else if (gen == 8 &&
1227 anv_can_sample_with_hiz(&cmd_buffer->device->info,
1228 iview->aspect_mask,
1229 iview->image->samples)) {
1230 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
1231 * fast-cleared portion of a HiZ buffer. Testing has revealed
1232 * that Gen8 only supports returning 0.0f. Gens prior to gen8 do
1233 * not support this feature at all.
1234 */
1235 clear_with_hiz = false;
1236 }
1237 }
1238
1239 if (clear_with_hiz) {
1240 blorp_gen8_hiz_clear_attachments(&batch, iview->image->samples,
1241 render_area.offset.x,
1242 render_area.offset.y,
1243 render_area.offset.x +
1244 render_area.extent.width,
1245 render_area.offset.y +
1246 render_area.extent.height,
1247 clear_depth, clear_stencil,
1248 clear_att.clearValue.
1249 depthStencil.stencil);
1250
1251 /* From the SKL PRM, Depth Buffer Clear:
1252 *
1253 * Depth Buffer Clear Workaround
1254 * Depth buffer clear pass using any of the methods (WM_STATE,
1255 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1256 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1257 * “set” before starting to render. DepthStall and DepthFlush are
1258 * not needed between consecutive depth clear passes nor is it
1259 * required if the depth-clear pass was done with “full_surf_clear”
1260 * bit set in the 3DSTATE_WM_HZ_OP.
1261 */
1262 if (clear_depth) {
1263 cmd_buffer->state.pending_pipe_bits |=
1264 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
1265 }
1266 }
1267 }
1268
1269 if (!clear_with_hiz) {
1270 clear_depth_stencil_attachment(cmd_buffer, &batch,
1271 &clear_att, 1, &clear_rect);
1272 }
1273
1274 cmd_state->attachments[ds].pending_clear_aspects = 0;
1275 }
1276
1277 blorp_batch_finish(&batch);
1278 }
1279
1280 static void
1281 resolve_image(struct blorp_batch *batch,
1282 const struct anv_image *src_image,
1283 enum isl_aux_usage src_aux_usage,
1284 uint32_t src_level, uint32_t src_layer,
1285 const struct anv_image *dst_image,
1286 enum isl_aux_usage dst_aux_usage,
1287 uint32_t dst_level, uint32_t dst_layer,
1288 VkImageAspectFlags aspect_mask,
1289 uint32_t src_x, uint32_t src_y, uint32_t dst_x, uint32_t dst_y,
1290 uint32_t width, uint32_t height)
1291 {
1292 assert(src_image->type == VK_IMAGE_TYPE_2D);
1293 assert(src_image->samples > 1);
1294 assert(dst_image->type == VK_IMAGE_TYPE_2D);
1295 assert(dst_image->samples == 1);
1296
1297 uint32_t a;
1298 for_each_bit(a, aspect_mask) {
1299 VkImageAspectFlagBits aspect = 1 << a;
1300
1301 struct blorp_surf src_surf, dst_surf;
1302 get_blorp_surf_for_anv_image(src_image, aspect,
1303 src_aux_usage, &src_surf);
1304 get_blorp_surf_for_anv_image(dst_image, aspect,
1305 dst_aux_usage, &dst_surf);
1306
1307 blorp_blit(batch,
1308 &src_surf, src_level, src_layer,
1309 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1310 &dst_surf, dst_level, dst_layer,
1311 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1312 src_x, src_y, src_x + width, src_y + height,
1313 dst_x, dst_y, dst_x + width, dst_y + height,
1314 0x2600 /* GL_NEAREST */, false, false);
1315 }
1316 }
1317
1318 void anv_CmdResolveImage(
1319 VkCommandBuffer commandBuffer,
1320 VkImage srcImage,
1321 VkImageLayout srcImageLayout,
1322 VkImage dstImage,
1323 VkImageLayout dstImageLayout,
1324 uint32_t regionCount,
1325 const VkImageResolve* pRegions)
1326 {
1327 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1328 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
1329 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
1330
1331 struct blorp_batch batch;
1332 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1333
1334 for (uint32_t r = 0; r < regionCount; r++) {
1335 assert(pRegions[r].srcSubresource.aspectMask ==
1336 pRegions[r].dstSubresource.aspectMask);
1337 assert(anv_get_layerCount(src_image, &pRegions[r].srcSubresource) ==
1338 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource));
1339
1340 const uint32_t layer_count =
1341 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
1342
1343 for (uint32_t layer = 0; layer < layer_count; layer++) {
1344 resolve_image(&batch,
1345 src_image, src_image->aux_usage,
1346 pRegions[r].srcSubresource.mipLevel,
1347 pRegions[r].srcSubresource.baseArrayLayer + layer,
1348 dst_image, dst_image->aux_usage,
1349 pRegions[r].dstSubresource.mipLevel,
1350 pRegions[r].dstSubresource.baseArrayLayer + layer,
1351 pRegions[r].dstSubresource.aspectMask,
1352 pRegions[r].srcOffset.x, pRegions[r].srcOffset.y,
1353 pRegions[r].dstOffset.x, pRegions[r].dstOffset.y,
1354 pRegions[r].extent.width, pRegions[r].extent.height);
1355 }
1356 }
1357
1358 blorp_batch_finish(&batch);
1359 }
1360
1361 void
1362 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
1363 const struct anv_image *image,
1364 const uint32_t base_level, const uint32_t level_count,
1365 const uint32_t base_layer, uint32_t layer_count)
1366 {
1367 assert(image->type == VK_IMAGE_TYPE_3D || image->extent.depth == 1);
1368
1369 if (image->type == VK_IMAGE_TYPE_3D) {
1370 assert(base_layer == 0);
1371 assert(layer_count == anv_minify(image->extent.depth, base_level));
1372 }
1373
1374 struct blorp_batch batch;
1375 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1376
1377 struct blorp_surf surf;
1378 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1379 image->aux_usage == ISL_AUX_USAGE_NONE ?
1380 ISL_AUX_USAGE_CCS_D : image->aux_usage,
1381 &surf);
1382
1383 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1384 *
1385 * "After Render target fast clear, pipe-control with color cache
1386 * write-flush must be issued before sending any DRAW commands on
1387 * that render target."
1388 *
1389 * This comment is a bit cryptic and doesn't really tell you what's going
1390 * or what's really needed. It appears that fast clear ops are not
1391 * properly synchronized with other drawing. This means that we cannot
1392 * have a fast clear operation in the pipe at the same time as other
1393 * regular drawing operations. We need to use a PIPE_CONTROL to ensure
1394 * that the contents of the previous draw hit the render target before we
1395 * resolve and then use a second PIPE_CONTROL after the resolve to ensure
1396 * that it is completed before any additional drawing occurs.
1397 */
1398 cmd_buffer->state.pending_pipe_bits |=
1399 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1400
1401 for (uint32_t l = 0; l < level_count; l++) {
1402 const uint32_t level = base_level + l;
1403
1404 const VkExtent3D extent = {
1405 .width = anv_minify(image->extent.width, level),
1406 .height = anv_minify(image->extent.height, level),
1407 .depth = anv_minify(image->extent.depth, level),
1408 };
1409
1410 if (image->type == VK_IMAGE_TYPE_3D)
1411 layer_count = extent.depth;
1412
1413 assert(level < anv_image_aux_levels(image));
1414 assert(base_layer + layer_count <= anv_image_aux_layers(image, level));
1415 blorp_fast_clear(&batch, &surf, surf.surf->format,
1416 level, base_layer, layer_count,
1417 0, 0, extent.width, extent.height);
1418 }
1419
1420 cmd_buffer->state.pending_pipe_bits |=
1421 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1422 }
1423
1424 void
1425 anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer)
1426 {
1427 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1428 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1429
1430 if (subpass->has_resolve) {
1431 struct blorp_batch batch;
1432 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1433
1434 /* We are about to do some MSAA resolves. We need to flush so that the
1435 * result of writes to the MSAA color attachments show up in the sampler
1436 * when we blit to the single-sampled resolve target.
1437 */
1438 cmd_buffer->state.pending_pipe_bits |=
1439 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
1440 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1441
1442 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1443 uint32_t src_att = subpass->color_attachments[i].attachment;
1444 uint32_t dst_att = subpass->resolve_attachments[i].attachment;
1445
1446 if (dst_att == VK_ATTACHMENT_UNUSED)
1447 continue;
1448
1449 assert(src_att < cmd_buffer->state.pass->attachment_count);
1450 assert(dst_att < cmd_buffer->state.pass->attachment_count);
1451
1452 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
1453 /* From the Vulkan 1.0 spec:
1454 *
1455 * If the first use of an attachment in a render pass is as a
1456 * resolve attachment, then the loadOp is effectively ignored
1457 * as the resolve is guaranteed to overwrite all pixels in the
1458 * render area.
1459 */
1460 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
1461 }
1462
1463 struct anv_image_view *src_iview = fb->attachments[src_att];
1464 struct anv_image_view *dst_iview = fb->attachments[dst_att];
1465
1466 enum isl_aux_usage src_aux_usage =
1467 cmd_buffer->state.attachments[src_att].aux_usage;
1468 enum isl_aux_usage dst_aux_usage =
1469 cmd_buffer->state.attachments[dst_att].aux_usage;
1470
1471 const VkRect2D render_area = cmd_buffer->state.render_area;
1472
1473 assert(src_iview->aspect_mask == dst_iview->aspect_mask);
1474
1475 resolve_image(&batch, src_iview->image, src_aux_usage,
1476 src_iview->isl.base_level,
1477 src_iview->isl.base_array_layer,
1478 dst_iview->image, dst_aux_usage,
1479 dst_iview->isl.base_level,
1480 dst_iview->isl.base_array_layer,
1481 src_iview->aspect_mask,
1482 render_area.offset.x, render_area.offset.y,
1483 render_area.offset.x, render_area.offset.y,
1484 render_area.extent.width, render_area.extent.height);
1485 }
1486
1487 blorp_batch_finish(&batch);
1488 }
1489 }
1490
1491 void
1492 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
1493 const struct anv_image *image,
1494 enum blorp_hiz_op op)
1495 {
1496 assert(image);
1497
1498 /* Don't resolve depth buffers without an auxiliary HiZ buffer and
1499 * don't perform such a resolve on gens that don't support it.
1500 */
1501 if (cmd_buffer->device->info.gen < 8 ||
1502 image->aux_usage != ISL_AUX_USAGE_HIZ)
1503 return;
1504
1505 assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
1506 op == BLORP_HIZ_OP_DEPTH_RESOLVE);
1507
1508 struct blorp_batch batch;
1509 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1510
1511 struct blorp_surf surf;
1512 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
1513 ISL_AUX_USAGE_NONE, &surf);
1514
1515 /* Manually add the aux HiZ surf */
1516 surf.aux_surf = &image->aux_surface.isl,
1517 surf.aux_addr = (struct blorp_address) {
1518 .buffer = image->bo,
1519 .offset = image->offset + image->aux_surface.offset,
1520 };
1521 surf.aux_usage = ISL_AUX_USAGE_HIZ;
1522
1523 surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
1524
1525 blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
1526 blorp_batch_finish(&batch);
1527 }
1528
1529 void
1530 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
1531 const struct anv_state surface_state,
1532 const struct anv_image * const image,
1533 const uint8_t level, const uint32_t layer_count,
1534 const enum blorp_fast_clear_op op)
1535 {
1536 assert(cmd_buffer && image);
1537
1538 /* The resolved subresource range must have a CCS buffer. */
1539 assert(level < anv_image_aux_levels(image));
1540 assert(layer_count <= anv_image_aux_layers(image, level));
1541 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT && image->samples == 1);
1542
1543 /* Create a binding table for this surface state. */
1544 uint32_t binding_table;
1545 VkResult result =
1546 binding_table_for_surface_state(cmd_buffer, surface_state,
1547 &binding_table);
1548 if (result != VK_SUCCESS)
1549 return;
1550
1551 struct blorp_batch batch;
1552 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1553 BLORP_BATCH_PREDICATE_ENABLE);
1554
1555 struct blorp_surf surf;
1556 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1557 image->aux_usage == ISL_AUX_USAGE_CCS_E ?
1558 ISL_AUX_USAGE_CCS_E : ISL_AUX_USAGE_CCS_D,
1559 &surf);
1560
1561 blorp_ccs_resolve_attachment(&batch, binding_table, &surf, level,
1562 layer_count, image->color_surface.isl.format,
1563 op);
1564
1565 blorp_batch_finish(&batch);
1566 }