2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
35 #include "util/u_math.h"
37 #include "vk_format_info.h"
39 static isl_surf_usage_flags_t
40 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
41 VkImageUsageFlags vk_usage
,
42 isl_surf_usage_flags_t isl_extra_usage
,
43 VkImageAspectFlagBits aspect
)
45 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
47 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
48 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
50 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
51 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
53 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
54 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
56 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
57 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
59 /* Even if we're only using it for transfer operations, clears to depth and
60 * stencil images happen as depth and stencil so they need the right ISL
61 * usage bits or else things will fall apart.
64 case VK_IMAGE_ASPECT_DEPTH_BIT
:
65 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
67 case VK_IMAGE_ASPECT_STENCIL_BIT
:
68 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
70 case VK_IMAGE_ASPECT_COLOR_BIT
:
71 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
72 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
73 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
76 unreachable("bad VkImageAspect");
79 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
80 /* blorp implements transfers by sampling from the source image. */
81 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
84 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
85 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
86 /* blorp implements transfers by rendering into the destination image.
87 * Only request this with color images, as we deal with depth/stencil
88 * formats differently. */
89 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
95 static isl_tiling_flags_t
96 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
,
97 const struct isl_drm_modifier_info
*isl_mod_info
,
100 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
101 isl_tiling_flags_t flags
= 0;
103 switch (base_info
->tiling
) {
105 unreachable("bad VkImageTiling");
106 case VK_IMAGE_TILING_OPTIMAL
:
107 flags
= ISL_TILING_ANY_MASK
;
109 case VK_IMAGE_TILING_LINEAR
:
110 flags
= ISL_TILING_LINEAR_BIT
;
114 if (anv_info
->isl_tiling_flags
)
115 flags
&= anv_info
->isl_tiling_flags
;
118 flags
&= ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
;
121 flags
&= 1 << isl_mod_info
->tiling
;
128 static struct anv_surface
*
129 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
131 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
132 return &image
->planes
[plane
].surface
;
136 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
138 assert(surf
->isl
.size_B
> 0); /* isl surface must be initialized */
140 if (image
->disjoint
) {
141 surf
->offset
= align_u32(image
->planes
[plane
].size
,
142 surf
->isl
.alignment_B
);
143 /* Plane offset is always 0 when it's disjoint. */
145 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment_B
);
146 /* Determine plane's offset only once when the first surface is added. */
147 if (image
->planes
[plane
].size
== 0)
148 image
->planes
[plane
].offset
= image
->size
;
151 image
->size
= surf
->offset
+ surf
->isl
.size_B
;
152 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size_B
) - image
->planes
[plane
].offset
;
154 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment_B
);
155 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
156 surf
->isl
.alignment_B
);
161 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
162 const struct VkImageCreateInfo
*vk_info
)
164 enum isl_format format
=
165 anv_get_isl_format(devinfo
, vk_info
->format
,
166 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
168 if (!isl_format_supports_ccs_e(devinfo
, format
))
171 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
174 const VkImageFormatListCreateInfoKHR
*fmt_list
=
175 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
177 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
180 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
181 enum isl_format view_format
=
182 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
183 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
185 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
193 * For color images that have an auxiliary surface, request allocation for an
194 * additional buffer that mainly stores fast-clear values. Use of this buffer
195 * allows us to access the image's subresources while being aware of their
196 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
197 * which a fast clear has occurred).
199 * In order to avoid having multiple clear colors for a single plane of an
200 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
201 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
202 * 2018), there were no known applications which would benefit from fast-
203 * clearing more than just the first slice.
205 * The fast clear portion of the image is laid out in the following order:
207 * * 1 or 4 dwords (depending on hardware generation) for the clear color
208 * * 1 dword for the anv_fast_clear_type of the clear color
209 * * On gen9+, 1 dword per level and layer of the image (3D levels count
210 * multiple layers) in level-major order for compression state.
212 * For the purpose of discoverability, the algorithm used to manage
213 * compression and fast-clears is described here:
215 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
216 * all of the values in the fast clear portion of the image are initialized
219 * * On fast-clear, the clear value is written into surface state and also
220 * into the buffer and the fast clear type is set appropriately. Both
221 * setting the fast-clear value in the buffer and setting the fast-clear
222 * type happen from the GPU using MI commands.
224 * * Whenever a render or blorp operation is performed with CCS_E, we call
225 * genX(cmd_buffer_mark_image_written) to set the compression state to
226 * true (which is represented by UINT32_MAX).
228 * * On pipeline barrier transitions, the worst-case transition is computed
229 * from the image layouts. The command streamer inspects the fast clear
230 * type and compression state dwords and constructs a predicate. The
231 * worst-case resolve is performed with the given predicate and the fast
232 * clear and compression state is set accordingly.
234 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
235 * details on exactly what is allowed in what layouts.
237 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
238 * In order to deal with this, we have to do some clear color management.
240 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
241 * value from the buffer into the surface state with MI commands.
243 * * For any blorp operations, we pass the address to the clear value into
244 * blorp and it knows to copy the clear color.
247 add_aux_state_tracking_buffer(struct anv_image
*image
,
248 VkImageAspectFlagBits aspect
,
250 const struct anv_device
*device
)
252 assert(image
&& device
);
253 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 &&
254 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
256 /* Compressed images must be tiled and therefore everything should be 4K
257 * aligned. The CCS has the same alignment requirements. This is good
258 * because we need at least dword-alignment for MI_LOAD/STORE operations.
260 assert(image
->alignment
% 4 == 0);
261 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
263 /* This buffer should be at the very end of the plane. */
264 if (image
->disjoint
) {
265 assert(image
->planes
[plane
].size
==
266 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
268 assert(image
->size
==
269 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
272 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
273 device
->isl_dev
.ss
.clear_color_state_size
:
274 device
->isl_dev
.ss
.clear_value_size
;
276 /* Clear color and fast clear type */
277 unsigned state_size
= clear_color_state_size
+ 4;
279 /* We only need to track compression on CCS_E surfaces. */
280 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
281 if (image
->type
== VK_IMAGE_TYPE_3D
) {
282 for (uint32_t l
= 0; l
< image
->levels
; l
++)
283 state_size
+= anv_minify(image
->extent
.depth
, l
) * 4;
285 state_size
+= image
->levels
* image
->array_size
* 4;
289 image
->planes
[plane
].fast_clear_state_offset
=
290 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
292 image
->planes
[plane
].size
+= state_size
;
293 image
->size
+= state_size
;
297 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
298 * image's memory requirements (that is, the image's size and alignment).
301 make_surface(const struct anv_device
*dev
,
302 struct anv_image
*image
,
303 const struct anv_image_create_info
*anv_info
,
304 isl_tiling_flags_t tiling_flags
,
305 VkImageAspectFlagBits aspect
)
307 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
310 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
311 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
312 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
313 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
316 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
319 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
320 const struct anv_format_plane plane_format
=
321 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
322 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
324 const isl_surf_usage_flags_t usage
=
325 choose_isl_surf_usage(vk_info
->flags
, image
->usage
,
326 anv_info
->isl_extra_usage_flags
, aspect
);
328 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
329 * fall back to linear on Broadwell and earlier because we aren't
330 * guaranteed that we can handle offsets correctly. On Sky Lake, the
331 * horizontal and vertical alignments are sufficiently high that we can
332 * just use RENDER_SURFACE_STATE::X/Y Offset.
334 bool needs_shadow
= false;
335 if (dev
->info
.gen
<= 8 &&
336 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT
) &&
337 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
338 assert(isl_format_is_compressed(plane_format
.isl_format
));
339 tiling_flags
= ISL_TILING_LINEAR_BIT
;
343 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
344 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
345 .format
= plane_format
.isl_format
,
346 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
347 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
348 .depth
= image
->extent
.depth
,
349 .levels
= vk_info
->mipLevels
,
350 .array_len
= vk_info
->arrayLayers
,
351 .samples
= vk_info
->samples
,
352 .min_alignment_B
= 0,
353 .row_pitch_B
= anv_info
->stride
,
355 .tiling_flags
= tiling_flags
);
358 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
360 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
362 add_surface(image
, anv_surf
, plane
);
364 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
365 * create an identical tiled shadow surface for use while texturing so we
366 * don't get garbage performance.
369 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
370 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
372 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
373 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
374 .format
= plane_format
.isl_format
,
375 .width
= image
->extent
.width
,
376 .height
= image
->extent
.height
,
377 .depth
= image
->extent
.depth
,
378 .levels
= vk_info
->mipLevels
,
379 .array_len
= vk_info
->arrayLayers
,
380 .samples
= vk_info
->samples
,
381 .min_alignment_B
= 0,
382 .row_pitch_B
= anv_info
->stride
,
384 .tiling_flags
= ISL_TILING_ANY_MASK
);
386 /* isl_surf_init() will fail only if provided invalid input. Invalid input
387 * is illegal in Vulkan.
391 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
394 /* Add a HiZ surface to a depth buffer that will be used for rendering.
396 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
397 /* We don't advertise that depth buffers could be used as storage
400 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
402 /* Allow the user to control HiZ enabling. Disable by default on gen7
403 * because resolves are not currently implemented pre-BDW.
405 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
406 /* It will never be used as an attachment, HiZ is pointless. */
407 } else if (dev
->info
.gen
== 7) {
408 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
409 } else if (vk_info
->mipLevels
> 1) {
410 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
411 } else if (vk_info
->arrayLayers
> 1) {
412 anv_perf_warn(dev
->instance
, image
,
413 "Implement multi-arrayLayer HiZ clears and resolves");
414 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
415 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
416 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
417 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
418 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
419 &image
->planes
[plane
].surface
.isl
,
420 &image
->planes
[plane
].aux_surface
.isl
);
422 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
423 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
425 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
== 1) {
426 /* TODO: Disallow compression with :
428 * 1) non multiplanar images (We appear to hit a sampler bug with
429 * CCS & R16G16 format. Putting the clear state a page/4096bytes
430 * further fixes the issue).
432 * 2) alias images, because they might be aliases of images
435 * 3) compression disabled by debug
437 const bool allow_compression
=
438 image
->n_planes
== 1 &&
439 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT
) == 0 &&
440 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
442 if (allow_compression
) {
443 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
444 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
445 &image
->planes
[plane
].surface
.isl
,
446 &image
->planes
[plane
].aux_surface
.isl
, 0);
449 /* Disable CCS when it is not useful (i.e., when you can't render
450 * to the image with CCS enabled).
452 if (!isl_format_supports_rendering(&dev
->info
,
453 plane_format
.isl_format
)) {
454 /* While it may be technically possible to enable CCS for this
455 * image, we currently don't have things hooked up to get it
458 anv_perf_warn(dev
->instance
, image
,
459 "This image format doesn't support rendering. "
460 "Not allocating an CCS buffer.");
461 image
->planes
[plane
].aux_surface
.isl
.size_B
= 0;
465 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
466 add_aux_state_tracking_buffer(image
, aspect
, plane
, dev
);
468 /* For images created without MUTABLE_FORMAT_BIT set, we know that
469 * they will always be used with the original format. In
470 * particular, they will always be used with a format that
471 * supports color compression. If it's never used as a storage
472 * image, then it will only be used through the sampler or the as
473 * a render target. This means that it's safe to just leave
474 * compression on at all times for these formats.
476 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
477 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
478 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
482 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
> 1) {
483 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
484 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
485 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
486 &image
->planes
[plane
].surface
.isl
,
487 &image
->planes
[plane
].aux_surface
.isl
);
489 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
490 add_aux_state_tracking_buffer(image
, aspect
, plane
, dev
);
491 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
495 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
497 /* Upper bound of the last surface should be smaller than the plane's
500 assert((MAX2(image
->planes
[plane
].surface
.offset
,
501 image
->planes
[plane
].aux_surface
.offset
) +
502 (image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
503 image
->planes
[plane
].aux_surface
.isl
.size_B
:
504 image
->planes
[plane
].surface
.isl
.size_B
)) <=
505 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
507 if (image
->planes
[plane
].aux_surface
.isl
.size_B
) {
508 /* assert(image->planes[plane].fast_clear_state_offset == */
509 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */
510 assert(image
->planes
[plane
].fast_clear_state_offset
<
511 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
518 score_drm_format_mod(uint64_t modifier
)
521 case DRM_FORMAT_MOD_LINEAR
: return 1;
522 case I915_FORMAT_MOD_X_TILED
: return 2;
523 case I915_FORMAT_MOD_Y_TILED
: return 3;
524 case I915_FORMAT_MOD_Y_TILED_CCS
: return 4;
525 default: unreachable("bad DRM format modifier");
529 static const struct isl_drm_modifier_info
*
530 choose_drm_format_mod(const struct anv_physical_device
*device
,
531 uint32_t modifier_count
, const uint64_t *modifiers
)
533 uint64_t best_mod
= UINT64_MAX
;
534 uint32_t best_score
= 0;
536 for (uint32_t i
= 0; i
< modifier_count
; ++i
) {
537 uint32_t score
= score_drm_format_mod(modifiers
[i
]);
538 if (score
> best_score
) {
539 best_mod
= modifiers
[i
];
545 return isl_drm_modifier_get_info(best_mod
);
551 anv_image_create(VkDevice _device
,
552 const struct anv_image_create_info
*create_info
,
553 const VkAllocationCallbacks
* alloc
,
556 ANV_FROM_HANDLE(anv_device
, device
, _device
);
557 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
558 const struct isl_drm_modifier_info
*isl_mod_info
= NULL
;
559 struct anv_image
*image
= NULL
;
562 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
564 const struct wsi_image_create_info
*wsi_info
=
565 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
566 if (wsi_info
&& wsi_info
->modifier_count
> 0) {
567 isl_mod_info
= choose_drm_format_mod(&device
->instance
->physicalDevice
,
568 wsi_info
->modifier_count
,
569 wsi_info
->modifiers
);
570 assert(isl_mod_info
);
573 anv_assert(pCreateInfo
->mipLevels
> 0);
574 anv_assert(pCreateInfo
->arrayLayers
> 0);
575 anv_assert(pCreateInfo
->samples
> 0);
576 anv_assert(pCreateInfo
->extent
.width
> 0);
577 anv_assert(pCreateInfo
->extent
.height
> 0);
578 anv_assert(pCreateInfo
->extent
.depth
> 0);
580 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
581 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
583 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
585 image
->type
= pCreateInfo
->imageType
;
586 image
->extent
= pCreateInfo
->extent
;
587 image
->vk_format
= pCreateInfo
->format
;
588 image
->format
= anv_get_format(pCreateInfo
->format
);
589 image
->aspects
= vk_format_aspects(image
->vk_format
);
590 image
->levels
= pCreateInfo
->mipLevels
;
591 image
->array_size
= pCreateInfo
->arrayLayers
;
592 image
->samples
= pCreateInfo
->samples
;
593 image
->usage
= pCreateInfo
->usage
;
594 image
->tiling
= pCreateInfo
->tiling
;
595 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT
;
596 image
->needs_set_tiling
= wsi_info
&& wsi_info
->scanout
;
597 image
->drm_format_mod
= isl_mod_info
? isl_mod_info
->modifier
:
598 DRM_FORMAT_MOD_INVALID
;
600 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
601 assert(format
!= NULL
);
603 const isl_tiling_flags_t isl_tiling_flags
=
604 choose_isl_tiling_flags(create_info
, isl_mod_info
,
605 image
->needs_set_tiling
);
607 image
->n_planes
= format
->n_planes
;
610 for_each_bit(b
, image
->aspects
) {
611 r
= make_surface(device
, image
, create_info
, isl_tiling_flags
,
617 *pImage
= anv_image_to_handle(image
);
623 vk_free2(&device
->alloc
, alloc
, image
);
629 anv_CreateImage(VkDevice device
,
630 const VkImageCreateInfo
*pCreateInfo
,
631 const VkAllocationCallbacks
*pAllocator
,
635 const VkNativeBufferANDROID
*gralloc_info
=
636 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
639 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
643 return anv_image_create(device
,
644 &(struct anv_image_create_info
) {
645 .vk_info
= pCreateInfo
,
652 anv_DestroyImage(VkDevice _device
, VkImage _image
,
653 const VkAllocationCallbacks
*pAllocator
)
655 ANV_FROM_HANDLE(anv_device
, device
, _device
);
656 ANV_FROM_HANDLE(anv_image
, image
, _image
);
661 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
662 if (image
->planes
[p
].bo_is_owned
) {
663 assert(image
->planes
[p
].address
.bo
!= NULL
);
664 anv_bo_cache_release(device
, &device
->bo_cache
,
665 image
->planes
[p
].address
.bo
);
669 vk_free2(&device
->alloc
, pAllocator
, image
);
672 static void anv_image_bind_memory_plane(struct anv_device
*device
,
673 struct anv_image
*image
,
675 struct anv_device_memory
*memory
,
676 uint32_t memory_offset
)
678 assert(!image
->planes
[plane
].bo_is_owned
);
681 image
->planes
[plane
].address
= ANV_NULL_ADDRESS
;
685 image
->planes
[plane
].address
= (struct anv_address
) {
687 .offset
= memory_offset
,
691 VkResult
anv_BindImageMemory(
694 VkDeviceMemory _memory
,
695 VkDeviceSize memoryOffset
)
697 ANV_FROM_HANDLE(anv_device
, device
, _device
);
698 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
699 ANV_FROM_HANDLE(anv_image
, image
, _image
);
702 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
704 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
705 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
711 VkResult
anv_BindImageMemory2(
713 uint32_t bindInfoCount
,
714 const VkBindImageMemoryInfo
* pBindInfos
)
716 ANV_FROM_HANDLE(anv_device
, device
, _device
);
718 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
719 const VkBindImageMemoryInfo
*bind_info
= &pBindInfos
[i
];
720 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
721 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
722 VkImageAspectFlags aspects
= image
->aspects
;
724 vk_foreach_struct_const(s
, bind_info
->pNext
) {
726 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO
: {
727 const VkBindImagePlaneMemoryInfo
*plane_info
=
728 (const VkBindImagePlaneMemoryInfo
*) s
;
730 aspects
= plane_info
->planeAspect
;
734 anv_debug_ignored_stype(s
->sType
);
740 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
742 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
743 anv_image_bind_memory_plane(device
, image
, plane
,
744 mem
, bind_info
->memoryOffset
);
751 void anv_GetImageSubresourceLayout(
754 const VkImageSubresource
* subresource
,
755 VkSubresourceLayout
* layout
)
757 ANV_FROM_HANDLE(anv_image
, image
, _image
);
759 const struct anv_surface
*surface
;
760 if (subresource
->aspectMask
== VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
&&
761 image
->drm_format_mod
!= DRM_FORMAT_MOD_INVALID
&&
762 isl_drm_modifier_has_aux(image
->drm_format_mod
))
763 surface
= &image
->planes
[0].aux_surface
;
765 surface
= get_surface(image
, subresource
->aspectMask
);
767 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
769 layout
->offset
= surface
->offset
;
770 layout
->rowPitch
= surface
->isl
.row_pitch_B
;
771 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
772 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
774 if (subresource
->mipLevel
> 0 || subresource
->arrayLayer
> 0) {
775 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
778 isl_surf_get_image_offset_B_tile_sa(&surface
->isl
,
779 subresource
->mipLevel
,
780 subresource
->arrayLayer
,
781 0 /* logical_z_offset_px */,
782 &offset_B
, NULL
, NULL
);
783 layout
->offset
+= offset_B
;
784 layout
->size
= layout
->rowPitch
* anv_minify(image
->extent
.height
,
785 subresource
->mipLevel
);
787 layout
->size
= surface
->isl
.size_B
;
792 * This function determines the optimal buffer to use for a given
793 * VkImageLayout and other pieces of information needed to make that
794 * determination. This does not determine the optimal buffer to use
795 * during a resolve operation.
797 * @param devinfo The device information of the Intel GPU.
798 * @param image The image that may contain a collection of buffers.
799 * @param aspect The aspect of the image to be accessed.
800 * @param layout The current layout of the image aspect(s).
802 * @return The primary buffer that should be used for the given layout.
805 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
806 const struct anv_image
* const image
,
807 const VkImageAspectFlagBits aspect
,
808 const VkImageLayout layout
)
810 /* Validate the inputs. */
812 /* The devinfo is needed as the optimal buffer varies across generations. */
813 assert(devinfo
!= NULL
);
815 /* The layout of a NULL image is not properly defined. */
816 assert(image
!= NULL
);
818 /* The aspect must be exactly one of the image aspects. */
819 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
821 /* Determine the optimal buffer. */
823 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
825 /* If there is no auxiliary surface allocated, we must use the one and only
828 if (image
->planes
[plane
].aux_surface
.isl
.size_B
== 0)
829 return ISL_AUX_USAGE_NONE
;
831 /* All images that use an auxiliary surface are required to be tiled. */
832 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
834 /* Stencil has no aux */
835 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
839 /* Invalid Layouts */
840 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
841 case VK_IMAGE_LAYOUT_MAX_ENUM
:
842 unreachable("Invalid image layout.");
846 * The pre-initialized layout is equivalent to the undefined layout for
847 * optimally-tiled images. We can only do color compression (CCS or HiZ)
850 case VK_IMAGE_LAYOUT_UNDEFINED
:
851 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
852 return ISL_AUX_USAGE_NONE
;
857 case VK_IMAGE_LAYOUT_GENERAL
:
858 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
859 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
860 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
861 /* This buffer could be a depth buffer used in a transfer operation.
862 * BLORP currently doesn't use HiZ for transfer operations so we must
863 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
865 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_HIZ
);
866 return ISL_AUX_USAGE_NONE
;
868 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
869 return image
->planes
[plane
].aux_usage
;
873 /* Sampling Layouts */
874 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
875 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
:
876 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
878 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
879 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
880 if (anv_can_sample_with_hiz(devinfo
, image
))
881 return ISL_AUX_USAGE_HIZ
;
883 return ISL_AUX_USAGE_NONE
;
885 return image
->planes
[plane
].aux_usage
;
889 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
: {
890 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
892 /* When handing the image off to the presentation engine, we need to
893 * ensure that things are properly resolved. For images with no
894 * modifier, we assume that they follow the old rules and always need
895 * a full resolve because the PE doesn't understand any form of
896 * compression. For images with modifiers, we use the aux usage from
899 const struct isl_drm_modifier_info
*mod_info
=
900 isl_drm_modifier_get_info(image
->drm_format_mod
);
901 return mod_info
? mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
905 /* Rendering Layouts */
906 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
907 assert(aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
908 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
) {
909 assert(image
->samples
== 1);
910 return ISL_AUX_USAGE_CCS_D
;
912 assert(image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_D
);
913 return image
->planes
[plane
].aux_usage
;
916 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
917 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
:
918 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
919 return ISL_AUX_USAGE_HIZ
;
921 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
922 unreachable("VK_KHR_shared_presentable_image is unsupported");
925 /* If the layout isn't recognized in the exhaustive switch above, the
926 * VkImageLayout value is not defined in vulkan.h.
928 unreachable("layout is not a VkImageLayout enumeration member.");
932 * This function returns the level of unresolved fast-clear support of the
933 * given image in the given VkImageLayout.
935 * @param devinfo The device information of the Intel GPU.
936 * @param image The image that may contain a collection of buffers.
937 * @param aspect The aspect of the image to be accessed.
938 * @param layout The current layout of the image aspect(s).
940 enum anv_fast_clear_type
941 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
942 const struct anv_image
* const image
,
943 const VkImageAspectFlagBits aspect
,
944 const VkImageLayout layout
)
946 /* The aspect must be exactly one of the image aspects. */
947 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
949 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
951 /* If there is no auxiliary surface allocated, there are no fast-clears */
952 if (image
->planes
[plane
].aux_surface
.isl
.size_B
== 0)
953 return ANV_FAST_CLEAR_NONE
;
955 /* All images that use an auxiliary surface are required to be tiled. */
956 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
958 /* Stencil has no aux */
959 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
961 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
962 /* For depth images (with HiZ), the layout supports fast-clears if and
963 * only if it supports HiZ. However, we only support fast-clears to the
964 * default depth value.
966 enum isl_aux_usage aux_usage
=
967 anv_layout_to_aux_usage(devinfo
, image
, aspect
, layout
);
968 return aux_usage
== ISL_AUX_USAGE_HIZ
?
969 ANV_FAST_CLEAR_DEFAULT_VALUE
: ANV_FAST_CLEAR_NONE
;
972 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
974 /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
975 * lack the MI ALU which we need to determine the predicates.
977 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&& image
->samples
> 1)
978 return ANV_FAST_CLEAR_NONE
;
981 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
982 return ANV_FAST_CLEAR_ANY
;
984 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
: {
985 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
987 /* We do not yet support any modifiers which support clear color so we
988 * just always return NONE. One day, this will change.
990 const struct isl_drm_modifier_info
*mod_info
=
991 isl_drm_modifier_get_info(image
->drm_format_mod
);
992 assert(!mod_info
|| !mod_info
->supports_clear_color
);
994 return ANV_FAST_CLEAR_NONE
;
998 /* If the image has MCS or CCS_E enabled all the time then we can use
999 * fast-clear as long as the clear color is the default value of zero
1000 * since this is the default value we program into every surface state
1001 * used for texturing.
1003 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_MCS
||
1004 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
)
1005 return ANV_FAST_CLEAR_DEFAULT_VALUE
;
1007 return ANV_FAST_CLEAR_NONE
;
1012 static struct anv_state
1013 alloc_surface_state(struct anv_device
*device
)
1015 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
1018 static enum isl_channel_select
1019 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
1020 struct isl_swizzle format_swizzle
)
1022 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
1023 swizzle
= component
;
1026 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
1027 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
1028 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
1029 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
1030 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
1031 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
1033 unreachable("Invalid swizzle");
1038 anv_image_fill_surface_state(struct anv_device
*device
,
1039 const struct anv_image
*image
,
1040 VkImageAspectFlagBits aspect
,
1041 const struct isl_view
*view_in
,
1042 isl_surf_usage_flags_t view_usage
,
1043 enum isl_aux_usage aux_usage
,
1044 const union isl_color_value
*clear_color
,
1045 enum anv_image_view_state_flags flags
,
1046 struct anv_surface_state
*state_inout
,
1047 struct brw_image_param
*image_param_out
)
1049 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1051 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
1052 *aux_surface
= &image
->planes
[plane
].aux_surface
;
1054 struct isl_view view
= *view_in
;
1055 view
.usage
|= view_usage
;
1057 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
1058 * compressed surface with a shadow surface, we use the shadow instead of
1059 * the primary surface. The shadow surface will be tiled, unlike the main
1060 * surface, so it should get significantly better performance.
1062 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1063 isl_format_is_compressed(view
.format
) &&
1064 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
1065 assert(isl_format_is_compressed(surface
->isl
.format
));
1066 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1067 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1068 surface
= &image
->planes
[plane
].shadow_surface
;
1071 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
1072 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
1074 /* If this is a HiZ buffer we can sample from with a programmable clear
1075 * value (SKL+), define the clear value to the optimal constant.
1077 union isl_color_value default_clear_color
= { .u32
= { 0, } };
1078 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
1079 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1081 clear_color
= &default_clear_color
;
1083 const struct anv_address address
=
1084 anv_address_add(image
->planes
[plane
].address
, surface
->offset
);
1086 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1087 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
1088 !isl_has_matching_typed_storage_image_format(&device
->info
,
1090 /* In this case, we are a writeable storage buffer which needs to be
1091 * lowered to linear. All tiling and offset calculations will be done in
1094 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1095 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1096 .address
= anv_address_physical(address
),
1097 .size_B
= surface
->isl
.size_B
,
1098 .format
= ISL_FORMAT_RAW
,
1100 .mocs
= device
->default_mocs
);
1101 state_inout
->address
= address
,
1102 state_inout
->aux_address
= ANV_NULL_ADDRESS
;
1103 state_inout
->clear_address
= ANV_NULL_ADDRESS
;
1105 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1106 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
1107 /* Typed surface reads support a very limited subset of the shader
1108 * image formats. Translate it into the closest format the hardware
1111 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1112 view
.format
= isl_lower_storage_image_format(&device
->info
,
1116 const struct isl_surf
*isl_surf
= &surface
->isl
;
1118 struct isl_surf tmp_surf
;
1119 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1120 if (isl_format_is_compressed(surface
->isl
.format
) &&
1121 !isl_format_is_compressed(view
.format
)) {
1122 /* We're creating an uncompressed view of a compressed surface. This
1123 * is allowed but only for a single level/layer.
1125 assert(surface
->isl
.samples
== 1);
1126 assert(view
.levels
== 1);
1127 assert(view
.array_len
== 1);
1129 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
1131 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1132 0 : view
.base_array_layer
,
1133 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1134 view
.base_array_layer
: 0,
1136 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1138 /* The newly created image represents the one subimage we're
1139 * referencing with this view so it only has one array slice and
1142 view
.base_array_layer
= 0;
1143 view
.base_level
= 0;
1145 /* We're making an uncompressed view here. The image dimensions need
1146 * to be scaled down by the block size.
1148 const struct isl_format_layout
*fmtl
=
1149 isl_format_get_layout(surface
->isl
.format
);
1150 tmp_surf
.format
= view
.format
;
1151 tmp_surf
.logical_level0_px
.width
=
1152 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
1153 tmp_surf
.logical_level0_px
.height
=
1154 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
1155 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1156 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1157 tile_x_sa
/= fmtl
->bw
;
1158 tile_y_sa
/= fmtl
->bh
;
1160 isl_surf
= &tmp_surf
;
1162 if (device
->info
.gen
<= 8) {
1163 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1164 assert(tile_x_sa
== 0);
1165 assert(tile_y_sa
== 0);
1169 state_inout
->address
= anv_address_add(address
, offset_B
);
1171 struct anv_address aux_address
= ANV_NULL_ADDRESS
;
1172 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1173 aux_address
= anv_address_add(image
->planes
[plane
].address
,
1174 aux_surface
->offset
);
1176 state_inout
->aux_address
= aux_address
;
1178 struct anv_address clear_address
= ANV_NULL_ADDRESS
;
1179 if (device
->info
.gen
>= 10 && aux_usage
!= ISL_AUX_USAGE_NONE
) {
1180 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1181 clear_address
= (struct anv_address
) {
1182 .bo
= &device
->hiz_clear_bo
,
1186 clear_address
= anv_image_get_clear_color_addr(device
, image
, aspect
);
1189 state_inout
->clear_address
= clear_address
;
1191 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1194 .address
= anv_address_physical(state_inout
->address
),
1195 .clear_color
= *clear_color
,
1196 .aux_surf
= &aux_surface
->isl
,
1197 .aux_usage
= aux_usage
,
1198 .aux_address
= anv_address_physical(aux_address
),
1199 .clear_address
= anv_address_physical(clear_address
),
1200 .use_clear_address
= !anv_address_is_null(clear_address
),
1201 .mocs
= device
->default_mocs
,
1202 .x_offset_sa
= tile_x_sa
,
1203 .y_offset_sa
= tile_y_sa
);
1205 /* With the exception of gen8, the bottom 12 bits of the MCS base address
1206 * are used to store other information. This should be ok, however,
1207 * because the surface buffer addresses are always 4K page aligned.
1209 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1210 device
->isl_dev
.ss
.aux_addr_offset
;
1211 assert((aux_address
.offset
& 0xfff) == 0);
1212 state_inout
->aux_address
.offset
|= *aux_addr_dw
& 0xfff;
1214 if (device
->info
.gen
>= 10 && clear_address
.bo
) {
1215 uint32_t *clear_addr_dw
= state_inout
->state
.map
+
1216 device
->isl_dev
.ss
.clear_color_state_offset
;
1217 assert((clear_address
.offset
& 0x3f) == 0);
1218 state_inout
->clear_address
.offset
|= *clear_addr_dw
& 0x3f;
1222 anv_state_flush(device
, state_inout
->state
);
1224 if (image_param_out
) {
1225 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1226 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1227 &surface
->isl
, &view
);
1231 static VkImageAspectFlags
1232 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1234 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1235 if (util_bitcount(view_aspects
) == 1)
1236 return VK_IMAGE_ASPECT_COLOR_BIT
;
1238 VkImageAspectFlags color_aspects
= 0;
1239 for (uint32_t i
= 0; i
< util_bitcount(view_aspects
); i
++)
1240 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT
<< i
;
1241 return color_aspects
;
1243 /* No special remapping needed for depth & stencil aspects. */
1244 return view_aspects
;
1248 anv_CreateImageView(VkDevice _device
,
1249 const VkImageViewCreateInfo
*pCreateInfo
,
1250 const VkAllocationCallbacks
*pAllocator
,
1253 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1254 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1255 struct anv_image_view
*iview
;
1257 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1258 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1260 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1262 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1264 assert(range
->layerCount
> 0);
1265 assert(range
->baseMipLevel
< image
->levels
);
1267 const VkImageViewUsageCreateInfo
*usage_info
=
1268 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO
);
1269 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1270 /* View usage should be a subset of image usage */
1271 assert((view_usage
& ~image
->usage
) == 0);
1272 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1273 VK_IMAGE_USAGE_STORAGE_BIT
|
1274 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1275 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1276 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1278 switch (image
->type
) {
1280 unreachable("bad VkImageType");
1281 case VK_IMAGE_TYPE_1D
:
1282 case VK_IMAGE_TYPE_2D
:
1283 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1285 case VK_IMAGE_TYPE_3D
:
1286 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1287 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1291 /* First expand aspects to the image's ones (for example
1292 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1293 * VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT |
1294 * VK_IMAGE_ASPECT_PLANE_2_BIT for an image of format
1295 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1297 VkImageAspectFlags expanded_aspects
=
1298 anv_image_expand_aspects(image
, range
->aspectMask
);
1300 iview
->image
= image
;
1302 /* Remap the expanded aspects for the image view. For example if only
1303 * VK_IMAGE_ASPECT_PLANE_1_BIT was given in range->aspectMask, we will
1304 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1305 * the image view, it only has a single plane.
1307 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1308 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1309 iview
->vk_format
= pCreateInfo
->format
;
1311 iview
->extent
= (VkExtent3D
) {
1312 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1313 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1314 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1317 /* Now go through the underlying image selected planes (computed in
1318 * expanded_aspects) and map them to planes in the image view.
1320 uint32_t iaspect_bit
, vplane
= 0;
1321 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1323 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1324 VkImageAspectFlags vplane_aspect
=
1325 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1326 struct anv_format_plane format
=
1327 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1328 vplane_aspect
, image
->tiling
);
1330 iview
->planes
[vplane
].image_plane
= iplane
;
1332 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1333 .format
= format
.isl_format
,
1334 .base_level
= range
->baseMipLevel
,
1335 .levels
= anv_get_levelCount(image
, range
),
1336 .base_array_layer
= range
->baseArrayLayer
,
1337 .array_len
= anv_get_layerCount(image
, range
),
1339 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1340 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1341 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1342 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1343 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1344 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1345 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1346 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1350 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1351 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1352 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1355 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1356 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1357 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1359 iview
->planes
[vplane
].isl
.usage
= 0;
1362 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1363 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1364 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1365 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1366 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1368 enum isl_aux_usage general_aux_usage
=
1369 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1370 VK_IMAGE_LAYOUT_GENERAL
);
1371 enum isl_aux_usage optimal_aux_usage
=
1372 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1373 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1375 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1376 &iview
->planes
[vplane
].isl
,
1377 ISL_SURF_USAGE_TEXTURE_BIT
,
1378 optimal_aux_usage
, NULL
,
1379 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1380 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1383 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1384 &iview
->planes
[vplane
].isl
,
1385 ISL_SURF_USAGE_TEXTURE_BIT
,
1386 general_aux_usage
, NULL
,
1388 &iview
->planes
[vplane
].general_sampler_surface_state
,
1392 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1393 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1394 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1395 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1397 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1398 &iview
->planes
[vplane
].isl
,
1399 ISL_SURF_USAGE_STORAGE_BIT
,
1400 ISL_AUX_USAGE_NONE
, NULL
,
1402 &iview
->planes
[vplane
].storage_surface_state
,
1403 &iview
->planes
[vplane
].storage_image_param
);
1405 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1406 &iview
->planes
[vplane
].isl
,
1407 ISL_SURF_USAGE_STORAGE_BIT
,
1408 ISL_AUX_USAGE_NONE
, NULL
,
1409 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1410 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1417 *pView
= anv_image_view_to_handle(iview
);
1423 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1424 const VkAllocationCallbacks
*pAllocator
)
1426 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1427 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1432 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1433 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1434 anv_state_pool_free(&device
->surface_state_pool
,
1435 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1438 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1439 anv_state_pool_free(&device
->surface_state_pool
,
1440 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1443 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1444 anv_state_pool_free(&device
->surface_state_pool
,
1445 iview
->planes
[plane
].storage_surface_state
.state
);
1448 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1449 anv_state_pool_free(&device
->surface_state_pool
,
1450 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1454 vk_free2(&device
->alloc
, pAllocator
, iview
);
1459 anv_CreateBufferView(VkDevice _device
,
1460 const VkBufferViewCreateInfo
*pCreateInfo
,
1461 const VkAllocationCallbacks
*pAllocator
,
1462 VkBufferView
*pView
)
1464 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1465 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1466 struct anv_buffer_view
*view
;
1468 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1469 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1471 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1473 /* TODO: Handle the format swizzle? */
1475 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1476 VK_IMAGE_ASPECT_COLOR_BIT
,
1477 VK_IMAGE_TILING_LINEAR
);
1478 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1479 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1480 pCreateInfo
->range
);
1481 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1483 view
->address
= anv_address_add(buffer
->address
, pCreateInfo
->offset
);
1485 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1486 view
->surface_state
= alloc_surface_state(device
);
1488 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1490 view
->address
, view
->range
, format_bs
);
1492 view
->surface_state
= (struct anv_state
){ 0 };
1495 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1496 view
->storage_surface_state
= alloc_surface_state(device
);
1497 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1499 enum isl_format storage_format
=
1500 isl_has_matching_typed_storage_image_format(&device
->info
,
1502 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1505 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1507 view
->address
, view
->range
,
1508 (storage_format
== ISL_FORMAT_RAW
? 1 :
1509 isl_format_get_layout(storage_format
)->bpb
/ 8));
1511 /* Write-only accesses should use the original format. */
1512 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1514 view
->address
, view
->range
,
1515 isl_format_get_layout(view
->format
)->bpb
/ 8);
1517 isl_buffer_fill_image_param(&device
->isl_dev
,
1518 &view
->storage_image_param
,
1519 view
->format
, view
->range
);
1521 view
->storage_surface_state
= (struct anv_state
){ 0 };
1522 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1525 *pView
= anv_buffer_view_to_handle(view
);
1531 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1532 const VkAllocationCallbacks
*pAllocator
)
1534 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1535 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1540 if (view
->surface_state
.alloc_size
> 0)
1541 anv_state_pool_free(&device
->surface_state_pool
,
1542 view
->surface_state
);
1544 if (view
->storage_surface_state
.alloc_size
> 0)
1545 anv_state_pool_free(&device
->surface_state_pool
,
1546 view
->storage_surface_state
);
1548 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1549 anv_state_pool_free(&device
->surface_state_pool
,
1550 view
->writeonly_storage_surface_state
);
1552 vk_free2(&device
->alloc
, pAllocator
, view
);
1555 const struct anv_surface
*
1556 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1557 VkImageAspectFlags aspect_mask
)
1559 VkImageAspectFlags sanitized_mask
;
1561 switch (aspect_mask
) {
1562 case VK_IMAGE_ASPECT_COLOR_BIT
:
1563 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1564 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1566 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1567 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1568 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1570 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1571 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1572 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1574 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1575 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1576 * combined depth stencil formats. Specifically, it states:
1578 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1579 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1581 * Image views with both depth and stencil aspects are only valid for
1582 * render target attachments, in which case
1583 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1584 * stencil surfaces from the underlying surface.
1586 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1587 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1589 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1590 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1593 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1594 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1595 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT
;
1597 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1598 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1599 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT
;
1601 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1602 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1603 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT
;
1606 unreachable("image does not have aspect");
1610 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1611 return &image
->planes
[plane
].surface
;