2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "anv_private.h"
32 #include "util/debug.h"
34 #include "vk_format_info.h"
37 * Exactly one bit must be set in \a aspect.
39 static isl_surf_usage_flags_t
40 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
41 VkImageUsageFlags vk_usage
,
42 VkImageAspectFlags aspect
)
44 isl_surf_usage_flags_t isl_usage
= 0;
46 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
47 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
49 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
50 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
52 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
53 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
55 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
56 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
58 /* Even if we're only using it for transfer operations, clears to depth and
59 * stencil images happen as depth and stencil so they need the right ISL
60 * usage bits or else things will fall apart.
63 case VK_IMAGE_ASPECT_DEPTH_BIT
:
64 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
66 case VK_IMAGE_ASPECT_STENCIL_BIT
:
67 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
69 case VK_IMAGE_ASPECT_COLOR_BIT
:
72 unreachable("bad VkImageAspect");
75 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
76 /* blorp implements transfers by sampling from the source image. */
77 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
80 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
81 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
82 /* blorp implements transfers by rendering into the destination image.
83 * Only request this with color images, as we deal with depth/stencil
84 * formats differently. */
85 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
92 * Exactly one bit must be set in \a aspect.
94 static struct anv_surface
*
95 get_surface(struct anv_image
*image
, VkImageAspectFlags aspect
)
99 unreachable("bad VkImageAspect");
100 case VK_IMAGE_ASPECT_COLOR_BIT
:
101 return &image
->color_surface
;
102 case VK_IMAGE_ASPECT_DEPTH_BIT
:
103 return &image
->depth_surface
;
104 case VK_IMAGE_ASPECT_STENCIL_BIT
:
105 return &image
->stencil_surface
;
110 add_surface(struct anv_image
*image
, struct anv_surface
*surf
)
112 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
114 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
115 image
->size
= surf
->offset
+ surf
->isl
.size
;
116 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
120 * For color images that have an auxiliary surface, request allocation for an
121 * additional buffer that mainly stores fast-clear values. Use of this buffer
122 * allows us to access the image's subresources while being aware of their
123 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
124 * which a fast clear has occurred).
126 * For the purpose of discoverability, the algorithm used to manage this buffer
127 * is described here. A clear value in this buffer is updated when a fast clear
128 * is performed on a subresource. One of two synchronization operations is
129 * performed in order for a following memory access to use the fast-clear
131 * a. Copy the value from the buffer to the surface state object used for
132 * reading. This is done implicitly when the value is the clear value
133 * predetermined to be the default in other surface state objects. This
134 * is currently only done explicitly for the operation below.
135 * b. Do (a) and use the surface state object to resolve the subresource.
136 * This is only done during layout transitions for decent performance.
138 * With the above scheme, we can fast-clear whenever the hardware allows except
139 * for two cases in which synchronization becomes impossible or undesirable:
140 * * The subresource is in the GENERAL layout and is cleared to a value
141 * other than the special default value.
143 * Performing a synchronization operation in order to read from the
144 * subresource is undesirable in this case. Firstly, b) is not an option
145 * because a layout transition isn't required between a write and read of
146 * an image in the GENERAL layout. Secondly, it's undesirable to do a)
147 * explicitly because it would require large infrastructural changes. The
148 * Vulkan API supports us in deciding not to optimize this layout by
149 * stating that using this layout may cause suboptimal performance. NOTE:
150 * the auxiliary buffer must always be enabled to support a) implicitly.
153 * * For the given miplevel, only some of the layers are cleared at once.
155 * If the user clears each layer to a different value, then tries to
156 * render to multiple layers at once, we have no ability to perform a
157 * synchronization operation in between. a) is not helpful because the
158 * object can only hold one clear value. b) is not an option because a
159 * layout transition isn't required in this case.
162 add_fast_clear_state_buffer(struct anv_image
*image
,
163 const struct anv_device
*device
)
165 assert(image
&& device
);
166 assert(image
->aux_surface
.isl
.size
> 0 &&
167 image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
169 /* The offset to the buffer of clear values must be dword-aligned for GPU
170 * memcpy operations. It is located immediately after the auxiliary surface.
173 /* Tiled images are guaranteed to be 4K aligned, so the image alignment
174 * should also be dword-aligned.
176 assert(image
->alignment
% 4 == 0);
178 /* Auxiliary buffers should be a multiple of 4K, so the start of the clear
179 * values buffer should already be dword-aligned.
181 assert(image
->aux_surface
.isl
.size
% 4 == 0);
183 /* This buffer should be at the very end of the image. */
184 assert(image
->size
==
185 image
->aux_surface
.offset
+ image
->aux_surface
.isl
.size
);
187 const unsigned entry_size
= anv_fast_clear_state_entry_size(device
);
188 /* There's no padding between entries, so ensure that they're always a
189 * multiple of 32 bits in order to enable GPU memcpy operations.
191 assert(entry_size
% 4 == 0);
192 image
->size
+= entry_size
* anv_image_aux_levels(image
);
196 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
197 * image's memory requirements (that is, the image's size and alignment).
199 * Exactly one bit must be set in \a aspect.
202 make_surface(const struct anv_device
*dev
,
203 struct anv_image
*image
,
204 const struct anv_image_create_info
*anv_info
,
205 VkImageAspectFlags aspect
)
207 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
210 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
211 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
212 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
213 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
216 /* Translate the Vulkan tiling to an equivalent ISL tiling, then filter the
217 * result with an optionally provided ISL tiling argument.
219 isl_tiling_flags_t tiling_flags
=
220 (vk_info
->tiling
== VK_IMAGE_TILING_LINEAR
) ?
221 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
223 if (anv_info
->isl_tiling_flags
)
224 tiling_flags
&= anv_info
->isl_tiling_flags
;
226 assert(tiling_flags
);
228 struct anv_surface
*anv_surf
= get_surface(image
, aspect
);
230 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
233 enum isl_format format
= anv_get_isl_format(&dev
->info
, vk_info
->format
,
234 aspect
, vk_info
->tiling
);
235 assert(format
!= ISL_FORMAT_UNSUPPORTED
);
237 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
238 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
240 .width
= image
->extent
.width
,
241 .height
= image
->extent
.height
,
242 .depth
= image
->extent
.depth
,
243 .levels
= vk_info
->mipLevels
,
244 .array_len
= vk_info
->arrayLayers
,
245 .samples
= vk_info
->samples
,
247 .row_pitch
= anv_info
->stride
,
248 .usage
= choose_isl_surf_usage(vk_info
->flags
, image
->usage
, aspect
),
249 .tiling_flags
= tiling_flags
);
251 /* isl_surf_init() will fail only if provided invalid input. Invalid input
252 * is illegal in Vulkan.
256 add_surface(image
, anv_surf
);
258 /* Add a HiZ surface to a depth buffer that will be used for rendering.
260 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
261 /* We don't advertise that depth buffers could be used as storage
264 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
266 /* Allow the user to control HiZ enabling. Disable by default on gen7
267 * because resolves are not currently implemented pre-BDW.
269 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
270 /* It will never be used as an attachment, HiZ is pointless. */
271 } else if (dev
->info
.gen
== 7) {
272 anv_perf_warn("Implement gen7 HiZ");
273 } else if (vk_info
->mipLevels
> 1) {
274 anv_perf_warn("Enable multi-LOD HiZ");
275 } else if (vk_info
->arrayLayers
> 1) {
276 anv_perf_warn("Implement multi-arrayLayer HiZ clears and resolves");
277 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
278 anv_perf_warn("Enable gen8 multisampled HiZ");
279 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
280 assert(image
->aux_surface
.isl
.size
== 0);
281 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
, &image
->depth_surface
.isl
,
282 &image
->aux_surface
.isl
);
284 add_surface(image
, &image
->aux_surface
);
285 image
->aux_usage
= ISL_AUX_USAGE_HIZ
;
287 } else if (aspect
== VK_IMAGE_ASPECT_COLOR_BIT
&& vk_info
->samples
== 1) {
288 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
)) {
289 assert(image
->aux_surface
.isl
.size
== 0);
290 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
, &anv_surf
->isl
,
291 &image
->aux_surface
.isl
, 0);
294 /* Disable CCS when it is not useful (i.e., when you can't render
295 * to the image with CCS enabled).
297 if (!isl_format_supports_rendering(&dev
->info
, format
)) {
298 /* While it may be technically possible to enable CCS for this
299 * image, we currently don't have things hooked up to get it
302 anv_perf_warn("This image format doesn't support rendering. "
303 "Not allocating an CCS buffer.");
304 image
->aux_surface
.isl
.size
= 0;
308 add_surface(image
, &image
->aux_surface
);
309 add_fast_clear_state_buffer(image
, dev
);
311 /* For images created without MUTABLE_FORMAT_BIT set, we know that
312 * they will always be used with the original format. In
313 * particular, they will always be used with a format that
314 * supports color compression. If it's never used as a storage
315 * image, then it will only be used through the sampler or the as
316 * a render target. This means that it's safe to just leave
317 * compression on at all times for these formats.
319 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
320 !(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) &&
321 isl_format_supports_ccs_e(&dev
->info
, format
)) {
322 image
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
326 } else if (aspect
== VK_IMAGE_ASPECT_COLOR_BIT
&& vk_info
->samples
> 1) {
327 assert(image
->aux_surface
.isl
.size
== 0);
328 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
329 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
, &anv_surf
->isl
,
330 &image
->aux_surface
.isl
);
332 add_surface(image
, &image
->aux_surface
);
333 add_fast_clear_state_buffer(image
, dev
);
334 image
->aux_usage
= ISL_AUX_USAGE_MCS
;
342 anv_image_create(VkDevice _device
,
343 const struct anv_image_create_info
*create_info
,
344 const VkAllocationCallbacks
* alloc
,
347 ANV_FROM_HANDLE(anv_device
, device
, _device
);
348 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
349 struct anv_image
*image
= NULL
;
352 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
354 anv_assert(pCreateInfo
->mipLevels
> 0);
355 anv_assert(pCreateInfo
->arrayLayers
> 0);
356 anv_assert(pCreateInfo
->samples
> 0);
357 anv_assert(pCreateInfo
->extent
.width
> 0);
358 anv_assert(pCreateInfo
->extent
.height
> 0);
359 anv_assert(pCreateInfo
->extent
.depth
> 0);
361 image
= vk_alloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
362 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
364 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
366 memset(image
, 0, sizeof(*image
));
367 image
->type
= pCreateInfo
->imageType
;
368 image
->extent
= pCreateInfo
->extent
;
369 image
->vk_format
= pCreateInfo
->format
;
370 image
->aspects
= vk_format_aspects(image
->vk_format
);
371 image
->levels
= pCreateInfo
->mipLevels
;
372 image
->array_size
= pCreateInfo
->arrayLayers
;
373 image
->samples
= pCreateInfo
->samples
;
374 image
->usage
= pCreateInfo
->usage
;
375 image
->tiling
= pCreateInfo
->tiling
;
376 image
->aux_usage
= ISL_AUX_USAGE_NONE
;
379 for_each_bit(b
, image
->aspects
) {
380 r
= make_surface(device
, image
, create_info
, (1 << b
));
385 *pImage
= anv_image_to_handle(image
);
391 vk_free2(&device
->alloc
, alloc
, image
);
397 anv_CreateImage(VkDevice device
,
398 const VkImageCreateInfo
*pCreateInfo
,
399 const VkAllocationCallbacks
*pAllocator
,
402 return anv_image_create(device
,
403 &(struct anv_image_create_info
) {
404 .vk_info
= pCreateInfo
,
411 anv_DestroyImage(VkDevice _device
, VkImage _image
,
412 const VkAllocationCallbacks
*pAllocator
)
414 ANV_FROM_HANDLE(anv_device
, device
, _device
);
415 ANV_FROM_HANDLE(anv_image
, image
, _image
);
420 vk_free2(&device
->alloc
, pAllocator
, image
);
423 VkResult
anv_BindImageMemory(
426 VkDeviceMemory _memory
,
427 VkDeviceSize memoryOffset
)
429 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
430 ANV_FROM_HANDLE(anv_image
, image
, _image
);
439 image
->offset
= memoryOffset
;
445 anv_surface_get_subresource_layout(struct anv_image
*image
,
446 struct anv_surface
*surface
,
447 const VkImageSubresource
*subresource
,
448 VkSubresourceLayout
*layout
)
450 /* If we are on a non-zero mip level or array slice, we need to
451 * calculate a real offset.
453 anv_assert(subresource
->mipLevel
== 0);
454 anv_assert(subresource
->arrayLayer
== 0);
456 layout
->offset
= surface
->offset
;
457 layout
->rowPitch
= surface
->isl
.row_pitch
;
458 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
459 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
460 layout
->size
= surface
->isl
.size
;
463 void anv_GetImageSubresourceLayout(
466 const VkImageSubresource
* pSubresource
,
467 VkSubresourceLayout
* pLayout
)
469 ANV_FROM_HANDLE(anv_image
, image
, _image
);
471 assert(__builtin_popcount(pSubresource
->aspectMask
) == 1);
473 switch (pSubresource
->aspectMask
) {
474 case VK_IMAGE_ASPECT_COLOR_BIT
:
475 anv_surface_get_subresource_layout(image
, &image
->color_surface
,
476 pSubresource
, pLayout
);
478 case VK_IMAGE_ASPECT_DEPTH_BIT
:
479 anv_surface_get_subresource_layout(image
, &image
->depth_surface
,
480 pSubresource
, pLayout
);
482 case VK_IMAGE_ASPECT_STENCIL_BIT
:
483 anv_surface_get_subresource_layout(image
, &image
->stencil_surface
,
484 pSubresource
, pLayout
);
487 assert(!"Invalid image aspect");
492 * This function determines the optimal buffer to use for a given
493 * VkImageLayout and other pieces of information needed to make that
494 * determination. This does not determine the optimal buffer to use
495 * during a resolve operation.
497 * @param devinfo The device information of the Intel GPU.
498 * @param image The image that may contain a collection of buffers.
499 * @param aspects The aspect(s) of the image to be accessed.
500 * @param layout The current layout of the image aspect(s).
502 * @return The primary buffer that should be used for the given layout.
505 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
506 const struct anv_image
* const image
,
507 const VkImageAspectFlags aspects
,
508 const VkImageLayout layout
)
510 /* Validate the inputs. */
512 /* The devinfo is needed as the optimal buffer varies across generations. */
513 assert(devinfo
!= NULL
);
515 /* The layout of a NULL image is not properly defined. */
516 assert(image
!= NULL
);
518 /* The aspects must be a subset of the image aspects. */
519 assert(aspects
& image
->aspects
&& aspects
<= image
->aspects
);
521 /* Determine the optimal buffer. */
523 /* If there is no auxiliary surface allocated, we must use the one and only
526 if (image
->aux_surface
.isl
.size
== 0)
527 return ISL_AUX_USAGE_NONE
;
529 /* All images that use an auxiliary surface are required to be tiled. */
530 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
532 /* On BDW+, when clearing the stencil aspect of a depth stencil image,
533 * the HiZ buffer allows us to record the clear with a relatively small
534 * number of packets. Prior to BDW, the HiZ buffer provides no known benefit
535 * to the stencil aspect.
537 if (devinfo
->gen
< 8 && aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
)
538 return ISL_AUX_USAGE_NONE
;
540 const bool color_aspect
= aspects
== VK_IMAGE_ASPECT_COLOR_BIT
;
542 /* The following switch currently only handles depth stencil aspects.
543 * TODO: Handle the color aspect.
546 return image
->aux_usage
;
550 /* Invalid Layouts */
551 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
552 case VK_IMAGE_LAYOUT_MAX_ENUM
:
553 unreachable("Invalid image layout.");
557 * The pre-initialized layout is equivalent to the undefined layout for
558 * optimally-tiled images. We can only do color compression (CCS or HiZ)
561 case VK_IMAGE_LAYOUT_UNDEFINED
:
562 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
563 return ISL_AUX_USAGE_NONE
;
568 * This buffer could be a depth buffer used in a transfer operation. BLORP
569 * currently doesn't use HiZ for transfer operations so we must use the main
570 * buffer for this layout. TODO: Enable HiZ in BLORP.
572 case VK_IMAGE_LAYOUT_GENERAL
:
573 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
574 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
575 return ISL_AUX_USAGE_NONE
;
578 /* Sampling Layouts */
579 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
580 assert(!color_aspect
);
582 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
583 if (anv_can_sample_with_hiz(devinfo
, aspects
, image
->samples
))
584 return ISL_AUX_USAGE_HIZ
;
586 return ISL_AUX_USAGE_NONE
;
588 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
589 assert(color_aspect
);
591 /* On SKL+, the render buffer can be decompressed by the presentation
592 * engine. Support for this feature has not yet landed in the wider
593 * ecosystem. TODO: Update this code when support lands.
595 * From the BDW PRM, Vol 7, Render Target Resolve:
597 * If the MCS is enabled on a non-multisampled render target, the
598 * render target must be resolved before being used for other
599 * purposes (display, texture, CPU lock) The clear value from
600 * SURFACE_STATE is written into pixels in the render target
601 * indicated as clear in the MCS.
603 * Pre-SKL, the render buffer must be resolved before being used for
604 * presentation. We can infer that the auxiliary buffer is not used.
606 return ISL_AUX_USAGE_NONE
;
609 /* Rendering Layouts */
610 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
611 assert(color_aspect
);
612 unreachable("Color images are not yet supported.");
614 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
615 assert(!color_aspect
);
616 return ISL_AUX_USAGE_HIZ
;
618 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
619 unreachable("VK_KHR_shared_presentable_image is unsupported");
622 /* If the layout isn't recognized in the exhaustive switch above, the
623 * VkImageLayout value is not defined in vulkan.h.
625 unreachable("layout is not a VkImageLayout enumeration member.");
629 static struct anv_state
630 alloc_surface_state(struct anv_device
*device
)
632 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
635 static enum isl_channel_select
636 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
637 struct isl_swizzle format_swizzle
)
639 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
643 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
644 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
645 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
646 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
647 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
648 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
650 unreachable("Invalid swizzle");
656 anv_CreateImageView(VkDevice _device
,
657 const VkImageViewCreateInfo
*pCreateInfo
,
658 const VkAllocationCallbacks
*pAllocator
,
661 ANV_FROM_HANDLE(anv_device
, device
, _device
);
662 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
663 struct anv_image_view
*iview
;
665 iview
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
666 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
668 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
670 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
672 assert(range
->layerCount
> 0);
673 assert(range
->baseMipLevel
< image
->levels
);
674 assert(image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
675 VK_IMAGE_USAGE_STORAGE_BIT
|
676 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
677 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
678 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
680 switch (image
->type
) {
682 unreachable("bad VkImageType");
683 case VK_IMAGE_TYPE_1D
:
684 case VK_IMAGE_TYPE_2D
:
685 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
687 case VK_IMAGE_TYPE_3D
:
688 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
689 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
693 const struct anv_surface
*surface
=
694 anv_image_get_surface_for_aspect_mask(image
, range
->aspectMask
);
696 iview
->image
= image
;
697 iview
->bo
= image
->bo
;
698 iview
->offset
= image
->offset
+ surface
->offset
;
700 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
701 iview
->vk_format
= pCreateInfo
->format
;
703 struct anv_format format
= anv_get_format(&device
->info
, pCreateInfo
->format
,
704 range
->aspectMask
, image
->tiling
);
706 iview
->isl
= (struct isl_view
) {
707 .format
= format
.isl_format
,
708 .base_level
= range
->baseMipLevel
,
709 .levels
= anv_get_levelCount(image
, range
),
710 .base_array_layer
= range
->baseArrayLayer
,
711 .array_len
= anv_get_layerCount(image
, range
),
713 .r
= remap_swizzle(pCreateInfo
->components
.r
,
714 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
715 .g
= remap_swizzle(pCreateInfo
->components
.g
,
716 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
717 .b
= remap_swizzle(pCreateInfo
->components
.b
,
718 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
719 .a
= remap_swizzle(pCreateInfo
->components
.a
,
720 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
724 iview
->extent
= (VkExtent3D
) {
725 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
726 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
727 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
730 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
731 iview
->isl
.base_array_layer
= 0;
732 iview
->isl
.array_len
= iview
->extent
.depth
;
735 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
736 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
737 iview
->isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
739 iview
->isl
.usage
= 0;
742 /* Input attachment surfaces for color are allocated and filled
743 * out at BeginRenderPass time because they need compression information.
744 * Compression is not yet enabled for depth textures and stencil doesn't
745 * allow compression so we can just use the texture surface state from the
748 if (image
->usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
749 (image
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
750 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
751 iview
->optimal_sampler_surface_state
= alloc_surface_state(device
);
752 iview
->general_sampler_surface_state
= alloc_surface_state(device
);
754 iview
->general_sampler_aux_usage
=
755 anv_layout_to_aux_usage(&device
->info
, image
, iview
->aspect_mask
,
756 VK_IMAGE_LAYOUT_GENERAL
);
757 iview
->optimal_sampler_aux_usage
=
758 anv_layout_to_aux_usage(&device
->info
, image
, iview
->aspect_mask
,
759 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
761 /* If this is a HiZ buffer we can sample from with a programmable clear
762 * value (SKL+), define the clear value to the optimal constant.
764 union isl_color_value clear_color
= { .u32
= { 0, } };
765 if ((iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
766 device
->info
.gen
>= 9)
767 clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
769 struct isl_view view
= iview
->isl
;
770 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
772 isl_surf_fill_state(&device
->isl_dev
,
773 iview
->optimal_sampler_surface_state
.map
,
774 .surf
= &surface
->isl
,
776 .clear_color
= clear_color
,
777 .aux_surf
= &image
->aux_surface
.isl
,
778 .aux_usage
= iview
->optimal_sampler_aux_usage
,
779 .mocs
= device
->default_mocs
);
781 isl_surf_fill_state(&device
->isl_dev
,
782 iview
->general_sampler_surface_state
.map
,
783 .surf
= &surface
->isl
,
785 .clear_color
= clear_color
,
786 .aux_surf
= &image
->aux_surface
.isl
,
787 .aux_usage
= iview
->general_sampler_aux_usage
,
788 .mocs
= device
->default_mocs
);
790 anv_state_flush(device
, iview
->optimal_sampler_surface_state
);
791 anv_state_flush(device
, iview
->general_sampler_surface_state
);
793 iview
->optimal_sampler_surface_state
.alloc_size
= 0;
794 iview
->general_sampler_surface_state
.alloc_size
= 0;
797 /* NOTE: This one needs to go last since it may stomp isl_view.format */
798 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
799 iview
->storage_surface_state
= alloc_surface_state(device
);
800 iview
->writeonly_storage_surface_state
= alloc_surface_state(device
);
802 struct isl_view view
= iview
->isl
;
803 view
.usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
805 /* Write-only accesses always used a typed write instruction and should
806 * therefore use the real format.
808 isl_surf_fill_state(&device
->isl_dev
,
809 iview
->writeonly_storage_surface_state
.map
,
810 .surf
= &surface
->isl
,
812 .aux_surf
= &image
->aux_surface
.isl
,
813 .aux_usage
= image
->aux_usage
,
814 .mocs
= device
->default_mocs
);
816 if (isl_has_matching_typed_storage_image_format(&device
->info
,
817 format
.isl_format
)) {
818 /* Typed surface reads support a very limited subset of the shader
819 * image formats. Translate it into the closest format the hardware
822 view
.format
= isl_lower_storage_image_format(&device
->info
,
825 isl_surf_fill_state(&device
->isl_dev
,
826 iview
->storage_surface_state
.map
,
827 .surf
= &surface
->isl
,
829 .aux_surf
= &image
->aux_surface
.isl
,
830 .aux_usage
= image
->aux_usage
,
831 .mocs
= device
->default_mocs
);
833 anv_fill_buffer_surface_state(device
, iview
->storage_surface_state
,
836 iview
->bo
->size
- iview
->offset
, 1);
839 isl_surf_fill_image_param(&device
->isl_dev
,
840 &iview
->storage_image_param
,
841 &surface
->isl
, &iview
->isl
);
843 anv_state_flush(device
, iview
->storage_surface_state
);
844 anv_state_flush(device
, iview
->writeonly_storage_surface_state
);
846 iview
->storage_surface_state
.alloc_size
= 0;
847 iview
->writeonly_storage_surface_state
.alloc_size
= 0;
850 *pView
= anv_image_view_to_handle(iview
);
856 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
857 const VkAllocationCallbacks
*pAllocator
)
859 ANV_FROM_HANDLE(anv_device
, device
, _device
);
860 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
865 if (iview
->optimal_sampler_surface_state
.alloc_size
> 0) {
866 anv_state_pool_free(&device
->surface_state_pool
,
867 iview
->optimal_sampler_surface_state
);
870 if (iview
->general_sampler_surface_state
.alloc_size
> 0) {
871 anv_state_pool_free(&device
->surface_state_pool
,
872 iview
->general_sampler_surface_state
);
875 if (iview
->storage_surface_state
.alloc_size
> 0) {
876 anv_state_pool_free(&device
->surface_state_pool
,
877 iview
->storage_surface_state
);
880 if (iview
->writeonly_storage_surface_state
.alloc_size
> 0) {
881 anv_state_pool_free(&device
->surface_state_pool
,
882 iview
->writeonly_storage_surface_state
);
885 vk_free2(&device
->alloc
, pAllocator
, iview
);
890 anv_CreateBufferView(VkDevice _device
,
891 const VkBufferViewCreateInfo
*pCreateInfo
,
892 const VkAllocationCallbacks
*pAllocator
,
895 ANV_FROM_HANDLE(anv_device
, device
, _device
);
896 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
897 struct anv_buffer_view
*view
;
899 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
900 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
902 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
904 /* TODO: Handle the format swizzle? */
906 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
907 VK_IMAGE_ASPECT_COLOR_BIT
,
908 VK_IMAGE_TILING_LINEAR
);
909 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
910 view
->bo
= buffer
->bo
;
911 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
912 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
914 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
916 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
917 view
->surface_state
= alloc_surface_state(device
);
919 anv_fill_buffer_surface_state(device
, view
->surface_state
,
921 view
->offset
, view
->range
, format_bs
);
923 view
->surface_state
= (struct anv_state
){ 0 };
926 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
927 view
->storage_surface_state
= alloc_surface_state(device
);
928 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
930 enum isl_format storage_format
=
931 isl_has_matching_typed_storage_image_format(&device
->info
,
933 isl_lower_storage_image_format(&device
->info
, view
->format
) :
936 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
938 view
->offset
, view
->range
,
939 (storage_format
== ISL_FORMAT_RAW
? 1 :
940 isl_format_get_layout(storage_format
)->bpb
/ 8));
942 /* Write-only accesses should use the original format. */
943 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
945 view
->offset
, view
->range
,
946 isl_format_get_layout(view
->format
)->bpb
/ 8);
948 isl_buffer_fill_image_param(&device
->isl_dev
,
949 &view
->storage_image_param
,
950 view
->format
, view
->range
);
952 view
->storage_surface_state
= (struct anv_state
){ 0 };
953 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
956 *pView
= anv_buffer_view_to_handle(view
);
962 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
963 const VkAllocationCallbacks
*pAllocator
)
965 ANV_FROM_HANDLE(anv_device
, device
, _device
);
966 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
971 if (view
->surface_state
.alloc_size
> 0)
972 anv_state_pool_free(&device
->surface_state_pool
,
973 view
->surface_state
);
975 if (view
->storage_surface_state
.alloc_size
> 0)
976 anv_state_pool_free(&device
->surface_state_pool
,
977 view
->storage_surface_state
);
979 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
980 anv_state_pool_free(&device
->surface_state_pool
,
981 view
->writeonly_storage_surface_state
);
983 vk_free2(&device
->alloc
, pAllocator
, view
);
986 const struct anv_surface
*
987 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
988 VkImageAspectFlags aspect_mask
)
990 switch (aspect_mask
) {
991 case VK_IMAGE_ASPECT_COLOR_BIT
:
992 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
993 return &image
->color_surface
;
994 case VK_IMAGE_ASPECT_DEPTH_BIT
:
995 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
996 return &image
->depth_surface
;
997 case VK_IMAGE_ASPECT_STENCIL_BIT
:
998 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
999 return &image
->stencil_surface
;
1000 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1001 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1002 * combined depth stencil formats. Specifically, it states:
1004 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1005 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1007 * Image views with both depth and stencil aspects are only valid for
1008 * render target attachments, in which case
1009 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1010 * stencil surfaces from the underlying surface.
1012 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1013 return &image
->depth_surface
;
1015 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1016 return &image
->stencil_surface
;
1019 unreachable("image does not have aspect");