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[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 const uint32_t *data =
127 spec_info->pData + spec_info->pMapEntries[i].offset;
128 assert((const void *)(data + 1) <=
129 spec_info->pData + spec_info->dataSize);
130
131 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
132 spec_entries[i].data = *data;
133 }
134 }
135
136 entry_point = spirv_to_nir(spirv, module->size / 4,
137 spec_entries, num_spec_entries,
138 stage, entrypoint_name, nir_options);
139 nir = entry_point->shader;
140 assert(nir->stage == stage);
141 nir_validate_shader(nir);
142
143 free(spec_entries);
144
145 nir_lower_returns(nir);
146 nir_validate_shader(nir);
147
148 nir_inline_functions(nir);
149 nir_validate_shader(nir);
150
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
153 if (func != entry_point)
154 exec_node_remove(&func->node);
155 }
156 assert(exec_list_length(&nir->functions) == 1);
157 entry_point->name = ralloc_strdup(entry_point, "main");
158
159 nir_remove_dead_variables(nir, nir_var_shader_in);
160 nir_remove_dead_variables(nir, nir_var_shader_out);
161 nir_remove_dead_variables(nir, nir_var_system_value);
162 nir_validate_shader(nir);
163
164 nir_lower_io_to_temporaries(entry_point->shader, entry_point, true, false);
165
166 nir_lower_system_values(nir);
167 nir_validate_shader(nir);
168 }
169
170 /* Vulkan uses the separate-shader linking model */
171 nir->info.separate_shader = true;
172
173 nir = brw_preprocess_nir(compiler, nir);
174
175 nir_shader_gather_info(nir, entry_point->impl);
176
177 nir_variable_mode indirect_mask = 0;
178 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
179 indirect_mask |= nir_var_shader_in;
180 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
181 indirect_mask |= nir_var_local;
182
183 nir_lower_indirect_derefs(nir, indirect_mask);
184
185 return nir;
186 }
187
188 void anv_DestroyPipeline(
189 VkDevice _device,
190 VkPipeline _pipeline,
191 const VkAllocationCallbacks* pAllocator)
192 {
193 ANV_FROM_HANDLE(anv_device, device, _device);
194 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
195
196 anv_reloc_list_finish(&pipeline->batch_relocs,
197 pAllocator ? pAllocator : &device->alloc);
198 if (pipeline->blend_state.map)
199 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
200 anv_free2(&device->alloc, pAllocator, pipeline);
201 }
202
203 static const uint32_t vk_to_gen_primitive_type[] = {
204 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
205 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
206 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
207 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
208 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
209 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
211 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
214 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
215 };
216
217 static void
218 populate_sampler_prog_key(const struct brw_device_info *devinfo,
219 struct brw_sampler_prog_key_data *key)
220 {
221 /* XXX: Handle texture swizzle on HSW- */
222 for (int i = 0; i < MAX_SAMPLERS; i++) {
223 /* Assume color sampler, no swizzling. (Works for BDW+) */
224 key->swizzles[i] = SWIZZLE_XYZW;
225 }
226 }
227
228 static void
229 populate_vs_prog_key(const struct brw_device_info *devinfo,
230 struct brw_vs_prog_key *key)
231 {
232 memset(key, 0, sizeof(*key));
233
234 populate_sampler_prog_key(devinfo, &key->tex);
235
236 /* XXX: Handle vertex input work-arounds */
237
238 /* XXX: Handle sampler_prog_key */
239 }
240
241 static void
242 populate_gs_prog_key(const struct brw_device_info *devinfo,
243 struct brw_gs_prog_key *key)
244 {
245 memset(key, 0, sizeof(*key));
246
247 populate_sampler_prog_key(devinfo, &key->tex);
248 }
249
250 static void
251 populate_wm_prog_key(const struct brw_device_info *devinfo,
252 const VkGraphicsPipelineCreateInfo *info,
253 const struct anv_graphics_pipeline_create_info *extra,
254 struct brw_wm_prog_key *key)
255 {
256 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
257
258 memset(key, 0, sizeof(*key));
259
260 populate_sampler_prog_key(devinfo, &key->tex);
261
262 /* TODO: Fill out key->input_slots_valid */
263
264 /* Vulkan doesn't specify a default */
265 key->high_quality_derivatives = false;
266
267 /* XXX Vulkan doesn't appear to specify */
268 key->clamp_fragment_color = false;
269
270 /* Vulkan always specifies upper-left coordinates */
271 key->drawable_height = 0;
272 key->render_to_fbo = false;
273
274 if (extra && extra->color_attachment_count >= 0) {
275 key->nr_color_regions = extra->color_attachment_count;
276 } else {
277 key->nr_color_regions =
278 render_pass->subpasses[info->subpass].color_count;
279 }
280
281 key->replicate_alpha = key->nr_color_regions > 1 &&
282 info->pMultisampleState &&
283 info->pMultisampleState->alphaToCoverageEnable;
284
285 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
286 /* We should probably pull this out of the shader, but it's fairly
287 * harmless to compute it and then let dead-code take care of it.
288 */
289 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
290 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
291 key->multisample_fbo = true;
292 }
293 }
294
295 static void
296 populate_cs_prog_key(const struct brw_device_info *devinfo,
297 struct brw_cs_prog_key *key)
298 {
299 memset(key, 0, sizeof(*key));
300
301 populate_sampler_prog_key(devinfo, &key->tex);
302 }
303
304 static nir_shader *
305 anv_pipeline_compile(struct anv_pipeline *pipeline,
306 struct anv_shader_module *module,
307 const char *entrypoint,
308 gl_shader_stage stage,
309 const VkSpecializationInfo *spec_info,
310 struct brw_stage_prog_data *prog_data,
311 struct anv_pipeline_bind_map *map)
312 {
313 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
314 module, entrypoint, stage,
315 spec_info);
316 if (nir == NULL)
317 return NULL;
318
319 anv_nir_lower_push_constants(nir);
320
321 /* Figure out the number of parameters */
322 prog_data->nr_params = 0;
323
324 if (nir->num_uniforms > 0) {
325 /* If the shader uses any push constants at all, we'll just give
326 * them the maximum possible number
327 */
328 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
329 }
330
331 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
332 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
333
334 if (nir->info.num_images > 0)
335 prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
336
337 if (prog_data->nr_params > 0) {
338 /* XXX: I think we're leaking this */
339 prog_data->param = (const union gl_constant_value **)
340 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
341
342 /* We now set the param values to be offsets into a
343 * anv_push_constant_data structure. Since the compiler doesn't
344 * actually dereference any of the gl_constant_value pointers in the
345 * params array, it doesn't really matter what we put here.
346 */
347 struct anv_push_constants *null_data = NULL;
348 if (nir->num_uniforms > 0) {
349 /* Fill out the push constants section of the param array */
350 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
351 prog_data->param[i] = (const union gl_constant_value *)
352 &null_data->client_data[i * sizeof(float)];
353 }
354 }
355
356 /* Set up dynamic offsets */
357 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
358
359 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
360 if (pipeline->layout)
361 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
362
363 /* nir_lower_io will only handle the push constants; we need to set this
364 * to the full number of possible uniforms.
365 */
366 nir->num_uniforms = prog_data->nr_params * 4;
367
368 return nir;
369 }
370
371 static void
372 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
373 {
374 prog_data->binding_table.size_bytes = 0;
375 prog_data->binding_table.texture_start = bias;
376 prog_data->binding_table.ubo_start = bias;
377 prog_data->binding_table.ssbo_start = bias;
378 prog_data->binding_table.image_start = bias;
379 }
380
381 static void
382 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
383 gl_shader_stage stage,
384 const struct brw_stage_prog_data *prog_data,
385 struct anv_pipeline_bind_map *map)
386 {
387 struct brw_device_info *devinfo = &pipeline->device->info;
388 uint32_t max_threads[] = {
389 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
390 [MESA_SHADER_TESS_CTRL] = devinfo->max_hs_threads,
391 [MESA_SHADER_TESS_EVAL] = devinfo->max_ds_threads,
392 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
393 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
394 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
395 };
396
397 pipeline->prog_data[stage] = prog_data;
398 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
399 pipeline->scratch_start[stage] = pipeline->total_scratch;
400 pipeline->total_scratch =
401 align_u32(pipeline->total_scratch, 1024) +
402 prog_data->total_scratch * max_threads[stage];
403 pipeline->bindings[stage] = *map;
404 }
405
406 static VkResult
407 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
408 struct anv_pipeline_cache *cache,
409 const VkGraphicsPipelineCreateInfo *info,
410 struct anv_shader_module *module,
411 const char *entrypoint,
412 const VkSpecializationInfo *spec_info)
413 {
414 const struct brw_compiler *compiler =
415 pipeline->device->instance->physicalDevice.compiler;
416 const struct brw_stage_prog_data *stage_prog_data;
417 struct anv_pipeline_bind_map map;
418 struct brw_vs_prog_key key;
419 uint32_t kernel = NO_KERNEL;
420 unsigned char sha1[20];
421
422 populate_vs_prog_key(&pipeline->device->info, &key);
423
424 if (module->size > 0) {
425 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
426 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
427 }
428
429 if (kernel == NO_KERNEL) {
430 struct brw_vs_prog_data prog_data = { 0, };
431 struct anv_pipeline_binding surface_to_descriptor[256];
432 struct anv_pipeline_binding sampler_to_descriptor[256];
433
434 map = (struct anv_pipeline_bind_map) {
435 .surface_to_descriptor = surface_to_descriptor,
436 .sampler_to_descriptor = sampler_to_descriptor
437 };
438
439 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
440 MESA_SHADER_VERTEX, spec_info,
441 &prog_data.base.base, &map);
442 if (nir == NULL)
443 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
444
445 anv_fill_binding_table(&prog_data.base.base, 0);
446
447 void *mem_ctx = ralloc_context(NULL);
448
449 if (module->nir == NULL)
450 ralloc_steal(mem_ctx, nir);
451
452 prog_data.inputs_read = nir->info.inputs_read;
453
454 brw_compute_vue_map(&pipeline->device->info,
455 &prog_data.base.vue_map,
456 nir->info.outputs_written,
457 nir->info.separate_shader);
458
459 unsigned code_size;
460 const unsigned *shader_code =
461 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
462 NULL, false, -1, &code_size, NULL);
463 if (shader_code == NULL) {
464 ralloc_free(mem_ctx);
465 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
466 }
467
468 stage_prog_data = &prog_data.base.base;
469 kernel = anv_pipeline_cache_upload_kernel(cache,
470 module->size > 0 ? sha1 : NULL,
471 shader_code, code_size,
472 &stage_prog_data, sizeof(prog_data),
473 &map);
474 ralloc_free(mem_ctx);
475 }
476
477 const struct brw_vs_prog_data *vs_prog_data =
478 (const struct brw_vs_prog_data *) stage_prog_data;
479
480 if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
481 pipeline->vs_simd8 = kernel;
482 pipeline->vs_vec4 = NO_KERNEL;
483 } else {
484 pipeline->vs_simd8 = NO_KERNEL;
485 pipeline->vs_vec4 = kernel;
486 }
487
488 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
489 stage_prog_data, &map);
490
491 return VK_SUCCESS;
492 }
493
494 static VkResult
495 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
496 struct anv_pipeline_cache *cache,
497 const VkGraphicsPipelineCreateInfo *info,
498 struct anv_shader_module *module,
499 const char *entrypoint,
500 const VkSpecializationInfo *spec_info)
501 {
502 const struct brw_compiler *compiler =
503 pipeline->device->instance->physicalDevice.compiler;
504 const struct brw_stage_prog_data *stage_prog_data;
505 struct anv_pipeline_bind_map map;
506 struct brw_gs_prog_key key;
507 uint32_t kernel = NO_KERNEL;
508 unsigned char sha1[20];
509
510 populate_gs_prog_key(&pipeline->device->info, &key);
511
512 if (module->size > 0) {
513 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
514 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
515 }
516
517 if (kernel == NO_KERNEL) {
518 struct brw_gs_prog_data prog_data = { 0, };
519 struct anv_pipeline_binding surface_to_descriptor[256];
520 struct anv_pipeline_binding sampler_to_descriptor[256];
521
522 map = (struct anv_pipeline_bind_map) {
523 .surface_to_descriptor = surface_to_descriptor,
524 .sampler_to_descriptor = sampler_to_descriptor
525 };
526
527 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
528 MESA_SHADER_GEOMETRY, spec_info,
529 &prog_data.base.base, &map);
530 if (nir == NULL)
531 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
532
533 anv_fill_binding_table(&prog_data.base.base, 0);
534
535 void *mem_ctx = ralloc_context(NULL);
536
537 if (module->nir == NULL)
538 ralloc_steal(mem_ctx, nir);
539
540 brw_compute_vue_map(&pipeline->device->info,
541 &prog_data.base.vue_map,
542 nir->info.outputs_written,
543 nir->info.separate_shader);
544
545 unsigned code_size;
546 const unsigned *shader_code =
547 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
548 NULL, -1, &code_size, NULL);
549 if (shader_code == NULL) {
550 ralloc_free(mem_ctx);
551 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
552 }
553
554 /* TODO: SIMD8 GS */
555 stage_prog_data = &prog_data.base.base;
556 kernel = anv_pipeline_cache_upload_kernel(cache,
557 module->size > 0 ? sha1 : NULL,
558 shader_code, code_size,
559 &stage_prog_data, sizeof(prog_data),
560 &map);
561
562 ralloc_free(mem_ctx);
563 }
564
565 pipeline->gs_kernel = kernel;
566
567 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
568 stage_prog_data, &map);
569
570 return VK_SUCCESS;
571 }
572
573 static VkResult
574 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
575 struct anv_pipeline_cache *cache,
576 const VkGraphicsPipelineCreateInfo *info,
577 const struct anv_graphics_pipeline_create_info *extra,
578 struct anv_shader_module *module,
579 const char *entrypoint,
580 const VkSpecializationInfo *spec_info)
581 {
582 const struct brw_compiler *compiler =
583 pipeline->device->instance->physicalDevice.compiler;
584 const struct brw_stage_prog_data *stage_prog_data;
585 struct anv_pipeline_bind_map map;
586 struct brw_wm_prog_key key;
587 uint32_t kernel = NO_KERNEL;
588 unsigned char sha1[20];
589
590 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
591
592 if (module->size > 0) {
593 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
594 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
595 }
596
597 if (kernel == NO_KERNEL) {
598 struct brw_wm_prog_data prog_data = { 0, };
599 struct anv_pipeline_binding surface_to_descriptor[256];
600 struct anv_pipeline_binding sampler_to_descriptor[256];
601
602 map = (struct anv_pipeline_bind_map) {
603 .surface_to_descriptor = surface_to_descriptor + 8,
604 .sampler_to_descriptor = sampler_to_descriptor
605 };
606
607 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
608 MESA_SHADER_FRAGMENT, spec_info,
609 &prog_data.base, &map);
610 if (nir == NULL)
611 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
612
613 unsigned num_rts = 0;
614 struct anv_pipeline_binding rt_bindings[8];
615 nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
616 nir_foreach_variable_safe(var, &nir->outputs) {
617 if (var->data.location < FRAG_RESULT_DATA0)
618 continue;
619
620 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
621 if (rt >= key.nr_color_regions) {
622 /* Out-of-bounds, throw it away */
623 var->data.mode = nir_var_local;
624 exec_node_remove(&var->node);
625 exec_list_push_tail(&impl->locals, &var->node);
626 continue;
627 }
628
629 /* Give it a new, compacted, location */
630 var->data.location = FRAG_RESULT_DATA0 + num_rts;
631
632 unsigned array_len =
633 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
634 assert(num_rts + array_len <= 8);
635
636 for (unsigned i = 0; i < array_len; i++) {
637 rt_bindings[num_rts] = (struct anv_pipeline_binding) {
638 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
639 .offset = rt + i,
640 };
641 }
642
643 num_rts += array_len;
644 }
645
646 if (pipeline->use_repclear) {
647 assert(num_rts == 1);
648 key.nr_color_regions = 1;
649 }
650
651 if (num_rts == 0) {
652 /* If we have no render targets, we need a null render target */
653 rt_bindings[0] = (struct anv_pipeline_binding) {
654 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
655 .offset = UINT16_MAX,
656 };
657 num_rts = 1;
658 }
659
660 assert(num_rts <= 8);
661 map.surface_to_descriptor -= num_rts;
662 map.surface_count += num_rts;
663 assert(map.surface_count <= 256);
664 memcpy(map.surface_to_descriptor, rt_bindings,
665 num_rts * sizeof(*rt_bindings));
666
667 anv_fill_binding_table(&prog_data.base, num_rts);
668
669 void *mem_ctx = ralloc_context(NULL);
670
671 if (module->nir == NULL)
672 ralloc_steal(mem_ctx, nir);
673
674 unsigned code_size;
675 const unsigned *shader_code =
676 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
677 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
678 if (shader_code == NULL) {
679 ralloc_free(mem_ctx);
680 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
681 }
682
683 stage_prog_data = &prog_data.base;
684 kernel = anv_pipeline_cache_upload_kernel(cache,
685 module->size > 0 ? sha1 : NULL,
686 shader_code, code_size,
687 &stage_prog_data, sizeof(prog_data),
688 &map);
689
690 ralloc_free(mem_ctx);
691 }
692
693 const struct brw_wm_prog_data *wm_prog_data =
694 (const struct brw_wm_prog_data *) stage_prog_data;
695
696 if (wm_prog_data->no_8)
697 pipeline->ps_simd8 = NO_KERNEL;
698 else
699 pipeline->ps_simd8 = kernel;
700
701 if (wm_prog_data->no_8 || wm_prog_data->prog_offset_16) {
702 pipeline->ps_simd16 = kernel + wm_prog_data->prog_offset_16;
703 } else {
704 pipeline->ps_simd16 = NO_KERNEL;
705 }
706
707 pipeline->ps_ksp2 = 0;
708 pipeline->ps_grf_start2 = 0;
709 if (pipeline->ps_simd8 != NO_KERNEL) {
710 pipeline->ps_ksp0 = pipeline->ps_simd8;
711 pipeline->ps_grf_start0 = wm_prog_data->base.dispatch_grf_start_reg;
712 if (pipeline->ps_simd16 != NO_KERNEL) {
713 pipeline->ps_ksp2 = pipeline->ps_simd16;
714 pipeline->ps_grf_start2 = wm_prog_data->dispatch_grf_start_reg_16;
715 }
716 } else if (pipeline->ps_simd16 != NO_KERNEL) {
717 pipeline->ps_ksp0 = pipeline->ps_simd16;
718 pipeline->ps_grf_start0 = wm_prog_data->dispatch_grf_start_reg_16;
719 }
720
721 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
722 stage_prog_data, &map);
723
724 return VK_SUCCESS;
725 }
726
727 VkResult
728 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
729 struct anv_pipeline_cache *cache,
730 const VkComputePipelineCreateInfo *info,
731 struct anv_shader_module *module,
732 const char *entrypoint,
733 const VkSpecializationInfo *spec_info)
734 {
735 const struct brw_compiler *compiler =
736 pipeline->device->instance->physicalDevice.compiler;
737 const struct brw_stage_prog_data *stage_prog_data;
738 struct anv_pipeline_bind_map map;
739 struct brw_cs_prog_key key;
740 uint32_t kernel = NO_KERNEL;
741 unsigned char sha1[20];
742
743 populate_cs_prog_key(&pipeline->device->info, &key);
744
745 if (module->size > 0) {
746 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
747 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
748 }
749
750 if (module->size == 0 || kernel == NO_KERNEL) {
751 struct brw_cs_prog_data prog_data = { 0, };
752 struct anv_pipeline_binding surface_to_descriptor[256];
753 struct anv_pipeline_binding sampler_to_descriptor[256];
754
755 map = (struct anv_pipeline_bind_map) {
756 .surface_to_descriptor = surface_to_descriptor,
757 .sampler_to_descriptor = sampler_to_descriptor
758 };
759
760 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
761 MESA_SHADER_COMPUTE, spec_info,
762 &prog_data.base, &map);
763 if (nir == NULL)
764 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
765
766 anv_fill_binding_table(&prog_data.base, 1);
767
768 void *mem_ctx = ralloc_context(NULL);
769
770 if (module->nir == NULL)
771 ralloc_steal(mem_ctx, nir);
772
773 unsigned code_size;
774 const unsigned *shader_code =
775 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
776 -1, &code_size, NULL);
777 if (shader_code == NULL) {
778 ralloc_free(mem_ctx);
779 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
780 }
781
782 stage_prog_data = &prog_data.base;
783 kernel = anv_pipeline_cache_upload_kernel(cache,
784 module->size > 0 ? sha1 : NULL,
785 shader_code, code_size,
786 &stage_prog_data, sizeof(prog_data),
787 &map);
788
789 ralloc_free(mem_ctx);
790 }
791
792 pipeline->cs_simd = kernel;
793
794 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
795 stage_prog_data, &map);
796
797 return VK_SUCCESS;
798 }
799
800 static void
801 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
802 {
803 const struct brw_device_info *devinfo = &pipeline->device->info;
804 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
805 unsigned vs_size = vs_present ?
806 get_vs_prog_data(pipeline)->base.urb_entry_size : 1;
807 unsigned vs_entry_size_bytes = vs_size * 64;
808 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
809 unsigned gs_size = gs_present ?
810 get_gs_prog_data(pipeline)->base.urb_entry_size : 1;
811 unsigned gs_entry_size_bytes = gs_size * 64;
812
813 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
814 *
815 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
816 * Allocation Size is less than 9 512-bit URB entries.
817 *
818 * Similar text exists for GS.
819 */
820 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
821 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
822
823 /* URB allocations must be done in 8k chunks. */
824 unsigned chunk_size_bytes = 8192;
825
826 /* Determine the size of the URB in chunks. */
827 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
828
829 /* Reserve space for push constants */
830 unsigned push_constant_kb;
831 if (pipeline->device->info.gen >= 8)
832 push_constant_kb = 32;
833 else if (pipeline->device->info.is_haswell)
834 push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
835 else
836 push_constant_kb = 16;
837
838 unsigned push_constant_bytes = push_constant_kb * 1024;
839 unsigned push_constant_chunks =
840 push_constant_bytes / chunk_size_bytes;
841
842 /* Initially, assign each stage the minimum amount of URB space it needs,
843 * and make a note of how much additional space it "wants" (the amount of
844 * additional space it could actually make use of).
845 */
846
847 /* VS has a lower limit on the number of URB entries */
848 unsigned vs_chunks =
849 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
850 chunk_size_bytes) / chunk_size_bytes;
851 unsigned vs_wants =
852 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
853 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
854
855 unsigned gs_chunks = 0;
856 unsigned gs_wants = 0;
857 if (gs_present) {
858 /* There are two constraints on the minimum amount of URB space we can
859 * allocate:
860 *
861 * (1) We need room for at least 2 URB entries, since we always operate
862 * the GS in DUAL_OBJECT mode.
863 *
864 * (2) We can't allocate less than nr_gs_entries_granularity.
865 */
866 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
867 chunk_size_bytes) / chunk_size_bytes;
868 gs_wants =
869 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
870 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
871 }
872
873 /* There should always be enough URB space to satisfy the minimum
874 * requirements of each stage.
875 */
876 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
877 assert(total_needs <= urb_chunks);
878
879 /* Mete out remaining space (if any) in proportion to "wants". */
880 unsigned total_wants = vs_wants + gs_wants;
881 unsigned remaining_space = urb_chunks - total_needs;
882 if (remaining_space > total_wants)
883 remaining_space = total_wants;
884 if (remaining_space > 0) {
885 unsigned vs_additional = (unsigned)
886 round(vs_wants * (((double) remaining_space) / total_wants));
887 vs_chunks += vs_additional;
888 remaining_space -= vs_additional;
889 gs_chunks += remaining_space;
890 }
891
892 /* Sanity check that we haven't over-allocated. */
893 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
894
895 /* Finally, compute the number of entries that can fit in the space
896 * allocated to each stage.
897 */
898 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
899 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
900
901 /* Since we rounded up when computing *_wants, this may be slightly more
902 * than the maximum allowed amount, so correct for that.
903 */
904 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
905 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
906
907 /* Ensure that we program a multiple of the granularity. */
908 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
909 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
910
911 /* Finally, sanity check to make sure we have at least the minimum number
912 * of entries needed for each stage.
913 */
914 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
915 if (gs_present)
916 assert(nr_gs_entries >= 2);
917
918 /* Lay out the URB in the following order:
919 * - push constants
920 * - VS
921 * - GS
922 */
923 pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
924 pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
925 pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
926
927 pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
928 pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
929 pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
930
931 pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
932 pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
933 pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
934
935 pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
936 pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
937 pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
938
939 const unsigned stages =
940 _mesa_bitcount(pipeline->active_stages & VK_SHADER_STAGE_ALL_GRAPHICS);
941 unsigned size_per_stage = stages ? (push_constant_kb / stages) : 0;
942 unsigned used_kb = 0;
943
944 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
945 * units of 2KB. Incidentally, these are the same platforms that have
946 * 32KB worth of push constant space.
947 */
948 if (push_constant_kb == 32)
949 size_per_stage &= ~1u;
950
951 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
952 pipeline->urb.push_size[i] =
953 (pipeline->active_stages & (1 << i)) ? size_per_stage : 0;
954 used_kb += pipeline->urb.push_size[i];
955 assert(used_kb <= push_constant_kb);
956 }
957
958 pipeline->urb.push_size[MESA_SHADER_FRAGMENT] =
959 push_constant_kb - used_kb;
960 }
961
962 static void
963 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
964 const VkGraphicsPipelineCreateInfo *pCreateInfo)
965 {
966 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
967 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
968 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
969
970 pipeline->dynamic_state = default_dynamic_state;
971
972 if (pCreateInfo->pDynamicState) {
973 /* Remove all of the states that are marked as dynamic */
974 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
975 for (uint32_t s = 0; s < count; s++)
976 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
977 }
978
979 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
980
981 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
982 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
983 typed_memcpy(dynamic->viewport.viewports,
984 pCreateInfo->pViewportState->pViewports,
985 pCreateInfo->pViewportState->viewportCount);
986 }
987
988 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
989 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
990 typed_memcpy(dynamic->scissor.scissors,
991 pCreateInfo->pViewportState->pScissors,
992 pCreateInfo->pViewportState->scissorCount);
993 }
994
995 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
996 assert(pCreateInfo->pRasterizationState);
997 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
998 }
999
1000 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1001 assert(pCreateInfo->pRasterizationState);
1002 dynamic->depth_bias.bias =
1003 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1004 dynamic->depth_bias.clamp =
1005 pCreateInfo->pRasterizationState->depthBiasClamp;
1006 dynamic->depth_bias.slope =
1007 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1008 }
1009
1010 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1011 assert(pCreateInfo->pColorBlendState);
1012 typed_memcpy(dynamic->blend_constants,
1013 pCreateInfo->pColorBlendState->blendConstants, 4);
1014 }
1015
1016 /* If there is no depthstencil attachment, then don't read
1017 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1018 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1019 * no need to override the depthstencil defaults in
1020 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1021 *
1022 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
1023 *
1024 * pDepthStencilState [...] may only be NULL if renderPass and subpass
1025 * specify a subpass that has no depth/stencil attachment.
1026 */
1027 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1028 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1029 assert(pCreateInfo->pDepthStencilState);
1030 dynamic->depth_bounds.min =
1031 pCreateInfo->pDepthStencilState->minDepthBounds;
1032 dynamic->depth_bounds.max =
1033 pCreateInfo->pDepthStencilState->maxDepthBounds;
1034 }
1035
1036 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1037 assert(pCreateInfo->pDepthStencilState);
1038 dynamic->stencil_compare_mask.front =
1039 pCreateInfo->pDepthStencilState->front.compareMask;
1040 dynamic->stencil_compare_mask.back =
1041 pCreateInfo->pDepthStencilState->back.compareMask;
1042 }
1043
1044 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1045 assert(pCreateInfo->pDepthStencilState);
1046 dynamic->stencil_write_mask.front =
1047 pCreateInfo->pDepthStencilState->front.writeMask;
1048 dynamic->stencil_write_mask.back =
1049 pCreateInfo->pDepthStencilState->back.writeMask;
1050 }
1051
1052 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1053 assert(pCreateInfo->pDepthStencilState);
1054 dynamic->stencil_reference.front =
1055 pCreateInfo->pDepthStencilState->front.reference;
1056 dynamic->stencil_reference.back =
1057 pCreateInfo->pDepthStencilState->back.reference;
1058 }
1059 }
1060
1061 pipeline->dynamic_state_mask = states;
1062 }
1063
1064 static void
1065 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1066 {
1067 struct anv_render_pass *renderpass = NULL;
1068 struct anv_subpass *subpass = NULL;
1069
1070 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1071 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1072 * 4.2 Graphics Pipeline.
1073 */
1074 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1075
1076 renderpass = anv_render_pass_from_handle(info->renderPass);
1077 assert(renderpass);
1078
1079 if (renderpass != &anv_meta_dummy_renderpass) {
1080 assert(info->subpass < renderpass->subpass_count);
1081 subpass = &renderpass->subpasses[info->subpass];
1082 }
1083
1084 assert(info->stageCount >= 1);
1085 assert(info->pVertexInputState);
1086 assert(info->pInputAssemblyState);
1087 assert(info->pViewportState);
1088 assert(info->pRasterizationState);
1089
1090 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1091 assert(info->pDepthStencilState);
1092
1093 if (subpass && subpass->color_count > 0)
1094 assert(info->pColorBlendState);
1095
1096 for (uint32_t i = 0; i < info->stageCount; ++i) {
1097 switch (info->pStages[i].stage) {
1098 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1099 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1100 assert(info->pTessellationState);
1101 break;
1102 default:
1103 break;
1104 }
1105 }
1106 }
1107
1108 VkResult
1109 anv_pipeline_init(struct anv_pipeline *pipeline,
1110 struct anv_device *device,
1111 struct anv_pipeline_cache *cache,
1112 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1113 const struct anv_graphics_pipeline_create_info *extra,
1114 const VkAllocationCallbacks *alloc)
1115 {
1116 VkResult result;
1117
1118 anv_validate {
1119 anv_pipeline_validate_create_info(pCreateInfo);
1120 }
1121
1122 if (alloc == NULL)
1123 alloc = &device->alloc;
1124
1125 pipeline->device = device;
1126 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1127
1128 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1129 if (result != VK_SUCCESS)
1130 return result;
1131
1132 pipeline->batch.alloc = alloc;
1133 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1134 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1135 pipeline->batch.relocs = &pipeline->batch_relocs;
1136
1137 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1138
1139 pipeline->use_repclear = extra && extra->use_repclear;
1140
1141 /* When we free the pipeline, we detect stages based on the NULL status
1142 * of various prog_data pointers. Make them NULL by default.
1143 */
1144 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1145 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1146 memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1147
1148 pipeline->vs_simd8 = NO_KERNEL;
1149 pipeline->vs_vec4 = NO_KERNEL;
1150 pipeline->gs_kernel = NO_KERNEL;
1151 pipeline->ps_ksp0 = NO_KERNEL;
1152
1153 pipeline->active_stages = 0;
1154 pipeline->total_scratch = 0;
1155
1156 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1157 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1158 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1159 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1160 pStages[stage] = &pCreateInfo->pStages[i];
1161 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1162 }
1163
1164 if (modules[MESA_SHADER_VERTEX]) {
1165 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1166 modules[MESA_SHADER_VERTEX],
1167 pStages[MESA_SHADER_VERTEX]->pName,
1168 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1169 }
1170
1171 if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
1172 anv_finishme("no tessellation support");
1173
1174 if (modules[MESA_SHADER_GEOMETRY]) {
1175 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1176 modules[MESA_SHADER_GEOMETRY],
1177 pStages[MESA_SHADER_GEOMETRY]->pName,
1178 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1179 }
1180
1181 if (modules[MESA_SHADER_FRAGMENT]) {
1182 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra,
1183 modules[MESA_SHADER_FRAGMENT],
1184 pStages[MESA_SHADER_FRAGMENT]->pName,
1185 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1186 }
1187
1188 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1189 /* Vertex is only optional if disable_vs is set */
1190 assert(extra->disable_vs);
1191 }
1192
1193 gen7_compute_urb_partition(pipeline);
1194
1195 const VkPipelineVertexInputStateCreateInfo *vi_info =
1196 pCreateInfo->pVertexInputState;
1197
1198 uint64_t inputs_read;
1199 if (extra && extra->disable_vs) {
1200 /* If the VS is disabled, just assume the user knows what they're
1201 * doing and apply the layout blindly. This can only come from
1202 * meta, so this *should* be safe.
1203 */
1204 inputs_read = ~0ull;
1205 } else {
1206 inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1207 }
1208
1209 pipeline->vb_used = 0;
1210 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1211 const VkVertexInputAttributeDescription *desc =
1212 &vi_info->pVertexAttributeDescriptions[i];
1213
1214 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1215 pipeline->vb_used |= 1 << desc->binding;
1216 }
1217
1218 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1219 const VkVertexInputBindingDescription *desc =
1220 &vi_info->pVertexBindingDescriptions[i];
1221
1222 pipeline->binding_stride[desc->binding] = desc->stride;
1223
1224 /* Step rate is programmed per vertex element (attribute), not
1225 * binding. Set up a map of which bindings step per instance, for
1226 * reference by vertex element setup. */
1227 switch (desc->inputRate) {
1228 default:
1229 case VK_VERTEX_INPUT_RATE_VERTEX:
1230 pipeline->instancing_enable[desc->binding] = false;
1231 break;
1232 case VK_VERTEX_INPUT_RATE_INSTANCE:
1233 pipeline->instancing_enable[desc->binding] = true;
1234 break;
1235 }
1236 }
1237
1238 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1239 pCreateInfo->pInputAssemblyState;
1240 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1241 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1242
1243 if (extra && extra->use_rectlist)
1244 pipeline->topology = _3DPRIM_RECTLIST;
1245
1246 while (anv_block_pool_size(&device->scratch_block_pool) <
1247 pipeline->total_scratch)
1248 anv_block_pool_alloc(&device->scratch_block_pool);
1249
1250 return VK_SUCCESS;
1251 }
1252
1253 VkResult
1254 anv_graphics_pipeline_create(
1255 VkDevice _device,
1256 VkPipelineCache _cache,
1257 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1258 const struct anv_graphics_pipeline_create_info *extra,
1259 const VkAllocationCallbacks *pAllocator,
1260 VkPipeline *pPipeline)
1261 {
1262 ANV_FROM_HANDLE(anv_device, device, _device);
1263 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1264
1265 if (cache == NULL)
1266 cache = &device->default_pipeline_cache;
1267
1268 switch (device->info.gen) {
1269 case 7:
1270 if (device->info.is_haswell)
1271 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1272 else
1273 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1274 case 8:
1275 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1276 case 9:
1277 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1278 default:
1279 unreachable("unsupported gen\n");
1280 }
1281 }
1282
1283 VkResult anv_CreateGraphicsPipelines(
1284 VkDevice _device,
1285 VkPipelineCache pipelineCache,
1286 uint32_t count,
1287 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1288 const VkAllocationCallbacks* pAllocator,
1289 VkPipeline* pPipelines)
1290 {
1291 VkResult result = VK_SUCCESS;
1292
1293 unsigned i = 0;
1294 for (; i < count; i++) {
1295 result = anv_graphics_pipeline_create(_device,
1296 pipelineCache,
1297 &pCreateInfos[i],
1298 NULL, pAllocator, &pPipelines[i]);
1299 if (result != VK_SUCCESS) {
1300 for (unsigned j = 0; j < i; j++) {
1301 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1302 }
1303
1304 return result;
1305 }
1306 }
1307
1308 return VK_SUCCESS;
1309 }
1310
1311 static VkResult anv_compute_pipeline_create(
1312 VkDevice _device,
1313 VkPipelineCache _cache,
1314 const VkComputePipelineCreateInfo* pCreateInfo,
1315 const VkAllocationCallbacks* pAllocator,
1316 VkPipeline* pPipeline)
1317 {
1318 ANV_FROM_HANDLE(anv_device, device, _device);
1319 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1320
1321 if (cache == NULL)
1322 cache = &device->default_pipeline_cache;
1323
1324 switch (device->info.gen) {
1325 case 7:
1326 if (device->info.is_haswell)
1327 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1328 else
1329 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1330 case 8:
1331 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1332 case 9:
1333 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1334 default:
1335 unreachable("unsupported gen\n");
1336 }
1337 }
1338
1339 VkResult anv_CreateComputePipelines(
1340 VkDevice _device,
1341 VkPipelineCache pipelineCache,
1342 uint32_t count,
1343 const VkComputePipelineCreateInfo* pCreateInfos,
1344 const VkAllocationCallbacks* pAllocator,
1345 VkPipeline* pPipelines)
1346 {
1347 VkResult result = VK_SUCCESS;
1348
1349 unsigned i = 0;
1350 for (; i < count; i++) {
1351 result = anv_compute_pipeline_create(_device, pipelineCache,
1352 &pCreateInfos[i],
1353 pAllocator, &pPipelines[i]);
1354 if (result != VK_SUCCESS) {
1355 for (unsigned j = 0; j < i; j++) {
1356 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1357 }
1358
1359 return result;
1360 }
1361 }
1362
1363 return VK_SUCCESS;
1364 }