2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 struct anv_spirv_debug_data
{
99 struct anv_device
*device
;
100 const struct anv_shader_module
*module
;
103 static void anv_spirv_nir_debug(void *private_data
,
104 enum nir_spirv_debug_level level
,
108 struct anv_spirv_debug_data
*debug_data
= private_data
;
109 static const VkDebugReportFlagsEXT vk_flags
[] = {
110 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
111 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
112 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
116 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
118 vk_debug_report(&debug_data
->device
->instance
->debug_report_callbacks
,
120 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
121 (uint64_t) (uintptr_t) debug_data
->module
,
122 0, 0, "anv", buffer
);
125 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
126 * we can't do that yet because we don't have the ability to copy nir.
129 anv_shader_compile_to_nir(struct anv_device
*device
,
131 const struct anv_shader_module
*module
,
132 const char *entrypoint_name
,
133 gl_shader_stage stage
,
134 const VkSpecializationInfo
*spec_info
)
136 const struct anv_physical_device
*pdevice
=
137 &device
->instance
->physicalDevice
;
138 const struct brw_compiler
*compiler
= pdevice
->compiler
;
139 const nir_shader_compiler_options
*nir_options
=
140 compiler
->glsl_compiler_options
[stage
].NirOptions
;
142 uint32_t *spirv
= (uint32_t *) module
->data
;
143 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
144 assert(module
->size
% 4 == 0);
146 uint32_t num_spec_entries
= 0;
147 struct nir_spirv_specialization
*spec_entries
= NULL
;
148 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
149 num_spec_entries
= spec_info
->mapEntryCount
;
150 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
151 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
152 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
153 const void *data
= spec_info
->pData
+ entry
.offset
;
154 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
156 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
157 if (spec_info
->dataSize
== 8)
158 spec_entries
[i
].data64
= *(const uint64_t *)data
;
160 spec_entries
[i
].data32
= *(const uint32_t *)data
;
164 struct anv_spirv_debug_data spirv_debug_data
= {
168 struct spirv_to_nir_options spirv_options
= {
169 .frag_coord_is_sysval
= true,
171 .demote_to_helper_invocation
= true,
172 .derivative_group
= true,
173 .descriptor_array_dynamic_indexing
= true,
174 .descriptor_array_non_uniform_indexing
= true,
175 .descriptor_indexing
= true,
176 .device_group
= true,
177 .draw_parameters
= true,
178 .float16
= pdevice
->info
.gen
>= 8,
179 .float64
= pdevice
->info
.gen
>= 8,
180 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
181 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
182 .geometry_streams
= true,
183 .image_write_without_format
= true,
184 .int8
= pdevice
->info
.gen
>= 8,
185 .int16
= pdevice
->info
.gen
>= 8,
186 .int64
= pdevice
->info
.gen
>= 8,
187 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
190 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
191 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
192 .runtime_descriptor_array
= true,
193 .shader_viewport_index_layer
= true,
194 .stencil_export
= pdevice
->info
.gen
>= 9,
195 .storage_8bit
= pdevice
->info
.gen
>= 8,
196 .storage_16bit
= pdevice
->info
.gen
>= 8,
197 .subgroup_arithmetic
= true,
198 .subgroup_basic
= true,
199 .subgroup_ballot
= true,
200 .subgroup_quad
= true,
201 .subgroup_shuffle
= true,
202 .subgroup_vote
= true,
203 .tessellation
= true,
204 .transform_feedback
= pdevice
->info
.gen
>= 8,
205 .variable_pointers
= true,
207 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
209 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
210 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
211 .push_const_addr_format
= nir_address_format_logical
,
213 /* TODO: Consider changing this to an address format that has the NULL
214 * pointer equals to 0. That might be a better format to play nice
215 * with certain code / code generators.
217 .shared_addr_format
= nir_address_format_32bit_offset
,
219 .func
= anv_spirv_nir_debug
,
220 .private_data
= &spirv_debug_data
,
226 spirv_to_nir(spirv
, module
->size
/ 4,
227 spec_entries
, num_spec_entries
,
228 stage
, entrypoint_name
, &spirv_options
, nir_options
);
229 assert(nir
->info
.stage
== stage
);
230 nir_validate_shader(nir
, "after spirv_to_nir");
231 ralloc_steal(mem_ctx
, nir
);
235 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
236 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
237 gl_shader_stage_name(stage
));
238 nir_print_shader(nir
, stderr
);
241 /* We have to lower away local constant initializers right before we
242 * inline functions. That way they get properly initialized at the top
243 * of the function and not at the top of its caller.
245 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
246 NIR_PASS_V(nir
, nir_lower_returns
);
247 NIR_PASS_V(nir
, nir_inline_functions
);
248 NIR_PASS_V(nir
, nir_opt_deref
);
250 /* Pick off the single entrypoint that we want */
251 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
252 if (!func
->is_entrypoint
)
253 exec_node_remove(&func
->node
);
255 assert(exec_list_length(&nir
->functions
) == 1);
257 /* Now that we've deleted all but the main function, we can go ahead and
258 * lower the rest of the constant initializers. We do this here so that
259 * nir_remove_dead_variables and split_per_member_structs below see the
260 * corresponding stores.
262 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
264 /* Split member structs. We do this before lower_io_to_temporaries so that
265 * it doesn't lower system values to temporaries by accident.
267 NIR_PASS_V(nir
, nir_split_var_copies
);
268 NIR_PASS_V(nir
, nir_split_per_member_structs
);
270 NIR_PASS_V(nir
, nir_remove_dead_variables
,
271 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
273 NIR_PASS_V(nir
, nir_propagate_invariant
);
274 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
275 nir_shader_get_entrypoint(nir
), true, false);
277 NIR_PASS_V(nir
, nir_lower_frexp
);
279 /* Vulkan uses the separate-shader linking model */
280 nir
->info
.separate_shader
= true;
282 brw_preprocess_nir(compiler
, nir
, NULL
);
287 void anv_DestroyPipeline(
289 VkPipeline _pipeline
,
290 const VkAllocationCallbacks
* pAllocator
)
292 ANV_FROM_HANDLE(anv_device
, device
, _device
);
293 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
298 anv_reloc_list_finish(&pipeline
->batch_relocs
,
299 pAllocator
? pAllocator
: &device
->alloc
);
300 if (pipeline
->blend_state
.map
)
301 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
303 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
304 if (pipeline
->shaders
[s
])
305 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
308 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
311 static const uint32_t vk_to_gen_primitive_type
[] = {
312 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
313 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
314 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
315 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
316 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
317 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
318 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
319 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
320 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
321 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
325 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
326 struct brw_sampler_prog_key_data
*key
)
328 /* Almost all multisampled textures are compressed. The only time when we
329 * don't compress a multisampled texture is for 16x MSAA with a surface
330 * width greater than 8k which is a bit of an edge case. Since the sampler
331 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
332 * to tell the compiler to always assume compression.
334 key
->compressed_multisample_layout_mask
= ~0;
336 /* SkyLake added support for 16x MSAA. With this came a new message for
337 * reading from a 16x MSAA surface with compression. The new message was
338 * needed because now the MCS data is 64 bits instead of 32 or lower as is
339 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
340 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
341 * so we can just use it unconditionally. This may not be quite as
342 * efficient but it saves us from recompiling.
344 if (devinfo
->gen
>= 9)
347 /* XXX: Handle texture swizzle on HSW- */
348 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
349 /* Assume color sampler, no swizzling. (Works for BDW+) */
350 key
->swizzles
[i
] = SWIZZLE_XYZW
;
355 populate_base_prog_key(const struct gen_device_info
*devinfo
,
356 VkPipelineShaderStageCreateFlags flags
,
357 struct brw_base_prog_key
*key
)
359 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
360 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
362 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
364 populate_sampler_prog_key(devinfo
, &key
->tex
);
368 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
369 VkPipelineShaderStageCreateFlags flags
,
370 struct brw_vs_prog_key
*key
)
372 memset(key
, 0, sizeof(*key
));
374 populate_base_prog_key(devinfo
, flags
, &key
->base
);
376 /* XXX: Handle vertex input work-arounds */
378 /* XXX: Handle sampler_prog_key */
382 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
383 VkPipelineShaderStageCreateFlags flags
,
384 unsigned input_vertices
,
385 struct brw_tcs_prog_key
*key
)
387 memset(key
, 0, sizeof(*key
));
389 populate_base_prog_key(devinfo
, flags
, &key
->base
);
391 key
->input_vertices
= input_vertices
;
395 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
396 VkPipelineShaderStageCreateFlags flags
,
397 struct brw_tes_prog_key
*key
)
399 memset(key
, 0, sizeof(*key
));
401 populate_base_prog_key(devinfo
, flags
, &key
->base
);
405 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
406 VkPipelineShaderStageCreateFlags flags
,
407 struct brw_gs_prog_key
*key
)
409 memset(key
, 0, sizeof(*key
));
411 populate_base_prog_key(devinfo
, flags
, &key
->base
);
415 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
416 VkPipelineShaderStageCreateFlags flags
,
417 const struct anv_subpass
*subpass
,
418 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
419 struct brw_wm_prog_key
*key
)
421 memset(key
, 0, sizeof(*key
));
423 populate_base_prog_key(devinfo
, flags
, &key
->base
);
425 /* We set this to 0 here and set to the actual value before we call
428 key
->input_slots_valid
= 0;
430 /* Vulkan doesn't specify a default */
431 key
->high_quality_derivatives
= false;
433 /* XXX Vulkan doesn't appear to specify */
434 key
->clamp_fragment_color
= false;
436 assert(subpass
->color_count
<= MAX_RTS
);
437 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
438 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
439 key
->color_outputs_valid
|= (1 << i
);
442 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
444 /* To reduce possible shader recompilations we would need to know if
445 * there is a SampleMask output variable to compute if we should emit
446 * code to workaround the issue that hardware disables alpha to coverage
447 * when there is SampleMask output.
449 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
451 /* Vulkan doesn't support fixed-function alpha test */
452 key
->alpha_test_replicate_alpha
= false;
455 /* We should probably pull this out of the shader, but it's fairly
456 * harmless to compute it and then let dead-code take care of it.
458 if (ms_info
->rasterizationSamples
> 1) {
459 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
460 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
461 key
->multisample_fbo
= true;
464 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
469 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
470 VkPipelineShaderStageCreateFlags flags
,
471 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
472 struct brw_cs_prog_key
*key
)
474 memset(key
, 0, sizeof(*key
));
476 populate_base_prog_key(devinfo
, flags
, &key
->base
);
479 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
481 /* These enum values are expressly chosen to be equal to the subgroup
482 * size that they require.
484 assert(rss_info
->requiredSubgroupSize
== 8 ||
485 rss_info
->requiredSubgroupSize
== 16 ||
486 rss_info
->requiredSubgroupSize
== 32);
487 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
488 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
489 /* If the client expressly requests full subgroups and they don't
490 * specify a subgroup size, we need to pick one. If they're requested
491 * varying subgroup sizes, we set it to UNIFORM and let the back-end
492 * compiler pick. Otherwise, we specify the API value of 32.
493 * Performance will likely be terrible in this case but there's nothing
494 * we can do about that. The client should have chosen a size.
496 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
497 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
499 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
503 struct anv_pipeline_stage
{
504 gl_shader_stage stage
;
506 const struct anv_shader_module
*module
;
507 const char *entrypoint
;
508 const VkSpecializationInfo
*spec_info
;
510 unsigned char shader_sha1
[20];
512 union brw_any_prog_key key
;
515 gl_shader_stage stage
;
516 unsigned char sha1
[20];
521 struct anv_pipeline_binding surface_to_descriptor
[256];
522 struct anv_pipeline_binding sampler_to_descriptor
[256];
523 struct anv_pipeline_bind_map bind_map
;
525 union brw_any_prog_data prog_data
;
527 VkPipelineCreationFeedbackEXT feedback
;
531 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
532 const char *entrypoint
,
533 gl_shader_stage stage
,
534 const VkSpecializationInfo
*spec_info
,
535 unsigned char *sha1_out
)
537 struct mesa_sha1 ctx
;
538 _mesa_sha1_init(&ctx
);
540 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
541 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
542 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
544 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
545 spec_info
->mapEntryCount
*
546 sizeof(*spec_info
->pMapEntries
));
547 _mesa_sha1_update(&ctx
, spec_info
->pData
,
548 spec_info
->dataSize
);
551 _mesa_sha1_final(&ctx
, sha1_out
);
555 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
556 struct anv_pipeline_layout
*layout
,
557 struct anv_pipeline_stage
*stages
,
558 unsigned char *sha1_out
)
560 struct mesa_sha1 ctx
;
561 _mesa_sha1_init(&ctx
);
563 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
564 sizeof(pipeline
->subpass
->view_mask
));
567 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
569 const bool rba
= pipeline
->device
->robust_buffer_access
;
570 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
572 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
573 if (stages
[s
].entrypoint
) {
574 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
575 sizeof(stages
[s
].shader_sha1
));
576 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
580 _mesa_sha1_final(&ctx
, sha1_out
);
584 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
585 struct anv_pipeline_layout
*layout
,
586 struct anv_pipeline_stage
*stage
,
587 unsigned char *sha1_out
)
589 struct mesa_sha1 ctx
;
590 _mesa_sha1_init(&ctx
);
593 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
595 const bool rba
= pipeline
->device
->robust_buffer_access
;
596 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
598 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
599 sizeof(stage
->shader_sha1
));
600 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
602 _mesa_sha1_final(&ctx
, sha1_out
);
606 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
607 struct anv_pipeline_cache
*cache
,
609 struct anv_pipeline_stage
*stage
)
611 const struct brw_compiler
*compiler
=
612 pipeline
->device
->instance
->physicalDevice
.compiler
;
613 const nir_shader_compiler_options
*nir_options
=
614 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
617 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
622 assert(nir
->info
.stage
== stage
->stage
);
626 nir
= anv_shader_compile_to_nir(pipeline
->device
,
633 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
641 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
643 struct anv_pipeline_stage
*stage
,
644 struct anv_pipeline_layout
*layout
)
646 const struct anv_physical_device
*pdevice
=
647 &pipeline
->device
->instance
->physicalDevice
;
648 const struct brw_compiler
*compiler
= pdevice
->compiler
;
650 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
651 nir_shader
*nir
= stage
->nir
;
653 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
654 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
655 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
658 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
660 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
662 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
663 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
665 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
667 if (nir
->num_uniforms
> 0) {
668 assert(prog_data
->nr_params
== 0);
670 /* If the shader uses any push constants at all, we'll just give
671 * them the maximum possible number
673 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
674 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
675 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
676 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
678 /* We now set the param values to be offsets into a
679 * anv_push_constant_data structure. Since the compiler doesn't
680 * actually dereference any of the gl_constant_value pointers in the
681 * params array, it doesn't really matter what we put here.
683 struct anv_push_constants
*null_data
= NULL
;
684 /* Fill out the push constants section of the param array */
685 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
686 prog_data
->param
[i
] = ANV_PARAM_PUSH(
687 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
691 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
692 pipeline
->needs_data_cache
= true;
694 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
696 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
697 nir_address_format_64bit_global
);
699 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
701 anv_nir_apply_pipeline_layout(pdevice
,
702 pipeline
->device
->robust_buffer_access
,
703 layout
, nir
, prog_data
,
706 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
707 nir_address_format_32bit_index_offset
);
708 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
709 anv_nir_ssbo_addr_format(pdevice
,
710 pipeline
->device
->robust_buffer_access
));
712 NIR_PASS_V(nir
, nir_opt_constant_folding
);
714 /* We don't support non-uniform UBOs and non-uniform SSBO access is
715 * handled naturally by falling back to A64 messages.
717 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
718 nir_lower_non_uniform_texture_access
|
719 nir_lower_non_uniform_image_access
);
722 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
723 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
725 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
731 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
732 struct anv_pipeline_stage
*vs_stage
,
733 struct anv_pipeline_stage
*next_stage
)
736 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
739 static const unsigned *
740 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
742 struct anv_device
*device
,
743 struct anv_pipeline_stage
*vs_stage
)
745 brw_compute_vue_map(compiler
->devinfo
,
746 &vs_stage
->prog_data
.vs
.base
.vue_map
,
747 vs_stage
->nir
->info
.outputs_written
,
748 vs_stage
->nir
->info
.separate_shader
);
750 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
751 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
755 merge_tess_info(struct shader_info
*tes_info
,
756 const struct shader_info
*tcs_info
)
758 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
760 * "PointMode. Controls generation of points rather than triangles
761 * or lines. This functionality defaults to disabled, and is
762 * enabled if either shader stage includes the execution mode.
764 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
765 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
766 * and OutputVertices, it says:
768 * "One mode must be set in at least one of the tessellation
771 * So, the fields can be set in either the TCS or TES, but they must
772 * agree if set in both. Our backend looks at TES, so bitwise-or in
773 * the values from the TCS.
775 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
776 tes_info
->tess
.tcs_vertices_out
== 0 ||
777 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
778 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
780 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
781 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
782 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
783 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
785 assert(tcs_info
->tess
.primitive_mode
== 0 ||
786 tes_info
->tess
.primitive_mode
== 0 ||
787 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
788 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
789 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
790 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
794 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
795 struct anv_pipeline_stage
*tcs_stage
,
796 struct anv_pipeline_stage
*tes_stage
)
798 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
800 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
802 nir_lower_patch_vertices(tes_stage
->nir
,
803 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
806 /* Copy TCS info into the TES info */
807 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
809 /* Whacking the key after cache lookup is a bit sketchy, but all of
810 * this comes from the SPIR-V, which is part of the hash used for the
811 * pipeline cache. So it should be safe.
813 tcs_stage
->key
.tcs
.tes_primitive_mode
=
814 tes_stage
->nir
->info
.tess
.primitive_mode
;
815 tcs_stage
->key
.tcs
.quads_workaround
=
816 compiler
->devinfo
->gen
< 9 &&
817 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
818 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
821 static const unsigned *
822 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
824 struct anv_device
*device
,
825 struct anv_pipeline_stage
*tcs_stage
,
826 struct anv_pipeline_stage
*prev_stage
)
828 tcs_stage
->key
.tcs
.outputs_written
=
829 tcs_stage
->nir
->info
.outputs_written
;
830 tcs_stage
->key
.tcs
.patch_outputs_written
=
831 tcs_stage
->nir
->info
.patch_outputs_written
;
833 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
834 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
839 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
840 struct anv_pipeline_stage
*tes_stage
,
841 struct anv_pipeline_stage
*next_stage
)
844 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
847 static const unsigned *
848 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
850 struct anv_device
*device
,
851 struct anv_pipeline_stage
*tes_stage
,
852 struct anv_pipeline_stage
*tcs_stage
)
854 tes_stage
->key
.tes
.inputs_read
=
855 tcs_stage
->nir
->info
.outputs_written
;
856 tes_stage
->key
.tes
.patch_inputs_read
=
857 tcs_stage
->nir
->info
.patch_outputs_written
;
859 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
860 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
861 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
866 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
867 struct anv_pipeline_stage
*gs_stage
,
868 struct anv_pipeline_stage
*next_stage
)
871 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
874 static const unsigned *
875 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
877 struct anv_device
*device
,
878 struct anv_pipeline_stage
*gs_stage
,
879 struct anv_pipeline_stage
*prev_stage
)
881 brw_compute_vue_map(compiler
->devinfo
,
882 &gs_stage
->prog_data
.gs
.base
.vue_map
,
883 gs_stage
->nir
->info
.outputs_written
,
884 gs_stage
->nir
->info
.separate_shader
);
886 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
887 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
892 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
893 struct anv_pipeline_stage
*stage
)
895 unsigned num_rts
= 0;
896 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
897 struct anv_pipeline_binding rt_bindings
[max_rt
];
898 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
899 int rt_to_bindings
[max_rt
];
900 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
901 bool rt_used
[max_rt
];
902 memset(rt_used
, 0, sizeof(rt_used
));
904 /* Flag used render targets */
905 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
906 if (var
->data
.location
< FRAG_RESULT_DATA0
)
909 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
914 const unsigned array_len
=
915 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
916 assert(rt
+ array_len
<= max_rt
);
919 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
920 /* If this is the RT at location 0 and we have alpha to coverage
921 * enabled we will have to create a null RT for it, so mark it as
924 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
928 for (unsigned i
= 0; i
< array_len
; i
++)
929 rt_used
[rt
+ i
] = true;
932 /* Set new, compacted, location */
933 for (unsigned i
= 0; i
< max_rt
; i
++) {
937 rt_to_bindings
[i
] = num_rts
;
939 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
940 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
941 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
946 /* Setup a null render target */
947 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
948 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
957 bool deleted_output
= false;
958 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
959 if (var
->data
.location
< FRAG_RESULT_DATA0
)
962 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
964 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
965 /* Unused or out-of-bounds, throw it away, unless it is the first
966 * RT and we have alpha to coverage enabled.
968 deleted_output
= true;
969 var
->data
.mode
= nir_var_function_temp
;
970 exec_node_remove(&var
->node
);
971 exec_list_push_tail(&impl
->locals
, &var
->node
);
975 /* Give it the new location */
976 assert(rt_to_bindings
[rt
] != -1);
977 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
981 nir_fixup_deref_modes(stage
->nir
);
984 /* If we have no render targets, we need a null render target */
985 rt_bindings
[0] = (struct anv_pipeline_binding
) {
986 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
993 /* Now that we've determined the actual number of render targets, adjust
994 * the key accordingly.
996 stage
->key
.wm
.nr_color_regions
= num_rts
;
997 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
999 assert(num_rts
<= max_rt
);
1000 assert(stage
->bind_map
.surface_count
== 0);
1001 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
1002 rt_bindings
, num_rts
);
1003 stage
->bind_map
.surface_count
+= num_rts
;
1006 static const unsigned *
1007 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
1009 struct anv_device
*device
,
1010 struct anv_pipeline_stage
*fs_stage
,
1011 struct anv_pipeline_stage
*prev_stage
)
1013 /* TODO: we could set this to 0 based on the information in nir_shader, but
1014 * we need this before we call spirv_to_nir.
1017 fs_stage
->key
.wm
.input_slots_valid
=
1018 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
1020 const unsigned *code
=
1021 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
1022 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
1023 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
1025 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
1026 !fs_stage
->prog_data
.wm
.has_side_effects
&&
1027 !fs_stage
->prog_data
.wm
.uses_kill
&&
1028 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
1029 !fs_stage
->prog_data
.wm
.computed_stencil
) {
1030 /* This fragment shader has no outputs and no side effects. Go ahead
1031 * and return the code pointer so we don't accidentally think the
1032 * compile failed but zero out prog_data which will set program_size to
1033 * zero and disable the stage.
1035 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1042 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1043 struct anv_pipeline_cache
*cache
,
1044 const VkGraphicsPipelineCreateInfo
*info
)
1046 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1047 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1049 int64_t pipeline_start
= os_time_get_nano();
1051 const struct brw_compiler
*compiler
=
1052 pipeline
->device
->instance
->physicalDevice
.compiler
;
1053 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1055 pipeline
->active_stages
= 0;
1058 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1059 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1060 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1062 pipeline
->active_stages
|= sinfo
->stage
;
1064 int64_t stage_start
= os_time_get_nano();
1066 stages
[stage
].stage
= stage
;
1067 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1068 stages
[stage
].entrypoint
= sinfo
->pName
;
1069 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1070 anv_pipeline_hash_shader(stages
[stage
].module
,
1071 stages
[stage
].entrypoint
,
1073 stages
[stage
].spec_info
,
1074 stages
[stage
].shader_sha1
);
1076 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1078 case MESA_SHADER_VERTEX
:
1079 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1081 case MESA_SHADER_TESS_CTRL
:
1082 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1083 info
->pTessellationState
->patchControlPoints
,
1084 &stages
[stage
].key
.tcs
);
1086 case MESA_SHADER_TESS_EVAL
:
1087 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1089 case MESA_SHADER_GEOMETRY
:
1090 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1092 case MESA_SHADER_FRAGMENT
:
1093 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1095 info
->pMultisampleState
,
1096 &stages
[stage
].key
.wm
);
1099 unreachable("Invalid graphics shader stage");
1102 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1103 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1106 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1107 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1109 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1111 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1113 unsigned char sha1
[20];
1114 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1117 unsigned cache_hits
= 0;
1118 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1119 if (!stages
[s
].entrypoint
)
1122 int64_t stage_start
= os_time_get_nano();
1124 stages
[s
].cache_key
.stage
= s
;
1125 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1128 struct anv_shader_bin
*bin
=
1129 anv_device_search_for_kernel(pipeline
->device
, cache
,
1130 &stages
[s
].cache_key
,
1131 sizeof(stages
[s
].cache_key
), &cache_hit
);
1134 pipeline
->shaders
[s
] = bin
;
1139 stages
[s
].feedback
.flags
|=
1140 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1142 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1145 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1146 if (cache_hits
== found
) {
1147 pipeline_feedback
.flags
|=
1148 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1150 /* We found all our shaders in the cache. We're done. */
1152 } else if (found
> 0) {
1153 /* We found some but not all of our shaders. This shouldn't happen
1154 * most of the time but it can if we have a partially populated
1157 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1159 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1160 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1161 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1162 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1163 (uint64_t)(uintptr_t)cache
,
1165 "Found a partial pipeline in the cache. This is "
1166 "most likely caused by an incomplete pipeline cache "
1167 "import or export");
1169 /* We're going to have to recompile anyway, so just throw away our
1170 * references to the shaders in the cache. We'll get them out of the
1171 * cache again as part of the compilation process.
1173 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1174 stages
[s
].feedback
.flags
= 0;
1175 if (pipeline
->shaders
[s
]) {
1176 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1177 pipeline
->shaders
[s
] = NULL
;
1182 void *pipeline_ctx
= ralloc_context(NULL
);
1184 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1185 if (!stages
[s
].entrypoint
)
1188 int64_t stage_start
= os_time_get_nano();
1190 assert(stages
[s
].stage
== s
);
1191 assert(pipeline
->shaders
[s
] == NULL
);
1193 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1194 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1195 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1198 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1201 if (stages
[s
].nir
== NULL
) {
1202 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1206 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1209 /* Walk backwards to link */
1210 struct anv_pipeline_stage
*next_stage
= NULL
;
1211 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1212 if (!stages
[s
].entrypoint
)
1216 case MESA_SHADER_VERTEX
:
1217 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1219 case MESA_SHADER_TESS_CTRL
:
1220 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1222 case MESA_SHADER_TESS_EVAL
:
1223 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1225 case MESA_SHADER_GEOMETRY
:
1226 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1228 case MESA_SHADER_FRAGMENT
:
1229 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1232 unreachable("Invalid graphics shader stage");
1235 next_stage
= &stages
[s
];
1238 struct anv_pipeline_stage
*prev_stage
= NULL
;
1239 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1240 if (!stages
[s
].entrypoint
)
1243 int64_t stage_start
= os_time_get_nano();
1245 void *stage_ctx
= ralloc_context(NULL
);
1247 nir_xfb_info
*xfb_info
= NULL
;
1248 if (s
== MESA_SHADER_VERTEX
||
1249 s
== MESA_SHADER_TESS_EVAL
||
1250 s
== MESA_SHADER_GEOMETRY
)
1251 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1253 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1255 const unsigned *code
;
1257 case MESA_SHADER_VERTEX
:
1258 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1261 case MESA_SHADER_TESS_CTRL
:
1262 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1263 &stages
[s
], prev_stage
);
1265 case MESA_SHADER_TESS_EVAL
:
1266 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1267 &stages
[s
], prev_stage
);
1269 case MESA_SHADER_GEOMETRY
:
1270 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1271 &stages
[s
], prev_stage
);
1273 case MESA_SHADER_FRAGMENT
:
1274 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1275 &stages
[s
], prev_stage
);
1278 unreachable("Invalid graphics shader stage");
1281 ralloc_free(stage_ctx
);
1282 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1286 struct anv_shader_bin
*bin
=
1287 anv_device_upload_kernel(pipeline
->device
, cache
,
1288 &stages
[s
].cache_key
,
1289 sizeof(stages
[s
].cache_key
),
1290 code
, stages
[s
].prog_data
.base
.program_size
,
1291 stages
[s
].nir
->constant_data
,
1292 stages
[s
].nir
->constant_data_size
,
1293 &stages
[s
].prog_data
.base
,
1294 brw_prog_data_size(s
),
1295 xfb_info
, &stages
[s
].bind_map
);
1297 ralloc_free(stage_ctx
);
1298 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1302 pipeline
->shaders
[s
] = bin
;
1303 ralloc_free(stage_ctx
);
1305 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1307 prev_stage
= &stages
[s
];
1310 ralloc_free(pipeline_ctx
);
1314 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1315 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1316 /* This can happen if we decided to implicitly disable the fragment
1317 * shader. See anv_pipeline_compile_fs().
1319 anv_shader_bin_unref(pipeline
->device
,
1320 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1321 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1322 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1325 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1327 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1328 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1329 if (create_feedback
) {
1330 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1332 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1333 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1334 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1335 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1342 ralloc_free(pipeline_ctx
);
1344 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1345 if (pipeline
->shaders
[s
])
1346 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1353 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1355 assert(glsl_type_is_vector_or_scalar(type
));
1357 uint32_t comp_size
= glsl_type_is_boolean(type
)
1358 ? 4 : glsl_get_bit_size(type
) / 8;
1359 unsigned length
= glsl_get_vector_elements(type
);
1360 *size
= comp_size
* length
,
1361 *align
= comp_size
* (length
== 3 ? 4 : length
);
1365 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1366 struct anv_pipeline_cache
*cache
,
1367 const VkComputePipelineCreateInfo
*info
,
1368 const struct anv_shader_module
*module
,
1369 const char *entrypoint
,
1370 const VkSpecializationInfo
*spec_info
)
1372 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1373 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1375 int64_t pipeline_start
= os_time_get_nano();
1377 const struct brw_compiler
*compiler
=
1378 pipeline
->device
->instance
->physicalDevice
.compiler
;
1380 struct anv_pipeline_stage stage
= {
1381 .stage
= MESA_SHADER_COMPUTE
,
1383 .entrypoint
= entrypoint
,
1384 .spec_info
= spec_info
,
1386 .stage
= MESA_SHADER_COMPUTE
,
1389 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1392 anv_pipeline_hash_shader(stage
.module
,
1394 MESA_SHADER_COMPUTE
,
1398 struct anv_shader_bin
*bin
= NULL
;
1400 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1401 vk_find_struct_const(info
->stage
.pNext
,
1402 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1404 populate_cs_prog_key(&pipeline
->device
->info
, info
->stage
.flags
,
1405 rss_info
, &stage
.key
.cs
);
1407 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1409 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1411 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1412 sizeof(stage
.cache_key
), &cache_hit
);
1415 int64_t stage_start
= os_time_get_nano();
1417 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1418 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1419 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1422 /* Set up a binding for the gl_NumWorkGroups */
1423 stage
.bind_map
.surface_count
= 1;
1424 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1425 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1428 void *mem_ctx
= ralloc_context(NULL
);
1430 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1431 if (stage
.nir
== NULL
) {
1432 ralloc_free(mem_ctx
);
1433 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1436 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1438 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1439 &stage
.prog_data
.cs
);
1441 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1442 nir_var_mem_shared
, shared_type_info
);
1443 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1444 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1446 stage
.prog_data
.cs
.base
.total_shared
= stage
.nir
->info
.cs
.shared_size
;
1448 const unsigned *shader_code
=
1449 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1450 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1451 if (shader_code
== NULL
) {
1452 ralloc_free(mem_ctx
);
1453 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1456 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1457 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1458 &stage
.cache_key
, sizeof(stage
.cache_key
),
1459 shader_code
, code_size
,
1460 stage
.nir
->constant_data
,
1461 stage
.nir
->constant_data_size
,
1462 &stage
.prog_data
.base
,
1463 sizeof(stage
.prog_data
.cs
),
1464 NULL
, &stage
.bind_map
);
1466 ralloc_free(mem_ctx
);
1467 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1470 ralloc_free(mem_ctx
);
1472 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1476 stage
.feedback
.flags
|=
1477 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1478 pipeline_feedback
.flags
|=
1479 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1481 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1483 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1484 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1485 if (create_feedback
) {
1486 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1488 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1489 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1492 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1493 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1499 * Copy pipeline state not marked as dynamic.
1500 * Dynamic state is pipeline state which hasn't been provided at pipeline
1501 * creation time, but is dynamically provided afterwards using various
1502 * vkCmdSet* functions.
1504 * The set of state considered "non_dynamic" is determined by the pieces of
1505 * state that have their corresponding VkDynamicState enums omitted from
1506 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1508 * @param[out] pipeline Destination non_dynamic state.
1509 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1512 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1513 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1515 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1516 struct anv_subpass
*subpass
= pipeline
->subpass
;
1518 pipeline
->dynamic_state
= default_dynamic_state
;
1520 if (pCreateInfo
->pDynamicState
) {
1521 /* Remove all of the states that are marked as dynamic */
1522 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1523 for (uint32_t s
= 0; s
< count
; s
++) {
1524 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1525 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1529 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1531 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1533 * pViewportState is [...] NULL if the pipeline
1534 * has rasterization disabled.
1536 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1537 assert(pCreateInfo
->pViewportState
);
1539 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1540 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1541 typed_memcpy(dynamic
->viewport
.viewports
,
1542 pCreateInfo
->pViewportState
->pViewports
,
1543 pCreateInfo
->pViewportState
->viewportCount
);
1546 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1547 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1548 typed_memcpy(dynamic
->scissor
.scissors
,
1549 pCreateInfo
->pViewportState
->pScissors
,
1550 pCreateInfo
->pViewportState
->scissorCount
);
1554 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1555 assert(pCreateInfo
->pRasterizationState
);
1556 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1559 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1560 assert(pCreateInfo
->pRasterizationState
);
1561 dynamic
->depth_bias
.bias
=
1562 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1563 dynamic
->depth_bias
.clamp
=
1564 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1565 dynamic
->depth_bias
.slope
=
1566 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1569 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1571 * pColorBlendState is [...] NULL if the pipeline has rasterization
1572 * disabled or if the subpass of the render pass the pipeline is
1573 * created against does not use any color attachments.
1575 bool uses_color_att
= false;
1576 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1577 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1578 uses_color_att
= true;
1583 if (uses_color_att
&&
1584 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1585 assert(pCreateInfo
->pColorBlendState
);
1587 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1588 typed_memcpy(dynamic
->blend_constants
,
1589 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1592 /* If there is no depthstencil attachment, then don't read
1593 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1594 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1595 * no need to override the depthstencil defaults in
1596 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1598 * Section 9.2 of the Vulkan 1.0.15 spec says:
1600 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1601 * disabled or if the subpass of the render pass the pipeline is created
1602 * against does not use a depth/stencil attachment.
1604 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1605 subpass
->depth_stencil_attachment
) {
1606 assert(pCreateInfo
->pDepthStencilState
);
1608 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1609 dynamic
->depth_bounds
.min
=
1610 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1611 dynamic
->depth_bounds
.max
=
1612 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1615 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1616 dynamic
->stencil_compare_mask
.front
=
1617 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1618 dynamic
->stencil_compare_mask
.back
=
1619 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1622 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1623 dynamic
->stencil_write_mask
.front
=
1624 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1625 dynamic
->stencil_write_mask
.back
=
1626 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1629 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1630 dynamic
->stencil_reference
.front
=
1631 pCreateInfo
->pDepthStencilState
->front
.reference
;
1632 dynamic
->stencil_reference
.back
=
1633 pCreateInfo
->pDepthStencilState
->back
.reference
;
1637 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1638 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1639 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1641 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1642 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1643 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1647 pipeline
->dynamic_state_mask
= states
;
1651 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1654 struct anv_render_pass
*renderpass
= NULL
;
1655 struct anv_subpass
*subpass
= NULL
;
1657 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1658 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1660 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1662 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1665 assert(info
->subpass
< renderpass
->subpass_count
);
1666 subpass
= &renderpass
->subpasses
[info
->subpass
];
1668 assert(info
->stageCount
>= 1);
1669 assert(info
->pVertexInputState
);
1670 assert(info
->pInputAssemblyState
);
1671 assert(info
->pRasterizationState
);
1672 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1673 assert(info
->pViewportState
);
1674 assert(info
->pMultisampleState
);
1676 if (subpass
&& subpass
->depth_stencil_attachment
)
1677 assert(info
->pDepthStencilState
);
1679 if (subpass
&& subpass
->color_count
> 0) {
1680 bool all_color_unused
= true;
1681 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1682 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1683 all_color_unused
= false;
1685 /* pColorBlendState is ignored if the pipeline has rasterization
1686 * disabled or if the subpass of the render pass the pipeline is
1687 * created against does not use any color attachments.
1689 assert(info
->pColorBlendState
|| all_color_unused
);
1693 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1694 switch (info
->pStages
[i
].stage
) {
1695 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1696 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1697 assert(info
->pTessellationState
);
1707 * Calculate the desired L3 partitioning based on the current state of the
1708 * pipeline. For now this simply returns the conservative defaults calculated
1709 * by get_default_l3_weights(), but we could probably do better by gathering
1710 * more statistics from the pipeline state (e.g. guess of expected URB usage
1711 * and bound surfaces), or by using feed-back from performance counters.
1714 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1716 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1718 const struct gen_l3_weights w
=
1719 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1721 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1722 pipeline
->urb
.total_size
=
1723 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1727 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1728 struct anv_device
*device
,
1729 struct anv_pipeline_cache
*cache
,
1730 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1731 const VkAllocationCallbacks
*alloc
)
1735 anv_pipeline_validate_create_info(pCreateInfo
);
1738 alloc
= &device
->alloc
;
1740 pipeline
->device
= device
;
1742 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1743 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1744 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1746 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1747 if (result
!= VK_SUCCESS
)
1750 pipeline
->batch
.alloc
= alloc
;
1751 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1752 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1753 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1754 pipeline
->batch
.status
= VK_SUCCESS
;
1756 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1757 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1758 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1760 /* Previously we enabled depth clipping when !depthClampEnable.
1761 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1762 * clipping info is available, use its enable value to determine clipping,
1763 * otherwise fallback to the previous !depthClampEnable logic.
1765 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1766 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1767 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1768 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1770 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1771 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1773 pipeline
->needs_data_cache
= false;
1775 /* When we free the pipeline, we detect stages based on the NULL status
1776 * of various prog_data pointers. Make them NULL by default.
1778 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1780 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1781 if (result
!= VK_SUCCESS
) {
1782 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1786 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1788 anv_pipeline_setup_l3_config(pipeline
, false);
1790 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1791 pCreateInfo
->pVertexInputState
;
1793 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1795 pipeline
->vb_used
= 0;
1796 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1797 const VkVertexInputAttributeDescription
*desc
=
1798 &vi_info
->pVertexAttributeDescriptions
[i
];
1800 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1801 pipeline
->vb_used
|= 1 << desc
->binding
;
1804 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1805 const VkVertexInputBindingDescription
*desc
=
1806 &vi_info
->pVertexBindingDescriptions
[i
];
1808 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1810 /* Step rate is programmed per vertex element (attribute), not
1811 * binding. Set up a map of which bindings step per instance, for
1812 * reference by vertex element setup. */
1813 switch (desc
->inputRate
) {
1815 case VK_VERTEX_INPUT_RATE_VERTEX
:
1816 pipeline
->vb
[desc
->binding
].instanced
= false;
1818 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1819 pipeline
->vb
[desc
->binding
].instanced
= true;
1823 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1826 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1827 vk_find_struct_const(vi_info
->pNext
,
1828 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1830 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1831 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1832 &vi_div_state
->pVertexBindingDivisors
[i
];
1834 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1838 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1839 * different views. If the client asks for instancing, we need to multiply
1840 * the instance divisor by the number of views ensure that we repeat the
1841 * client's per-instance data once for each view.
1843 if (pipeline
->subpass
->view_mask
) {
1844 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1845 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1846 if (pipeline
->vb
[vb
].instanced
)
1847 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1851 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1852 pCreateInfo
->pInputAssemblyState
;
1853 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1854 pCreateInfo
->pTessellationState
;
1855 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1857 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1858 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1860 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];