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[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
34 #include "anv_nir.h"
35 #include "spirv/nir_spirv.h"
36
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
39
40 // Shader functions
41
42 VkResult anv_CreateShaderModule(
43 VkDevice _device,
44 const VkShaderModuleCreateInfo* pCreateInfo,
45 const VkAllocationCallbacks* pAllocator,
46 VkShaderModule* pShaderModule)
47 {
48 ANV_FROM_HANDLE(anv_device, device, _device);
49 struct anv_shader_module *module;
50
51 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
52 assert(pCreateInfo->flags == 0);
53
54 module = vk_alloc2(&device->alloc, pAllocator,
55 sizeof(*module) + pCreateInfo->codeSize, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
57 if (module == NULL)
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
59
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 if (!module)
79 return;
80
81 vk_free2(&device->alloc, pAllocator, module);
82 }
83
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
85
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
88 */
89 static nir_shader *
90 anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
91 struct anv_shader_module *module,
92 const char *entrypoint_name,
93 gl_shader_stage stage,
94 const VkSpecializationInfo *spec_info)
95 {
96 const struct anv_device *device = pipeline->device;
97
98 const struct brw_compiler *compiler =
99 device->instance->physicalDevice.compiler;
100 const nir_shader_compiler_options *nir_options =
101 compiler->glsl_compiler_options[stage].NirOptions;
102
103 uint32_t *spirv = (uint32_t *) module->data;
104 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
105 assert(module->size % 4 == 0);
106
107 uint32_t num_spec_entries = 0;
108 struct nir_spirv_specialization *spec_entries = NULL;
109 if (spec_info && spec_info->mapEntryCount > 0) {
110 num_spec_entries = spec_info->mapEntryCount;
111 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
112 for (uint32_t i = 0; i < num_spec_entries; i++) {
113 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
114 const void *data = spec_info->pData + entry.offset;
115 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
116
117 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
118 if (spec_info->dataSize == 8)
119 spec_entries[i].data64 = *(const uint64_t *)data;
120 else
121 spec_entries[i].data32 = *(const uint32_t *)data;
122 }
123 }
124
125 const struct nir_spirv_supported_extensions supported_ext = {
126 .float64 = device->instance->physicalDevice.info.gen >= 8,
127 .int64 = device->instance->physicalDevice.info.gen >= 8,
128 .tessellation = true,
129 .draw_parameters = true,
130 .image_write_without_format = true,
131 .multiview = true,
132 };
133
134 nir_function *entry_point =
135 spirv_to_nir(spirv, module->size / 4,
136 spec_entries, num_spec_entries,
137 stage, entrypoint_name, &supported_ext, nir_options);
138 nir_shader *nir = entry_point->shader;
139 assert(nir->stage == stage);
140 nir_validate_shader(nir);
141
142 free(spec_entries);
143
144 /* We have to lower away local constant initializers right before we
145 * inline functions. That way they get properly initialized at the top
146 * of the function and not at the top of its caller.
147 */
148 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
149 NIR_PASS_V(nir, nir_lower_returns);
150 NIR_PASS_V(nir, nir_inline_functions);
151
152 /* Pick off the single entrypoint that we want */
153 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
154 if (func != entry_point)
155 exec_node_remove(&func->node);
156 }
157 assert(exec_list_length(&nir->functions) == 1);
158 entry_point->name = ralloc_strdup(entry_point, "main");
159
160 NIR_PASS_V(nir, nir_remove_dead_variables,
161 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
162
163 if (stage == MESA_SHADER_FRAGMENT)
164 NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
165
166 /* Now that we've deleted all but the main function, we can go ahead and
167 * lower the rest of the constant initializers.
168 */
169 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
170 NIR_PASS_V(nir, nir_propagate_invariant);
171 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
172 entry_point->impl, true, false);
173 NIR_PASS_V(nir, nir_lower_system_values);
174
175 /* Vulkan uses the separate-shader linking model */
176 nir->info->separate_shader = true;
177
178 nir = brw_preprocess_nir(compiler, nir);
179
180 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
181
182 if (stage == MESA_SHADER_FRAGMENT)
183 NIR_PASS_V(nir, anv_nir_lower_input_attachments);
184
185 return nir;
186 }
187
188 void anv_DestroyPipeline(
189 VkDevice _device,
190 VkPipeline _pipeline,
191 const VkAllocationCallbacks* pAllocator)
192 {
193 ANV_FROM_HANDLE(anv_device, device, _device);
194 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
195
196 if (!pipeline)
197 return;
198
199 anv_reloc_list_finish(&pipeline->batch_relocs,
200 pAllocator ? pAllocator : &device->alloc);
201 if (pipeline->blend_state.map)
202 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
203
204 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
205 if (pipeline->shaders[s])
206 anv_shader_bin_unref(device, pipeline->shaders[s]);
207 }
208
209 vk_free2(&device->alloc, pAllocator, pipeline);
210 }
211
212 static const uint32_t vk_to_gen_primitive_type[] = {
213 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
215 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
218 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
219 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
220 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
222 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
223 };
224
225 static void
226 populate_sampler_prog_key(const struct gen_device_info *devinfo,
227 struct brw_sampler_prog_key_data *key)
228 {
229 /* Almost all multisampled textures are compressed. The only time when we
230 * don't compress a multisampled texture is for 16x MSAA with a surface
231 * width greater than 8k which is a bit of an edge case. Since the sampler
232 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
233 * to tell the compiler to always assume compression.
234 */
235 key->compressed_multisample_layout_mask = ~0;
236
237 /* SkyLake added support for 16x MSAA. With this came a new message for
238 * reading from a 16x MSAA surface with compression. The new message was
239 * needed because now the MCS data is 64 bits instead of 32 or lower as is
240 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
241 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
242 * so we can just use it unconditionally. This may not be quite as
243 * efficient but it saves us from recompiling.
244 */
245 if (devinfo->gen >= 9)
246 key->msaa_16 = ~0;
247
248 /* XXX: Handle texture swizzle on HSW- */
249 for (int i = 0; i < MAX_SAMPLERS; i++) {
250 /* Assume color sampler, no swizzling. (Works for BDW+) */
251 key->swizzles[i] = SWIZZLE_XYZW;
252 }
253 }
254
255 static void
256 populate_vs_prog_key(const struct gen_device_info *devinfo,
257 struct brw_vs_prog_key *key)
258 {
259 memset(key, 0, sizeof(*key));
260
261 populate_sampler_prog_key(devinfo, &key->tex);
262
263 /* XXX: Handle vertex input work-arounds */
264
265 /* XXX: Handle sampler_prog_key */
266 }
267
268 static void
269 populate_gs_prog_key(const struct gen_device_info *devinfo,
270 struct brw_gs_prog_key *key)
271 {
272 memset(key, 0, sizeof(*key));
273
274 populate_sampler_prog_key(devinfo, &key->tex);
275 }
276
277 static void
278 populate_wm_prog_key(const struct anv_pipeline *pipeline,
279 const VkGraphicsPipelineCreateInfo *info,
280 struct brw_wm_prog_key *key)
281 {
282 const struct gen_device_info *devinfo = &pipeline->device->info;
283
284 memset(key, 0, sizeof(*key));
285
286 populate_sampler_prog_key(devinfo, &key->tex);
287
288 /* TODO: we could set this to 0 based on the information in nir_shader, but
289 * this function is called before spirv_to_nir. */
290 const struct brw_vue_map *vue_map =
291 &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
292 key->input_slots_valid = vue_map->slots_valid;
293
294 /* Vulkan doesn't specify a default */
295 key->high_quality_derivatives = false;
296
297 /* XXX Vulkan doesn't appear to specify */
298 key->clamp_fragment_color = false;
299
300 key->nr_color_regions = pipeline->subpass->color_count;
301
302 key->replicate_alpha = key->nr_color_regions > 1 &&
303 info->pMultisampleState &&
304 info->pMultisampleState->alphaToCoverageEnable;
305
306 if (info->pMultisampleState) {
307 /* We should probably pull this out of the shader, but it's fairly
308 * harmless to compute it and then let dead-code take care of it.
309 */
310 if (info->pMultisampleState->rasterizationSamples > 1) {
311 key->persample_interp =
312 (info->pMultisampleState->minSampleShading *
313 info->pMultisampleState->rasterizationSamples) > 1;
314 key->multisample_fbo = true;
315 }
316
317 key->frag_coord_adds_sample_pos =
318 info->pMultisampleState->sampleShadingEnable;
319 }
320 }
321
322 static void
323 populate_cs_prog_key(const struct gen_device_info *devinfo,
324 struct brw_cs_prog_key *key)
325 {
326 memset(key, 0, sizeof(*key));
327
328 populate_sampler_prog_key(devinfo, &key->tex);
329 }
330
331 static void
332 anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
333 struct anv_shader_module *module,
334 const char *entrypoint,
335 gl_shader_stage stage,
336 const VkSpecializationInfo *spec_info,
337 const void *key, size_t key_size,
338 unsigned char *sha1_out)
339 {
340 struct mesa_sha1 ctx;
341
342 _mesa_sha1_init(&ctx);
343 if (stage != MESA_SHADER_COMPUTE) {
344 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
345 sizeof(pipeline->subpass->view_mask));
346 }
347 if (pipeline->layout) {
348 _mesa_sha1_update(&ctx, pipeline->layout->sha1,
349 sizeof(pipeline->layout->sha1));
350 }
351 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
352 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
353 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
354 if (spec_info) {
355 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
356 spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
357 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
358 }
359 _mesa_sha1_update(&ctx, key, key_size);
360 _mesa_sha1_final(&ctx, sha1_out);
361 }
362
363 static nir_shader *
364 anv_pipeline_compile(struct anv_pipeline *pipeline,
365 struct anv_shader_module *module,
366 const char *entrypoint,
367 gl_shader_stage stage,
368 const VkSpecializationInfo *spec_info,
369 struct brw_stage_prog_data *prog_data,
370 struct anv_pipeline_bind_map *map)
371 {
372 nir_shader *nir = anv_shader_compile_to_nir(pipeline,
373 module, entrypoint, stage,
374 spec_info);
375 if (nir == NULL)
376 return NULL;
377
378 NIR_PASS_V(nir, anv_nir_lower_push_constants);
379
380 if (stage != MESA_SHADER_COMPUTE)
381 NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask);
382
383 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
384
385 /* Figure out the number of parameters */
386 prog_data->nr_params = 0;
387
388 if (nir->num_uniforms > 0) {
389 /* If the shader uses any push constants at all, we'll just give
390 * them the maximum possible number
391 */
392 assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
393 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
394 }
395
396 if (nir->info->num_images > 0) {
397 prog_data->nr_params += nir->info->num_images * BRW_IMAGE_PARAM_SIZE;
398 pipeline->needs_data_cache = true;
399 }
400
401 if (stage == MESA_SHADER_COMPUTE)
402 ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
403 prog_data->nr_params++; /* The CS Thread ID uniform */
404
405 if (nir->info->num_ssbos > 0)
406 pipeline->needs_data_cache = true;
407
408 if (prog_data->nr_params > 0) {
409 /* XXX: I think we're leaking this */
410 prog_data->param = (const union gl_constant_value **)
411 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
412
413 /* We now set the param values to be offsets into a
414 * anv_push_constant_data structure. Since the compiler doesn't
415 * actually dereference any of the gl_constant_value pointers in the
416 * params array, it doesn't really matter what we put here.
417 */
418 struct anv_push_constants *null_data = NULL;
419 if (nir->num_uniforms > 0) {
420 /* Fill out the push constants section of the param array */
421 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
422 prog_data->param[i] = (const union gl_constant_value *)
423 &null_data->client_data[i * sizeof(float)];
424 }
425 }
426
427 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
428 if (pipeline->layout)
429 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
430
431 /* nir_lower_io will only handle the push constants; we need to set this
432 * to the full number of possible uniforms.
433 */
434 nir->num_uniforms = prog_data->nr_params * 4;
435
436 return nir;
437 }
438
439 static void
440 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
441 {
442 prog_data->binding_table.size_bytes = 0;
443 prog_data->binding_table.texture_start = bias;
444 prog_data->binding_table.gather_texture_start = bias;
445 prog_data->binding_table.ubo_start = bias;
446 prog_data->binding_table.ssbo_start = bias;
447 prog_data->binding_table.image_start = bias;
448 }
449
450 static struct anv_shader_bin *
451 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
452 struct anv_pipeline_cache *cache,
453 const void *key_data, uint32_t key_size,
454 const void *kernel_data, uint32_t kernel_size,
455 const struct brw_stage_prog_data *prog_data,
456 uint32_t prog_data_size,
457 const struct anv_pipeline_bind_map *bind_map)
458 {
459 if (cache) {
460 return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
461 kernel_data, kernel_size,
462 prog_data, prog_data_size,
463 bind_map);
464 } else {
465 return anv_shader_bin_create(pipeline->device, key_data, key_size,
466 kernel_data, kernel_size,
467 prog_data, prog_data_size,
468 prog_data->param, bind_map);
469 }
470 }
471
472
473 static void
474 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
475 gl_shader_stage stage,
476 struct anv_shader_bin *shader)
477 {
478 pipeline->shaders[stage] = shader;
479 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
480 }
481
482 static VkResult
483 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
484 struct anv_pipeline_cache *cache,
485 const VkGraphicsPipelineCreateInfo *info,
486 struct anv_shader_module *module,
487 const char *entrypoint,
488 const VkSpecializationInfo *spec_info)
489 {
490 const struct brw_compiler *compiler =
491 pipeline->device->instance->physicalDevice.compiler;
492 struct anv_pipeline_bind_map map;
493 struct brw_vs_prog_key key;
494 struct anv_shader_bin *bin = NULL;
495 unsigned char sha1[20];
496
497 populate_vs_prog_key(&pipeline->device->info, &key);
498
499 if (cache) {
500 anv_pipeline_hash_shader(pipeline, module, entrypoint,
501 MESA_SHADER_VERTEX, spec_info,
502 &key, sizeof(key), sha1);
503 bin = anv_pipeline_cache_search(cache, sha1, 20);
504 }
505
506 if (bin == NULL) {
507 struct brw_vs_prog_data prog_data = { 0, };
508 struct anv_pipeline_binding surface_to_descriptor[256];
509 struct anv_pipeline_binding sampler_to_descriptor[256];
510
511 map = (struct anv_pipeline_bind_map) {
512 .surface_to_descriptor = surface_to_descriptor,
513 .sampler_to_descriptor = sampler_to_descriptor
514 };
515
516 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
517 MESA_SHADER_VERTEX, spec_info,
518 &prog_data.base.base, &map);
519 if (nir == NULL)
520 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
521
522 anv_fill_binding_table(&prog_data.base.base, 0);
523
524 void *mem_ctx = ralloc_context(NULL);
525
526 ralloc_steal(mem_ctx, nir);
527
528 prog_data.inputs_read = nir->info->inputs_read;
529 prog_data.double_inputs_read = nir->info->double_inputs_read;
530
531 brw_compute_vue_map(&pipeline->device->info,
532 &prog_data.base.vue_map,
533 nir->info->outputs_written,
534 nir->info->separate_shader);
535
536 unsigned code_size;
537 const unsigned *shader_code =
538 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
539 NULL, false, -1, &code_size, NULL);
540 if (shader_code == NULL) {
541 ralloc_free(mem_ctx);
542 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
543 }
544
545 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
546 shader_code, code_size,
547 &prog_data.base.base, sizeof(prog_data),
548 &map);
549 if (!bin) {
550 ralloc_free(mem_ctx);
551 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
552 }
553
554 ralloc_free(mem_ctx);
555 }
556
557 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
558
559 return VK_SUCCESS;
560 }
561
562 static void
563 merge_tess_info(struct shader_info *tes_info,
564 const struct shader_info *tcs_info)
565 {
566 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
567 *
568 * "PointMode. Controls generation of points rather than triangles
569 * or lines. This functionality defaults to disabled, and is
570 * enabled if either shader stage includes the execution mode.
571 *
572 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
573 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
574 * and OutputVertices, it says:
575 *
576 * "One mode must be set in at least one of the tessellation
577 * shader stages."
578 *
579 * So, the fields can be set in either the TCS or TES, but they must
580 * agree if set in both. Our backend looks at TES, so bitwise-or in
581 * the values from the TCS.
582 */
583 assert(tcs_info->tess.tcs_vertices_out == 0 ||
584 tes_info->tess.tcs_vertices_out == 0 ||
585 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
586 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
587
588 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
589 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
590 tcs_info->tess.spacing == tes_info->tess.spacing);
591 tes_info->tess.spacing |= tcs_info->tess.spacing;
592
593 tes_info->tess.ccw |= tcs_info->tess.ccw;
594 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
595 }
596
597 static VkResult
598 anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
599 struct anv_pipeline_cache *cache,
600 const VkGraphicsPipelineCreateInfo *info,
601 struct anv_shader_module *tcs_module,
602 const char *tcs_entrypoint,
603 const VkSpecializationInfo *tcs_spec_info,
604 struct anv_shader_module *tes_module,
605 const char *tes_entrypoint,
606 const VkSpecializationInfo *tes_spec_info)
607 {
608 const struct gen_device_info *devinfo = &pipeline->device->info;
609 const struct brw_compiler *compiler =
610 pipeline->device->instance->physicalDevice.compiler;
611 struct anv_pipeline_bind_map tcs_map;
612 struct anv_pipeline_bind_map tes_map;
613 struct brw_tcs_prog_key tcs_key = { 0, };
614 struct brw_tes_prog_key tes_key = { 0, };
615 struct anv_shader_bin *tcs_bin = NULL;
616 struct anv_shader_bin *tes_bin = NULL;
617 unsigned char tcs_sha1[40];
618 unsigned char tes_sha1[40];
619
620 populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
621 populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
622 tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
623
624 if (cache) {
625 anv_pipeline_hash_shader(pipeline, tcs_module, tcs_entrypoint,
626 MESA_SHADER_TESS_CTRL, tcs_spec_info,
627 &tcs_key, sizeof(tcs_key), tcs_sha1);
628 anv_pipeline_hash_shader(pipeline, tes_module, tes_entrypoint,
629 MESA_SHADER_TESS_EVAL, tes_spec_info,
630 &tes_key, sizeof(tes_key), tes_sha1);
631 memcpy(&tcs_sha1[20], tes_sha1, 20);
632 memcpy(&tes_sha1[20], tcs_sha1, 20);
633 tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
634 tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
635 }
636
637 if (tcs_bin == NULL || tes_bin == NULL) {
638 struct brw_tcs_prog_data tcs_prog_data = { 0, };
639 struct brw_tes_prog_data tes_prog_data = { 0, };
640 struct anv_pipeline_binding tcs_surface_to_descriptor[256];
641 struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
642 struct anv_pipeline_binding tes_surface_to_descriptor[256];
643 struct anv_pipeline_binding tes_sampler_to_descriptor[256];
644
645 tcs_map = (struct anv_pipeline_bind_map) {
646 .surface_to_descriptor = tcs_surface_to_descriptor,
647 .sampler_to_descriptor = tcs_sampler_to_descriptor
648 };
649 tes_map = (struct anv_pipeline_bind_map) {
650 .surface_to_descriptor = tes_surface_to_descriptor,
651 .sampler_to_descriptor = tes_sampler_to_descriptor
652 };
653
654 nir_shader *tcs_nir =
655 anv_pipeline_compile(pipeline, tcs_module, tcs_entrypoint,
656 MESA_SHADER_TESS_CTRL, tcs_spec_info,
657 &tcs_prog_data.base.base, &tcs_map);
658 nir_shader *tes_nir =
659 anv_pipeline_compile(pipeline, tes_module, tes_entrypoint,
660 MESA_SHADER_TESS_EVAL, tes_spec_info,
661 &tes_prog_data.base.base, &tes_map);
662 if (tcs_nir == NULL || tes_nir == NULL)
663 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
664
665 nir_lower_tes_patch_vertices(tes_nir,
666 tcs_nir->info->tess.tcs_vertices_out);
667
668 /* Copy TCS info into the TES info */
669 merge_tess_info(tes_nir->info, tcs_nir->info);
670
671 anv_fill_binding_table(&tcs_prog_data.base.base, 0);
672 anv_fill_binding_table(&tes_prog_data.base.base, 0);
673
674 void *mem_ctx = ralloc_context(NULL);
675
676 ralloc_steal(mem_ctx, tcs_nir);
677 ralloc_steal(mem_ctx, tes_nir);
678
679 /* Whacking the key after cache lookup is a bit sketchy, but all of
680 * this comes from the SPIR-V, which is part of the hash used for the
681 * pipeline cache. So it should be safe.
682 */
683 tcs_key.tes_primitive_mode = tes_nir->info->tess.primitive_mode;
684 tcs_key.outputs_written = tcs_nir->info->outputs_written;
685 tcs_key.patch_outputs_written = tcs_nir->info->patch_outputs_written;
686 tcs_key.quads_workaround =
687 devinfo->gen < 9 &&
688 tes_nir->info->tess.primitive_mode == 7 /* GL_QUADS */ &&
689 tes_nir->info->tess.spacing == TESS_SPACING_EQUAL;
690
691 tes_key.inputs_read = tcs_key.outputs_written;
692 tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
693
694 unsigned code_size;
695 const int shader_time_index = -1;
696 const unsigned *shader_code;
697
698 shader_code =
699 brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
700 tcs_nir, shader_time_index, &code_size, NULL);
701 if (shader_code == NULL) {
702 ralloc_free(mem_ctx);
703 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
704 }
705
706 tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
707 tcs_sha1, sizeof(tcs_sha1),
708 shader_code, code_size,
709 &tcs_prog_data.base.base,
710 sizeof(tcs_prog_data),
711 &tcs_map);
712 if (!tcs_bin) {
713 ralloc_free(mem_ctx);
714 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
715 }
716
717 shader_code =
718 brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
719 &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
720 NULL, shader_time_index, &code_size, NULL);
721 if (shader_code == NULL) {
722 ralloc_free(mem_ctx);
723 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
724 }
725
726 tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
727 tes_sha1, sizeof(tes_sha1),
728 shader_code, code_size,
729 &tes_prog_data.base.base,
730 sizeof(tes_prog_data),
731 &tes_map);
732 if (!tes_bin) {
733 ralloc_free(mem_ctx);
734 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
735 }
736
737 ralloc_free(mem_ctx);
738 }
739
740 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
741 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
742
743 return VK_SUCCESS;
744 }
745
746 static VkResult
747 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
748 struct anv_pipeline_cache *cache,
749 const VkGraphicsPipelineCreateInfo *info,
750 struct anv_shader_module *module,
751 const char *entrypoint,
752 const VkSpecializationInfo *spec_info)
753 {
754 const struct brw_compiler *compiler =
755 pipeline->device->instance->physicalDevice.compiler;
756 struct anv_pipeline_bind_map map;
757 struct brw_gs_prog_key key;
758 struct anv_shader_bin *bin = NULL;
759 unsigned char sha1[20];
760
761 populate_gs_prog_key(&pipeline->device->info, &key);
762
763 if (cache) {
764 anv_pipeline_hash_shader(pipeline, module, entrypoint,
765 MESA_SHADER_GEOMETRY, spec_info,
766 &key, sizeof(key), sha1);
767 bin = anv_pipeline_cache_search(cache, sha1, 20);
768 }
769
770 if (bin == NULL) {
771 struct brw_gs_prog_data prog_data = { 0, };
772 struct anv_pipeline_binding surface_to_descriptor[256];
773 struct anv_pipeline_binding sampler_to_descriptor[256];
774
775 map = (struct anv_pipeline_bind_map) {
776 .surface_to_descriptor = surface_to_descriptor,
777 .sampler_to_descriptor = sampler_to_descriptor
778 };
779
780 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
781 MESA_SHADER_GEOMETRY, spec_info,
782 &prog_data.base.base, &map);
783 if (nir == NULL)
784 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
785
786 anv_fill_binding_table(&prog_data.base.base, 0);
787
788 void *mem_ctx = ralloc_context(NULL);
789
790 ralloc_steal(mem_ctx, nir);
791
792 brw_compute_vue_map(&pipeline->device->info,
793 &prog_data.base.vue_map,
794 nir->info->outputs_written,
795 nir->info->separate_shader);
796
797 unsigned code_size;
798 const unsigned *shader_code =
799 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
800 NULL, -1, &code_size, NULL);
801 if (shader_code == NULL) {
802 ralloc_free(mem_ctx);
803 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
804 }
805
806 /* TODO: SIMD8 GS */
807 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
808 shader_code, code_size,
809 &prog_data.base.base, sizeof(prog_data),
810 &map);
811 if (!bin) {
812 ralloc_free(mem_ctx);
813 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
814 }
815
816 ralloc_free(mem_ctx);
817 }
818
819 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
820
821 return VK_SUCCESS;
822 }
823
824 static VkResult
825 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
826 struct anv_pipeline_cache *cache,
827 const VkGraphicsPipelineCreateInfo *info,
828 struct anv_shader_module *module,
829 const char *entrypoint,
830 const VkSpecializationInfo *spec_info)
831 {
832 const struct brw_compiler *compiler =
833 pipeline->device->instance->physicalDevice.compiler;
834 struct anv_pipeline_bind_map map;
835 struct brw_wm_prog_key key;
836 struct anv_shader_bin *bin = NULL;
837 unsigned char sha1[20];
838
839 populate_wm_prog_key(pipeline, info, &key);
840
841 if (cache) {
842 anv_pipeline_hash_shader(pipeline, module, entrypoint,
843 MESA_SHADER_FRAGMENT, spec_info,
844 &key, sizeof(key), sha1);
845 bin = anv_pipeline_cache_search(cache, sha1, 20);
846 }
847
848 if (bin == NULL) {
849 struct brw_wm_prog_data prog_data = { 0, };
850 struct anv_pipeline_binding surface_to_descriptor[256];
851 struct anv_pipeline_binding sampler_to_descriptor[256];
852
853 map = (struct anv_pipeline_bind_map) {
854 .surface_to_descriptor = surface_to_descriptor + 8,
855 .sampler_to_descriptor = sampler_to_descriptor
856 };
857
858 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
859 MESA_SHADER_FRAGMENT, spec_info,
860 &prog_data.base, &map);
861 if (nir == NULL)
862 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
863
864 unsigned num_rts = 0;
865 struct anv_pipeline_binding rt_bindings[8];
866 nir_function_impl *impl = nir_shader_get_entrypoint(nir);
867 nir_foreach_variable_safe(var, &nir->outputs) {
868 if (var->data.location < FRAG_RESULT_DATA0)
869 continue;
870
871 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
872 if (rt >= key.nr_color_regions) {
873 /* Out-of-bounds, throw it away */
874 var->data.mode = nir_var_local;
875 exec_node_remove(&var->node);
876 exec_list_push_tail(&impl->locals, &var->node);
877 continue;
878 }
879
880 /* Give it a new, compacted, location */
881 var->data.location = FRAG_RESULT_DATA0 + num_rts;
882
883 unsigned array_len =
884 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
885 assert(num_rts + array_len <= 8);
886
887 for (unsigned i = 0; i < array_len; i++) {
888 rt_bindings[num_rts + i] = (struct anv_pipeline_binding) {
889 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
890 .binding = 0,
891 .index = rt + i,
892 };
893 }
894
895 num_rts += array_len;
896 }
897
898 if (num_rts == 0) {
899 /* If we have no render targets, we need a null render target */
900 rt_bindings[0] = (struct anv_pipeline_binding) {
901 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
902 .binding = 0,
903 .index = UINT8_MAX,
904 };
905 num_rts = 1;
906 }
907
908 assert(num_rts <= 8);
909 map.surface_to_descriptor -= num_rts;
910 map.surface_count += num_rts;
911 assert(map.surface_count <= 256);
912 memcpy(map.surface_to_descriptor, rt_bindings,
913 num_rts * sizeof(*rt_bindings));
914
915 anv_fill_binding_table(&prog_data.base, num_rts);
916
917 void *mem_ctx = ralloc_context(NULL);
918
919 ralloc_steal(mem_ctx, nir);
920
921 unsigned code_size;
922 const unsigned *shader_code =
923 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
924 NULL, -1, -1, true, false, NULL, &code_size, NULL);
925 if (shader_code == NULL) {
926 ralloc_free(mem_ctx);
927 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
928 }
929
930 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
931 shader_code, code_size,
932 &prog_data.base, sizeof(prog_data),
933 &map);
934 if (!bin) {
935 ralloc_free(mem_ctx);
936 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
937 }
938
939 ralloc_free(mem_ctx);
940 }
941
942 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
943
944 return VK_SUCCESS;
945 }
946
947 VkResult
948 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
949 struct anv_pipeline_cache *cache,
950 const VkComputePipelineCreateInfo *info,
951 struct anv_shader_module *module,
952 const char *entrypoint,
953 const VkSpecializationInfo *spec_info)
954 {
955 const struct brw_compiler *compiler =
956 pipeline->device->instance->physicalDevice.compiler;
957 struct anv_pipeline_bind_map map;
958 struct brw_cs_prog_key key;
959 struct anv_shader_bin *bin = NULL;
960 unsigned char sha1[20];
961
962 populate_cs_prog_key(&pipeline->device->info, &key);
963
964 if (cache) {
965 anv_pipeline_hash_shader(pipeline, module, entrypoint,
966 MESA_SHADER_COMPUTE, spec_info,
967 &key, sizeof(key), sha1);
968 bin = anv_pipeline_cache_search(cache, sha1, 20);
969 }
970
971 if (bin == NULL) {
972 struct brw_cs_prog_data prog_data = { 0, };
973 struct anv_pipeline_binding surface_to_descriptor[256];
974 struct anv_pipeline_binding sampler_to_descriptor[256];
975
976 map = (struct anv_pipeline_bind_map) {
977 .surface_to_descriptor = surface_to_descriptor,
978 .sampler_to_descriptor = sampler_to_descriptor
979 };
980
981 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
982 MESA_SHADER_COMPUTE, spec_info,
983 &prog_data.base, &map);
984 if (nir == NULL)
985 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
986
987 anv_fill_binding_table(&prog_data.base, 1);
988
989 void *mem_ctx = ralloc_context(NULL);
990
991 ralloc_steal(mem_ctx, nir);
992
993 unsigned code_size;
994 const unsigned *shader_code =
995 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
996 -1, &code_size, NULL);
997 if (shader_code == NULL) {
998 ralloc_free(mem_ctx);
999 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1000 }
1001
1002 bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
1003 shader_code, code_size,
1004 &prog_data.base, sizeof(prog_data),
1005 &map);
1006 if (!bin) {
1007 ralloc_free(mem_ctx);
1008 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1009 }
1010
1011 ralloc_free(mem_ctx);
1012 }
1013
1014 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
1015
1016 return VK_SUCCESS;
1017 }
1018
1019 /**
1020 * Copy pipeline state not marked as dynamic.
1021 * Dynamic state is pipeline state which hasn't been provided at pipeline
1022 * creation time, but is dynamically provided afterwards using various
1023 * vkCmdSet* functions.
1024 *
1025 * The set of state considered "non_dynamic" is determined by the pieces of
1026 * state that have their corresponding VkDynamicState enums omitted from
1027 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1028 *
1029 * @param[out] pipeline Destination non_dynamic state.
1030 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1031 */
1032 static void
1033 copy_non_dynamic_state(struct anv_pipeline *pipeline,
1034 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1035 {
1036 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1037 struct anv_subpass *subpass = pipeline->subpass;
1038
1039 pipeline->dynamic_state = default_dynamic_state;
1040
1041 if (pCreateInfo->pDynamicState) {
1042 /* Remove all of the states that are marked as dynamic */
1043 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1044 for (uint32_t s = 0; s < count; s++)
1045 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1046 }
1047
1048 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1049
1050 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1051 *
1052 * pViewportState is [...] NULL if the pipeline
1053 * has rasterization disabled.
1054 */
1055 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1056 assert(pCreateInfo->pViewportState);
1057
1058 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1059 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1060 typed_memcpy(dynamic->viewport.viewports,
1061 pCreateInfo->pViewportState->pViewports,
1062 pCreateInfo->pViewportState->viewportCount);
1063 }
1064
1065 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1066 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1067 typed_memcpy(dynamic->scissor.scissors,
1068 pCreateInfo->pViewportState->pScissors,
1069 pCreateInfo->pViewportState->scissorCount);
1070 }
1071 }
1072
1073 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1074 assert(pCreateInfo->pRasterizationState);
1075 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1076 }
1077
1078 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1079 assert(pCreateInfo->pRasterizationState);
1080 dynamic->depth_bias.bias =
1081 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1082 dynamic->depth_bias.clamp =
1083 pCreateInfo->pRasterizationState->depthBiasClamp;
1084 dynamic->depth_bias.slope =
1085 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1086 }
1087
1088 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1089 *
1090 * pColorBlendState is [...] NULL if the pipeline has rasterization
1091 * disabled or if the subpass of the render pass the pipeline is
1092 * created against does not use any color attachments.
1093 */
1094 bool uses_color_att = false;
1095 for (unsigned i = 0; i < subpass->color_count; ++i) {
1096 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1097 uses_color_att = true;
1098 break;
1099 }
1100 }
1101
1102 if (uses_color_att &&
1103 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1104 assert(pCreateInfo->pColorBlendState);
1105
1106 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
1107 typed_memcpy(dynamic->blend_constants,
1108 pCreateInfo->pColorBlendState->blendConstants, 4);
1109 }
1110
1111 /* If there is no depthstencil attachment, then don't read
1112 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1113 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1114 * no need to override the depthstencil defaults in
1115 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1116 *
1117 * Section 9.2 of the Vulkan 1.0.15 spec says:
1118 *
1119 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1120 * disabled or if the subpass of the render pass the pipeline is created
1121 * against does not use a depth/stencil attachment.
1122 */
1123 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1124 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1125 assert(pCreateInfo->pDepthStencilState);
1126
1127 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1128 dynamic->depth_bounds.min =
1129 pCreateInfo->pDepthStencilState->minDepthBounds;
1130 dynamic->depth_bounds.max =
1131 pCreateInfo->pDepthStencilState->maxDepthBounds;
1132 }
1133
1134 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1135 dynamic->stencil_compare_mask.front =
1136 pCreateInfo->pDepthStencilState->front.compareMask;
1137 dynamic->stencil_compare_mask.back =
1138 pCreateInfo->pDepthStencilState->back.compareMask;
1139 }
1140
1141 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1142 dynamic->stencil_write_mask.front =
1143 pCreateInfo->pDepthStencilState->front.writeMask;
1144 dynamic->stencil_write_mask.back =
1145 pCreateInfo->pDepthStencilState->back.writeMask;
1146 }
1147
1148 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1149 dynamic->stencil_reference.front =
1150 pCreateInfo->pDepthStencilState->front.reference;
1151 dynamic->stencil_reference.back =
1152 pCreateInfo->pDepthStencilState->back.reference;
1153 }
1154 }
1155
1156 pipeline->dynamic_state_mask = states;
1157 }
1158
1159 static void
1160 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1161 {
1162 #ifdef DEBUG
1163 struct anv_render_pass *renderpass = NULL;
1164 struct anv_subpass *subpass = NULL;
1165
1166 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1167 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1168 */
1169 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1170
1171 renderpass = anv_render_pass_from_handle(info->renderPass);
1172 assert(renderpass);
1173
1174 assert(info->subpass < renderpass->subpass_count);
1175 subpass = &renderpass->subpasses[info->subpass];
1176
1177 assert(info->stageCount >= 1);
1178 assert(info->pVertexInputState);
1179 assert(info->pInputAssemblyState);
1180 assert(info->pRasterizationState);
1181 if (!info->pRasterizationState->rasterizerDiscardEnable) {
1182 assert(info->pViewportState);
1183 assert(info->pMultisampleState);
1184
1185 if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
1186 assert(info->pDepthStencilState);
1187
1188 if (subpass && subpass->color_count > 0)
1189 assert(info->pColorBlendState);
1190 }
1191
1192 for (uint32_t i = 0; i < info->stageCount; ++i) {
1193 switch (info->pStages[i].stage) {
1194 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1195 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1196 assert(info->pTessellationState);
1197 break;
1198 default:
1199 break;
1200 }
1201 }
1202 #endif
1203 }
1204
1205 /**
1206 * Calculate the desired L3 partitioning based on the current state of the
1207 * pipeline. For now this simply returns the conservative defaults calculated
1208 * by get_default_l3_weights(), but we could probably do better by gathering
1209 * more statistics from the pipeline state (e.g. guess of expected URB usage
1210 * and bound surfaces), or by using feed-back from performance counters.
1211 */
1212 void
1213 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
1214 {
1215 const struct gen_device_info *devinfo = &pipeline->device->info;
1216
1217 const struct gen_l3_weights w =
1218 gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
1219
1220 pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
1221 pipeline->urb.total_size =
1222 gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
1223 }
1224
1225 VkResult
1226 anv_pipeline_init(struct anv_pipeline *pipeline,
1227 struct anv_device *device,
1228 struct anv_pipeline_cache *cache,
1229 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1230 const VkAllocationCallbacks *alloc)
1231 {
1232 VkResult result;
1233
1234 anv_pipeline_validate_create_info(pCreateInfo);
1235
1236 if (alloc == NULL)
1237 alloc = &device->alloc;
1238
1239 pipeline->device = device;
1240
1241 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
1242 assert(pCreateInfo->subpass < render_pass->subpass_count);
1243 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
1244
1245 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1246
1247 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1248 if (result != VK_SUCCESS)
1249 return result;
1250
1251 pipeline->batch.alloc = alloc;
1252 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1253 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1254 pipeline->batch.relocs = &pipeline->batch_relocs;
1255 pipeline->batch.status = VK_SUCCESS;
1256
1257 copy_non_dynamic_state(pipeline, pCreateInfo);
1258 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
1259 pCreateInfo->pRasterizationState->depthClampEnable;
1260
1261 pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
1262 pCreateInfo->pMultisampleState->sampleShadingEnable;
1263
1264 pipeline->needs_data_cache = false;
1265
1266 /* When we free the pipeline, we detect stages based on the NULL status
1267 * of various prog_data pointers. Make them NULL by default.
1268 */
1269 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
1270
1271 pipeline->active_stages = 0;
1272
1273 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1274 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1275 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1276 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1277 pStages[stage] = &pCreateInfo->pStages[i];
1278 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1279 }
1280
1281 if (modules[MESA_SHADER_VERTEX]) {
1282 result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1283 modules[MESA_SHADER_VERTEX],
1284 pStages[MESA_SHADER_VERTEX]->pName,
1285 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1286 if (result != VK_SUCCESS)
1287 goto compile_fail;
1288 }
1289
1290 if (modules[MESA_SHADER_TESS_EVAL]) {
1291 anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
1292 modules[MESA_SHADER_TESS_CTRL],
1293 pStages[MESA_SHADER_TESS_CTRL]->pName,
1294 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1295 modules[MESA_SHADER_TESS_EVAL],
1296 pStages[MESA_SHADER_TESS_EVAL]->pName,
1297 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
1298 }
1299
1300 if (modules[MESA_SHADER_GEOMETRY]) {
1301 result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1302 modules[MESA_SHADER_GEOMETRY],
1303 pStages[MESA_SHADER_GEOMETRY]->pName,
1304 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1305 if (result != VK_SUCCESS)
1306 goto compile_fail;
1307 }
1308
1309 if (modules[MESA_SHADER_FRAGMENT]) {
1310 result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
1311 modules[MESA_SHADER_FRAGMENT],
1312 pStages[MESA_SHADER_FRAGMENT]->pName,
1313 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1314 if (result != VK_SUCCESS)
1315 goto compile_fail;
1316 }
1317
1318 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1319
1320 anv_pipeline_setup_l3_config(pipeline, false);
1321
1322 const VkPipelineVertexInputStateCreateInfo *vi_info =
1323 pCreateInfo->pVertexInputState;
1324
1325 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1326
1327 pipeline->vb_used = 0;
1328 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1329 const VkVertexInputAttributeDescription *desc =
1330 &vi_info->pVertexAttributeDescriptions[i];
1331
1332 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1333 pipeline->vb_used |= 1 << desc->binding;
1334 }
1335
1336 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1337 const VkVertexInputBindingDescription *desc =
1338 &vi_info->pVertexBindingDescriptions[i];
1339
1340 pipeline->binding_stride[desc->binding] = desc->stride;
1341
1342 /* Step rate is programmed per vertex element (attribute), not
1343 * binding. Set up a map of which bindings step per instance, for
1344 * reference by vertex element setup. */
1345 switch (desc->inputRate) {
1346 default:
1347 case VK_VERTEX_INPUT_RATE_VERTEX:
1348 pipeline->instancing_enable[desc->binding] = false;
1349 break;
1350 case VK_VERTEX_INPUT_RATE_INSTANCE:
1351 pipeline->instancing_enable[desc->binding] = true;
1352 break;
1353 }
1354 }
1355
1356 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1357 pCreateInfo->pInputAssemblyState;
1358 const VkPipelineTessellationStateCreateInfo *tess_info =
1359 pCreateInfo->pTessellationState;
1360 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1361
1362 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1363 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1364 else
1365 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1366
1367 return VK_SUCCESS;
1368
1369 compile_fail:
1370 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1371 if (pipeline->shaders[s])
1372 anv_shader_bin_unref(device, pipeline->shaders[s]);
1373 }
1374
1375 anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
1376
1377 return result;
1378 }