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anv/pipeline: Use dynamic checks for max push constants
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "nir/spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 const uint32_t *data =
127 spec_info->pData + spec_info->pMapEntries[i].offset;
128 assert((const void *)(data + 1) <=
129 spec_info->pData + spec_info->dataSize);
130
131 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
132 spec_entries[i].data = *data;
133 }
134 }
135
136 entry_point = spirv_to_nir(spirv, module->size / 4,
137 spec_entries, num_spec_entries,
138 stage, entrypoint_name, nir_options);
139 nir = entry_point->shader;
140 assert(nir->stage == stage);
141 nir_validate_shader(nir);
142
143 free(spec_entries);
144
145 nir_lower_returns(nir);
146 nir_validate_shader(nir);
147
148 nir_inline_functions(nir);
149 nir_validate_shader(nir);
150
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
153 if (func != entry_point)
154 exec_node_remove(&func->node);
155 }
156 assert(exec_list_length(&nir->functions) == 1);
157 entry_point->name = ralloc_strdup(entry_point, "main");
158
159 nir_remove_dead_variables(nir, nir_var_shader_in);
160 nir_remove_dead_variables(nir, nir_var_shader_out);
161 nir_remove_dead_variables(nir, nir_var_system_value);
162 nir_validate_shader(nir);
163
164 nir_lower_outputs_to_temporaries(entry_point->shader, entry_point);
165
166 nir_lower_system_values(nir);
167 nir_validate_shader(nir);
168 }
169
170 /* Vulkan uses the separate-shader linking model */
171 nir->info.separate_shader = true;
172
173 nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
174
175 nir_shader_gather_info(nir, entry_point->impl);
176
177 uint32_t indirect_mask = 0;
178 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
179 indirect_mask |= (1 << nir_var_shader_in);
180 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
181 indirect_mask |= 1 << nir_var_local;
182
183 nir_lower_indirect_derefs(nir, indirect_mask);
184
185 return nir;
186 }
187
188 void anv_DestroyPipeline(
189 VkDevice _device,
190 VkPipeline _pipeline,
191 const VkAllocationCallbacks* pAllocator)
192 {
193 ANV_FROM_HANDLE(anv_device, device, _device);
194 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
195
196 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
197 free(pipeline->bindings[s].surface_to_descriptor);
198 free(pipeline->bindings[s].sampler_to_descriptor);
199 }
200
201 anv_reloc_list_finish(&pipeline->batch_relocs,
202 pAllocator ? pAllocator : &device->alloc);
203 if (pipeline->blend_state.map)
204 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
205 anv_free2(&device->alloc, pAllocator, pipeline);
206 }
207
208 static const uint32_t vk_to_gen_primitive_type[] = {
209 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
211 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
215 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
216 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
218 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
219 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
220 };
221
222 static void
223 populate_sampler_prog_key(const struct brw_device_info *devinfo,
224 struct brw_sampler_prog_key_data *key)
225 {
226 /* XXX: Handle texture swizzle on HSW- */
227 for (int i = 0; i < MAX_SAMPLERS; i++) {
228 /* Assume color sampler, no swizzling. (Works for BDW+) */
229 key->swizzles[i] = SWIZZLE_XYZW;
230 }
231 }
232
233 static void
234 populate_vs_prog_key(const struct brw_device_info *devinfo,
235 struct brw_vs_prog_key *key)
236 {
237 memset(key, 0, sizeof(*key));
238
239 populate_sampler_prog_key(devinfo, &key->tex);
240
241 /* XXX: Handle vertex input work-arounds */
242
243 /* XXX: Handle sampler_prog_key */
244 }
245
246 static void
247 populate_gs_prog_key(const struct brw_device_info *devinfo,
248 struct brw_gs_prog_key *key)
249 {
250 memset(key, 0, sizeof(*key));
251
252 populate_sampler_prog_key(devinfo, &key->tex);
253 }
254
255 static void
256 populate_wm_prog_key(const struct brw_device_info *devinfo,
257 const VkGraphicsPipelineCreateInfo *info,
258 const struct anv_graphics_pipeline_create_info *extra,
259 struct brw_wm_prog_key *key)
260 {
261 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
262
263 memset(key, 0, sizeof(*key));
264
265 populate_sampler_prog_key(devinfo, &key->tex);
266
267 /* TODO: Fill out key->input_slots_valid */
268
269 /* Vulkan doesn't specify a default */
270 key->high_quality_derivatives = false;
271
272 /* XXX Vulkan doesn't appear to specify */
273 key->clamp_fragment_color = false;
274
275 /* Vulkan always specifies upper-left coordinates */
276 key->drawable_height = 0;
277 key->render_to_fbo = false;
278
279 if (extra && extra->color_attachment_count >= 0) {
280 key->nr_color_regions = extra->color_attachment_count;
281 } else {
282 key->nr_color_regions =
283 render_pass->subpasses[info->subpass].color_count;
284 }
285
286 key->replicate_alpha = key->nr_color_regions > 1 &&
287 info->pMultisampleState &&
288 info->pMultisampleState->alphaToCoverageEnable;
289
290 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
291 /* We should probably pull this out of the shader, but it's fairly
292 * harmless to compute it and then let dead-code take care of it.
293 */
294 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
295 if (key->persample_shading)
296 key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
297
298 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
299 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
300 }
301 }
302
303 static void
304 populate_cs_prog_key(const struct brw_device_info *devinfo,
305 struct brw_cs_prog_key *key)
306 {
307 memset(key, 0, sizeof(*key));
308
309 populate_sampler_prog_key(devinfo, &key->tex);
310 }
311
312 static nir_shader *
313 anv_pipeline_compile(struct anv_pipeline *pipeline,
314 struct anv_shader_module *module,
315 const char *entrypoint,
316 gl_shader_stage stage,
317 const VkSpecializationInfo *spec_info,
318 struct brw_stage_prog_data *prog_data)
319 {
320 const struct brw_compiler *compiler =
321 pipeline->device->instance->physicalDevice.compiler;
322
323 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
324 module, entrypoint, stage,
325 spec_info);
326 if (nir == NULL)
327 return NULL;
328
329 anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
330
331 /* Figure out the number of parameters */
332 prog_data->nr_params = 0;
333
334 if (nir->num_uniforms > 0) {
335 /* If the shader uses any push constants at all, we'll just give
336 * them the maximum possible number
337 */
338 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
339 }
340
341 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
342 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
343
344 if (nir->info.num_images > 0)
345 prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
346
347 if (prog_data->nr_params > 0) {
348 /* XXX: I think we're leaking this */
349 prog_data->param = (const union gl_constant_value **)
350 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
351
352 /* We now set the param values to be offsets into a
353 * anv_push_constant_data structure. Since the compiler doesn't
354 * actually dereference any of the gl_constant_value pointers in the
355 * params array, it doesn't really matter what we put here.
356 */
357 struct anv_push_constants *null_data = NULL;
358 if (nir->num_uniforms > 0) {
359 /* Fill out the push constants section of the param array */
360 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
361 prog_data->param[i] = (const union gl_constant_value *)
362 &null_data->client_data[i * sizeof(float)];
363 }
364 }
365
366 /* Set up dynamic offsets */
367 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
368
369 char surface_usage_mask[256], sampler_usage_mask[256];
370 zero(surface_usage_mask);
371 zero(sampler_usage_mask);
372
373 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
374 if (pipeline->layout)
375 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data);
376
377 /* All binding table offsets provided by apply_pipeline_layout() are
378 * relative to the start of the bindint table (plus MAX_RTS for VS).
379 */
380 unsigned bias;
381 switch (stage) {
382 case MESA_SHADER_FRAGMENT:
383 bias = MAX_RTS;
384 break;
385 case MESA_SHADER_COMPUTE:
386 bias = 1;
387 break;
388 default:
389 bias = 0;
390 break;
391 }
392 prog_data->binding_table.size_bytes = 0;
393 prog_data->binding_table.texture_start = bias;
394 prog_data->binding_table.ubo_start = bias;
395 prog_data->binding_table.ssbo_start = bias;
396 prog_data->binding_table.image_start = bias;
397
398 /* Finish the optimization and compilation process */
399 if (nir->stage != MESA_SHADER_VERTEX &&
400 nir->stage != MESA_SHADER_TESS_CTRL &&
401 nir->stage != MESA_SHADER_TESS_EVAL &&
402 nir->stage != MESA_SHADER_FRAGMENT) {
403 nir = brw_nir_lower_io(nir, &pipeline->device->info,
404 compiler->scalar_stage[stage], false, NULL);
405 }
406
407 /* nir_lower_io will only handle the push constants; we need to set this
408 * to the full number of possible uniforms.
409 */
410 nir->num_uniforms = prog_data->nr_params * 4;
411
412 return nir;
413 }
414
415 static void
416 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
417 gl_shader_stage stage,
418 struct brw_stage_prog_data *prog_data)
419 {
420 struct brw_device_info *devinfo = &pipeline->device->info;
421 uint32_t max_threads[] = {
422 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
423 [MESA_SHADER_TESS_CTRL] = devinfo->max_hs_threads,
424 [MESA_SHADER_TESS_EVAL] = devinfo->max_ds_threads,
425 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
426 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
427 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
428 };
429
430 pipeline->prog_data[stage] = prog_data;
431 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
432 pipeline->scratch_start[stage] = pipeline->total_scratch;
433 pipeline->total_scratch =
434 align_u32(pipeline->total_scratch, 1024) +
435 prog_data->total_scratch * max_threads[stage];
436 }
437
438 static VkResult
439 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
440 struct anv_pipeline_cache *cache,
441 const VkGraphicsPipelineCreateInfo *info,
442 struct anv_shader_module *module,
443 const char *entrypoint,
444 const VkSpecializationInfo *spec_info)
445 {
446 const struct brw_compiler *compiler =
447 pipeline->device->instance->physicalDevice.compiler;
448 struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
449 struct brw_vs_prog_key key;
450 uint32_t kernel;
451 unsigned char sha1[20], *hash;
452
453 populate_vs_prog_key(&pipeline->device->info, &key);
454
455 if (module->size > 0) {
456 hash = sha1;
457 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
458 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
459 } else {
460 hash = NULL;
461 }
462
463 if (module->size == 0 || kernel == NO_KERNEL) {
464 memset(prog_data, 0, sizeof(*prog_data));
465
466 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
467 MESA_SHADER_VERTEX, spec_info,
468 &prog_data->base.base);
469 if (nir == NULL)
470 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
471
472 void *mem_ctx = ralloc_context(NULL);
473
474 if (module->nir == NULL)
475 ralloc_steal(mem_ctx, nir);
476
477 prog_data->inputs_read = nir->info.inputs_read;
478 if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
479 pipeline->writes_point_size = true;
480
481 brw_compute_vue_map(&pipeline->device->info,
482 &prog_data->base.vue_map,
483 nir->info.outputs_written,
484 nir->info.separate_shader);
485
486 unsigned code_size;
487 const unsigned *shader_code =
488 brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
489 NULL, false, -1, &code_size, NULL);
490 if (shader_code == NULL) {
491 ralloc_free(mem_ctx);
492 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
493 }
494
495 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
496 shader_code, code_size,
497 prog_data, sizeof(*prog_data));
498 ralloc_free(mem_ctx);
499 }
500
501 if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
502 pipeline->vs_simd8 = kernel;
503 pipeline->vs_vec4 = NO_KERNEL;
504 } else {
505 pipeline->vs_simd8 = NO_KERNEL;
506 pipeline->vs_vec4 = kernel;
507 }
508
509 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
510 &prog_data->base.base);
511
512 return VK_SUCCESS;
513 }
514
515 static VkResult
516 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
517 struct anv_pipeline_cache *cache,
518 const VkGraphicsPipelineCreateInfo *info,
519 struct anv_shader_module *module,
520 const char *entrypoint,
521 const VkSpecializationInfo *spec_info)
522 {
523 const struct brw_compiler *compiler =
524 pipeline->device->instance->physicalDevice.compiler;
525 struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
526 struct brw_gs_prog_key key;
527 uint32_t kernel;
528 unsigned char sha1[20], *hash;
529
530 populate_gs_prog_key(&pipeline->device->info, &key);
531
532 if (module->size > 0) {
533 hash = sha1;
534 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
535 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
536 } else {
537 hash = NULL;
538 }
539
540 if (module->size == 0 || kernel == NO_KERNEL) {
541 memset(prog_data, 0, sizeof(*prog_data));
542
543 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
544 MESA_SHADER_GEOMETRY, spec_info,
545 &prog_data->base.base);
546 if (nir == NULL)
547 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
548
549 void *mem_ctx = ralloc_context(NULL);
550
551 if (module->nir == NULL)
552 ralloc_steal(mem_ctx, nir);
553
554 if (nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ))
555 pipeline->writes_point_size = true;
556
557 brw_compute_vue_map(&pipeline->device->info,
558 &prog_data->base.vue_map,
559 nir->info.outputs_written,
560 nir->info.separate_shader);
561
562 unsigned code_size;
563 const unsigned *shader_code =
564 brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
565 NULL, -1, &code_size, NULL);
566 if (shader_code == NULL) {
567 ralloc_free(mem_ctx);
568 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
569 }
570
571 /* TODO: SIMD8 GS */
572 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
573 shader_code, code_size,
574 prog_data, sizeof(*prog_data));
575
576 ralloc_free(mem_ctx);
577 }
578
579 pipeline->gs_kernel = kernel;
580
581 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
582 &prog_data->base.base);
583
584 return VK_SUCCESS;
585 }
586
587 static VkResult
588 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
589 struct anv_pipeline_cache *cache,
590 const VkGraphicsPipelineCreateInfo *info,
591 const struct anv_graphics_pipeline_create_info *extra,
592 struct anv_shader_module *module,
593 const char *entrypoint,
594 const VkSpecializationInfo *spec_info)
595 {
596 const struct brw_compiler *compiler =
597 pipeline->device->instance->physicalDevice.compiler;
598 struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
599 struct brw_wm_prog_key key;
600 uint32_t kernel;
601 unsigned char sha1[20], *hash;
602
603 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
604
605 if (pipeline->use_repclear)
606 key.nr_color_regions = 1;
607
608 if (module->size > 0) {
609 hash = sha1;
610 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
611 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
612 } else {
613 hash = NULL;
614 }
615
616 if (module->size == 0 || kernel == NO_KERNEL) {
617 memset(prog_data, 0, sizeof(*prog_data));
618
619 prog_data->binding_table.render_target_start = 0;
620
621 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
622 MESA_SHADER_FRAGMENT, spec_info,
623 &prog_data->base);
624 if (nir == NULL)
625 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
626
627 nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
628 nir_foreach_variable_safe(var, &nir->outputs) {
629 if (var->data.location < FRAG_RESULT_DATA0)
630 continue;
631
632 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
633 if (rt >= key.nr_color_regions) {
634 var->data.mode = nir_var_local;
635 exec_node_remove(&var->node);
636 exec_list_push_tail(&impl->locals, &var->node);
637 }
638 }
639
640 void *mem_ctx = ralloc_context(NULL);
641
642 if (module->nir == NULL)
643 ralloc_steal(mem_ctx, nir);
644
645 unsigned code_size;
646 const unsigned *shader_code =
647 brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
648 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
649 if (shader_code == NULL) {
650 ralloc_free(mem_ctx);
651 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
652 }
653
654 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
655 shader_code, code_size,
656 prog_data, sizeof(*prog_data));
657
658 ralloc_free(mem_ctx);
659 }
660
661 if (prog_data->no_8)
662 pipeline->ps_simd8 = NO_KERNEL;
663 else
664 pipeline->ps_simd8 = kernel;
665
666 if (prog_data->no_8 || prog_data->prog_offset_16) {
667 pipeline->ps_simd16 = kernel + prog_data->prog_offset_16;
668 } else {
669 pipeline->ps_simd16 = NO_KERNEL;
670 }
671
672 pipeline->ps_ksp2 = 0;
673 pipeline->ps_grf_start2 = 0;
674 if (pipeline->ps_simd8 != NO_KERNEL) {
675 pipeline->ps_ksp0 = pipeline->ps_simd8;
676 pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
677 if (pipeline->ps_simd16 != NO_KERNEL) {
678 pipeline->ps_ksp2 = pipeline->ps_simd16;
679 pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
680 }
681 } else if (pipeline->ps_simd16 != NO_KERNEL) {
682 pipeline->ps_ksp0 = pipeline->ps_simd16;
683 pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
684 }
685
686 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
687 &prog_data->base);
688
689 return VK_SUCCESS;
690 }
691
692 VkResult
693 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
694 struct anv_pipeline_cache *cache,
695 const VkComputePipelineCreateInfo *info,
696 struct anv_shader_module *module,
697 const char *entrypoint,
698 const VkSpecializationInfo *spec_info)
699 {
700 const struct brw_compiler *compiler =
701 pipeline->device->instance->physicalDevice.compiler;
702 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
703 struct brw_cs_prog_key key;
704 uint32_t kernel;
705 unsigned char sha1[20], *hash;
706
707 populate_cs_prog_key(&pipeline->device->info, &key);
708
709 if (module->size > 0) {
710 hash = sha1;
711 anv_hash_shader(hash, &key, sizeof(key), module, entrypoint, spec_info);
712 kernel = anv_pipeline_cache_search(cache, hash, prog_data);
713 } else {
714 hash = NULL;
715 }
716
717 if (module->size == 0 || kernel == NO_KERNEL) {
718 memset(prog_data, 0, sizeof(*prog_data));
719
720 prog_data->binding_table.work_groups_start = 0;
721
722 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
723 MESA_SHADER_COMPUTE, spec_info,
724 &prog_data->base);
725 if (nir == NULL)
726 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
727
728 prog_data->base.total_shared = nir->num_shared;
729
730 void *mem_ctx = ralloc_context(NULL);
731
732 if (module->nir == NULL)
733 ralloc_steal(mem_ctx, nir);
734
735 unsigned code_size;
736 const unsigned *shader_code =
737 brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
738 -1, &code_size, NULL);
739 if (shader_code == NULL) {
740 ralloc_free(mem_ctx);
741 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
742 }
743
744 kernel = anv_pipeline_cache_upload_kernel(cache, hash,
745 shader_code, code_size,
746 prog_data, sizeof(*prog_data));
747 ralloc_free(mem_ctx);
748 }
749
750 pipeline->cs_simd = kernel;
751
752 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
753 &prog_data->base);
754
755 return VK_SUCCESS;
756 }
757
758 static void
759 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
760 {
761 const struct brw_device_info *devinfo = &pipeline->device->info;
762 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
763 unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
764 unsigned vs_entry_size_bytes = vs_size * 64;
765 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
766 unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
767 unsigned gs_entry_size_bytes = gs_size * 64;
768
769 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
770 *
771 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
772 * Allocation Size is less than 9 512-bit URB entries.
773 *
774 * Similar text exists for GS.
775 */
776 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
777 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
778
779 /* URB allocations must be done in 8k chunks. */
780 unsigned chunk_size_bytes = 8192;
781
782 /* Determine the size of the URB in chunks. */
783 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
784
785 /* Reserve space for push constants */
786 unsigned push_constant_kb;
787 if (pipeline->device->info.gen >= 8)
788 push_constant_kb = 32;
789 else if (pipeline->device->info.is_haswell)
790 push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
791 else
792 push_constant_kb = 16;
793
794 unsigned push_constant_bytes = push_constant_kb * 1024;
795 unsigned push_constant_chunks =
796 push_constant_bytes / chunk_size_bytes;
797
798 /* Initially, assign each stage the minimum amount of URB space it needs,
799 * and make a note of how much additional space it "wants" (the amount of
800 * additional space it could actually make use of).
801 */
802
803 /* VS has a lower limit on the number of URB entries */
804 unsigned vs_chunks =
805 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
806 chunk_size_bytes) / chunk_size_bytes;
807 unsigned vs_wants =
808 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
809 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
810
811 unsigned gs_chunks = 0;
812 unsigned gs_wants = 0;
813 if (gs_present) {
814 /* There are two constraints on the minimum amount of URB space we can
815 * allocate:
816 *
817 * (1) We need room for at least 2 URB entries, since we always operate
818 * the GS in DUAL_OBJECT mode.
819 *
820 * (2) We can't allocate less than nr_gs_entries_granularity.
821 */
822 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
823 chunk_size_bytes) / chunk_size_bytes;
824 gs_wants =
825 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
826 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
827 }
828
829 /* There should always be enough URB space to satisfy the minimum
830 * requirements of each stage.
831 */
832 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
833 assert(total_needs <= urb_chunks);
834
835 /* Mete out remaining space (if any) in proportion to "wants". */
836 unsigned total_wants = vs_wants + gs_wants;
837 unsigned remaining_space = urb_chunks - total_needs;
838 if (remaining_space > total_wants)
839 remaining_space = total_wants;
840 if (remaining_space > 0) {
841 unsigned vs_additional = (unsigned)
842 round(vs_wants * (((double) remaining_space) / total_wants));
843 vs_chunks += vs_additional;
844 remaining_space -= vs_additional;
845 gs_chunks += remaining_space;
846 }
847
848 /* Sanity check that we haven't over-allocated. */
849 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
850
851 /* Finally, compute the number of entries that can fit in the space
852 * allocated to each stage.
853 */
854 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
855 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
856
857 /* Since we rounded up when computing *_wants, this may be slightly more
858 * than the maximum allowed amount, so correct for that.
859 */
860 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
861 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
862
863 /* Ensure that we program a multiple of the granularity. */
864 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
865 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
866
867 /* Finally, sanity check to make sure we have at least the minimum number
868 * of entries needed for each stage.
869 */
870 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
871 if (gs_present)
872 assert(nr_gs_entries >= 2);
873
874 /* Lay out the URB in the following order:
875 * - push constants
876 * - VS
877 * - GS
878 */
879 pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
880 pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
881 pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
882
883 pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
884 pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
885 pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
886
887 pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
888 pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
889 pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
890
891 pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
892 pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
893 pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
894
895 const unsigned stages =
896 _mesa_bitcount(pipeline->active_stages & VK_SHADER_STAGE_ALL_GRAPHICS);
897 const unsigned size_per_stage = push_constant_kb / stages;
898 unsigned used_kb = 0;
899
900 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
901 pipeline->urb.push_size[i] =
902 (pipeline->active_stages & (1 << i)) ? size_per_stage : 0;
903 used_kb += pipeline->urb.push_size[i];
904 assert(used_kb <= push_constant_kb);
905 }
906
907 pipeline->urb.push_size[MESA_SHADER_FRAGMENT] =
908 push_constant_kb - used_kb;
909 }
910
911 static void
912 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
913 const VkGraphicsPipelineCreateInfo *pCreateInfo)
914 {
915 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
916 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
917 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
918
919 pipeline->dynamic_state = default_dynamic_state;
920
921 if (pCreateInfo->pDynamicState) {
922 /* Remove all of the states that are marked as dynamic */
923 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
924 for (uint32_t s = 0; s < count; s++)
925 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
926 }
927
928 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
929
930 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
931 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
932 typed_memcpy(dynamic->viewport.viewports,
933 pCreateInfo->pViewportState->pViewports,
934 pCreateInfo->pViewportState->viewportCount);
935 }
936
937 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
938 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
939 typed_memcpy(dynamic->scissor.scissors,
940 pCreateInfo->pViewportState->pScissors,
941 pCreateInfo->pViewportState->scissorCount);
942 }
943
944 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
945 assert(pCreateInfo->pRasterizationState);
946 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
947 }
948
949 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
950 assert(pCreateInfo->pRasterizationState);
951 dynamic->depth_bias.bias =
952 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
953 dynamic->depth_bias.clamp =
954 pCreateInfo->pRasterizationState->depthBiasClamp;
955 dynamic->depth_bias.slope =
956 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
957 }
958
959 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
960 assert(pCreateInfo->pColorBlendState);
961 typed_memcpy(dynamic->blend_constants,
962 pCreateInfo->pColorBlendState->blendConstants, 4);
963 }
964
965 /* If there is no depthstencil attachment, then don't read
966 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
967 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
968 * no need to override the depthstencil defaults in
969 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
970 *
971 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
972 *
973 * pDepthStencilState [...] may only be NULL if renderPass and subpass
974 * specify a subpass that has no depth/stencil attachment.
975 */
976 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
977 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
978 assert(pCreateInfo->pDepthStencilState);
979 dynamic->depth_bounds.min =
980 pCreateInfo->pDepthStencilState->minDepthBounds;
981 dynamic->depth_bounds.max =
982 pCreateInfo->pDepthStencilState->maxDepthBounds;
983 }
984
985 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
986 assert(pCreateInfo->pDepthStencilState);
987 dynamic->stencil_compare_mask.front =
988 pCreateInfo->pDepthStencilState->front.compareMask;
989 dynamic->stencil_compare_mask.back =
990 pCreateInfo->pDepthStencilState->back.compareMask;
991 }
992
993 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
994 assert(pCreateInfo->pDepthStencilState);
995 dynamic->stencil_write_mask.front =
996 pCreateInfo->pDepthStencilState->front.writeMask;
997 dynamic->stencil_write_mask.back =
998 pCreateInfo->pDepthStencilState->back.writeMask;
999 }
1000
1001 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1002 assert(pCreateInfo->pDepthStencilState);
1003 dynamic->stencil_reference.front =
1004 pCreateInfo->pDepthStencilState->front.reference;
1005 dynamic->stencil_reference.back =
1006 pCreateInfo->pDepthStencilState->back.reference;
1007 }
1008 }
1009
1010 pipeline->dynamic_state_mask = states;
1011 }
1012
1013 static void
1014 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1015 {
1016 struct anv_render_pass *renderpass = NULL;
1017 struct anv_subpass *subpass = NULL;
1018
1019 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1020 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1021 * 4.2 Graphics Pipeline.
1022 */
1023 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1024
1025 renderpass = anv_render_pass_from_handle(info->renderPass);
1026 assert(renderpass);
1027
1028 if (renderpass != &anv_meta_dummy_renderpass) {
1029 assert(info->subpass < renderpass->subpass_count);
1030 subpass = &renderpass->subpasses[info->subpass];
1031 }
1032
1033 assert(info->stageCount >= 1);
1034 assert(info->pVertexInputState);
1035 assert(info->pInputAssemblyState);
1036 assert(info->pViewportState);
1037 assert(info->pRasterizationState);
1038
1039 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1040 assert(info->pDepthStencilState);
1041
1042 if (subpass && subpass->color_count > 0)
1043 assert(info->pColorBlendState);
1044
1045 for (uint32_t i = 0; i < info->stageCount; ++i) {
1046 switch (info->pStages[i].stage) {
1047 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1048 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1049 assert(info->pTessellationState);
1050 break;
1051 default:
1052 break;
1053 }
1054 }
1055 }
1056
1057 VkResult
1058 anv_pipeline_init(struct anv_pipeline *pipeline,
1059 struct anv_device *device,
1060 struct anv_pipeline_cache *cache,
1061 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1062 const struct anv_graphics_pipeline_create_info *extra,
1063 const VkAllocationCallbacks *alloc)
1064 {
1065 VkResult result;
1066
1067 anv_validate {
1068 anv_pipeline_validate_create_info(pCreateInfo);
1069 }
1070
1071 if (alloc == NULL)
1072 alloc = &device->alloc;
1073
1074 pipeline->device = device;
1075 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1076
1077 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1078 if (result != VK_SUCCESS)
1079 return result;
1080
1081 pipeline->batch.alloc = alloc;
1082 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1083 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1084 pipeline->batch.relocs = &pipeline->batch_relocs;
1085
1086 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1087
1088 if (pCreateInfo->pTessellationState)
1089 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1090
1091 pipeline->use_repclear = extra && extra->use_repclear;
1092 pipeline->writes_point_size = false;
1093
1094 /* When we free the pipeline, we detect stages based on the NULL status
1095 * of various prog_data pointers. Make them NULL by default.
1096 */
1097 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1098 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1099 memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1100
1101 pipeline->vs_simd8 = NO_KERNEL;
1102 pipeline->vs_vec4 = NO_KERNEL;
1103 pipeline->gs_kernel = NO_KERNEL;
1104 pipeline->ps_ksp0 = NO_KERNEL;
1105
1106 pipeline->active_stages = 0;
1107 pipeline->total_scratch = 0;
1108
1109 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1110 ANV_FROM_HANDLE(anv_shader_module, module,
1111 pCreateInfo->pStages[i].module);
1112
1113 switch (pCreateInfo->pStages[i].stage) {
1114 case VK_SHADER_STAGE_VERTEX_BIT:
1115 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo, module,
1116 pCreateInfo->pStages[i].pName,
1117 pCreateInfo->pStages[i].pSpecializationInfo);
1118 break;
1119 case VK_SHADER_STAGE_GEOMETRY_BIT:
1120 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo, module,
1121 pCreateInfo->pStages[i].pName,
1122 pCreateInfo->pStages[i].pSpecializationInfo);
1123 break;
1124 case VK_SHADER_STAGE_FRAGMENT_BIT:
1125 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra, module,
1126 pCreateInfo->pStages[i].pName,
1127 pCreateInfo->pStages[i].pSpecializationInfo);
1128 break;
1129 default:
1130 anv_finishme("Unsupported shader stage");
1131 }
1132 }
1133
1134 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1135 /* Vertex is only optional if disable_vs is set */
1136 assert(extra->disable_vs);
1137 memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1138 }
1139
1140 gen7_compute_urb_partition(pipeline);
1141
1142 const VkPipelineVertexInputStateCreateInfo *vi_info =
1143 pCreateInfo->pVertexInputState;
1144
1145 uint64_t inputs_read;
1146 if (extra && extra->disable_vs) {
1147 /* If the VS is disabled, just assume the user knows what they're
1148 * doing and apply the layout blindly. This can only come from
1149 * meta, so this *should* be safe.
1150 */
1151 inputs_read = ~0ull;
1152 } else {
1153 inputs_read = pipeline->vs_prog_data.inputs_read;
1154 }
1155
1156 pipeline->vb_used = 0;
1157 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1158 const VkVertexInputAttributeDescription *desc =
1159 &vi_info->pVertexAttributeDescriptions[i];
1160
1161 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1162 pipeline->vb_used |= 1 << desc->binding;
1163 }
1164
1165 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1166 const VkVertexInputBindingDescription *desc =
1167 &vi_info->pVertexBindingDescriptions[i];
1168
1169 pipeline->binding_stride[desc->binding] = desc->stride;
1170
1171 /* Step rate is programmed per vertex element (attribute), not
1172 * binding. Set up a map of which bindings step per instance, for
1173 * reference by vertex element setup. */
1174 switch (desc->inputRate) {
1175 default:
1176 case VK_VERTEX_INPUT_RATE_VERTEX:
1177 pipeline->instancing_enable[desc->binding] = false;
1178 break;
1179 case VK_VERTEX_INPUT_RATE_INSTANCE:
1180 pipeline->instancing_enable[desc->binding] = true;
1181 break;
1182 }
1183 }
1184
1185 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1186 pCreateInfo->pInputAssemblyState;
1187 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1188 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1189
1190 if (extra && extra->use_rectlist)
1191 pipeline->topology = _3DPRIM_RECTLIST;
1192
1193 while (anv_block_pool_size(&device->scratch_block_pool) <
1194 pipeline->total_scratch)
1195 anv_block_pool_alloc(&device->scratch_block_pool);
1196
1197 return VK_SUCCESS;
1198 }
1199
1200 VkResult
1201 anv_graphics_pipeline_create(
1202 VkDevice _device,
1203 VkPipelineCache _cache,
1204 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1205 const struct anv_graphics_pipeline_create_info *extra,
1206 const VkAllocationCallbacks *pAllocator,
1207 VkPipeline *pPipeline)
1208 {
1209 ANV_FROM_HANDLE(anv_device, device, _device);
1210 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1211
1212 if (cache == NULL)
1213 cache = &device->default_pipeline_cache;
1214
1215 switch (device->info.gen) {
1216 case 7:
1217 if (device->info.is_haswell)
1218 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1219 else
1220 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1221 case 8:
1222 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1223 case 9:
1224 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1225 default:
1226 unreachable("unsupported gen\n");
1227 }
1228 }
1229
1230 VkResult anv_CreateGraphicsPipelines(
1231 VkDevice _device,
1232 VkPipelineCache pipelineCache,
1233 uint32_t count,
1234 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1235 const VkAllocationCallbacks* pAllocator,
1236 VkPipeline* pPipelines)
1237 {
1238 VkResult result = VK_SUCCESS;
1239
1240 unsigned i = 0;
1241 for (; i < count; i++) {
1242 result = anv_graphics_pipeline_create(_device,
1243 pipelineCache,
1244 &pCreateInfos[i],
1245 NULL, pAllocator, &pPipelines[i]);
1246 if (result != VK_SUCCESS) {
1247 for (unsigned j = 0; j < i; j++) {
1248 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1249 }
1250
1251 return result;
1252 }
1253 }
1254
1255 return VK_SUCCESS;
1256 }
1257
1258 static VkResult anv_compute_pipeline_create(
1259 VkDevice _device,
1260 VkPipelineCache _cache,
1261 const VkComputePipelineCreateInfo* pCreateInfo,
1262 const VkAllocationCallbacks* pAllocator,
1263 VkPipeline* pPipeline)
1264 {
1265 ANV_FROM_HANDLE(anv_device, device, _device);
1266 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1267
1268 if (cache == NULL)
1269 cache = &device->default_pipeline_cache;
1270
1271 switch (device->info.gen) {
1272 case 7:
1273 if (device->info.is_haswell)
1274 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1275 else
1276 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1277 case 8:
1278 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1279 case 9:
1280 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1281 default:
1282 unreachable("unsupported gen\n");
1283 }
1284 }
1285
1286 VkResult anv_CreateComputePipelines(
1287 VkDevice _device,
1288 VkPipelineCache pipelineCache,
1289 uint32_t count,
1290 const VkComputePipelineCreateInfo* pCreateInfos,
1291 const VkAllocationCallbacks* pAllocator,
1292 VkPipeline* pPipelines)
1293 {
1294 VkResult result = VK_SUCCESS;
1295
1296 unsigned i = 0;
1297 for (; i < count; i++) {
1298 result = anv_compute_pipeline_create(_device, pipelineCache,
1299 &pCreateInfos[i],
1300 pAllocator, &pPipelines[i]);
1301 if (result != VK_SUCCESS) {
1302 for (unsigned j = 0; j < i; j++) {
1303 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1304 }
1305
1306 return result;
1307 }
1308 }
1309
1310 return VK_SUCCESS;
1311 }