2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "common/gen_l3_config.h"
32 #include "anv_private.h"
33 #include "compiler/brw_nir.h"
35 #include "spirv/nir_spirv.h"
37 /* Needed for SWIZZLE macros */
38 #include "program/prog_instruction.h"
42 VkResult
anv_CreateShaderModule(
44 const VkShaderModuleCreateInfo
* pCreateInfo
,
45 const VkAllocationCallbacks
* pAllocator
,
46 VkShaderModule
* pShaderModule
)
48 ANV_FROM_HANDLE(anv_device
, device
, _device
);
49 struct anv_shader_module
*module
;
51 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
52 assert(pCreateInfo
->flags
== 0);
54 module
= vk_alloc2(&device
->alloc
, pAllocator
,
55 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
56 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
58 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
81 vk_free2(&device
->alloc
, pAllocator
, module
);
84 #define SPIR_V_MAGIC_NUMBER 0x07230203
86 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
87 * we can't do that yet because we don't have the ability to copy nir.
90 anv_shader_compile_to_nir(struct anv_device
*device
,
91 struct anv_shader_module
*module
,
92 const char *entrypoint_name
,
93 gl_shader_stage stage
,
94 const VkSpecializationInfo
*spec_info
)
96 const struct brw_compiler
*compiler
=
97 device
->instance
->physicalDevice
.compiler
;
98 const nir_shader_compiler_options
*nir_options
=
99 compiler
->glsl_compiler_options
[stage
].NirOptions
;
101 uint32_t *spirv
= (uint32_t *) module
->data
;
102 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
103 assert(module
->size
% 4 == 0);
105 uint32_t num_spec_entries
= 0;
106 struct nir_spirv_specialization
*spec_entries
= NULL
;
107 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
108 num_spec_entries
= spec_info
->mapEntryCount
;
109 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
110 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
111 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
112 const void *data
= spec_info
->pData
+ entry
.offset
;
113 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
115 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
116 if (spec_info
->dataSize
== 8)
117 spec_entries
[i
].data64
= *(const uint64_t *)data
;
119 spec_entries
[i
].data32
= *(const uint32_t *)data
;
123 const struct nir_spirv_supported_extensions supported_ext
= {
124 .float64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
125 .int64
= device
->instance
->physicalDevice
.info
.gen
>= 8,
126 .tessellation
= true,
127 .draw_parameters
= true,
128 .image_write_without_format
= true,
131 nir_function
*entry_point
=
132 spirv_to_nir(spirv
, module
->size
/ 4,
133 spec_entries
, num_spec_entries
,
134 stage
, entrypoint_name
, &supported_ext
, nir_options
);
135 nir_shader
*nir
= entry_point
->shader
;
136 assert(nir
->stage
== stage
);
137 nir_validate_shader(nir
);
141 /* We have to lower away local constant initializers right before we
142 * inline functions. That way they get properly initialized at the top
143 * of the function and not at the top of its caller.
145 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
146 NIR_PASS_V(nir
, nir_lower_returns
);
147 NIR_PASS_V(nir
, nir_inline_functions
);
149 /* Pick off the single entrypoint that we want */
150 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
151 if (func
!= entry_point
)
152 exec_node_remove(&func
->node
);
154 assert(exec_list_length(&nir
->functions
) == 1);
155 entry_point
->name
= ralloc_strdup(entry_point
, "main");
157 NIR_PASS_V(nir
, nir_remove_dead_variables
,
158 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
160 if (stage
== MESA_SHADER_FRAGMENT
)
161 NIR_PASS_V(nir
, nir_lower_wpos_center
);
163 /* Now that we've deleted all but the main function, we can go ahead and
164 * lower the rest of the constant initializers.
166 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
167 NIR_PASS_V(nir
, nir_propagate_invariant
);
168 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
169 entry_point
->impl
, true, false);
170 NIR_PASS_V(nir
, nir_lower_system_values
);
172 /* Vulkan uses the separate-shader linking model */
173 nir
->info
->separate_shader
= true;
175 nir
= brw_preprocess_nir(compiler
, nir
);
177 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
179 if (stage
== MESA_SHADER_FRAGMENT
)
180 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
182 nir_shader_gather_info(nir
, entry_point
->impl
);
187 void anv_DestroyPipeline(
189 VkPipeline _pipeline
,
190 const VkAllocationCallbacks
* pAllocator
)
192 ANV_FROM_HANDLE(anv_device
, device
, _device
);
193 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
198 anv_reloc_list_finish(&pipeline
->batch_relocs
,
199 pAllocator
? pAllocator
: &device
->alloc
);
200 if (pipeline
->blend_state
.map
)
201 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
203 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
204 if (pipeline
->shaders
[s
])
205 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
208 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
211 static const uint32_t vk_to_gen_primitive_type
[] = {
212 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
214 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
217 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
219 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
221 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
225 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
226 struct brw_sampler_prog_key_data
*key
)
228 /* Almost all multisampled textures are compressed. The only time when we
229 * don't compress a multisampled texture is for 16x MSAA with a surface
230 * width greater than 8k which is a bit of an edge case. Since the sampler
231 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
232 * to tell the compiler to always assume compression.
234 key
->compressed_multisample_layout_mask
= ~0;
236 /* SkyLake added support for 16x MSAA. With this came a new message for
237 * reading from a 16x MSAA surface with compression. The new message was
238 * needed because now the MCS data is 64 bits instead of 32 or lower as is
239 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
240 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
241 * so we can just use it unconditionally. This may not be quite as
242 * efficient but it saves us from recompiling.
244 if (devinfo
->gen
>= 9)
247 /* XXX: Handle texture swizzle on HSW- */
248 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
249 /* Assume color sampler, no swizzling. (Works for BDW+) */
250 key
->swizzles
[i
] = SWIZZLE_XYZW
;
255 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
256 struct brw_vs_prog_key
*key
)
258 memset(key
, 0, sizeof(*key
));
260 populate_sampler_prog_key(devinfo
, &key
->tex
);
262 /* XXX: Handle vertex input work-arounds */
264 /* XXX: Handle sampler_prog_key */
268 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
269 struct brw_gs_prog_key
*key
)
271 memset(key
, 0, sizeof(*key
));
273 populate_sampler_prog_key(devinfo
, &key
->tex
);
277 populate_wm_prog_key(const struct anv_pipeline
*pipeline
,
278 const VkGraphicsPipelineCreateInfo
*info
,
279 struct brw_wm_prog_key
*key
)
281 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
282 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
284 memset(key
, 0, sizeof(*key
));
286 populate_sampler_prog_key(devinfo
, &key
->tex
);
288 /* TODO: we could set this to 0 based on the information in nir_shader, but
289 * this function is called before spirv_to_nir. */
290 const struct brw_vue_map
*vue_map
=
291 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
292 key
->input_slots_valid
= vue_map
->slots_valid
;
294 /* Vulkan doesn't specify a default */
295 key
->high_quality_derivatives
= false;
297 /* XXX Vulkan doesn't appear to specify */
298 key
->clamp_fragment_color
= false;
300 key
->nr_color_regions
=
301 render_pass
->subpasses
[info
->subpass
].color_count
;
303 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
304 info
->pMultisampleState
&&
305 info
->pMultisampleState
->alphaToCoverageEnable
;
307 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
308 /* We should probably pull this out of the shader, but it's fairly
309 * harmless to compute it and then let dead-code take care of it.
311 key
->persample_interp
=
312 (info
->pMultisampleState
->minSampleShading
*
313 info
->pMultisampleState
->rasterizationSamples
) > 1;
314 key
->multisample_fbo
= true;
319 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
320 struct brw_cs_prog_key
*key
)
322 memset(key
, 0, sizeof(*key
));
324 populate_sampler_prog_key(devinfo
, &key
->tex
);
328 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
329 struct anv_shader_module
*module
,
330 const char *entrypoint
,
331 gl_shader_stage stage
,
332 const VkSpecializationInfo
*spec_info
,
333 struct brw_stage_prog_data
*prog_data
,
334 struct anv_pipeline_bind_map
*map
)
336 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
337 module
, entrypoint
, stage
,
342 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
344 /* Figure out the number of parameters */
345 prog_data
->nr_params
= 0;
347 if (nir
->num_uniforms
> 0) {
348 /* If the shader uses any push constants at all, we'll just give
349 * them the maximum possible number
351 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
352 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
355 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
356 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
* 2;
358 if (nir
->info
->num_images
> 0) {
359 prog_data
->nr_params
+= nir
->info
->num_images
* BRW_IMAGE_PARAM_SIZE
;
360 pipeline
->needs_data_cache
= true;
363 if (stage
== MESA_SHADER_COMPUTE
)
364 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
365 prog_data
->nr_params
++; /* The CS Thread ID uniform */
367 if (nir
->info
->num_ssbos
> 0)
368 pipeline
->needs_data_cache
= true;
370 if (prog_data
->nr_params
> 0) {
371 /* XXX: I think we're leaking this */
372 prog_data
->param
= (const union gl_constant_value
**)
373 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
375 /* We now set the param values to be offsets into a
376 * anv_push_constant_data structure. Since the compiler doesn't
377 * actually dereference any of the gl_constant_value pointers in the
378 * params array, it doesn't really matter what we put here.
380 struct anv_push_constants
*null_data
= NULL
;
381 if (nir
->num_uniforms
> 0) {
382 /* Fill out the push constants section of the param array */
383 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
384 prog_data
->param
[i
] = (const union gl_constant_value
*)
385 &null_data
->client_data
[i
* sizeof(float)];
389 /* Set up dynamic offsets */
390 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
392 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
393 if (pipeline
->layout
)
394 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
396 /* nir_lower_io will only handle the push constants; we need to set this
397 * to the full number of possible uniforms.
399 nir
->num_uniforms
= prog_data
->nr_params
* 4;
405 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
407 prog_data
->binding_table
.size_bytes
= 0;
408 prog_data
->binding_table
.texture_start
= bias
;
409 prog_data
->binding_table
.gather_texture_start
= bias
;
410 prog_data
->binding_table
.ubo_start
= bias
;
411 prog_data
->binding_table
.ssbo_start
= bias
;
412 prog_data
->binding_table
.image_start
= bias
;
415 static struct anv_shader_bin
*
416 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
417 struct anv_pipeline_cache
*cache
,
418 const void *key_data
, uint32_t key_size
,
419 const void *kernel_data
, uint32_t kernel_size
,
420 const struct brw_stage_prog_data
*prog_data
,
421 uint32_t prog_data_size
,
422 const struct anv_pipeline_bind_map
*bind_map
)
425 return anv_pipeline_cache_upload_kernel(cache
, key_data
, key_size
,
426 kernel_data
, kernel_size
,
427 prog_data
, prog_data_size
,
430 return anv_shader_bin_create(pipeline
->device
, key_data
, key_size
,
431 kernel_data
, kernel_size
,
432 prog_data
, prog_data_size
,
433 prog_data
->param
, bind_map
);
439 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
440 gl_shader_stage stage
,
441 struct anv_shader_bin
*shader
)
443 pipeline
->shaders
[stage
] = shader
;
444 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
448 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
449 struct anv_pipeline_cache
*cache
,
450 const VkGraphicsPipelineCreateInfo
*info
,
451 struct anv_shader_module
*module
,
452 const char *entrypoint
,
453 const VkSpecializationInfo
*spec_info
)
455 const struct brw_compiler
*compiler
=
456 pipeline
->device
->instance
->physicalDevice
.compiler
;
457 struct anv_pipeline_bind_map map
;
458 struct brw_vs_prog_key key
;
459 struct anv_shader_bin
*bin
= NULL
;
460 unsigned char sha1
[20];
462 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
465 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
466 pipeline
->layout
, spec_info
);
467 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
471 struct brw_vs_prog_data prog_data
= { 0, };
472 struct anv_pipeline_binding surface_to_descriptor
[256];
473 struct anv_pipeline_binding sampler_to_descriptor
[256];
475 map
= (struct anv_pipeline_bind_map
) {
476 .surface_to_descriptor
= surface_to_descriptor
,
477 .sampler_to_descriptor
= sampler_to_descriptor
480 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
481 MESA_SHADER_VERTEX
, spec_info
,
482 &prog_data
.base
.base
, &map
);
484 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
486 anv_fill_binding_table(&prog_data
.base
.base
, 0);
488 void *mem_ctx
= ralloc_context(NULL
);
490 ralloc_steal(mem_ctx
, nir
);
492 prog_data
.inputs_read
= nir
->info
->inputs_read
;
493 prog_data
.double_inputs_read
= nir
->info
->double_inputs_read
;
495 brw_compute_vue_map(&pipeline
->device
->info
,
496 &prog_data
.base
.vue_map
,
497 nir
->info
->outputs_written
,
498 nir
->info
->separate_shader
);
501 const unsigned *shader_code
=
502 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
503 NULL
, false, -1, &code_size
, NULL
);
504 if (shader_code
== NULL
) {
505 ralloc_free(mem_ctx
);
506 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
509 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
510 shader_code
, code_size
,
511 &prog_data
.base
.base
, sizeof(prog_data
),
514 ralloc_free(mem_ctx
);
515 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
518 ralloc_free(mem_ctx
);
521 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
, bin
);
527 merge_tess_info(struct shader_info
*tes_info
,
528 const struct shader_info
*tcs_info
)
530 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
532 * "PointMode. Controls generation of points rather than triangles
533 * or lines. This functionality defaults to disabled, and is
534 * enabled if either shader stage includes the execution mode.
536 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
537 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
538 * and OutputVertices, it says:
540 * "One mode must be set in at least one of the tessellation
543 * So, the fields can be set in either the TCS or TES, but they must
544 * agree if set in both. Our backend looks at TES, so bitwise-or in
545 * the values from the TCS.
547 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
548 tes_info
->tess
.tcs_vertices_out
== 0 ||
549 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
550 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
552 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
553 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
554 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
555 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
557 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
558 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
562 anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline
,
563 struct anv_pipeline_cache
*cache
,
564 const VkGraphicsPipelineCreateInfo
*info
,
565 struct anv_shader_module
*tcs_module
,
566 const char *tcs_entrypoint
,
567 const VkSpecializationInfo
*tcs_spec_info
,
568 struct anv_shader_module
*tes_module
,
569 const char *tes_entrypoint
,
570 const VkSpecializationInfo
*tes_spec_info
)
572 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
573 const struct brw_compiler
*compiler
=
574 pipeline
->device
->instance
->physicalDevice
.compiler
;
575 struct anv_pipeline_bind_map tcs_map
;
576 struct anv_pipeline_bind_map tes_map
;
577 struct brw_tcs_prog_key tcs_key
= { 0, };
578 struct brw_tes_prog_key tes_key
= { 0, };
579 struct anv_shader_bin
*tcs_bin
= NULL
;
580 struct anv_shader_bin
*tes_bin
= NULL
;
581 unsigned char tcs_sha1
[40];
582 unsigned char tes_sha1
[40];
584 populate_sampler_prog_key(&pipeline
->device
->info
, &tcs_key
.tex
);
585 populate_sampler_prog_key(&pipeline
->device
->info
, &tes_key
.tex
);
586 tcs_key
.input_vertices
= info
->pTessellationState
->patchControlPoints
;
589 anv_hash_shader(tcs_sha1
, &tcs_key
, sizeof(tcs_key
), tcs_module
,
590 tcs_entrypoint
, pipeline
->layout
, tcs_spec_info
);
591 anv_hash_shader(tes_sha1
, &tes_key
, sizeof(tes_key
), tes_module
,
592 tes_entrypoint
, pipeline
->layout
, tes_spec_info
);
593 memcpy(&tcs_sha1
[20], tes_sha1
, 20);
594 memcpy(&tes_sha1
[20], tcs_sha1
, 20);
595 tcs_bin
= anv_pipeline_cache_search(cache
, tcs_sha1
, sizeof(tcs_sha1
));
596 tes_bin
= anv_pipeline_cache_search(cache
, tes_sha1
, sizeof(tes_sha1
));
599 if (tcs_bin
== NULL
|| tes_bin
== NULL
) {
600 struct brw_tcs_prog_data tcs_prog_data
= { 0, };
601 struct brw_tes_prog_data tes_prog_data
= { 0, };
602 struct anv_pipeline_binding tcs_surface_to_descriptor
[256];
603 struct anv_pipeline_binding tcs_sampler_to_descriptor
[256];
604 struct anv_pipeline_binding tes_surface_to_descriptor
[256];
605 struct anv_pipeline_binding tes_sampler_to_descriptor
[256];
607 tcs_map
= (struct anv_pipeline_bind_map
) {
608 .surface_to_descriptor
= tcs_surface_to_descriptor
,
609 .sampler_to_descriptor
= tcs_sampler_to_descriptor
611 tes_map
= (struct anv_pipeline_bind_map
) {
612 .surface_to_descriptor
= tes_surface_to_descriptor
,
613 .sampler_to_descriptor
= tes_sampler_to_descriptor
616 nir_shader
*tcs_nir
=
617 anv_pipeline_compile(pipeline
, tcs_module
, tcs_entrypoint
,
618 MESA_SHADER_TESS_CTRL
, tcs_spec_info
,
619 &tcs_prog_data
.base
.base
, &tcs_map
);
620 nir_shader
*tes_nir
=
621 anv_pipeline_compile(pipeline
, tes_module
, tes_entrypoint
,
622 MESA_SHADER_TESS_EVAL
, tes_spec_info
,
623 &tes_prog_data
.base
.base
, &tes_map
);
624 if (tcs_nir
== NULL
|| tes_nir
== NULL
)
625 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
627 nir_lower_tes_patch_vertices(tes_nir
,
628 tcs_nir
->info
->tess
.tcs_vertices_out
);
630 /* Copy TCS info into the TES info */
631 merge_tess_info(tes_nir
->info
, tcs_nir
->info
);
633 anv_fill_binding_table(&tcs_prog_data
.base
.base
, 0);
634 anv_fill_binding_table(&tes_prog_data
.base
.base
, 0);
636 void *mem_ctx
= ralloc_context(NULL
);
638 ralloc_steal(mem_ctx
, tcs_nir
);
639 ralloc_steal(mem_ctx
, tes_nir
);
641 /* Whacking the key after cache lookup is a bit sketchy, but all of
642 * this comes from the SPIR-V, which is part of the hash used for the
643 * pipeline cache. So it should be safe.
645 tcs_key
.tes_primitive_mode
= tes_nir
->info
->tess
.primitive_mode
;
646 tcs_key
.outputs_written
= tcs_nir
->info
->outputs_written
;
647 tcs_key
.patch_outputs_written
= tcs_nir
->info
->patch_outputs_written
;
648 tcs_key
.quads_workaround
=
650 tes_nir
->info
->tess
.primitive_mode
== 7 /* GL_QUADS */ &&
651 tes_nir
->info
->tess
.spacing
== TESS_SPACING_EQUAL
;
653 tes_key
.inputs_read
= tcs_key
.outputs_written
;
654 tes_key
.patch_inputs_read
= tcs_key
.patch_outputs_written
;
657 const int shader_time_index
= -1;
658 const unsigned *shader_code
;
661 brw_compile_tcs(compiler
, NULL
, mem_ctx
, &tcs_key
, &tcs_prog_data
,
662 tcs_nir
, shader_time_index
, &code_size
, NULL
);
663 if (shader_code
== NULL
) {
664 ralloc_free(mem_ctx
);
665 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
668 tcs_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
669 tcs_sha1
, sizeof(tcs_sha1
),
670 shader_code
, code_size
,
671 &tcs_prog_data
.base
.base
,
672 sizeof(tcs_prog_data
),
675 ralloc_free(mem_ctx
);
676 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
680 brw_compile_tes(compiler
, NULL
, mem_ctx
, &tes_key
,
681 &tcs_prog_data
.base
.vue_map
, &tes_prog_data
, tes_nir
,
682 NULL
, shader_time_index
, &code_size
, NULL
);
683 if (shader_code
== NULL
) {
684 ralloc_free(mem_ctx
);
685 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
688 tes_bin
= anv_pipeline_upload_kernel(pipeline
, cache
,
689 tes_sha1
, sizeof(tes_sha1
),
690 shader_code
, code_size
,
691 &tes_prog_data
.base
.base
,
692 sizeof(tes_prog_data
),
695 ralloc_free(mem_ctx
);
696 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
699 ralloc_free(mem_ctx
);
702 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
703 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
709 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
710 struct anv_pipeline_cache
*cache
,
711 const VkGraphicsPipelineCreateInfo
*info
,
712 struct anv_shader_module
*module
,
713 const char *entrypoint
,
714 const VkSpecializationInfo
*spec_info
)
716 const struct brw_compiler
*compiler
=
717 pipeline
->device
->instance
->physicalDevice
.compiler
;
718 struct anv_pipeline_bind_map map
;
719 struct brw_gs_prog_key key
;
720 struct anv_shader_bin
*bin
= NULL
;
721 unsigned char sha1
[20];
723 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
726 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
727 pipeline
->layout
, spec_info
);
728 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
732 struct brw_gs_prog_data prog_data
= { 0, };
733 struct anv_pipeline_binding surface_to_descriptor
[256];
734 struct anv_pipeline_binding sampler_to_descriptor
[256];
736 map
= (struct anv_pipeline_bind_map
) {
737 .surface_to_descriptor
= surface_to_descriptor
,
738 .sampler_to_descriptor
= sampler_to_descriptor
741 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
742 MESA_SHADER_GEOMETRY
, spec_info
,
743 &prog_data
.base
.base
, &map
);
745 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
747 anv_fill_binding_table(&prog_data
.base
.base
, 0);
749 void *mem_ctx
= ralloc_context(NULL
);
751 ralloc_steal(mem_ctx
, nir
);
753 brw_compute_vue_map(&pipeline
->device
->info
,
754 &prog_data
.base
.vue_map
,
755 nir
->info
->outputs_written
,
756 nir
->info
->separate_shader
);
759 const unsigned *shader_code
=
760 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
761 NULL
, -1, &code_size
, NULL
);
762 if (shader_code
== NULL
) {
763 ralloc_free(mem_ctx
);
764 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
768 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
769 shader_code
, code_size
,
770 &prog_data
.base
.base
, sizeof(prog_data
),
773 ralloc_free(mem_ctx
);
774 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
777 ralloc_free(mem_ctx
);
780 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
, bin
);
786 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
787 struct anv_pipeline_cache
*cache
,
788 const VkGraphicsPipelineCreateInfo
*info
,
789 struct anv_shader_module
*module
,
790 const char *entrypoint
,
791 const VkSpecializationInfo
*spec_info
)
793 const struct brw_compiler
*compiler
=
794 pipeline
->device
->instance
->physicalDevice
.compiler
;
795 struct anv_pipeline_bind_map map
;
796 struct brw_wm_prog_key key
;
797 struct anv_shader_bin
*bin
= NULL
;
798 unsigned char sha1
[20];
800 populate_wm_prog_key(pipeline
, info
, &key
);
803 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
804 pipeline
->layout
, spec_info
);
805 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
809 struct brw_wm_prog_data prog_data
= { 0, };
810 struct anv_pipeline_binding surface_to_descriptor
[256];
811 struct anv_pipeline_binding sampler_to_descriptor
[256];
813 map
= (struct anv_pipeline_bind_map
) {
814 .surface_to_descriptor
= surface_to_descriptor
+ 8,
815 .sampler_to_descriptor
= sampler_to_descriptor
818 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
819 MESA_SHADER_FRAGMENT
, spec_info
,
820 &prog_data
.base
, &map
);
822 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
824 unsigned num_rts
= 0;
825 struct anv_pipeline_binding rt_bindings
[8];
826 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
827 nir_foreach_variable_safe(var
, &nir
->outputs
) {
828 if (var
->data
.location
< FRAG_RESULT_DATA0
)
831 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
832 if (rt
>= key
.nr_color_regions
) {
833 /* Out-of-bounds, throw it away */
834 var
->data
.mode
= nir_var_local
;
835 exec_node_remove(&var
->node
);
836 exec_list_push_tail(&impl
->locals
, &var
->node
);
840 /* Give it a new, compacted, location */
841 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
844 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
845 assert(num_rts
+ array_len
<= 8);
847 for (unsigned i
= 0; i
< array_len
; i
++) {
848 rt_bindings
[num_rts
+ i
] = (struct anv_pipeline_binding
) {
849 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
855 num_rts
+= array_len
;
859 /* If we have no render targets, we need a null render target */
860 rt_bindings
[0] = (struct anv_pipeline_binding
) {
861 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
868 assert(num_rts
<= 8);
869 map
.surface_to_descriptor
-= num_rts
;
870 map
.surface_count
+= num_rts
;
871 assert(map
.surface_count
<= 256);
872 memcpy(map
.surface_to_descriptor
, rt_bindings
,
873 num_rts
* sizeof(*rt_bindings
));
875 anv_fill_binding_table(&prog_data
.base
, num_rts
);
877 void *mem_ctx
= ralloc_context(NULL
);
879 ralloc_steal(mem_ctx
, nir
);
882 const unsigned *shader_code
=
883 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
884 NULL
, -1, -1, true, false, NULL
, &code_size
, NULL
);
885 if (shader_code
== NULL
) {
886 ralloc_free(mem_ctx
);
887 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
890 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
891 shader_code
, code_size
,
892 &prog_data
.base
, sizeof(prog_data
),
895 ralloc_free(mem_ctx
);
896 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
899 ralloc_free(mem_ctx
);
902 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
, bin
);
908 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
909 struct anv_pipeline_cache
*cache
,
910 const VkComputePipelineCreateInfo
*info
,
911 struct anv_shader_module
*module
,
912 const char *entrypoint
,
913 const VkSpecializationInfo
*spec_info
)
915 const struct brw_compiler
*compiler
=
916 pipeline
->device
->instance
->physicalDevice
.compiler
;
917 struct anv_pipeline_bind_map map
;
918 struct brw_cs_prog_key key
;
919 struct anv_shader_bin
*bin
= NULL
;
920 unsigned char sha1
[20];
922 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
925 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
,
926 pipeline
->layout
, spec_info
);
927 bin
= anv_pipeline_cache_search(cache
, sha1
, 20);
931 struct brw_cs_prog_data prog_data
= { 0, };
932 struct anv_pipeline_binding surface_to_descriptor
[256];
933 struct anv_pipeline_binding sampler_to_descriptor
[256];
935 map
= (struct anv_pipeline_bind_map
) {
936 .surface_to_descriptor
= surface_to_descriptor
,
937 .sampler_to_descriptor
= sampler_to_descriptor
940 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
941 MESA_SHADER_COMPUTE
, spec_info
,
942 &prog_data
.base
, &map
);
944 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
946 anv_fill_binding_table(&prog_data
.base
, 1);
948 void *mem_ctx
= ralloc_context(NULL
);
950 ralloc_steal(mem_ctx
, nir
);
953 const unsigned *shader_code
=
954 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
955 -1, &code_size
, NULL
);
956 if (shader_code
== NULL
) {
957 ralloc_free(mem_ctx
);
958 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
961 bin
= anv_pipeline_upload_kernel(pipeline
, cache
, sha1
, 20,
962 shader_code
, code_size
,
963 &prog_data
.base
, sizeof(prog_data
),
966 ralloc_free(mem_ctx
);
967 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
970 ralloc_free(mem_ctx
);
973 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
, bin
);
979 * Copy pipeline state not marked as dynamic.
980 * Dynamic state is pipeline state which hasn't been provided at pipeline
981 * creation time, but is dynamically provided afterwards using various
982 * vkCmdSet* functions.
984 * The set of state considered "non_dynamic" is determined by the pieces of
985 * state that have their corresponding VkDynamicState enums omitted from
986 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
988 * @param[out] pipeline Destination non_dynamic state.
989 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
992 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
993 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
995 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
996 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
997 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
999 pipeline
->dynamic_state
= default_dynamic_state
;
1001 if (pCreateInfo
->pDynamicState
) {
1002 /* Remove all of the states that are marked as dynamic */
1003 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1004 for (uint32_t s
= 0; s
< count
; s
++)
1005 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1008 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1010 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1012 * pViewportState is [...] NULL if the pipeline
1013 * has rasterization disabled.
1015 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1016 assert(pCreateInfo
->pViewportState
);
1018 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1019 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1020 typed_memcpy(dynamic
->viewport
.viewports
,
1021 pCreateInfo
->pViewportState
->pViewports
,
1022 pCreateInfo
->pViewportState
->viewportCount
);
1025 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1026 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1027 typed_memcpy(dynamic
->scissor
.scissors
,
1028 pCreateInfo
->pViewportState
->pScissors
,
1029 pCreateInfo
->pViewportState
->scissorCount
);
1033 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1034 assert(pCreateInfo
->pRasterizationState
);
1035 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1038 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1039 assert(pCreateInfo
->pRasterizationState
);
1040 dynamic
->depth_bias
.bias
=
1041 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1042 dynamic
->depth_bias
.clamp
=
1043 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1044 dynamic
->depth_bias
.slope
=
1045 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1048 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1050 * pColorBlendState is [...] NULL if the pipeline has rasterization
1051 * disabled or if the subpass of the render pass the pipeline is
1052 * created against does not use any color attachments.
1054 bool uses_color_att
= false;
1055 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1056 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1057 uses_color_att
= true;
1062 if (uses_color_att
&&
1063 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1064 assert(pCreateInfo
->pColorBlendState
);
1066 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1067 typed_memcpy(dynamic
->blend_constants
,
1068 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1071 /* If there is no depthstencil attachment, then don't read
1072 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1073 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1074 * no need to override the depthstencil defaults in
1075 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1077 * Section 9.2 of the Vulkan 1.0.15 spec says:
1079 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1080 * disabled or if the subpass of the render pass the pipeline is created
1081 * against does not use a depth/stencil attachment.
1083 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1084 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1085 assert(pCreateInfo
->pDepthStencilState
);
1087 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1088 dynamic
->depth_bounds
.min
=
1089 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1090 dynamic
->depth_bounds
.max
=
1091 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1094 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1095 dynamic
->stencil_compare_mask
.front
=
1096 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1097 dynamic
->stencil_compare_mask
.back
=
1098 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1101 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1102 dynamic
->stencil_write_mask
.front
=
1103 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1104 dynamic
->stencil_write_mask
.back
=
1105 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1108 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1109 dynamic
->stencil_reference
.front
=
1110 pCreateInfo
->pDepthStencilState
->front
.reference
;
1111 dynamic
->stencil_reference
.back
=
1112 pCreateInfo
->pDepthStencilState
->back
.reference
;
1116 pipeline
->dynamic_state_mask
= states
;
1120 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1123 struct anv_render_pass
*renderpass
= NULL
;
1124 struct anv_subpass
*subpass
= NULL
;
1126 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1127 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1129 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1131 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1134 assert(info
->subpass
< renderpass
->subpass_count
);
1135 subpass
= &renderpass
->subpasses
[info
->subpass
];
1137 assert(info
->stageCount
>= 1);
1138 assert(info
->pVertexInputState
);
1139 assert(info
->pInputAssemblyState
);
1140 assert(info
->pRasterizationState
);
1141 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1142 assert(info
->pViewportState
);
1143 assert(info
->pMultisampleState
);
1145 if (subpass
&& subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
)
1146 assert(info
->pDepthStencilState
);
1148 if (subpass
&& subpass
->color_count
> 0)
1149 assert(info
->pColorBlendState
);
1152 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1153 switch (info
->pStages
[i
].stage
) {
1154 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1155 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1156 assert(info
->pTessellationState
);
1166 * Calculate the desired L3 partitioning based on the current state of the
1167 * pipeline. For now this simply returns the conservative defaults calculated
1168 * by get_default_l3_weights(), but we could probably do better by gathering
1169 * more statistics from the pipeline state (e.g. guess of expected URB usage
1170 * and bound surfaces), or by using feed-back from performance counters.
1173 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1175 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1177 const struct gen_l3_weights w
=
1178 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1180 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1181 pipeline
->urb
.total_size
=
1182 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1186 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1187 struct anv_device
*device
,
1188 struct anv_pipeline_cache
*cache
,
1189 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1190 const VkAllocationCallbacks
*alloc
)
1194 anv_pipeline_validate_create_info(pCreateInfo
);
1197 alloc
= &device
->alloc
;
1199 pipeline
->device
= device
;
1200 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1202 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1203 if (result
!= VK_SUCCESS
)
1206 pipeline
->batch
.alloc
= alloc
;
1207 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1208 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1209 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1211 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1212 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1213 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1215 pipeline
->needs_data_cache
= false;
1217 /* When we free the pipeline, we detect stages based on the NULL status
1218 * of various prog_data pointers. Make them NULL by default.
1220 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1222 pipeline
->active_stages
= 0;
1224 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1225 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1226 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1227 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1228 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1229 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1232 if (modules
[MESA_SHADER_VERTEX
]) {
1233 result
= anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1234 modules
[MESA_SHADER_VERTEX
],
1235 pStages
[MESA_SHADER_VERTEX
]->pName
,
1236 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1237 if (result
!= VK_SUCCESS
)
1241 if (modules
[MESA_SHADER_TESS_EVAL
]) {
1242 anv_pipeline_compile_tcs_tes(pipeline
, cache
, pCreateInfo
,
1243 modules
[MESA_SHADER_TESS_CTRL
],
1244 pStages
[MESA_SHADER_TESS_CTRL
]->pName
,
1245 pStages
[MESA_SHADER_TESS_CTRL
]->pSpecializationInfo
,
1246 modules
[MESA_SHADER_TESS_EVAL
],
1247 pStages
[MESA_SHADER_TESS_EVAL
]->pName
,
1248 pStages
[MESA_SHADER_TESS_EVAL
]->pSpecializationInfo
);
1251 if (modules
[MESA_SHADER_GEOMETRY
]) {
1252 result
= anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1253 modules
[MESA_SHADER_GEOMETRY
],
1254 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1255 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1256 if (result
!= VK_SUCCESS
)
1260 if (modules
[MESA_SHADER_FRAGMENT
]) {
1261 result
= anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
,
1262 modules
[MESA_SHADER_FRAGMENT
],
1263 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1264 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1265 if (result
!= VK_SUCCESS
)
1269 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1271 anv_pipeline_setup_l3_config(pipeline
, false);
1273 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1274 pCreateInfo
->pVertexInputState
;
1276 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1278 pipeline
->vb_used
= 0;
1279 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1280 const VkVertexInputAttributeDescription
*desc
=
1281 &vi_info
->pVertexAttributeDescriptions
[i
];
1283 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1284 pipeline
->vb_used
|= 1 << desc
->binding
;
1287 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1288 const VkVertexInputBindingDescription
*desc
=
1289 &vi_info
->pVertexBindingDescriptions
[i
];
1291 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1293 /* Step rate is programmed per vertex element (attribute), not
1294 * binding. Set up a map of which bindings step per instance, for
1295 * reference by vertex element setup. */
1296 switch (desc
->inputRate
) {
1298 case VK_VERTEX_INPUT_RATE_VERTEX
:
1299 pipeline
->instancing_enable
[desc
->binding
] = false;
1301 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1302 pipeline
->instancing_enable
[desc
->binding
] = true;
1307 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1308 pCreateInfo
->pInputAssemblyState
;
1309 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1310 pCreateInfo
->pTessellationState
;
1311 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1313 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1314 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1316 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1321 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1322 if (pipeline
->shaders
[s
])
1323 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
1326 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);