2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
99 * we can't do that yet because we don't have the ability to copy nir.
102 anv_shader_compile_to_nir(struct anv_device
*device
,
104 const struct anv_shader_module
*module
,
105 const char *entrypoint_name
,
106 gl_shader_stage stage
,
107 const VkSpecializationInfo
*spec_info
)
109 const struct anv_physical_device
*pdevice
=
110 &device
->instance
->physicalDevice
;
111 const struct brw_compiler
*compiler
= pdevice
->compiler
;
112 const nir_shader_compiler_options
*nir_options
=
113 compiler
->glsl_compiler_options
[stage
].NirOptions
;
115 uint32_t *spirv
= (uint32_t *) module
->data
;
116 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
117 assert(module
->size
% 4 == 0);
119 uint32_t num_spec_entries
= 0;
120 struct nir_spirv_specialization
*spec_entries
= NULL
;
121 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
122 num_spec_entries
= spec_info
->mapEntryCount
;
123 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
124 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
125 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
126 const void *data
= spec_info
->pData
+ entry
.offset
;
127 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
129 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
130 if (spec_info
->dataSize
== 8)
131 spec_entries
[i
].data64
= *(const uint64_t *)data
;
133 spec_entries
[i
].data32
= *(const uint32_t *)data
;
137 nir_address_format ssbo_addr_format
=
138 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
);
139 struct spirv_to_nir_options spirv_options
= {
140 .lower_workgroup_access_to_offsets
= true,
142 .derivative_group
= true,
143 .descriptor_array_dynamic_indexing
= true,
144 .descriptor_array_non_uniform_indexing
= true,
145 .descriptor_indexing
= true,
146 .device_group
= true,
147 .draw_parameters
= true,
148 .float16
= pdevice
->info
.gen
>= 8,
149 .float64
= pdevice
->info
.gen
>= 8,
150 .geometry_streams
= true,
151 .image_write_without_format
= true,
152 .int8
= pdevice
->info
.gen
>= 8,
153 .int16
= pdevice
->info
.gen
>= 8,
154 .int64
= pdevice
->info
.gen
>= 8,
155 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
158 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
159 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
160 .runtime_descriptor_array
= true,
161 .shader_viewport_index_layer
= true,
162 .stencil_export
= pdevice
->info
.gen
>= 9,
163 .storage_8bit
= pdevice
->info
.gen
>= 8,
164 .storage_16bit
= pdevice
->info
.gen
>= 8,
165 .subgroup_arithmetic
= true,
166 .subgroup_basic
= true,
167 .subgroup_ballot
= true,
168 .subgroup_quad
= true,
169 .subgroup_shuffle
= true,
170 .subgroup_vote
= true,
171 .tessellation
= true,
172 .transform_feedback
= pdevice
->info
.gen
>= 8,
173 .variable_pointers
= true,
175 .ubo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT
, 2),
176 .ssbo_ptr_type
= nir_address_format_to_glsl_type(ssbo_addr_format
),
177 .phys_ssbo_ptr_type
= glsl_vector_type(GLSL_TYPE_UINT64
, 1),
178 .push_const_ptr_type
= glsl_uint_type(),
179 .shared_ptr_type
= glsl_uint_type(),
183 nir_function
*entry_point
=
184 spirv_to_nir(spirv
, module
->size
/ 4,
185 spec_entries
, num_spec_entries
,
186 stage
, entrypoint_name
, &spirv_options
, nir_options
);
187 nir_shader
*nir
= entry_point
->shader
;
188 assert(nir
->info
.stage
== stage
);
189 nir_validate_shader(nir
, "after spirv_to_nir");
190 ralloc_steal(mem_ctx
, nir
);
194 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
195 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
196 gl_shader_stage_name(stage
));
197 nir_print_shader(nir
, stderr
);
200 /* We have to lower away local constant initializers right before we
201 * inline functions. That way they get properly initialized at the top
202 * of the function and not at the top of its caller.
204 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
205 NIR_PASS_V(nir
, nir_lower_returns
);
206 NIR_PASS_V(nir
, nir_inline_functions
);
207 NIR_PASS_V(nir
, nir_opt_deref
);
209 /* Pick off the single entrypoint that we want */
210 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
211 if (func
!= entry_point
)
212 exec_node_remove(&func
->node
);
214 assert(exec_list_length(&nir
->functions
) == 1);
216 /* Now that we've deleted all but the main function, we can go ahead and
217 * lower the rest of the constant initializers. We do this here so that
218 * nir_remove_dead_variables and split_per_member_structs below see the
219 * corresponding stores.
221 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
223 /* Split member structs. We do this before lower_io_to_temporaries so that
224 * it doesn't lower system values to temporaries by accident.
226 NIR_PASS_V(nir
, nir_split_var_copies
);
227 NIR_PASS_V(nir
, nir_split_per_member_structs
);
229 NIR_PASS_V(nir
, nir_remove_dead_variables
,
230 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
232 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
233 nir_address_format_64bit_global
);
235 NIR_PASS_V(nir
, nir_propagate_invariant
);
236 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
237 entry_point
->impl
, true, false);
239 NIR_PASS_V(nir
, nir_lower_frexp
);
241 /* Vulkan uses the separate-shader linking model */
242 nir
->info
.separate_shader
= true;
244 nir
= brw_preprocess_nir(compiler
, nir
, NULL
);
249 void anv_DestroyPipeline(
251 VkPipeline _pipeline
,
252 const VkAllocationCallbacks
* pAllocator
)
254 ANV_FROM_HANDLE(anv_device
, device
, _device
);
255 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
260 anv_reloc_list_finish(&pipeline
->batch_relocs
,
261 pAllocator
? pAllocator
: &device
->alloc
);
262 if (pipeline
->blend_state
.map
)
263 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
265 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
266 if (pipeline
->shaders
[s
])
267 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
270 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
273 static const uint32_t vk_to_gen_primitive_type
[] = {
274 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
275 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
276 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
277 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
278 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
279 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
280 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
281 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
282 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
283 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
287 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
288 struct brw_sampler_prog_key_data
*key
)
290 /* Almost all multisampled textures are compressed. The only time when we
291 * don't compress a multisampled texture is for 16x MSAA with a surface
292 * width greater than 8k which is a bit of an edge case. Since the sampler
293 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
294 * to tell the compiler to always assume compression.
296 key
->compressed_multisample_layout_mask
= ~0;
298 /* SkyLake added support for 16x MSAA. With this came a new message for
299 * reading from a 16x MSAA surface with compression. The new message was
300 * needed because now the MCS data is 64 bits instead of 32 or lower as is
301 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
302 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
303 * so we can just use it unconditionally. This may not be quite as
304 * efficient but it saves us from recompiling.
306 if (devinfo
->gen
>= 9)
309 /* XXX: Handle texture swizzle on HSW- */
310 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
311 /* Assume color sampler, no swizzling. (Works for BDW+) */
312 key
->swizzles
[i
] = SWIZZLE_XYZW
;
317 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
318 struct brw_vs_prog_key
*key
)
320 memset(key
, 0, sizeof(*key
));
322 populate_sampler_prog_key(devinfo
, &key
->tex
);
324 /* XXX: Handle vertex input work-arounds */
326 /* XXX: Handle sampler_prog_key */
330 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
331 unsigned input_vertices
,
332 struct brw_tcs_prog_key
*key
)
334 memset(key
, 0, sizeof(*key
));
336 populate_sampler_prog_key(devinfo
, &key
->tex
);
338 key
->input_vertices
= input_vertices
;
342 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
343 struct brw_tes_prog_key
*key
)
345 memset(key
, 0, sizeof(*key
));
347 populate_sampler_prog_key(devinfo
, &key
->tex
);
351 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
352 struct brw_gs_prog_key
*key
)
354 memset(key
, 0, sizeof(*key
));
356 populate_sampler_prog_key(devinfo
, &key
->tex
);
360 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
361 const struct anv_subpass
*subpass
,
362 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
363 struct brw_wm_prog_key
*key
)
365 memset(key
, 0, sizeof(*key
));
367 populate_sampler_prog_key(devinfo
, &key
->tex
);
369 /* We set this to 0 here and set to the actual value before we call
372 key
->input_slots_valid
= 0;
374 /* Vulkan doesn't specify a default */
375 key
->high_quality_derivatives
= false;
377 /* XXX Vulkan doesn't appear to specify */
378 key
->clamp_fragment_color
= false;
380 assert(subpass
->color_count
<= MAX_RTS
);
381 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
382 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
383 key
->color_outputs_valid
|= (1 << i
);
386 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
388 /* To reduce possible shader recompilations we would need to know if
389 * there is a SampleMask output variable to compute if we should emit
390 * code to workaround the issue that hardware disables alpha to coverage
391 * when there is SampleMask output.
393 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
395 /* Vulkan doesn't support fixed-function alpha test */
396 key
->alpha_test_replicate_alpha
= false;
399 /* We should probably pull this out of the shader, but it's fairly
400 * harmless to compute it and then let dead-code take care of it.
402 if (ms_info
->rasterizationSamples
> 1) {
403 key
->persample_interp
=
404 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
405 key
->multisample_fbo
= true;
408 key
->frag_coord_adds_sample_pos
= ms_info
->sampleShadingEnable
;
413 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
414 struct brw_cs_prog_key
*key
)
416 memset(key
, 0, sizeof(*key
));
418 populate_sampler_prog_key(devinfo
, &key
->tex
);
421 struct anv_pipeline_stage
{
422 gl_shader_stage stage
;
424 const struct anv_shader_module
*module
;
425 const char *entrypoint
;
426 const VkSpecializationInfo
*spec_info
;
428 unsigned char shader_sha1
[20];
430 union brw_any_prog_key key
;
433 gl_shader_stage stage
;
434 unsigned char sha1
[20];
439 struct anv_pipeline_binding surface_to_descriptor
[256];
440 struct anv_pipeline_binding sampler_to_descriptor
[256];
441 struct anv_pipeline_bind_map bind_map
;
443 union brw_any_prog_data prog_data
;
445 VkPipelineCreationFeedbackEXT feedback
;
449 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
450 const char *entrypoint
,
451 gl_shader_stage stage
,
452 const VkSpecializationInfo
*spec_info
,
453 unsigned char *sha1_out
)
455 struct mesa_sha1 ctx
;
456 _mesa_sha1_init(&ctx
);
458 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
459 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
460 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
462 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
463 spec_info
->mapEntryCount
*
464 sizeof(*spec_info
->pMapEntries
));
465 _mesa_sha1_update(&ctx
, spec_info
->pData
,
466 spec_info
->dataSize
);
469 _mesa_sha1_final(&ctx
, sha1_out
);
473 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
474 struct anv_pipeline_layout
*layout
,
475 struct anv_pipeline_stage
*stages
,
476 unsigned char *sha1_out
)
478 struct mesa_sha1 ctx
;
479 _mesa_sha1_init(&ctx
);
481 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
482 sizeof(pipeline
->subpass
->view_mask
));
485 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
487 const bool rba
= pipeline
->device
->robust_buffer_access
;
488 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
490 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
491 if (stages
[s
].entrypoint
) {
492 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
493 sizeof(stages
[s
].shader_sha1
));
494 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
498 _mesa_sha1_final(&ctx
, sha1_out
);
502 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
503 struct anv_pipeline_layout
*layout
,
504 struct anv_pipeline_stage
*stage
,
505 unsigned char *sha1_out
)
507 struct mesa_sha1 ctx
;
508 _mesa_sha1_init(&ctx
);
511 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
513 const bool rba
= pipeline
->device
->robust_buffer_access
;
514 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
516 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
517 sizeof(stage
->shader_sha1
));
518 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
520 _mesa_sha1_final(&ctx
, sha1_out
);
524 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
525 struct anv_pipeline_cache
*cache
,
527 struct anv_pipeline_stage
*stage
)
529 const struct brw_compiler
*compiler
=
530 pipeline
->device
->instance
->physicalDevice
.compiler
;
531 const nir_shader_compiler_options
*nir_options
=
532 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
535 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
540 assert(nir
->info
.stage
== stage
->stage
);
544 nir
= anv_shader_compile_to_nir(pipeline
->device
,
551 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
559 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
561 struct anv_pipeline_stage
*stage
,
562 struct anv_pipeline_layout
*layout
)
564 const struct anv_physical_device
*pdevice
=
565 &pipeline
->device
->instance
->physicalDevice
;
566 const struct brw_compiler
*compiler
= pdevice
->compiler
;
568 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
569 nir_shader
*nir
= stage
->nir
;
571 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
572 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
573 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
576 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
578 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
580 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
581 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
583 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
584 prog_data
->total_shared
= nir
->num_shared
;
586 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
588 if (nir
->num_uniforms
> 0) {
589 assert(prog_data
->nr_params
== 0);
591 /* If the shader uses any push constants at all, we'll just give
592 * them the maximum possible number
594 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
595 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
596 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
597 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
599 /* We now set the param values to be offsets into a
600 * anv_push_constant_data structure. Since the compiler doesn't
601 * actually dereference any of the gl_constant_value pointers in the
602 * params array, it doesn't really matter what we put here.
604 struct anv_push_constants
*null_data
= NULL
;
605 /* Fill out the push constants section of the param array */
606 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
607 prog_data
->param
[i
] = ANV_PARAM_PUSH(
608 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
612 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
613 pipeline
->needs_data_cache
= true;
615 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
617 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
619 anv_nir_apply_pipeline_layout(pdevice
,
620 pipeline
->device
->robust_buffer_access
,
621 layout
, nir
, prog_data
,
624 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
625 nir_address_format_32bit_index_offset
);
626 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
627 anv_nir_ssbo_addr_format(pdevice
,
628 pipeline
->device
->robust_buffer_access
));
630 NIR_PASS_V(nir
, nir_opt_constant_folding
);
632 /* We don't support non-uniform UBOs and non-uniform SSBO access is
633 * handled naturally by falling back to A64 messages.
635 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
636 nir_lower_non_uniform_texture_access
|
637 nir_lower_non_uniform_image_access
);
640 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
641 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
643 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
649 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
650 struct anv_pipeline_stage
*vs_stage
,
651 struct anv_pipeline_stage
*next_stage
)
654 brw_nir_link_shaders(compiler
, &vs_stage
->nir
, &next_stage
->nir
);
657 static const unsigned *
658 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
660 struct anv_device
*device
,
661 struct anv_pipeline_stage
*vs_stage
)
663 brw_compute_vue_map(compiler
->devinfo
,
664 &vs_stage
->prog_data
.vs
.base
.vue_map
,
665 vs_stage
->nir
->info
.outputs_written
,
666 vs_stage
->nir
->info
.separate_shader
);
668 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
669 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
673 merge_tess_info(struct shader_info
*tes_info
,
674 const struct shader_info
*tcs_info
)
676 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
678 * "PointMode. Controls generation of points rather than triangles
679 * or lines. This functionality defaults to disabled, and is
680 * enabled if either shader stage includes the execution mode.
682 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
683 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
684 * and OutputVertices, it says:
686 * "One mode must be set in at least one of the tessellation
689 * So, the fields can be set in either the TCS or TES, but they must
690 * agree if set in both. Our backend looks at TES, so bitwise-or in
691 * the values from the TCS.
693 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
694 tes_info
->tess
.tcs_vertices_out
== 0 ||
695 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
696 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
698 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
699 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
700 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
701 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
703 assert(tcs_info
->tess
.primitive_mode
== 0 ||
704 tes_info
->tess
.primitive_mode
== 0 ||
705 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
706 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
707 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
708 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
712 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
713 struct anv_pipeline_stage
*tcs_stage
,
714 struct anv_pipeline_stage
*tes_stage
)
716 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
718 brw_nir_link_shaders(compiler
, &tcs_stage
->nir
, &tes_stage
->nir
);
720 nir_lower_patch_vertices(tes_stage
->nir
,
721 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
724 /* Copy TCS info into the TES info */
725 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
727 /* Whacking the key after cache lookup is a bit sketchy, but all of
728 * this comes from the SPIR-V, which is part of the hash used for the
729 * pipeline cache. So it should be safe.
731 tcs_stage
->key
.tcs
.tes_primitive_mode
=
732 tes_stage
->nir
->info
.tess
.primitive_mode
;
733 tcs_stage
->key
.tcs
.quads_workaround
=
734 compiler
->devinfo
->gen
< 9 &&
735 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
736 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
739 static const unsigned *
740 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
742 struct anv_device
*device
,
743 struct anv_pipeline_stage
*tcs_stage
,
744 struct anv_pipeline_stage
*prev_stage
)
746 tcs_stage
->key
.tcs
.outputs_written
=
747 tcs_stage
->nir
->info
.outputs_written
;
748 tcs_stage
->key
.tcs
.patch_outputs_written
=
749 tcs_stage
->nir
->info
.patch_outputs_written
;
751 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
752 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
757 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
758 struct anv_pipeline_stage
*tes_stage
,
759 struct anv_pipeline_stage
*next_stage
)
762 brw_nir_link_shaders(compiler
, &tes_stage
->nir
, &next_stage
->nir
);
765 static const unsigned *
766 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
768 struct anv_device
*device
,
769 struct anv_pipeline_stage
*tes_stage
,
770 struct anv_pipeline_stage
*tcs_stage
)
772 tes_stage
->key
.tes
.inputs_read
=
773 tcs_stage
->nir
->info
.outputs_written
;
774 tes_stage
->key
.tes
.patch_inputs_read
=
775 tcs_stage
->nir
->info
.patch_outputs_written
;
777 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
778 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
779 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
784 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
785 struct anv_pipeline_stage
*gs_stage
,
786 struct anv_pipeline_stage
*next_stage
)
789 brw_nir_link_shaders(compiler
, &gs_stage
->nir
, &next_stage
->nir
);
792 static const unsigned *
793 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
795 struct anv_device
*device
,
796 struct anv_pipeline_stage
*gs_stage
,
797 struct anv_pipeline_stage
*prev_stage
)
799 brw_compute_vue_map(compiler
->devinfo
,
800 &gs_stage
->prog_data
.gs
.base
.vue_map
,
801 gs_stage
->nir
->info
.outputs_written
,
802 gs_stage
->nir
->info
.separate_shader
);
804 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
805 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
810 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
811 struct anv_pipeline_stage
*stage
)
813 unsigned num_rts
= 0;
814 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
815 struct anv_pipeline_binding rt_bindings
[max_rt
];
816 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
817 int rt_to_bindings
[max_rt
];
818 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
819 bool rt_used
[max_rt
];
820 memset(rt_used
, 0, sizeof(rt_used
));
822 /* Flag used render targets */
823 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
824 if (var
->data
.location
< FRAG_RESULT_DATA0
)
827 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
832 const unsigned array_len
=
833 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
834 assert(rt
+ array_len
<= max_rt
);
837 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
838 /* If this is the RT at location 0 and we have alpha to coverage
839 * enabled we will have to create a null RT for it, so mark it as
842 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
846 for (unsigned i
= 0; i
< array_len
; i
++)
847 rt_used
[rt
+ i
] = true;
850 /* Set new, compacted, location */
851 for (unsigned i
= 0; i
< max_rt
; i
++) {
855 rt_to_bindings
[i
] = num_rts
;
857 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
858 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
859 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
864 /* Setup a null render target */
865 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
866 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
875 bool deleted_output
= false;
876 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
877 if (var
->data
.location
< FRAG_RESULT_DATA0
)
880 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
882 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
883 /* Unused or out-of-bounds, throw it away, unless it is the first
884 * RT and we have alpha to coverage enabled.
886 deleted_output
= true;
887 var
->data
.mode
= nir_var_function_temp
;
888 exec_node_remove(&var
->node
);
889 exec_list_push_tail(&impl
->locals
, &var
->node
);
893 /* Give it the new location */
894 assert(rt_to_bindings
[rt
] != -1);
895 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
899 nir_fixup_deref_modes(stage
->nir
);
902 /* If we have no render targets, we need a null render target */
903 rt_bindings
[0] = (struct anv_pipeline_binding
) {
904 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
911 /* Now that we've determined the actual number of render targets, adjust
912 * the key accordingly.
914 stage
->key
.wm
.nr_color_regions
= num_rts
;
915 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
917 assert(num_rts
<= max_rt
);
918 assert(stage
->bind_map
.surface_count
== 0);
919 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
920 rt_bindings
, num_rts
);
921 stage
->bind_map
.surface_count
+= num_rts
;
924 static const unsigned *
925 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
927 struct anv_device
*device
,
928 struct anv_pipeline_stage
*fs_stage
,
929 struct anv_pipeline_stage
*prev_stage
)
931 /* TODO: we could set this to 0 based on the information in nir_shader, but
932 * we need this before we call spirv_to_nir.
935 fs_stage
->key
.wm
.input_slots_valid
=
936 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
938 const unsigned *code
=
939 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
940 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
941 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
943 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
944 !fs_stage
->prog_data
.wm
.has_side_effects
&&
945 !fs_stage
->prog_data
.wm
.uses_kill
&&
946 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
947 !fs_stage
->prog_data
.wm
.computed_stencil
) {
948 /* This fragment shader has no outputs and no side effects. Go ahead
949 * and return the code pointer so we don't accidentally think the
950 * compile failed but zero out prog_data which will set program_size to
951 * zero and disable the stage.
953 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
960 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
961 struct anv_pipeline_cache
*cache
,
962 const VkGraphicsPipelineCreateInfo
*info
)
964 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
965 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
967 int64_t pipeline_start
= os_time_get_nano();
969 const struct brw_compiler
*compiler
=
970 pipeline
->device
->instance
->physicalDevice
.compiler
;
971 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
973 pipeline
->active_stages
= 0;
976 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
977 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
978 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
980 pipeline
->active_stages
|= sinfo
->stage
;
982 int64_t stage_start
= os_time_get_nano();
984 stages
[stage
].stage
= stage
;
985 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
986 stages
[stage
].entrypoint
= sinfo
->pName
;
987 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
988 anv_pipeline_hash_shader(stages
[stage
].module
,
989 stages
[stage
].entrypoint
,
991 stages
[stage
].spec_info
,
992 stages
[stage
].shader_sha1
);
994 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
996 case MESA_SHADER_VERTEX
:
997 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
999 case MESA_SHADER_TESS_CTRL
:
1000 populate_tcs_prog_key(devinfo
,
1001 info
->pTessellationState
->patchControlPoints
,
1002 &stages
[stage
].key
.tcs
);
1004 case MESA_SHADER_TESS_EVAL
:
1005 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
1007 case MESA_SHADER_GEOMETRY
:
1008 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
1010 case MESA_SHADER_FRAGMENT
:
1011 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
1012 info
->pMultisampleState
,
1013 &stages
[stage
].key
.wm
);
1016 unreachable("Invalid graphics shader stage");
1019 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1020 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1023 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1024 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1026 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1028 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1030 unsigned char sha1
[20];
1031 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1034 unsigned cache_hits
= 0;
1035 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1036 if (!stages
[s
].entrypoint
)
1039 int64_t stage_start
= os_time_get_nano();
1041 stages
[s
].cache_key
.stage
= s
;
1042 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1045 struct anv_shader_bin
*bin
=
1046 anv_device_search_for_kernel(pipeline
->device
, cache
,
1047 &stages
[s
].cache_key
,
1048 sizeof(stages
[s
].cache_key
), &cache_hit
);
1051 pipeline
->shaders
[s
] = bin
;
1056 stages
[s
].feedback
.flags
|=
1057 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1059 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1062 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1063 if (cache_hits
== found
) {
1064 pipeline_feedback
.flags
|=
1065 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1067 /* We found all our shaders in the cache. We're done. */
1069 } else if (found
> 0) {
1070 /* We found some but not all of our shaders. This shouldn't happen
1071 * most of the time but it can if we have a partially populated
1074 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1076 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1077 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1078 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1079 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1080 (uint64_t)(uintptr_t)cache
,
1082 "Found a partial pipeline in the cache. This is "
1083 "most likely caused by an incomplete pipeline cache "
1084 "import or export");
1086 /* We're going to have to recompile anyway, so just throw away our
1087 * references to the shaders in the cache. We'll get them out of the
1088 * cache again as part of the compilation process.
1090 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1091 stages
[s
].feedback
.flags
= 0;
1092 if (pipeline
->shaders
[s
]) {
1093 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1094 pipeline
->shaders
[s
] = NULL
;
1099 void *pipeline_ctx
= ralloc_context(NULL
);
1101 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1102 if (!stages
[s
].entrypoint
)
1105 int64_t stage_start
= os_time_get_nano();
1107 assert(stages
[s
].stage
== s
);
1108 assert(pipeline
->shaders
[s
] == NULL
);
1110 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1111 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1112 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1115 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1118 if (stages
[s
].nir
== NULL
) {
1119 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1123 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1126 /* Walk backwards to link */
1127 struct anv_pipeline_stage
*next_stage
= NULL
;
1128 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1129 if (!stages
[s
].entrypoint
)
1133 case MESA_SHADER_VERTEX
:
1134 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1136 case MESA_SHADER_TESS_CTRL
:
1137 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1139 case MESA_SHADER_TESS_EVAL
:
1140 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1142 case MESA_SHADER_GEOMETRY
:
1143 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1145 case MESA_SHADER_FRAGMENT
:
1146 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1149 unreachable("Invalid graphics shader stage");
1152 next_stage
= &stages
[s
];
1155 struct anv_pipeline_stage
*prev_stage
= NULL
;
1156 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1157 if (!stages
[s
].entrypoint
)
1160 int64_t stage_start
= os_time_get_nano();
1162 void *stage_ctx
= ralloc_context(NULL
);
1164 nir_xfb_info
*xfb_info
= NULL
;
1165 if (s
== MESA_SHADER_VERTEX
||
1166 s
== MESA_SHADER_TESS_EVAL
||
1167 s
== MESA_SHADER_GEOMETRY
)
1168 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1170 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1172 const unsigned *code
;
1174 case MESA_SHADER_VERTEX
:
1175 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1178 case MESA_SHADER_TESS_CTRL
:
1179 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1180 &stages
[s
], prev_stage
);
1182 case MESA_SHADER_TESS_EVAL
:
1183 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1184 &stages
[s
], prev_stage
);
1186 case MESA_SHADER_GEOMETRY
:
1187 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1188 &stages
[s
], prev_stage
);
1190 case MESA_SHADER_FRAGMENT
:
1191 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1192 &stages
[s
], prev_stage
);
1195 unreachable("Invalid graphics shader stage");
1198 ralloc_free(stage_ctx
);
1199 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1203 struct anv_shader_bin
*bin
=
1204 anv_device_upload_kernel(pipeline
->device
, cache
,
1205 &stages
[s
].cache_key
,
1206 sizeof(stages
[s
].cache_key
),
1207 code
, stages
[s
].prog_data
.base
.program_size
,
1208 stages
[s
].nir
->constant_data
,
1209 stages
[s
].nir
->constant_data_size
,
1210 &stages
[s
].prog_data
.base
,
1211 brw_prog_data_size(s
),
1212 xfb_info
, &stages
[s
].bind_map
);
1214 ralloc_free(stage_ctx
);
1215 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1219 pipeline
->shaders
[s
] = bin
;
1220 ralloc_free(stage_ctx
);
1222 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1224 prev_stage
= &stages
[s
];
1227 ralloc_free(pipeline_ctx
);
1231 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1232 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1233 /* This can happen if we decided to implicitly disable the fragment
1234 * shader. See anv_pipeline_compile_fs().
1236 anv_shader_bin_unref(pipeline
->device
,
1237 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1238 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1239 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1242 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1244 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1245 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1246 if (create_feedback
) {
1247 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1249 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1250 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1251 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1252 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1259 ralloc_free(pipeline_ctx
);
1261 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1262 if (pipeline
->shaders
[s
])
1263 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1270 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1271 struct anv_pipeline_cache
*cache
,
1272 const VkComputePipelineCreateInfo
*info
,
1273 const struct anv_shader_module
*module
,
1274 const char *entrypoint
,
1275 const VkSpecializationInfo
*spec_info
)
1277 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1278 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1280 int64_t pipeline_start
= os_time_get_nano();
1282 const struct brw_compiler
*compiler
=
1283 pipeline
->device
->instance
->physicalDevice
.compiler
;
1285 struct anv_pipeline_stage stage
= {
1286 .stage
= MESA_SHADER_COMPUTE
,
1288 .entrypoint
= entrypoint
,
1289 .spec_info
= spec_info
,
1291 .stage
= MESA_SHADER_COMPUTE
,
1294 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1297 anv_pipeline_hash_shader(stage
.module
,
1299 MESA_SHADER_COMPUTE
,
1303 struct anv_shader_bin
*bin
= NULL
;
1305 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1307 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1309 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1311 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1312 sizeof(stage
.cache_key
), &cache_hit
);
1315 int64_t stage_start
= os_time_get_nano();
1317 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1318 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1319 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1322 /* Set up a binding for the gl_NumWorkGroups */
1323 stage
.bind_map
.surface_count
= 1;
1324 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1325 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1328 void *mem_ctx
= ralloc_context(NULL
);
1330 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1331 if (stage
.nir
== NULL
) {
1332 ralloc_free(mem_ctx
);
1333 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1336 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1338 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1339 &stage
.prog_data
.cs
);
1341 const unsigned *shader_code
=
1342 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1343 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1344 if (shader_code
== NULL
) {
1345 ralloc_free(mem_ctx
);
1346 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1349 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1350 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1351 &stage
.cache_key
, sizeof(stage
.cache_key
),
1352 shader_code
, code_size
,
1353 stage
.nir
->constant_data
,
1354 stage
.nir
->constant_data_size
,
1355 &stage
.prog_data
.base
,
1356 sizeof(stage
.prog_data
.cs
),
1357 NULL
, &stage
.bind_map
);
1359 ralloc_free(mem_ctx
);
1360 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1363 ralloc_free(mem_ctx
);
1365 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1369 stage
.feedback
.flags
|=
1370 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1371 pipeline_feedback
.flags
|=
1372 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1374 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1376 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1377 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1378 if (create_feedback
) {
1379 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1381 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1382 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1385 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1386 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1392 * Copy pipeline state not marked as dynamic.
1393 * Dynamic state is pipeline state which hasn't been provided at pipeline
1394 * creation time, but is dynamically provided afterwards using various
1395 * vkCmdSet* functions.
1397 * The set of state considered "non_dynamic" is determined by the pieces of
1398 * state that have their corresponding VkDynamicState enums omitted from
1399 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1401 * @param[out] pipeline Destination non_dynamic state.
1402 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1405 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1406 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1408 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1409 struct anv_subpass
*subpass
= pipeline
->subpass
;
1411 pipeline
->dynamic_state
= default_dynamic_state
;
1413 if (pCreateInfo
->pDynamicState
) {
1414 /* Remove all of the states that are marked as dynamic */
1415 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1416 for (uint32_t s
= 0; s
< count
; s
++)
1417 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1420 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1422 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1424 * pViewportState is [...] NULL if the pipeline
1425 * has rasterization disabled.
1427 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1428 assert(pCreateInfo
->pViewportState
);
1430 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1431 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1432 typed_memcpy(dynamic
->viewport
.viewports
,
1433 pCreateInfo
->pViewportState
->pViewports
,
1434 pCreateInfo
->pViewportState
->viewportCount
);
1437 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1438 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1439 typed_memcpy(dynamic
->scissor
.scissors
,
1440 pCreateInfo
->pViewportState
->pScissors
,
1441 pCreateInfo
->pViewportState
->scissorCount
);
1445 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1446 assert(pCreateInfo
->pRasterizationState
);
1447 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1450 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1451 assert(pCreateInfo
->pRasterizationState
);
1452 dynamic
->depth_bias
.bias
=
1453 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1454 dynamic
->depth_bias
.clamp
=
1455 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1456 dynamic
->depth_bias
.slope
=
1457 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1460 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1462 * pColorBlendState is [...] NULL if the pipeline has rasterization
1463 * disabled or if the subpass of the render pass the pipeline is
1464 * created against does not use any color attachments.
1466 bool uses_color_att
= false;
1467 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1468 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1469 uses_color_att
= true;
1474 if (uses_color_att
&&
1475 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1476 assert(pCreateInfo
->pColorBlendState
);
1478 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1479 typed_memcpy(dynamic
->blend_constants
,
1480 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1483 /* If there is no depthstencil attachment, then don't read
1484 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1485 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1486 * no need to override the depthstencil defaults in
1487 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1489 * Section 9.2 of the Vulkan 1.0.15 spec says:
1491 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1492 * disabled or if the subpass of the render pass the pipeline is created
1493 * against does not use a depth/stencil attachment.
1495 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1496 subpass
->depth_stencil_attachment
) {
1497 assert(pCreateInfo
->pDepthStencilState
);
1499 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1500 dynamic
->depth_bounds
.min
=
1501 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1502 dynamic
->depth_bounds
.max
=
1503 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1506 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1507 dynamic
->stencil_compare_mask
.front
=
1508 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1509 dynamic
->stencil_compare_mask
.back
=
1510 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1513 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1514 dynamic
->stencil_write_mask
.front
=
1515 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1516 dynamic
->stencil_write_mask
.back
=
1517 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1520 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1521 dynamic
->stencil_reference
.front
=
1522 pCreateInfo
->pDepthStencilState
->front
.reference
;
1523 dynamic
->stencil_reference
.back
=
1524 pCreateInfo
->pDepthStencilState
->back
.reference
;
1528 pipeline
->dynamic_state_mask
= states
;
1532 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1535 struct anv_render_pass
*renderpass
= NULL
;
1536 struct anv_subpass
*subpass
= NULL
;
1538 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1539 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1541 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1543 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1546 assert(info
->subpass
< renderpass
->subpass_count
);
1547 subpass
= &renderpass
->subpasses
[info
->subpass
];
1549 assert(info
->stageCount
>= 1);
1550 assert(info
->pVertexInputState
);
1551 assert(info
->pInputAssemblyState
);
1552 assert(info
->pRasterizationState
);
1553 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1554 assert(info
->pViewportState
);
1555 assert(info
->pMultisampleState
);
1557 if (subpass
&& subpass
->depth_stencil_attachment
)
1558 assert(info
->pDepthStencilState
);
1560 if (subpass
&& subpass
->color_count
> 0) {
1561 bool all_color_unused
= true;
1562 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1563 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1564 all_color_unused
= false;
1566 /* pColorBlendState is ignored if the pipeline has rasterization
1567 * disabled or if the subpass of the render pass the pipeline is
1568 * created against does not use any color attachments.
1570 assert(info
->pColorBlendState
|| all_color_unused
);
1574 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1575 switch (info
->pStages
[i
].stage
) {
1576 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1577 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1578 assert(info
->pTessellationState
);
1588 * Calculate the desired L3 partitioning based on the current state of the
1589 * pipeline. For now this simply returns the conservative defaults calculated
1590 * by get_default_l3_weights(), but we could probably do better by gathering
1591 * more statistics from the pipeline state (e.g. guess of expected URB usage
1592 * and bound surfaces), or by using feed-back from performance counters.
1595 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1597 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1599 const struct gen_l3_weights w
=
1600 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1602 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1603 pipeline
->urb
.total_size
=
1604 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1608 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1609 struct anv_device
*device
,
1610 struct anv_pipeline_cache
*cache
,
1611 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1612 const VkAllocationCallbacks
*alloc
)
1616 anv_pipeline_validate_create_info(pCreateInfo
);
1619 alloc
= &device
->alloc
;
1621 pipeline
->device
= device
;
1623 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1624 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1625 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1627 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1628 if (result
!= VK_SUCCESS
)
1631 pipeline
->batch
.alloc
= alloc
;
1632 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1633 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1634 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1635 pipeline
->batch
.status
= VK_SUCCESS
;
1637 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1638 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1639 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1641 /* Previously we enabled depth clipping when !depthClampEnable.
1642 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1643 * clipping info is available, use its enable value to determine clipping,
1644 * otherwise fallback to the previous !depthClampEnable logic.
1646 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1647 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1648 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1649 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1651 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1652 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1654 pipeline
->needs_data_cache
= false;
1656 /* When we free the pipeline, we detect stages based on the NULL status
1657 * of various prog_data pointers. Make them NULL by default.
1659 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1661 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1662 if (result
!= VK_SUCCESS
) {
1663 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1667 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1669 anv_pipeline_setup_l3_config(pipeline
, false);
1671 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1672 pCreateInfo
->pVertexInputState
;
1674 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1676 pipeline
->vb_used
= 0;
1677 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1678 const VkVertexInputAttributeDescription
*desc
=
1679 &vi_info
->pVertexAttributeDescriptions
[i
];
1681 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1682 pipeline
->vb_used
|= 1 << desc
->binding
;
1685 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1686 const VkVertexInputBindingDescription
*desc
=
1687 &vi_info
->pVertexBindingDescriptions
[i
];
1689 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1691 /* Step rate is programmed per vertex element (attribute), not
1692 * binding. Set up a map of which bindings step per instance, for
1693 * reference by vertex element setup. */
1694 switch (desc
->inputRate
) {
1696 case VK_VERTEX_INPUT_RATE_VERTEX
:
1697 pipeline
->vb
[desc
->binding
].instanced
= false;
1699 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1700 pipeline
->vb
[desc
->binding
].instanced
= true;
1704 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1707 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1708 vk_find_struct_const(vi_info
->pNext
,
1709 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1711 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1712 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1713 &vi_div_state
->pVertexBindingDivisors
[i
];
1715 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1719 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1720 * different views. If the client asks for instancing, we need to multiply
1721 * the instance divisor by the number of views ensure that we repeat the
1722 * client's per-instance data once for each view.
1724 if (pipeline
->subpass
->view_mask
) {
1725 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1726 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1727 if (pipeline
->vb
[vb
].instanced
)
1728 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1732 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1733 pCreateInfo
->pInputAssemblyState
;
1734 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1735 pCreateInfo
->pTessellationState
;
1736 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1738 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1739 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1741 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];