2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
34 #include "spirv/nir_spirv.h"
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
41 VkResult
anv_CreateShaderModule(
43 const VkShaderModuleCreateInfo
* pCreateInfo
,
44 const VkAllocationCallbacks
* pAllocator
,
45 VkShaderModule
* pShaderModule
)
47 ANV_FROM_HANDLE(anv_device
, device
, _device
);
48 struct anv_shader_module
*module
;
50 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
51 assert(pCreateInfo
->flags
== 0);
53 module
= anv_alloc2(&device
->alloc
, pAllocator
,
54 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
60 module
->size
= pCreateInfo
->codeSize
;
61 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
63 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
65 *pShaderModule
= anv_shader_module_to_handle(module
);
70 void anv_DestroyShaderModule(
72 VkShaderModule _module
,
73 const VkAllocationCallbacks
* pAllocator
)
75 ANV_FROM_HANDLE(anv_device
, device
, _device
);
76 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
78 anv_free2(&device
->alloc
, pAllocator
, module
);
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
87 anv_shader_compile_to_nir(struct anv_device
*device
,
88 struct anv_shader_module
*module
,
89 const char *entrypoint_name
,
90 gl_shader_stage stage
,
91 const VkSpecializationInfo
*spec_info
)
93 if (strcmp(entrypoint_name
, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
97 const struct brw_compiler
*compiler
=
98 device
->instance
->physicalDevice
.compiler
;
99 const nir_shader_compiler_options
*nir_options
=
100 compiler
->glsl_compiler_options
[stage
].NirOptions
;
103 nir_function
*entry_point
;
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
109 nir
->options
= nir_options
;
110 nir_validate_shader(nir
);
112 assert(exec_list_length(&nir
->functions
) == 1);
113 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
114 entry_point
= exec_node_data(nir_function
, node
, node
);
116 uint32_t *spirv
= (uint32_t *) module
->data
;
117 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
118 assert(module
->size
% 4 == 0);
120 uint32_t num_spec_entries
= 0;
121 struct nir_spirv_specialization
*spec_entries
= NULL
;
122 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
123 num_spec_entries
= spec_info
->mapEntryCount
;
124 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
125 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
126 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
127 const void *data
= spec_info
->pData
+ entry
.offset
;
128 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
130 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
131 spec_entries
[i
].data
= *(const uint32_t *)data
;
135 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
136 spec_entries
, num_spec_entries
,
137 stage
, entrypoint_name
, nir_options
);
138 nir
= entry_point
->shader
;
139 assert(nir
->stage
== stage
);
140 nir_validate_shader(nir
);
144 if (stage
== MESA_SHADER_FRAGMENT
) {
145 nir_lower_wpos_center(nir
);
146 nir_validate_shader(nir
);
149 nir_lower_returns(nir
);
150 nir_validate_shader(nir
);
152 nir_inline_functions(nir
);
153 nir_validate_shader(nir
);
155 /* Pick off the single entrypoint that we want */
156 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
157 if (func
!= entry_point
)
158 exec_node_remove(&func
->node
);
160 assert(exec_list_length(&nir
->functions
) == 1);
161 entry_point
->name
= ralloc_strdup(entry_point
, "main");
163 nir_remove_dead_variables(nir
, nir_var_shader_in
);
164 nir_remove_dead_variables(nir
, nir_var_shader_out
);
165 nir_remove_dead_variables(nir
, nir_var_system_value
);
166 nir_validate_shader(nir
);
168 nir_propagate_invariant(nir
);
169 nir_validate_shader(nir
);
171 nir_lower_io_to_temporaries(entry_point
->shader
, entry_point
, true, false);
173 nir_lower_system_values(nir
);
174 nir_validate_shader(nir
);
177 /* Vulkan uses the separate-shader linking model */
178 nir
->info
.separate_shader
= true;
180 nir
= brw_preprocess_nir(compiler
, nir
);
182 nir_shader_gather_info(nir
, entry_point
->impl
);
184 nir_variable_mode indirect_mask
= 0;
185 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
186 indirect_mask
|= nir_var_shader_in
;
187 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
188 indirect_mask
|= nir_var_local
;
190 nir_lower_indirect_derefs(nir
, indirect_mask
);
195 void anv_DestroyPipeline(
197 VkPipeline _pipeline
,
198 const VkAllocationCallbacks
* pAllocator
)
200 ANV_FROM_HANDLE(anv_device
, device
, _device
);
201 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
203 anv_reloc_list_finish(&pipeline
->batch_relocs
,
204 pAllocator
? pAllocator
: &device
->alloc
);
205 if (pipeline
->blend_state
.map
)
206 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
207 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
210 static const uint32_t vk_to_gen_primitive_type
[] = {
211 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
212 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
213 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
214 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
215 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
216 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
217 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
218 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
219 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
220 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
221 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
225 populate_sampler_prog_key(const struct brw_device_info
*devinfo
,
226 struct brw_sampler_prog_key_data
*key
)
228 /* XXX: Handle texture swizzle on HSW- */
229 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
230 /* Assume color sampler, no swizzling. (Works for BDW+) */
231 key
->swizzles
[i
] = SWIZZLE_XYZW
;
236 populate_vs_prog_key(const struct brw_device_info
*devinfo
,
237 struct brw_vs_prog_key
*key
)
239 memset(key
, 0, sizeof(*key
));
241 populate_sampler_prog_key(devinfo
, &key
->tex
);
243 /* XXX: Handle vertex input work-arounds */
245 /* XXX: Handle sampler_prog_key */
249 populate_gs_prog_key(const struct brw_device_info
*devinfo
,
250 struct brw_gs_prog_key
*key
)
252 memset(key
, 0, sizeof(*key
));
254 populate_sampler_prog_key(devinfo
, &key
->tex
);
258 populate_wm_prog_key(const struct brw_device_info
*devinfo
,
259 const VkGraphicsPipelineCreateInfo
*info
,
260 const struct anv_graphics_pipeline_create_info
*extra
,
261 struct brw_wm_prog_key
*key
)
263 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
265 memset(key
, 0, sizeof(*key
));
267 populate_sampler_prog_key(devinfo
, &key
->tex
);
269 /* TODO: Fill out key->input_slots_valid */
271 /* Vulkan doesn't specify a default */
272 key
->high_quality_derivatives
= false;
274 /* XXX Vulkan doesn't appear to specify */
275 key
->clamp_fragment_color
= false;
277 if (extra
&& extra
->color_attachment_count
>= 0) {
278 key
->nr_color_regions
= extra
->color_attachment_count
;
280 key
->nr_color_regions
=
281 render_pass
->subpasses
[info
->subpass
].color_count
;
284 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
285 info
->pMultisampleState
&&
286 info
->pMultisampleState
->alphaToCoverageEnable
;
288 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterizationSamples
> 1) {
289 /* We should probably pull this out of the shader, but it's fairly
290 * harmless to compute it and then let dead-code take care of it.
292 key
->persample_interp
=
293 (info
->pMultisampleState
->minSampleShading
*
294 info
->pMultisampleState
->rasterizationSamples
) > 1;
295 key
->multisample_fbo
= true;
300 populate_cs_prog_key(const struct brw_device_info
*devinfo
,
301 struct brw_cs_prog_key
*key
)
303 memset(key
, 0, sizeof(*key
));
305 populate_sampler_prog_key(devinfo
, &key
->tex
);
309 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
310 struct anv_shader_module
*module
,
311 const char *entrypoint
,
312 gl_shader_stage stage
,
313 const VkSpecializationInfo
*spec_info
,
314 struct brw_stage_prog_data
*prog_data
,
315 struct anv_pipeline_bind_map
*map
)
317 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
,
318 module
, entrypoint
, stage
,
323 anv_nir_lower_push_constants(nir
);
325 /* Figure out the number of parameters */
326 prog_data
->nr_params
= 0;
328 if (nir
->num_uniforms
> 0) {
329 /* If the shader uses any push constants at all, we'll just give
330 * them the maximum possible number
332 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
335 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
336 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
* 2;
338 if (nir
->info
.num_images
> 0) {
339 prog_data
->nr_params
+= nir
->info
.num_images
* BRW_IMAGE_PARAM_SIZE
;
340 pipeline
->needs_data_cache
= true;
343 if (stage
== MESA_SHADER_COMPUTE
)
344 ((struct brw_cs_prog_data
*)prog_data
)->thread_local_id_index
=
345 prog_data
->nr_params
++; /* The CS Thread ID uniform */
347 if (nir
->info
.num_ssbos
> 0)
348 pipeline
->needs_data_cache
= true;
350 if (prog_data
->nr_params
> 0) {
351 /* XXX: I think we're leaking this */
352 prog_data
->param
= (const union gl_constant_value
**)
353 malloc(prog_data
->nr_params
* sizeof(union gl_constant_value
*));
355 /* We now set the param values to be offsets into a
356 * anv_push_constant_data structure. Since the compiler doesn't
357 * actually dereference any of the gl_constant_value pointers in the
358 * params array, it doesn't really matter what we put here.
360 struct anv_push_constants
*null_data
= NULL
;
361 if (nir
->num_uniforms
> 0) {
362 /* Fill out the push constants section of the param array */
363 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
364 prog_data
->param
[i
] = (const union gl_constant_value
*)
365 &null_data
->client_data
[i
* sizeof(float)];
369 /* Set up dynamic offsets */
370 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
372 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
373 if (pipeline
->layout
)
374 anv_nir_apply_pipeline_layout(pipeline
, nir
, prog_data
, map
);
376 /* nir_lower_io will only handle the push constants; we need to set this
377 * to the full number of possible uniforms.
379 nir
->num_uniforms
= prog_data
->nr_params
* 4;
385 anv_fill_binding_table(struct brw_stage_prog_data
*prog_data
, unsigned bias
)
387 prog_data
->binding_table
.size_bytes
= 0;
388 prog_data
->binding_table
.texture_start
= bias
;
389 prog_data
->binding_table
.ubo_start
= bias
;
390 prog_data
->binding_table
.ssbo_start
= bias
;
391 prog_data
->binding_table
.image_start
= bias
;
395 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
396 gl_shader_stage stage
,
397 const struct brw_stage_prog_data
*prog_data
,
398 struct anv_pipeline_bind_map
*map
)
400 pipeline
->prog_data
[stage
] = prog_data
;
401 pipeline
->active_stages
|= mesa_to_vk_shader_stage(stage
);
402 pipeline
->bindings
[stage
] = *map
;
406 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
407 struct anv_pipeline_cache
*cache
,
408 const VkGraphicsPipelineCreateInfo
*info
,
409 struct anv_shader_module
*module
,
410 const char *entrypoint
,
411 const VkSpecializationInfo
*spec_info
)
413 const struct brw_compiler
*compiler
=
414 pipeline
->device
->instance
->physicalDevice
.compiler
;
415 const struct brw_stage_prog_data
*stage_prog_data
;
416 struct anv_pipeline_bind_map map
;
417 struct brw_vs_prog_key key
;
418 uint32_t kernel
= NO_KERNEL
;
419 unsigned char sha1
[20];
421 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
423 if (module
->size
> 0) {
424 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
425 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
428 if (kernel
== NO_KERNEL
) {
429 struct brw_vs_prog_data prog_data
= { 0, };
430 struct anv_pipeline_binding surface_to_descriptor
[256];
431 struct anv_pipeline_binding sampler_to_descriptor
[256];
433 map
= (struct anv_pipeline_bind_map
) {
434 .surface_to_descriptor
= surface_to_descriptor
,
435 .sampler_to_descriptor
= sampler_to_descriptor
438 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
439 MESA_SHADER_VERTEX
, spec_info
,
440 &prog_data
.base
.base
, &map
);
442 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
444 anv_fill_binding_table(&prog_data
.base
.base
, 0);
446 void *mem_ctx
= ralloc_context(NULL
);
448 if (module
->nir
== NULL
)
449 ralloc_steal(mem_ctx
, nir
);
451 prog_data
.inputs_read
= nir
->info
.inputs_read
;
453 brw_compute_vue_map(&pipeline
->device
->info
,
454 &prog_data
.base
.vue_map
,
455 nir
->info
.outputs_written
,
456 nir
->info
.separate_shader
);
459 const unsigned *shader_code
=
460 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
461 NULL
, false, -1, &code_size
, NULL
);
462 if (shader_code
== NULL
) {
463 ralloc_free(mem_ctx
);
464 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
467 stage_prog_data
= &prog_data
.base
.base
;
468 kernel
= anv_pipeline_cache_upload_kernel(cache
,
469 module
->size
> 0 ? sha1
: NULL
,
470 shader_code
, code_size
,
471 &stage_prog_data
, sizeof(prog_data
),
473 ralloc_free(mem_ctx
);
476 const struct brw_vs_prog_data
*vs_prog_data
=
477 (const struct brw_vs_prog_data
*) stage_prog_data
;
479 if (vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
) {
480 pipeline
->vs_simd8
= kernel
;
481 pipeline
->vs_vec4
= NO_KERNEL
;
483 pipeline
->vs_simd8
= NO_KERNEL
;
484 pipeline
->vs_vec4
= kernel
;
487 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_VERTEX
,
488 stage_prog_data
, &map
);
494 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
495 struct anv_pipeline_cache
*cache
,
496 const VkGraphicsPipelineCreateInfo
*info
,
497 struct anv_shader_module
*module
,
498 const char *entrypoint
,
499 const VkSpecializationInfo
*spec_info
)
501 const struct brw_compiler
*compiler
=
502 pipeline
->device
->instance
->physicalDevice
.compiler
;
503 const struct brw_stage_prog_data
*stage_prog_data
;
504 struct anv_pipeline_bind_map map
;
505 struct brw_gs_prog_key key
;
506 uint32_t kernel
= NO_KERNEL
;
507 unsigned char sha1
[20];
509 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
511 if (module
->size
> 0) {
512 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
513 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
516 if (kernel
== NO_KERNEL
) {
517 struct brw_gs_prog_data prog_data
= { 0, };
518 struct anv_pipeline_binding surface_to_descriptor
[256];
519 struct anv_pipeline_binding sampler_to_descriptor
[256];
521 map
= (struct anv_pipeline_bind_map
) {
522 .surface_to_descriptor
= surface_to_descriptor
,
523 .sampler_to_descriptor
= sampler_to_descriptor
526 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
527 MESA_SHADER_GEOMETRY
, spec_info
,
528 &prog_data
.base
.base
, &map
);
530 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
532 anv_fill_binding_table(&prog_data
.base
.base
, 0);
534 void *mem_ctx
= ralloc_context(NULL
);
536 if (module
->nir
== NULL
)
537 ralloc_steal(mem_ctx
, nir
);
539 brw_compute_vue_map(&pipeline
->device
->info
,
540 &prog_data
.base
.vue_map
,
541 nir
->info
.outputs_written
,
542 nir
->info
.separate_shader
);
545 const unsigned *shader_code
=
546 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
547 NULL
, -1, &code_size
, NULL
);
548 if (shader_code
== NULL
) {
549 ralloc_free(mem_ctx
);
550 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
554 stage_prog_data
= &prog_data
.base
.base
;
555 kernel
= anv_pipeline_cache_upload_kernel(cache
,
556 module
->size
> 0 ? sha1
: NULL
,
557 shader_code
, code_size
,
558 &stage_prog_data
, sizeof(prog_data
),
561 ralloc_free(mem_ctx
);
564 pipeline
->gs_kernel
= kernel
;
566 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_GEOMETRY
,
567 stage_prog_data
, &map
);
573 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
574 struct anv_pipeline_cache
*cache
,
575 const VkGraphicsPipelineCreateInfo
*info
,
576 const struct anv_graphics_pipeline_create_info
*extra
,
577 struct anv_shader_module
*module
,
578 const char *entrypoint
,
579 const VkSpecializationInfo
*spec_info
)
581 const struct brw_compiler
*compiler
=
582 pipeline
->device
->instance
->physicalDevice
.compiler
;
583 const struct brw_stage_prog_data
*stage_prog_data
;
584 struct anv_pipeline_bind_map map
;
585 struct brw_wm_prog_key key
;
586 unsigned char sha1
[20];
588 populate_wm_prog_key(&pipeline
->device
->info
, info
, extra
, &key
);
590 if (module
->size
> 0) {
591 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
593 anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
596 if (pipeline
->ps_ksp0
== NO_KERNEL
) {
597 struct brw_wm_prog_data prog_data
= { 0, };
598 struct anv_pipeline_binding surface_to_descriptor
[256];
599 struct anv_pipeline_binding sampler_to_descriptor
[256];
601 map
= (struct anv_pipeline_bind_map
) {
602 .surface_to_descriptor
= surface_to_descriptor
+ 8,
603 .sampler_to_descriptor
= sampler_to_descriptor
606 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
607 MESA_SHADER_FRAGMENT
, spec_info
,
608 &prog_data
.base
, &map
);
610 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
612 unsigned num_rts
= 0;
613 struct anv_pipeline_binding rt_bindings
[8];
614 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
)->impl
;
615 nir_foreach_variable_safe(var
, &nir
->outputs
) {
616 if (var
->data
.location
< FRAG_RESULT_DATA0
)
619 unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
620 if (rt
>= key
.nr_color_regions
) {
621 /* Out-of-bounds, throw it away */
622 var
->data
.mode
= nir_var_local
;
623 exec_node_remove(&var
->node
);
624 exec_list_push_tail(&impl
->locals
, &var
->node
);
628 /* Give it a new, compacted, location */
629 var
->data
.location
= FRAG_RESULT_DATA0
+ num_rts
;
632 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
633 assert(num_rts
+ array_len
<= 8);
635 for (unsigned i
= 0; i
< array_len
; i
++) {
636 rt_bindings
[num_rts
] = (struct anv_pipeline_binding
) {
637 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
643 num_rts
+= array_len
;
646 if (pipeline
->use_repclear
) {
647 assert(num_rts
== 1);
648 key
.nr_color_regions
= 1;
652 /* If we have no render targets, we need a null render target */
653 rt_bindings
[0] = (struct anv_pipeline_binding
) {
654 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
661 assert(num_rts
<= 8);
662 map
.surface_to_descriptor
-= num_rts
;
663 map
.surface_count
+= num_rts
;
664 assert(map
.surface_count
<= 256);
665 memcpy(map
.surface_to_descriptor
, rt_bindings
,
666 num_rts
* sizeof(*rt_bindings
));
668 anv_fill_binding_table(&prog_data
.base
, num_rts
);
670 void *mem_ctx
= ralloc_context(NULL
);
672 if (module
->nir
== NULL
)
673 ralloc_steal(mem_ctx
, nir
);
676 const unsigned *shader_code
=
677 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
678 NULL
, -1, -1, true, pipeline
->use_repclear
,
680 if (shader_code
== NULL
) {
681 ralloc_free(mem_ctx
);
682 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
685 stage_prog_data
= &prog_data
.base
;
687 anv_pipeline_cache_upload_kernel(cache
,
688 module
->size
> 0 ? sha1
: NULL
,
689 shader_code
, code_size
,
690 &stage_prog_data
, sizeof(prog_data
),
693 ralloc_free(mem_ctx
);
696 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_FRAGMENT
,
697 stage_prog_data
, &map
);
703 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
704 struct anv_pipeline_cache
*cache
,
705 const VkComputePipelineCreateInfo
*info
,
706 struct anv_shader_module
*module
,
707 const char *entrypoint
,
708 const VkSpecializationInfo
*spec_info
)
710 const struct brw_compiler
*compiler
=
711 pipeline
->device
->instance
->physicalDevice
.compiler
;
712 const struct brw_stage_prog_data
*stage_prog_data
;
713 struct anv_pipeline_bind_map map
;
714 struct brw_cs_prog_key key
;
715 uint32_t kernel
= NO_KERNEL
;
716 unsigned char sha1
[20];
718 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
720 if (module
->size
> 0) {
721 anv_hash_shader(sha1
, &key
, sizeof(key
), module
, entrypoint
, spec_info
);
722 kernel
= anv_pipeline_cache_search(cache
, sha1
, &stage_prog_data
, &map
);
725 if (module
->size
== 0 || kernel
== NO_KERNEL
) {
726 struct brw_cs_prog_data prog_data
= { 0, };
727 struct anv_pipeline_binding surface_to_descriptor
[256];
728 struct anv_pipeline_binding sampler_to_descriptor
[256];
730 map
= (struct anv_pipeline_bind_map
) {
731 .surface_to_descriptor
= surface_to_descriptor
,
732 .sampler_to_descriptor
= sampler_to_descriptor
735 nir_shader
*nir
= anv_pipeline_compile(pipeline
, module
, entrypoint
,
736 MESA_SHADER_COMPUTE
, spec_info
,
737 &prog_data
.base
, &map
);
739 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
741 anv_fill_binding_table(&prog_data
.base
, 1);
743 void *mem_ctx
= ralloc_context(NULL
);
745 if (module
->nir
== NULL
)
746 ralloc_steal(mem_ctx
, nir
);
749 const unsigned *shader_code
=
750 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, &prog_data
, nir
,
751 -1, &code_size
, NULL
);
752 if (shader_code
== NULL
) {
753 ralloc_free(mem_ctx
);
754 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
757 stage_prog_data
= &prog_data
.base
;
758 kernel
= anv_pipeline_cache_upload_kernel(cache
,
759 module
->size
> 0 ? sha1
: NULL
,
760 shader_code
, code_size
,
761 &stage_prog_data
, sizeof(prog_data
),
764 ralloc_free(mem_ctx
);
767 pipeline
->cs_simd
= kernel
;
769 anv_pipeline_add_compiled_stage(pipeline
, MESA_SHADER_COMPUTE
,
770 stage_prog_data
, &map
);
777 anv_setup_pipeline_l3_config(struct anv_pipeline
*pipeline
)
779 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
780 switch (devinfo
->gen
) {
782 if (devinfo
->is_haswell
)
783 gen75_setup_pipeline_l3_config(pipeline
);
785 gen7_setup_pipeline_l3_config(pipeline
);
788 gen8_setup_pipeline_l3_config(pipeline
);
791 gen9_setup_pipeline_l3_config(pipeline
);
794 unreachable("unsupported gen\n");
799 anv_compute_urb_partition(struct anv_pipeline
*pipeline
)
801 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
803 bool vs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
;
804 unsigned vs_size
= vs_present
?
805 get_vs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
806 unsigned vs_entry_size_bytes
= vs_size
* 64;
807 bool gs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
;
808 unsigned gs_size
= gs_present
?
809 get_gs_prog_data(pipeline
)->base
.urb_entry_size
: 1;
810 unsigned gs_entry_size_bytes
= gs_size
* 64;
812 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
814 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
815 * Allocation Size is less than 9 512-bit URB entries.
817 * Similar text exists for GS.
819 unsigned vs_granularity
= (vs_size
< 9) ? 8 : 1;
820 unsigned gs_granularity
= (gs_size
< 9) ? 8 : 1;
822 /* URB allocations must be done in 8k chunks. */
823 unsigned chunk_size_bytes
= 8192;
825 /* Determine the size of the URB in chunks. */
826 unsigned urb_chunks
= pipeline
->urb
.total_size
* 1024 / chunk_size_bytes
;
828 /* Reserve space for push constants */
829 unsigned push_constant_kb
;
830 if (pipeline
->device
->info
.gen
>= 8)
831 push_constant_kb
= 32;
832 else if (pipeline
->device
->info
.is_haswell
)
833 push_constant_kb
= pipeline
->device
->info
.gt
== 3 ? 32 : 16;
835 push_constant_kb
= 16;
837 unsigned push_constant_bytes
= push_constant_kb
* 1024;
838 unsigned push_constant_chunks
=
839 push_constant_bytes
/ chunk_size_bytes
;
841 /* Initially, assign each stage the minimum amount of URB space it needs,
842 * and make a note of how much additional space it "wants" (the amount of
843 * additional space it could actually make use of).
846 /* VS has a lower limit on the number of URB entries */
848 ALIGN(devinfo
->urb
.min_vs_entries
* vs_entry_size_bytes
,
849 chunk_size_bytes
) / chunk_size_bytes
;
851 ALIGN(devinfo
->urb
.max_vs_entries
* vs_entry_size_bytes
,
852 chunk_size_bytes
) / chunk_size_bytes
- vs_chunks
;
854 unsigned gs_chunks
= 0;
855 unsigned gs_wants
= 0;
857 /* There are two constraints on the minimum amount of URB space we can
860 * (1) We need room for at least 2 URB entries, since we always operate
861 * the GS in DUAL_OBJECT mode.
863 * (2) We can't allocate less than nr_gs_entries_granularity.
865 gs_chunks
= ALIGN(MAX2(gs_granularity
, 2) * gs_entry_size_bytes
,
866 chunk_size_bytes
) / chunk_size_bytes
;
868 ALIGN(devinfo
->urb
.max_gs_entries
* gs_entry_size_bytes
,
869 chunk_size_bytes
) / chunk_size_bytes
- gs_chunks
;
872 /* There should always be enough URB space to satisfy the minimum
873 * requirements of each stage.
875 unsigned total_needs
= push_constant_chunks
+ vs_chunks
+ gs_chunks
;
876 assert(total_needs
<= urb_chunks
);
878 /* Mete out remaining space (if any) in proportion to "wants". */
879 unsigned total_wants
= vs_wants
+ gs_wants
;
880 unsigned remaining_space
= urb_chunks
- total_needs
;
881 if (remaining_space
> total_wants
)
882 remaining_space
= total_wants
;
883 if (remaining_space
> 0) {
884 unsigned vs_additional
= (unsigned)
885 round(vs_wants
* (((double) remaining_space
) / total_wants
));
886 vs_chunks
+= vs_additional
;
887 remaining_space
-= vs_additional
;
888 gs_chunks
+= remaining_space
;
891 /* Sanity check that we haven't over-allocated. */
892 assert(push_constant_chunks
+ vs_chunks
+ gs_chunks
<= urb_chunks
);
894 /* Finally, compute the number of entries that can fit in the space
895 * allocated to each stage.
897 unsigned nr_vs_entries
= vs_chunks
* chunk_size_bytes
/ vs_entry_size_bytes
;
898 unsigned nr_gs_entries
= gs_chunks
* chunk_size_bytes
/ gs_entry_size_bytes
;
900 /* Since we rounded up when computing *_wants, this may be slightly more
901 * than the maximum allowed amount, so correct for that.
903 nr_vs_entries
= MIN2(nr_vs_entries
, devinfo
->urb
.max_vs_entries
);
904 nr_gs_entries
= MIN2(nr_gs_entries
, devinfo
->urb
.max_gs_entries
);
906 /* Ensure that we program a multiple of the granularity. */
907 nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, vs_granularity
);
908 nr_gs_entries
= ROUND_DOWN_TO(nr_gs_entries
, gs_granularity
);
910 /* Finally, sanity check to make sure we have at least the minimum number
911 * of entries needed for each stage.
913 assert(nr_vs_entries
>= devinfo
->urb
.min_vs_entries
);
915 assert(nr_gs_entries
>= 2);
917 /* Lay out the URB in the following order:
922 pipeline
->urb
.start
[MESA_SHADER_VERTEX
] = push_constant_chunks
;
923 pipeline
->urb
.size
[MESA_SHADER_VERTEX
] = vs_size
;
924 pipeline
->urb
.entries
[MESA_SHADER_VERTEX
] = nr_vs_entries
;
926 pipeline
->urb
.start
[MESA_SHADER_GEOMETRY
] = push_constant_chunks
+ vs_chunks
;
927 pipeline
->urb
.size
[MESA_SHADER_GEOMETRY
] = gs_size
;
928 pipeline
->urb
.entries
[MESA_SHADER_GEOMETRY
] = nr_gs_entries
;
930 pipeline
->urb
.start
[MESA_SHADER_TESS_CTRL
] = push_constant_chunks
;
931 pipeline
->urb
.size
[MESA_SHADER_TESS_CTRL
] = 1;
932 pipeline
->urb
.entries
[MESA_SHADER_TESS_CTRL
] = 0;
934 pipeline
->urb
.start
[MESA_SHADER_TESS_EVAL
] = push_constant_chunks
;
935 pipeline
->urb
.size
[MESA_SHADER_TESS_EVAL
] = 1;
936 pipeline
->urb
.entries
[MESA_SHADER_TESS_EVAL
] = 0;
940 * Copy pipeline state not marked as dynamic.
941 * Dynamic state is pipeline state which hasn't been provided at pipeline
942 * creation time, but is dynamically provided afterwards using various
943 * vkCmdSet* functions.
945 * The set of state considered "non_dynamic" is determined by the pieces of
946 * state that have their corresponding VkDynamicState enums omitted from
947 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
949 * @param[out] pipeline Destination non_dynamic state.
950 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
953 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
954 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
956 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
957 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
958 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
960 pipeline
->dynamic_state
= default_dynamic_state
;
962 if (pCreateInfo
->pDynamicState
) {
963 /* Remove all of the states that are marked as dynamic */
964 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
965 for (uint32_t s
= 0; s
< count
; s
++)
966 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
969 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
971 /* Section 9.2 of the Vulkan 1.0.15 spec says:
973 * pViewportState is [...] NULL if the pipeline
974 * has rasterization disabled.
976 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
977 assert(pCreateInfo
->pViewportState
);
979 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
980 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
981 typed_memcpy(dynamic
->viewport
.viewports
,
982 pCreateInfo
->pViewportState
->pViewports
,
983 pCreateInfo
->pViewportState
->viewportCount
);
986 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
987 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
988 typed_memcpy(dynamic
->scissor
.scissors
,
989 pCreateInfo
->pViewportState
->pScissors
,
990 pCreateInfo
->pViewportState
->scissorCount
);
994 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
995 assert(pCreateInfo
->pRasterizationState
);
996 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
999 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1000 assert(pCreateInfo
->pRasterizationState
);
1001 dynamic
->depth_bias
.bias
=
1002 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1003 dynamic
->depth_bias
.clamp
=
1004 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1005 dynamic
->depth_bias
.slope
=
1006 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1009 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1011 * pColorBlendState is [...] NULL if the pipeline has rasterization
1012 * disabled or if the subpass of the render pass the pipeline is
1013 * created against does not use any color attachments.
1015 bool uses_color_att
= false;
1016 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1017 if (subpass
->color_attachments
[i
] != VK_ATTACHMENT_UNUSED
) {
1018 uses_color_att
= true;
1023 if (uses_color_att
&&
1024 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1025 assert(pCreateInfo
->pColorBlendState
);
1027 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1028 typed_memcpy(dynamic
->blend_constants
,
1029 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1032 /* If there is no depthstencil attachment, then don't read
1033 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1034 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1035 * no need to override the depthstencil defaults in
1036 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1038 * Section 9.2 of the Vulkan 1.0.15 spec says:
1040 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1041 * disabled or if the subpass of the render pass the pipeline is created
1042 * against does not use a depth/stencil attachment.
1044 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1045 subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
1046 assert(pCreateInfo
->pDepthStencilState
);
1048 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1049 dynamic
->depth_bounds
.min
=
1050 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1051 dynamic
->depth_bounds
.max
=
1052 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1055 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1056 dynamic
->stencil_compare_mask
.front
=
1057 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1058 dynamic
->stencil_compare_mask
.back
=
1059 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1062 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1063 dynamic
->stencil_write_mask
.front
=
1064 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1065 dynamic
->stencil_write_mask
.back
=
1066 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1069 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1070 dynamic
->stencil_reference
.front
=
1071 pCreateInfo
->pDepthStencilState
->front
.reference
;
1072 dynamic
->stencil_reference
.back
=
1073 pCreateInfo
->pDepthStencilState
->back
.reference
;
1077 pipeline
->dynamic_state_mask
= states
;
1081 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1083 struct anv_render_pass
*renderpass
= NULL
;
1084 struct anv_subpass
*subpass
= NULL
;
1086 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1087 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1088 * 4.2 Graphics Pipeline.
1090 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1092 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1095 if (renderpass
!= &anv_meta_dummy_renderpass
) {
1096 assert(info
->subpass
< renderpass
->subpass_count
);
1097 subpass
= &renderpass
->subpasses
[info
->subpass
];
1100 assert(info
->stageCount
>= 1);
1101 assert(info
->pVertexInputState
);
1102 assert(info
->pInputAssemblyState
);
1103 assert(info
->pViewportState
);
1104 assert(info
->pRasterizationState
);
1106 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
1107 assert(info
->pDepthStencilState
);
1109 if (subpass
&& subpass
->color_count
> 0)
1110 assert(info
->pColorBlendState
);
1112 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1113 switch (info
->pStages
[i
].stage
) {
1114 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1115 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1116 assert(info
->pTessellationState
);
1125 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1126 struct anv_device
*device
,
1127 struct anv_pipeline_cache
*cache
,
1128 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1129 const struct anv_graphics_pipeline_create_info
*extra
,
1130 const VkAllocationCallbacks
*alloc
)
1135 anv_pipeline_validate_create_info(pCreateInfo
);
1139 alloc
= &device
->alloc
;
1141 pipeline
->device
= device
;
1142 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
1144 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1145 if (result
!= VK_SUCCESS
)
1148 pipeline
->batch
.alloc
= alloc
;
1149 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1150 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1151 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1153 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1154 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1155 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1157 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
1159 pipeline
->needs_data_cache
= false;
1161 /* When we free the pipeline, we detect stages based on the NULL status
1162 * of various prog_data pointers. Make them NULL by default.
1164 memset(pipeline
->prog_data
, 0, sizeof(pipeline
->prog_data
));
1165 memset(pipeline
->bindings
, 0, sizeof(pipeline
->bindings
));
1167 pipeline
->vs_simd8
= NO_KERNEL
;
1168 pipeline
->vs_vec4
= NO_KERNEL
;
1169 pipeline
->gs_kernel
= NO_KERNEL
;
1170 pipeline
->ps_ksp0
= NO_KERNEL
;
1172 pipeline
->active_stages
= 0;
1174 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
1175 struct anv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
1176 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1177 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
1178 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
1179 modules
[stage
] = anv_shader_module_from_handle(pStages
[stage
]->module
);
1182 if (modules
[MESA_SHADER_VERTEX
]) {
1183 anv_pipeline_compile_vs(pipeline
, cache
, pCreateInfo
,
1184 modules
[MESA_SHADER_VERTEX
],
1185 pStages
[MESA_SHADER_VERTEX
]->pName
,
1186 pStages
[MESA_SHADER_VERTEX
]->pSpecializationInfo
);
1189 if (modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
])
1190 anv_finishme("no tessellation support");
1192 if (modules
[MESA_SHADER_GEOMETRY
]) {
1193 anv_pipeline_compile_gs(pipeline
, cache
, pCreateInfo
,
1194 modules
[MESA_SHADER_GEOMETRY
],
1195 pStages
[MESA_SHADER_GEOMETRY
]->pName
,
1196 pStages
[MESA_SHADER_GEOMETRY
]->pSpecializationInfo
);
1199 if (modules
[MESA_SHADER_FRAGMENT
]) {
1200 anv_pipeline_compile_fs(pipeline
, cache
, pCreateInfo
, extra
,
1201 modules
[MESA_SHADER_FRAGMENT
],
1202 pStages
[MESA_SHADER_FRAGMENT
]->pName
,
1203 pStages
[MESA_SHADER_FRAGMENT
]->pSpecializationInfo
);
1206 if (!(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
)) {
1207 /* Vertex is only optional if disable_vs is set */
1208 assert(extra
->disable_vs
);
1211 anv_setup_pipeline_l3_config(pipeline
);
1212 anv_compute_urb_partition(pipeline
);
1214 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1215 pCreateInfo
->pVertexInputState
;
1217 uint64_t inputs_read
;
1218 if (extra
&& extra
->disable_vs
) {
1219 /* If the VS is disabled, just assume the user knows what they're
1220 * doing and apply the layout blindly. This can only come from
1221 * meta, so this *should* be safe.
1223 inputs_read
= ~0ull;
1225 inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1228 pipeline
->vb_used
= 0;
1229 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1230 const VkVertexInputAttributeDescription
*desc
=
1231 &vi_info
->pVertexAttributeDescriptions
[i
];
1233 if (inputs_read
& (1 << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1234 pipeline
->vb_used
|= 1 << desc
->binding
;
1237 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1238 const VkVertexInputBindingDescription
*desc
=
1239 &vi_info
->pVertexBindingDescriptions
[i
];
1241 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
1243 /* Step rate is programmed per vertex element (attribute), not
1244 * binding. Set up a map of which bindings step per instance, for
1245 * reference by vertex element setup. */
1246 switch (desc
->inputRate
) {
1248 case VK_VERTEX_INPUT_RATE_VERTEX
:
1249 pipeline
->instancing_enable
[desc
->binding
] = false;
1251 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1252 pipeline
->instancing_enable
[desc
->binding
] = true;
1257 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1258 pCreateInfo
->pInputAssemblyState
;
1259 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1260 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1262 if (extra
&& extra
->use_rectlist
)
1263 pipeline
->topology
= _3DPRIM_RECTLIST
;
1269 anv_graphics_pipeline_create(
1271 VkPipelineCache _cache
,
1272 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1273 const struct anv_graphics_pipeline_create_info
*extra
,
1274 const VkAllocationCallbacks
*pAllocator
,
1275 VkPipeline
*pPipeline
)
1277 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1278 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1281 cache
= &device
->default_pipeline_cache
;
1283 switch (device
->info
.gen
) {
1285 if (device
->info
.is_haswell
)
1286 return gen75_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1288 return gen7_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1290 return gen8_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1292 return gen9_graphics_pipeline_create(_device
, cache
, pCreateInfo
, extra
, pAllocator
, pPipeline
);
1294 unreachable("unsupported gen\n");
1298 VkResult
anv_CreateGraphicsPipelines(
1300 VkPipelineCache pipelineCache
,
1302 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1303 const VkAllocationCallbacks
* pAllocator
,
1304 VkPipeline
* pPipelines
)
1306 VkResult result
= VK_SUCCESS
;
1309 for (; i
< count
; i
++) {
1310 result
= anv_graphics_pipeline_create(_device
,
1313 NULL
, pAllocator
, &pPipelines
[i
]);
1314 if (result
!= VK_SUCCESS
) {
1315 for (unsigned j
= 0; j
< i
; j
++) {
1316 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);
1326 static VkResult
anv_compute_pipeline_create(
1328 VkPipelineCache _cache
,
1329 const VkComputePipelineCreateInfo
* pCreateInfo
,
1330 const VkAllocationCallbacks
* pAllocator
,
1331 VkPipeline
* pPipeline
)
1333 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1334 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
1337 cache
= &device
->default_pipeline_cache
;
1339 switch (device
->info
.gen
) {
1341 if (device
->info
.is_haswell
)
1342 return gen75_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1344 return gen7_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1346 return gen8_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1348 return gen9_compute_pipeline_create(_device
, cache
, pCreateInfo
, pAllocator
, pPipeline
);
1350 unreachable("unsupported gen\n");
1354 VkResult
anv_CreateComputePipelines(
1356 VkPipelineCache pipelineCache
,
1358 const VkComputePipelineCreateInfo
* pCreateInfos
,
1359 const VkAllocationCallbacks
* pAllocator
,
1360 VkPipeline
* pPipelines
)
1362 VkResult result
= VK_SUCCESS
;
1365 for (; i
< count
; i
++) {
1366 result
= anv_compute_pipeline_create(_device
, pipelineCache
,
1368 pAllocator
, &pPipelines
[i
]);
1369 if (result
!= VK_SUCCESS
) {
1370 for (unsigned j
= 0; j
< i
; j
++) {
1371 anv_DestroyPipeline(_device
, pPipelines
[j
], pAllocator
);