2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
99 * we can't do that yet because we don't have the ability to copy nir.
102 anv_shader_compile_to_nir(struct anv_device
*device
,
104 const struct anv_shader_module
*module
,
105 const char *entrypoint_name
,
106 gl_shader_stage stage
,
107 const VkSpecializationInfo
*spec_info
)
109 const struct anv_physical_device
*pdevice
=
110 &device
->instance
->physicalDevice
;
111 const struct brw_compiler
*compiler
= pdevice
->compiler
;
112 const nir_shader_compiler_options
*nir_options
=
113 compiler
->glsl_compiler_options
[stage
].NirOptions
;
115 uint32_t *spirv
= (uint32_t *) module
->data
;
116 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
117 assert(module
->size
% 4 == 0);
119 uint32_t num_spec_entries
= 0;
120 struct nir_spirv_specialization
*spec_entries
= NULL
;
121 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
122 num_spec_entries
= spec_info
->mapEntryCount
;
123 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
124 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
125 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
126 const void *data
= spec_info
->pData
+ entry
.offset
;
127 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
129 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
130 if (spec_info
->dataSize
== 8)
131 spec_entries
[i
].data64
= *(const uint64_t *)data
;
133 spec_entries
[i
].data32
= *(const uint32_t *)data
;
137 struct spirv_to_nir_options spirv_options
= {
138 .lower_workgroup_access_to_offsets
= true,
140 .derivative_group
= true,
141 .descriptor_array_dynamic_indexing
= true,
142 .descriptor_array_non_uniform_indexing
= true,
143 .descriptor_indexing
= true,
144 .device_group
= true,
145 .draw_parameters
= true,
146 .float16
= pdevice
->info
.gen
>= 8,
147 .float64
= pdevice
->info
.gen
>= 8,
148 .geometry_streams
= true,
149 .image_write_without_format
= true,
150 .int8
= pdevice
->info
.gen
>= 8,
151 .int16
= pdevice
->info
.gen
>= 8,
152 .int64
= pdevice
->info
.gen
>= 8,
153 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
156 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
157 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
158 .runtime_descriptor_array
= true,
159 .shader_viewport_index_layer
= true,
160 .stencil_export
= pdevice
->info
.gen
>= 9,
161 .storage_8bit
= pdevice
->info
.gen
>= 8,
162 .storage_16bit
= pdevice
->info
.gen
>= 8,
163 .subgroup_arithmetic
= true,
164 .subgroup_basic
= true,
165 .subgroup_ballot
= true,
166 .subgroup_quad
= true,
167 .subgroup_shuffle
= true,
168 .subgroup_vote
= true,
169 .tessellation
= true,
170 .transform_feedback
= pdevice
->info
.gen
>= 8,
171 .variable_pointers
= true,
173 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
175 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
176 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
177 .push_const_addr_format
= nir_address_format_logical
,
179 /* TODO: Consider changing this to an address format that has the NULL
180 * pointer equals to 0. That might be a better format to play nice
181 * with certain code / code generators.
183 .shared_addr_format
= nir_address_format_32bit_offset
,
188 spirv_to_nir(spirv
, module
->size
/ 4,
189 spec_entries
, num_spec_entries
,
190 stage
, entrypoint_name
, &spirv_options
, nir_options
);
191 assert(nir
->info
.stage
== stage
);
192 nir_validate_shader(nir
, "after spirv_to_nir");
193 ralloc_steal(mem_ctx
, nir
);
197 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
198 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
199 gl_shader_stage_name(stage
));
200 nir_print_shader(nir
, stderr
);
203 /* We have to lower away local constant initializers right before we
204 * inline functions. That way they get properly initialized at the top
205 * of the function and not at the top of its caller.
207 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
208 NIR_PASS_V(nir
, nir_lower_returns
);
209 NIR_PASS_V(nir
, nir_inline_functions
);
210 NIR_PASS_V(nir
, nir_opt_deref
);
212 /* Pick off the single entrypoint that we want */
213 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
214 if (!func
->is_entrypoint
)
215 exec_node_remove(&func
->node
);
217 assert(exec_list_length(&nir
->functions
) == 1);
219 /* Now that we've deleted all but the main function, we can go ahead and
220 * lower the rest of the constant initializers. We do this here so that
221 * nir_remove_dead_variables and split_per_member_structs below see the
222 * corresponding stores.
224 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
226 /* Split member structs. We do this before lower_io_to_temporaries so that
227 * it doesn't lower system values to temporaries by accident.
229 NIR_PASS_V(nir
, nir_split_var_copies
);
230 NIR_PASS_V(nir
, nir_split_per_member_structs
);
232 NIR_PASS_V(nir
, nir_remove_dead_variables
,
233 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
235 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
236 nir_address_format_64bit_global
);
238 NIR_PASS_V(nir
, nir_propagate_invariant
);
239 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
240 nir_shader_get_entrypoint(nir
), true, false);
242 NIR_PASS_V(nir
, nir_lower_frexp
);
244 /* Vulkan uses the separate-shader linking model */
245 nir
->info
.separate_shader
= true;
247 nir
= brw_preprocess_nir(compiler
, nir
, NULL
);
252 void anv_DestroyPipeline(
254 VkPipeline _pipeline
,
255 const VkAllocationCallbacks
* pAllocator
)
257 ANV_FROM_HANDLE(anv_device
, device
, _device
);
258 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
263 anv_reloc_list_finish(&pipeline
->batch_relocs
,
264 pAllocator
? pAllocator
: &device
->alloc
);
265 if (pipeline
->blend_state
.map
)
266 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
268 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
269 if (pipeline
->shaders
[s
])
270 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
273 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
276 static const uint32_t vk_to_gen_primitive_type
[] = {
277 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
278 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
279 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
280 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
281 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
282 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
283 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
284 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
285 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
286 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
290 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
291 struct brw_sampler_prog_key_data
*key
)
293 /* Almost all multisampled textures are compressed. The only time when we
294 * don't compress a multisampled texture is for 16x MSAA with a surface
295 * width greater than 8k which is a bit of an edge case. Since the sampler
296 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
297 * to tell the compiler to always assume compression.
299 key
->compressed_multisample_layout_mask
= ~0;
301 /* SkyLake added support for 16x MSAA. With this came a new message for
302 * reading from a 16x MSAA surface with compression. The new message was
303 * needed because now the MCS data is 64 bits instead of 32 or lower as is
304 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
305 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
306 * so we can just use it unconditionally. This may not be quite as
307 * efficient but it saves us from recompiling.
309 if (devinfo
->gen
>= 9)
312 /* XXX: Handle texture swizzle on HSW- */
313 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
314 /* Assume color sampler, no swizzling. (Works for BDW+) */
315 key
->swizzles
[i
] = SWIZZLE_XYZW
;
320 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
321 struct brw_vs_prog_key
*key
)
323 memset(key
, 0, sizeof(*key
));
325 populate_sampler_prog_key(devinfo
, &key
->tex
);
327 /* XXX: Handle vertex input work-arounds */
329 /* XXX: Handle sampler_prog_key */
333 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
334 unsigned input_vertices
,
335 struct brw_tcs_prog_key
*key
)
337 memset(key
, 0, sizeof(*key
));
339 populate_sampler_prog_key(devinfo
, &key
->tex
);
341 key
->input_vertices
= input_vertices
;
345 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
346 struct brw_tes_prog_key
*key
)
348 memset(key
, 0, sizeof(*key
));
350 populate_sampler_prog_key(devinfo
, &key
->tex
);
354 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
355 struct brw_gs_prog_key
*key
)
357 memset(key
, 0, sizeof(*key
));
359 populate_sampler_prog_key(devinfo
, &key
->tex
);
363 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
364 const struct anv_subpass
*subpass
,
365 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
366 struct brw_wm_prog_key
*key
)
368 memset(key
, 0, sizeof(*key
));
370 populate_sampler_prog_key(devinfo
, &key
->tex
);
372 /* We set this to 0 here and set to the actual value before we call
375 key
->input_slots_valid
= 0;
377 /* Vulkan doesn't specify a default */
378 key
->high_quality_derivatives
= false;
380 /* XXX Vulkan doesn't appear to specify */
381 key
->clamp_fragment_color
= false;
383 assert(subpass
->color_count
<= MAX_RTS
);
384 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
385 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
386 key
->color_outputs_valid
|= (1 << i
);
389 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
391 /* To reduce possible shader recompilations we would need to know if
392 * there is a SampleMask output variable to compute if we should emit
393 * code to workaround the issue that hardware disables alpha to coverage
394 * when there is SampleMask output.
396 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
398 /* Vulkan doesn't support fixed-function alpha test */
399 key
->alpha_test_replicate_alpha
= false;
402 /* We should probably pull this out of the shader, but it's fairly
403 * harmless to compute it and then let dead-code take care of it.
405 if (ms_info
->rasterizationSamples
> 1) {
406 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
407 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
408 key
->multisample_fbo
= true;
411 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
416 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
417 struct brw_cs_prog_key
*key
)
419 memset(key
, 0, sizeof(*key
));
421 populate_sampler_prog_key(devinfo
, &key
->tex
);
424 struct anv_pipeline_stage
{
425 gl_shader_stage stage
;
427 const struct anv_shader_module
*module
;
428 const char *entrypoint
;
429 const VkSpecializationInfo
*spec_info
;
431 unsigned char shader_sha1
[20];
433 union brw_any_prog_key key
;
436 gl_shader_stage stage
;
437 unsigned char sha1
[20];
442 struct anv_pipeline_binding surface_to_descriptor
[256];
443 struct anv_pipeline_binding sampler_to_descriptor
[256];
444 struct anv_pipeline_bind_map bind_map
;
446 union brw_any_prog_data prog_data
;
448 VkPipelineCreationFeedbackEXT feedback
;
452 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
453 const char *entrypoint
,
454 gl_shader_stage stage
,
455 const VkSpecializationInfo
*spec_info
,
456 unsigned char *sha1_out
)
458 struct mesa_sha1 ctx
;
459 _mesa_sha1_init(&ctx
);
461 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
462 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
463 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
465 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
466 spec_info
->mapEntryCount
*
467 sizeof(*spec_info
->pMapEntries
));
468 _mesa_sha1_update(&ctx
, spec_info
->pData
,
469 spec_info
->dataSize
);
472 _mesa_sha1_final(&ctx
, sha1_out
);
476 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
477 struct anv_pipeline_layout
*layout
,
478 struct anv_pipeline_stage
*stages
,
479 unsigned char *sha1_out
)
481 struct mesa_sha1 ctx
;
482 _mesa_sha1_init(&ctx
);
484 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
485 sizeof(pipeline
->subpass
->view_mask
));
488 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
490 const bool rba
= pipeline
->device
->robust_buffer_access
;
491 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
493 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
494 if (stages
[s
].entrypoint
) {
495 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
496 sizeof(stages
[s
].shader_sha1
));
497 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
501 _mesa_sha1_final(&ctx
, sha1_out
);
505 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
506 struct anv_pipeline_layout
*layout
,
507 struct anv_pipeline_stage
*stage
,
508 unsigned char *sha1_out
)
510 struct mesa_sha1 ctx
;
511 _mesa_sha1_init(&ctx
);
514 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
516 const bool rba
= pipeline
->device
->robust_buffer_access
;
517 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
519 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
520 sizeof(stage
->shader_sha1
));
521 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
523 _mesa_sha1_final(&ctx
, sha1_out
);
527 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
528 struct anv_pipeline_cache
*cache
,
530 struct anv_pipeline_stage
*stage
)
532 const struct brw_compiler
*compiler
=
533 pipeline
->device
->instance
->physicalDevice
.compiler
;
534 const nir_shader_compiler_options
*nir_options
=
535 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
538 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
543 assert(nir
->info
.stage
== stage
->stage
);
547 nir
= anv_shader_compile_to_nir(pipeline
->device
,
554 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
562 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
564 struct anv_pipeline_stage
*stage
,
565 struct anv_pipeline_layout
*layout
)
567 const struct anv_physical_device
*pdevice
=
568 &pipeline
->device
->instance
->physicalDevice
;
569 const struct brw_compiler
*compiler
= pdevice
->compiler
;
571 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
572 nir_shader
*nir
= stage
->nir
;
574 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
575 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
576 NIR_PASS_V(nir
, anv_nir_lower_input_attachments
);
579 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
581 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
583 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
584 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
586 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
587 prog_data
->total_shared
= nir
->num_shared
;
589 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
591 if (nir
->num_uniforms
> 0) {
592 assert(prog_data
->nr_params
== 0);
594 /* If the shader uses any push constants at all, we'll just give
595 * them the maximum possible number
597 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
598 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
599 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
600 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
602 /* We now set the param values to be offsets into a
603 * anv_push_constant_data structure. Since the compiler doesn't
604 * actually dereference any of the gl_constant_value pointers in the
605 * params array, it doesn't really matter what we put here.
607 struct anv_push_constants
*null_data
= NULL
;
608 /* Fill out the push constants section of the param array */
609 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
610 prog_data
->param
[i
] = ANV_PARAM_PUSH(
611 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
615 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
616 pipeline
->needs_data_cache
= true;
618 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
620 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
622 anv_nir_apply_pipeline_layout(pdevice
,
623 pipeline
->device
->robust_buffer_access
,
624 layout
, nir
, prog_data
,
627 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
628 nir_address_format_32bit_index_offset
);
629 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
630 anv_nir_ssbo_addr_format(pdevice
,
631 pipeline
->device
->robust_buffer_access
));
633 NIR_PASS_V(nir
, nir_opt_constant_folding
);
635 /* We don't support non-uniform UBOs and non-uniform SSBO access is
636 * handled naturally by falling back to A64 messages.
638 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
639 nir_lower_non_uniform_texture_access
|
640 nir_lower_non_uniform_image_access
);
643 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
644 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
646 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
652 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
653 struct anv_pipeline_stage
*vs_stage
,
654 struct anv_pipeline_stage
*next_stage
)
657 brw_nir_link_shaders(compiler
, &vs_stage
->nir
, &next_stage
->nir
);
660 static const unsigned *
661 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
663 struct anv_device
*device
,
664 struct anv_pipeline_stage
*vs_stage
)
666 brw_compute_vue_map(compiler
->devinfo
,
667 &vs_stage
->prog_data
.vs
.base
.vue_map
,
668 vs_stage
->nir
->info
.outputs_written
,
669 vs_stage
->nir
->info
.separate_shader
);
671 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
672 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
676 merge_tess_info(struct shader_info
*tes_info
,
677 const struct shader_info
*tcs_info
)
679 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
681 * "PointMode. Controls generation of points rather than triangles
682 * or lines. This functionality defaults to disabled, and is
683 * enabled if either shader stage includes the execution mode.
685 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
686 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
687 * and OutputVertices, it says:
689 * "One mode must be set in at least one of the tessellation
692 * So, the fields can be set in either the TCS or TES, but they must
693 * agree if set in both. Our backend looks at TES, so bitwise-or in
694 * the values from the TCS.
696 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
697 tes_info
->tess
.tcs_vertices_out
== 0 ||
698 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
699 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
701 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
702 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
703 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
704 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
706 assert(tcs_info
->tess
.primitive_mode
== 0 ||
707 tes_info
->tess
.primitive_mode
== 0 ||
708 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
709 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
710 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
711 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
715 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
716 struct anv_pipeline_stage
*tcs_stage
,
717 struct anv_pipeline_stage
*tes_stage
)
719 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
721 brw_nir_link_shaders(compiler
, &tcs_stage
->nir
, &tes_stage
->nir
);
723 nir_lower_patch_vertices(tes_stage
->nir
,
724 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
727 /* Copy TCS info into the TES info */
728 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
730 /* Whacking the key after cache lookup is a bit sketchy, but all of
731 * this comes from the SPIR-V, which is part of the hash used for the
732 * pipeline cache. So it should be safe.
734 tcs_stage
->key
.tcs
.tes_primitive_mode
=
735 tes_stage
->nir
->info
.tess
.primitive_mode
;
736 tcs_stage
->key
.tcs
.quads_workaround
=
737 compiler
->devinfo
->gen
< 9 &&
738 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
739 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
742 static const unsigned *
743 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
745 struct anv_device
*device
,
746 struct anv_pipeline_stage
*tcs_stage
,
747 struct anv_pipeline_stage
*prev_stage
)
749 tcs_stage
->key
.tcs
.outputs_written
=
750 tcs_stage
->nir
->info
.outputs_written
;
751 tcs_stage
->key
.tcs
.patch_outputs_written
=
752 tcs_stage
->nir
->info
.patch_outputs_written
;
754 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
755 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
760 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
761 struct anv_pipeline_stage
*tes_stage
,
762 struct anv_pipeline_stage
*next_stage
)
765 brw_nir_link_shaders(compiler
, &tes_stage
->nir
, &next_stage
->nir
);
768 static const unsigned *
769 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
771 struct anv_device
*device
,
772 struct anv_pipeline_stage
*tes_stage
,
773 struct anv_pipeline_stage
*tcs_stage
)
775 tes_stage
->key
.tes
.inputs_read
=
776 tcs_stage
->nir
->info
.outputs_written
;
777 tes_stage
->key
.tes
.patch_inputs_read
=
778 tcs_stage
->nir
->info
.patch_outputs_written
;
780 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
781 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
782 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
787 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
788 struct anv_pipeline_stage
*gs_stage
,
789 struct anv_pipeline_stage
*next_stage
)
792 brw_nir_link_shaders(compiler
, &gs_stage
->nir
, &next_stage
->nir
);
795 static const unsigned *
796 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
798 struct anv_device
*device
,
799 struct anv_pipeline_stage
*gs_stage
,
800 struct anv_pipeline_stage
*prev_stage
)
802 brw_compute_vue_map(compiler
->devinfo
,
803 &gs_stage
->prog_data
.gs
.base
.vue_map
,
804 gs_stage
->nir
->info
.outputs_written
,
805 gs_stage
->nir
->info
.separate_shader
);
807 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
808 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
813 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
814 struct anv_pipeline_stage
*stage
)
816 unsigned num_rts
= 0;
817 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
818 struct anv_pipeline_binding rt_bindings
[max_rt
];
819 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
820 int rt_to_bindings
[max_rt
];
821 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
822 bool rt_used
[max_rt
];
823 memset(rt_used
, 0, sizeof(rt_used
));
825 /* Flag used render targets */
826 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
827 if (var
->data
.location
< FRAG_RESULT_DATA0
)
830 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
835 const unsigned array_len
=
836 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
837 assert(rt
+ array_len
<= max_rt
);
840 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
841 /* If this is the RT at location 0 and we have alpha to coverage
842 * enabled we will have to create a null RT for it, so mark it as
845 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
849 for (unsigned i
= 0; i
< array_len
; i
++)
850 rt_used
[rt
+ i
] = true;
853 /* Set new, compacted, location */
854 for (unsigned i
= 0; i
< max_rt
; i
++) {
858 rt_to_bindings
[i
] = num_rts
;
860 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
861 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
862 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
867 /* Setup a null render target */
868 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
869 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
878 bool deleted_output
= false;
879 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
880 if (var
->data
.location
< FRAG_RESULT_DATA0
)
883 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
885 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
886 /* Unused or out-of-bounds, throw it away, unless it is the first
887 * RT and we have alpha to coverage enabled.
889 deleted_output
= true;
890 var
->data
.mode
= nir_var_function_temp
;
891 exec_node_remove(&var
->node
);
892 exec_list_push_tail(&impl
->locals
, &var
->node
);
896 /* Give it the new location */
897 assert(rt_to_bindings
[rt
] != -1);
898 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
902 nir_fixup_deref_modes(stage
->nir
);
905 /* If we have no render targets, we need a null render target */
906 rt_bindings
[0] = (struct anv_pipeline_binding
) {
907 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
914 /* Now that we've determined the actual number of render targets, adjust
915 * the key accordingly.
917 stage
->key
.wm
.nr_color_regions
= num_rts
;
918 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
920 assert(num_rts
<= max_rt
);
921 assert(stage
->bind_map
.surface_count
== 0);
922 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
923 rt_bindings
, num_rts
);
924 stage
->bind_map
.surface_count
+= num_rts
;
927 static const unsigned *
928 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
930 struct anv_device
*device
,
931 struct anv_pipeline_stage
*fs_stage
,
932 struct anv_pipeline_stage
*prev_stage
)
934 /* TODO: we could set this to 0 based on the information in nir_shader, but
935 * we need this before we call spirv_to_nir.
938 fs_stage
->key
.wm
.input_slots_valid
=
939 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
941 const unsigned *code
=
942 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
943 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
944 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
946 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
947 !fs_stage
->prog_data
.wm
.has_side_effects
&&
948 !fs_stage
->prog_data
.wm
.uses_kill
&&
949 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
950 !fs_stage
->prog_data
.wm
.computed_stencil
) {
951 /* This fragment shader has no outputs and no side effects. Go ahead
952 * and return the code pointer so we don't accidentally think the
953 * compile failed but zero out prog_data which will set program_size to
954 * zero and disable the stage.
956 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
963 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
964 struct anv_pipeline_cache
*cache
,
965 const VkGraphicsPipelineCreateInfo
*info
)
967 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
968 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
970 int64_t pipeline_start
= os_time_get_nano();
972 const struct brw_compiler
*compiler
=
973 pipeline
->device
->instance
->physicalDevice
.compiler
;
974 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
976 pipeline
->active_stages
= 0;
979 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
980 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
981 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
983 pipeline
->active_stages
|= sinfo
->stage
;
985 int64_t stage_start
= os_time_get_nano();
987 stages
[stage
].stage
= stage
;
988 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
989 stages
[stage
].entrypoint
= sinfo
->pName
;
990 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
991 anv_pipeline_hash_shader(stages
[stage
].module
,
992 stages
[stage
].entrypoint
,
994 stages
[stage
].spec_info
,
995 stages
[stage
].shader_sha1
);
997 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
999 case MESA_SHADER_VERTEX
:
1000 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
1002 case MESA_SHADER_TESS_CTRL
:
1003 populate_tcs_prog_key(devinfo
,
1004 info
->pTessellationState
->patchControlPoints
,
1005 &stages
[stage
].key
.tcs
);
1007 case MESA_SHADER_TESS_EVAL
:
1008 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
1010 case MESA_SHADER_GEOMETRY
:
1011 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
1013 case MESA_SHADER_FRAGMENT
:
1014 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
1015 info
->pMultisampleState
,
1016 &stages
[stage
].key
.wm
);
1019 unreachable("Invalid graphics shader stage");
1022 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1023 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1026 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1027 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1029 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1031 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1033 unsigned char sha1
[20];
1034 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1037 unsigned cache_hits
= 0;
1038 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1039 if (!stages
[s
].entrypoint
)
1042 int64_t stage_start
= os_time_get_nano();
1044 stages
[s
].cache_key
.stage
= s
;
1045 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1048 struct anv_shader_bin
*bin
=
1049 anv_device_search_for_kernel(pipeline
->device
, cache
,
1050 &stages
[s
].cache_key
,
1051 sizeof(stages
[s
].cache_key
), &cache_hit
);
1054 pipeline
->shaders
[s
] = bin
;
1059 stages
[s
].feedback
.flags
|=
1060 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1062 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1065 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1066 if (cache_hits
== found
) {
1067 pipeline_feedback
.flags
|=
1068 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1070 /* We found all our shaders in the cache. We're done. */
1072 } else if (found
> 0) {
1073 /* We found some but not all of our shaders. This shouldn't happen
1074 * most of the time but it can if we have a partially populated
1077 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1079 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1080 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1081 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1082 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1083 (uint64_t)(uintptr_t)cache
,
1085 "Found a partial pipeline in the cache. This is "
1086 "most likely caused by an incomplete pipeline cache "
1087 "import or export");
1089 /* We're going to have to recompile anyway, so just throw away our
1090 * references to the shaders in the cache. We'll get them out of the
1091 * cache again as part of the compilation process.
1093 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1094 stages
[s
].feedback
.flags
= 0;
1095 if (pipeline
->shaders
[s
]) {
1096 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1097 pipeline
->shaders
[s
] = NULL
;
1102 void *pipeline_ctx
= ralloc_context(NULL
);
1104 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1105 if (!stages
[s
].entrypoint
)
1108 int64_t stage_start
= os_time_get_nano();
1110 assert(stages
[s
].stage
== s
);
1111 assert(pipeline
->shaders
[s
] == NULL
);
1113 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1114 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1115 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1118 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1121 if (stages
[s
].nir
== NULL
) {
1122 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1126 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1129 /* Walk backwards to link */
1130 struct anv_pipeline_stage
*next_stage
= NULL
;
1131 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1132 if (!stages
[s
].entrypoint
)
1136 case MESA_SHADER_VERTEX
:
1137 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1139 case MESA_SHADER_TESS_CTRL
:
1140 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1142 case MESA_SHADER_TESS_EVAL
:
1143 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1145 case MESA_SHADER_GEOMETRY
:
1146 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1148 case MESA_SHADER_FRAGMENT
:
1149 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1152 unreachable("Invalid graphics shader stage");
1155 next_stage
= &stages
[s
];
1158 struct anv_pipeline_stage
*prev_stage
= NULL
;
1159 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1160 if (!stages
[s
].entrypoint
)
1163 int64_t stage_start
= os_time_get_nano();
1165 void *stage_ctx
= ralloc_context(NULL
);
1167 nir_xfb_info
*xfb_info
= NULL
;
1168 if (s
== MESA_SHADER_VERTEX
||
1169 s
== MESA_SHADER_TESS_EVAL
||
1170 s
== MESA_SHADER_GEOMETRY
)
1171 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1173 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1175 const unsigned *code
;
1177 case MESA_SHADER_VERTEX
:
1178 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1181 case MESA_SHADER_TESS_CTRL
:
1182 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1183 &stages
[s
], prev_stage
);
1185 case MESA_SHADER_TESS_EVAL
:
1186 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1187 &stages
[s
], prev_stage
);
1189 case MESA_SHADER_GEOMETRY
:
1190 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1191 &stages
[s
], prev_stage
);
1193 case MESA_SHADER_FRAGMENT
:
1194 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1195 &stages
[s
], prev_stage
);
1198 unreachable("Invalid graphics shader stage");
1201 ralloc_free(stage_ctx
);
1202 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1206 struct anv_shader_bin
*bin
=
1207 anv_device_upload_kernel(pipeline
->device
, cache
,
1208 &stages
[s
].cache_key
,
1209 sizeof(stages
[s
].cache_key
),
1210 code
, stages
[s
].prog_data
.base
.program_size
,
1211 stages
[s
].nir
->constant_data
,
1212 stages
[s
].nir
->constant_data_size
,
1213 &stages
[s
].prog_data
.base
,
1214 brw_prog_data_size(s
),
1215 xfb_info
, &stages
[s
].bind_map
);
1217 ralloc_free(stage_ctx
);
1218 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1222 pipeline
->shaders
[s
] = bin
;
1223 ralloc_free(stage_ctx
);
1225 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1227 prev_stage
= &stages
[s
];
1230 ralloc_free(pipeline_ctx
);
1234 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1235 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1236 /* This can happen if we decided to implicitly disable the fragment
1237 * shader. See anv_pipeline_compile_fs().
1239 anv_shader_bin_unref(pipeline
->device
,
1240 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1241 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1242 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1245 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1247 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1248 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1249 if (create_feedback
) {
1250 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1252 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1253 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1254 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1255 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1262 ralloc_free(pipeline_ctx
);
1264 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1265 if (pipeline
->shaders
[s
])
1266 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1273 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1274 struct anv_pipeline_cache
*cache
,
1275 const VkComputePipelineCreateInfo
*info
,
1276 const struct anv_shader_module
*module
,
1277 const char *entrypoint
,
1278 const VkSpecializationInfo
*spec_info
)
1280 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1281 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1283 int64_t pipeline_start
= os_time_get_nano();
1285 const struct brw_compiler
*compiler
=
1286 pipeline
->device
->instance
->physicalDevice
.compiler
;
1288 struct anv_pipeline_stage stage
= {
1289 .stage
= MESA_SHADER_COMPUTE
,
1291 .entrypoint
= entrypoint
,
1292 .spec_info
= spec_info
,
1294 .stage
= MESA_SHADER_COMPUTE
,
1297 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1300 anv_pipeline_hash_shader(stage
.module
,
1302 MESA_SHADER_COMPUTE
,
1306 struct anv_shader_bin
*bin
= NULL
;
1308 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1310 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1312 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1314 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1315 sizeof(stage
.cache_key
), &cache_hit
);
1318 int64_t stage_start
= os_time_get_nano();
1320 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1321 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1322 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1325 /* Set up a binding for the gl_NumWorkGroups */
1326 stage
.bind_map
.surface_count
= 1;
1327 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1328 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1331 void *mem_ctx
= ralloc_context(NULL
);
1333 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1334 if (stage
.nir
== NULL
) {
1335 ralloc_free(mem_ctx
);
1336 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1339 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1341 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1342 &stage
.prog_data
.cs
);
1344 const unsigned *shader_code
=
1345 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1346 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1347 if (shader_code
== NULL
) {
1348 ralloc_free(mem_ctx
);
1349 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1352 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1353 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1354 &stage
.cache_key
, sizeof(stage
.cache_key
),
1355 shader_code
, code_size
,
1356 stage
.nir
->constant_data
,
1357 stage
.nir
->constant_data_size
,
1358 &stage
.prog_data
.base
,
1359 sizeof(stage
.prog_data
.cs
),
1360 NULL
, &stage
.bind_map
);
1362 ralloc_free(mem_ctx
);
1363 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1366 ralloc_free(mem_ctx
);
1368 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1372 stage
.feedback
.flags
|=
1373 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1374 pipeline_feedback
.flags
|=
1375 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1377 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1379 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1380 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1381 if (create_feedback
) {
1382 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1384 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1385 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1388 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1389 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1395 * Copy pipeline state not marked as dynamic.
1396 * Dynamic state is pipeline state which hasn't been provided at pipeline
1397 * creation time, but is dynamically provided afterwards using various
1398 * vkCmdSet* functions.
1400 * The set of state considered "non_dynamic" is determined by the pieces of
1401 * state that have their corresponding VkDynamicState enums omitted from
1402 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1404 * @param[out] pipeline Destination non_dynamic state.
1405 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1408 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1409 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1411 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1412 struct anv_subpass
*subpass
= pipeline
->subpass
;
1414 pipeline
->dynamic_state
= default_dynamic_state
;
1416 if (pCreateInfo
->pDynamicState
) {
1417 /* Remove all of the states that are marked as dynamic */
1418 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1419 for (uint32_t s
= 0; s
< count
; s
++)
1420 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1423 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1425 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1427 * pViewportState is [...] NULL if the pipeline
1428 * has rasterization disabled.
1430 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1431 assert(pCreateInfo
->pViewportState
);
1433 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1434 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1435 typed_memcpy(dynamic
->viewport
.viewports
,
1436 pCreateInfo
->pViewportState
->pViewports
,
1437 pCreateInfo
->pViewportState
->viewportCount
);
1440 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1441 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1442 typed_memcpy(dynamic
->scissor
.scissors
,
1443 pCreateInfo
->pViewportState
->pScissors
,
1444 pCreateInfo
->pViewportState
->scissorCount
);
1448 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1449 assert(pCreateInfo
->pRasterizationState
);
1450 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1453 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1454 assert(pCreateInfo
->pRasterizationState
);
1455 dynamic
->depth_bias
.bias
=
1456 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1457 dynamic
->depth_bias
.clamp
=
1458 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1459 dynamic
->depth_bias
.slope
=
1460 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1463 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1465 * pColorBlendState is [...] NULL if the pipeline has rasterization
1466 * disabled or if the subpass of the render pass the pipeline is
1467 * created against does not use any color attachments.
1469 bool uses_color_att
= false;
1470 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1471 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1472 uses_color_att
= true;
1477 if (uses_color_att
&&
1478 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1479 assert(pCreateInfo
->pColorBlendState
);
1481 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1482 typed_memcpy(dynamic
->blend_constants
,
1483 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1486 /* If there is no depthstencil attachment, then don't read
1487 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1488 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1489 * no need to override the depthstencil defaults in
1490 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1492 * Section 9.2 of the Vulkan 1.0.15 spec says:
1494 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1495 * disabled or if the subpass of the render pass the pipeline is created
1496 * against does not use a depth/stencil attachment.
1498 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1499 subpass
->depth_stencil_attachment
) {
1500 assert(pCreateInfo
->pDepthStencilState
);
1502 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1503 dynamic
->depth_bounds
.min
=
1504 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1505 dynamic
->depth_bounds
.max
=
1506 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1509 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1510 dynamic
->stencil_compare_mask
.front
=
1511 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1512 dynamic
->stencil_compare_mask
.back
=
1513 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1516 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1517 dynamic
->stencil_write_mask
.front
=
1518 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1519 dynamic
->stencil_write_mask
.back
=
1520 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1523 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1524 dynamic
->stencil_reference
.front
=
1525 pCreateInfo
->pDepthStencilState
->front
.reference
;
1526 dynamic
->stencil_reference
.back
=
1527 pCreateInfo
->pDepthStencilState
->back
.reference
;
1531 pipeline
->dynamic_state_mask
= states
;
1535 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1538 struct anv_render_pass
*renderpass
= NULL
;
1539 struct anv_subpass
*subpass
= NULL
;
1541 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1542 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1544 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1546 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1549 assert(info
->subpass
< renderpass
->subpass_count
);
1550 subpass
= &renderpass
->subpasses
[info
->subpass
];
1552 assert(info
->stageCount
>= 1);
1553 assert(info
->pVertexInputState
);
1554 assert(info
->pInputAssemblyState
);
1555 assert(info
->pRasterizationState
);
1556 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1557 assert(info
->pViewportState
);
1558 assert(info
->pMultisampleState
);
1560 if (subpass
&& subpass
->depth_stencil_attachment
)
1561 assert(info
->pDepthStencilState
);
1563 if (subpass
&& subpass
->color_count
> 0) {
1564 bool all_color_unused
= true;
1565 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1566 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1567 all_color_unused
= false;
1569 /* pColorBlendState is ignored if the pipeline has rasterization
1570 * disabled or if the subpass of the render pass the pipeline is
1571 * created against does not use any color attachments.
1573 assert(info
->pColorBlendState
|| all_color_unused
);
1577 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1578 switch (info
->pStages
[i
].stage
) {
1579 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1580 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1581 assert(info
->pTessellationState
);
1591 * Calculate the desired L3 partitioning based on the current state of the
1592 * pipeline. For now this simply returns the conservative defaults calculated
1593 * by get_default_l3_weights(), but we could probably do better by gathering
1594 * more statistics from the pipeline state (e.g. guess of expected URB usage
1595 * and bound surfaces), or by using feed-back from performance counters.
1598 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1600 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1602 const struct gen_l3_weights w
=
1603 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1605 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1606 pipeline
->urb
.total_size
=
1607 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1611 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1612 struct anv_device
*device
,
1613 struct anv_pipeline_cache
*cache
,
1614 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1615 const VkAllocationCallbacks
*alloc
)
1619 anv_pipeline_validate_create_info(pCreateInfo
);
1622 alloc
= &device
->alloc
;
1624 pipeline
->device
= device
;
1626 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1627 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1628 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1630 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1631 if (result
!= VK_SUCCESS
)
1634 pipeline
->batch
.alloc
= alloc
;
1635 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1636 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1637 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1638 pipeline
->batch
.status
= VK_SUCCESS
;
1640 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1641 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1642 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1644 /* Previously we enabled depth clipping when !depthClampEnable.
1645 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1646 * clipping info is available, use its enable value to determine clipping,
1647 * otherwise fallback to the previous !depthClampEnable logic.
1649 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1650 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1651 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1652 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1654 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1655 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1657 pipeline
->needs_data_cache
= false;
1659 /* When we free the pipeline, we detect stages based on the NULL status
1660 * of various prog_data pointers. Make them NULL by default.
1662 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1664 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1665 if (result
!= VK_SUCCESS
) {
1666 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1670 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1672 anv_pipeline_setup_l3_config(pipeline
, false);
1674 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1675 pCreateInfo
->pVertexInputState
;
1677 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1679 pipeline
->vb_used
= 0;
1680 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1681 const VkVertexInputAttributeDescription
*desc
=
1682 &vi_info
->pVertexAttributeDescriptions
[i
];
1684 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1685 pipeline
->vb_used
|= 1 << desc
->binding
;
1688 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1689 const VkVertexInputBindingDescription
*desc
=
1690 &vi_info
->pVertexBindingDescriptions
[i
];
1692 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1694 /* Step rate is programmed per vertex element (attribute), not
1695 * binding. Set up a map of which bindings step per instance, for
1696 * reference by vertex element setup. */
1697 switch (desc
->inputRate
) {
1699 case VK_VERTEX_INPUT_RATE_VERTEX
:
1700 pipeline
->vb
[desc
->binding
].instanced
= false;
1702 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1703 pipeline
->vb
[desc
->binding
].instanced
= true;
1707 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1710 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1711 vk_find_struct_const(vi_info
->pNext
,
1712 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1714 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1715 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1716 &vi_div_state
->pVertexBindingDivisors
[i
];
1718 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1722 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1723 * different views. If the client asks for instancing, we need to multiply
1724 * the instance divisor by the number of views ensure that we repeat the
1725 * client's per-instance data once for each view.
1727 if (pipeline
->subpass
->view_mask
) {
1728 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1729 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1730 if (pipeline
->vb
[vb
].instanced
)
1731 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1735 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1736 pCreateInfo
->pInputAssemblyState
;
1737 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1738 pCreateInfo
->pTessellationState
;
1739 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1741 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1742 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1744 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];