2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/bitset.h"
53 #include "util/macros.h"
54 #include "util/hash_table.h"
55 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
74 struct anv_buffer_view
;
75 struct anv_image_view
;
78 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
132 #define LOW_HEAP_SIZE \
133 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
134 #define DYNAMIC_STATE_POOL_SIZE \
135 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
136 #define BINDING_TABLE_POOL_SIZE \
137 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
138 #define SURFACE_STATE_POOL_SIZE \
139 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
140 #define INSTRUCTION_STATE_POOL_SIZE \
141 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
143 /* Allowing different clear colors requires us to perform a depth resolve at
144 * the end of certain render passes. This is because while slow clears store
145 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
146 * See the PRMs for examples describing when additional resolves would be
147 * necessary. To enable fast clears without requiring extra resolves, we set
148 * the clear value to a globally-defined one. We could allow different values
149 * if the user doesn't expect coherent data during or after a render passes
150 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
151 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
152 * 1.0f seems to be the only value used. The only application that doesn't set
153 * this value does so through the usage of an seemingly uninitialized clear
156 #define ANV_HZ_FC_VAL 1.0f
159 #define MAX_XFB_BUFFERS 4
160 #define MAX_XFB_STREAMS 4
163 #define MAX_VIEWPORTS 16
164 #define MAX_SCISSORS 16
165 #define MAX_PUSH_CONSTANTS_SIZE 128
166 #define MAX_DYNAMIC_BUFFERS 16
167 #define MAX_IMAGES 64
168 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
169 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
170 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
172 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
174 * "The surface state model is used when a Binding Table Index (specified
175 * in the message descriptor) of less than 240 is specified. In this model,
176 * the Binding Table Index is used to index into the binding table, and the
177 * binding table entry contains a pointer to the SURFACE_STATE."
179 * Binding table values above 240 are used for various things in the hardware
180 * such as stateless, stateless with incoherent cache, SLM, and bindless.
182 #define MAX_BINDING_TABLE_SIZE 240
184 /* The kernel relocation API has a limitation of a 32-bit delta value
185 * applied to the address before it is written which, in spite of it being
186 * unsigned, is treated as signed . Because of the way that this maps to
187 * the Vulkan API, we cannot handle an offset into a buffer that does not
188 * fit into a signed 32 bits. The only mechanism we have for dealing with
189 * this at the moment is to limit all VkDeviceMemory objects to a maximum
190 * of 2GB each. The Vulkan spec allows us to do this:
192 * "Some platforms may have a limit on the maximum size of a single
193 * allocation. For example, certain systems may fail to create
194 * allocations with a size greater than or equal to 4GB. Such a limit is
195 * implementation-dependent, and if such a failure occurs then the error
196 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
198 * We don't use vk_error here because it's not an error so much as an
199 * indication to the application that the allocation is too large.
201 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
203 #define ANV_SVGS_VB_INDEX MAX_VBS
204 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
206 /* We reserve this MI ALU register for the purpose of handling predication.
207 * Other code which uses the MI ALU should leave it alone.
209 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
211 /* For gen12 we set the streamout buffers using 4 separate commands
212 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
213 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
214 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
215 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
216 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
217 * 3DSTATE_SO_BUFFER_INDEX_0.
219 #define SO_BUFFER_INDEX_0_CMD 0x60
220 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
222 static inline uint32_t
223 align_down_npot_u32(uint32_t v
, uint32_t a
)
228 static inline uint32_t
229 align_u32(uint32_t v
, uint32_t a
)
231 assert(a
!= 0 && a
== (a
& -a
));
232 return (v
+ a
- 1) & ~(a
- 1);
235 static inline uint64_t
236 align_u64(uint64_t v
, uint64_t a
)
238 assert(a
!= 0 && a
== (a
& -a
));
239 return (v
+ a
- 1) & ~(a
- 1);
242 static inline int32_t
243 align_i32(int32_t v
, int32_t a
)
245 assert(a
!= 0 && a
== (a
& -a
));
246 return (v
+ a
- 1) & ~(a
- 1);
249 /** Alignment must be a power of 2. */
251 anv_is_aligned(uintmax_t n
, uintmax_t a
)
253 assert(a
== (a
& -a
));
254 return (n
& (a
- 1)) == 0;
257 static inline uint32_t
258 anv_minify(uint32_t n
, uint32_t levels
)
260 if (unlikely(n
== 0))
263 return MAX2(n
>> levels
, 1);
267 anv_clamp_f(float f
, float min
, float max
)
280 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
282 if (*inout_mask
& clear_mask
) {
283 *inout_mask
&= ~clear_mask
;
290 static inline union isl_color_value
291 vk_to_isl_color(VkClearColorValue color
)
293 return (union isl_color_value
) {
303 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
305 uintptr_t mask
= (1ull << bits
) - 1;
307 return (void *) (ptr
& ~mask
);
310 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
312 uintptr_t value
= (uintptr_t) ptr
;
313 uintptr_t mask
= (1ull << bits
) - 1;
314 return value
| (mask
& flags
);
317 #define for_each_bit(b, dword) \
318 for (uint32_t __dword = (dword); \
319 (b) = __builtin_ffs(__dword) - 1, __dword; \
320 __dword &= ~(1 << (b)))
322 #define typed_memcpy(dest, src, count) ({ \
323 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
324 memcpy((dest), (src), (count) * sizeof(*(src))); \
327 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
328 * to be added here in order to utilize mapping in debug/error/perf macros.
330 #define REPORT_OBJECT_TYPE(o) \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
376 __builtin_choose_expr ( \
377 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
378 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
379 __builtin_choose_expr ( \
380 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
381 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
382 __builtin_choose_expr ( \
383 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
384 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
385 __builtin_choose_expr ( \
386 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
387 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
388 __builtin_choose_expr ( \
389 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
390 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
391 __builtin_choose_expr ( \
392 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
393 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
394 __builtin_choose_expr ( \
395 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
396 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
397 __builtin_choose_expr ( \
398 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
399 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
400 __builtin_choose_expr ( \
401 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
402 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
403 __builtin_choose_expr ( \
404 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
405 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
406 __builtin_choose_expr ( \
407 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
408 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
409 __builtin_choose_expr ( \
410 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
411 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
412 __builtin_choose_expr ( \
413 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
414 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
415 __builtin_choose_expr ( \
416 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
417 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
418 __builtin_choose_expr ( \
419 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
420 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
421 __builtin_choose_expr ( \
422 __builtin_types_compatible_p (__typeof (o), void*), \
423 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
424 /* The void expression results in a compile-time error \
425 when assigning the result to something. */ \
426 (void)0)))))))))))))))))))))))))))))))
428 /* Whenever we generate an error, pass it through this function. Useful for
429 * debugging, where we can break on it. Only call at error site, not when
430 * propagating errors. Might be useful to plug in a stack trace here.
433 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
434 VkDebugReportObjectTypeEXT type
, VkResult error
,
435 const char *file
, int line
, const char *format
,
438 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
439 VkDebugReportObjectTypeEXT type
, VkResult error
,
440 const char *file
, int line
, const char *format
, ...)
441 anv_printflike(7, 8);
444 #define vk_error(error) __vk_errorf(NULL, NULL,\
445 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
446 error, __FILE__, __LINE__, NULL)
447 #define vk_errorv(instance, obj, error, format, args)\
448 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
449 __FILE__, __LINE__, format, args)
450 #define vk_errorf(instance, obj, error, format, ...)\
451 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
452 __FILE__, __LINE__, format, ## __VA_ARGS__)
454 #define vk_error(error) error
455 #define vk_errorf(instance, obj, error, format, ...) error
459 * Warn on ignored extension structs.
461 * The Vulkan spec requires us to ignore unsupported or unknown structs in
462 * a pNext chain. In debug mode, emitting warnings for ignored structs may
463 * help us discover structs that we should not have ignored.
466 * From the Vulkan 1.0.38 spec:
468 * Any component of the implementation (the loader, any enabled layers,
469 * and drivers) must skip over, without processing (other than reading the
470 * sType and pNext members) any chained structures with sType values not
471 * defined by extensions supported by that component.
473 #define anv_debug_ignored_stype(sType) \
474 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
476 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
477 VkDebugReportObjectTypeEXT type
, const char *file
,
478 int line
, const char *format
, ...)
479 anv_printflike(6, 7);
480 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
481 void anv_loge_v(const char *format
, va_list va
);
484 * Print a FINISHME message, including its source location.
486 #define anv_finishme(format, ...) \
488 static bool reported = false; \
490 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
497 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
499 #define anv_perf_warn(instance, obj, format, ...) \
501 static bool reported = false; \
502 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
503 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
504 format, ##__VA_ARGS__); \
509 /* A non-fatal assert. Useful for debugging. */
511 #define anv_assert(x) ({ \
512 if (unlikely(!(x))) \
513 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
516 #define anv_assert(x)
519 /* A multi-pointer allocator
521 * When copying data structures from the user (such as a render pass), it's
522 * common to need to allocate data for a bunch of different things. Instead
523 * of doing several allocations and having to handle all of the error checking
524 * that entails, it can be easier to do a single allocation. This struct
525 * helps facilitate that. The intended usage looks like this:
528 * anv_multialloc_add(&ma, &main_ptr, 1);
529 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
530 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
532 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
533 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
535 struct anv_multialloc
{
543 #define ANV_MULTIALLOC_INIT \
544 ((struct anv_multialloc) { 0, })
546 #define ANV_MULTIALLOC(_name) \
547 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
549 __attribute__((always_inline
))
551 _anv_multialloc_add(struct anv_multialloc
*ma
,
552 void **ptr
, size_t size
, size_t align
)
554 size_t offset
= align_u64(ma
->size
, align
);
555 ma
->size
= offset
+ size
;
556 ma
->align
= MAX2(ma
->align
, align
);
558 /* Store the offset in the pointer. */
559 *ptr
= (void *)(uintptr_t)offset
;
561 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
562 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
565 #define anv_multialloc_add_size(_ma, _ptr, _size) \
566 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
568 #define anv_multialloc_add(_ma, _ptr, _count) \
569 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
571 __attribute__((always_inline
))
573 anv_multialloc_alloc(struct anv_multialloc
*ma
,
574 const VkAllocationCallbacks
*alloc
,
575 VkSystemAllocationScope scope
)
577 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
581 /* Fill out each of the pointers with their final value.
583 * for (uint32_t i = 0; i < ma->ptr_count; i++)
584 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
586 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
587 * constant, GCC is incapable of figuring this out and unrolling the loop
588 * so we have to give it a little help.
590 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
591 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
592 if ((_i) < ma->ptr_count) \
593 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
594 _ANV_MULTIALLOC_UPDATE_POINTER(0);
595 _ANV_MULTIALLOC_UPDATE_POINTER(1);
596 _ANV_MULTIALLOC_UPDATE_POINTER(2);
597 _ANV_MULTIALLOC_UPDATE_POINTER(3);
598 _ANV_MULTIALLOC_UPDATE_POINTER(4);
599 _ANV_MULTIALLOC_UPDATE_POINTER(5);
600 _ANV_MULTIALLOC_UPDATE_POINTER(6);
601 _ANV_MULTIALLOC_UPDATE_POINTER(7);
602 #undef _ANV_MULTIALLOC_UPDATE_POINTER
607 __attribute__((always_inline
))
609 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
610 const VkAllocationCallbacks
*parent_alloc
,
611 const VkAllocationCallbacks
*alloc
,
612 VkSystemAllocationScope scope
)
614 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
622 /* Index into the current validation list. This is used by the
623 * validation list building alrogithm to track which buffers are already
624 * in the validation list so that we can ensure uniqueness.
628 /* Index for use with util_sparse_array_free_list */
631 /* Last known offset. This value is provided by the kernel when we
632 * execbuf and is used as the presumed offset for the next bunch of
639 /* Map for internally mapped BOs.
641 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
645 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
648 /** True if this BO may be shared with other processes */
651 /** True if this BO is a wrapper
653 * When set to true, none of the fields in this BO are meaningful except
654 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
655 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
656 * is set in the physical device.
660 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
661 bool has_fixed_address
:1;
663 /** True if this BO wraps a host pointer */
664 bool from_host_ptr
:1;
667 static inline struct anv_bo
*
668 anv_bo_unwrap(struct anv_bo
*bo
)
670 while (bo
->is_wrapper
)
675 /* Represents a lock-free linked list of "free" things. This is used by
676 * both the block pool and the state pools. Unfortunately, in order to
677 * solve the ABA problem, we can't use a single uint32_t head.
679 union anv_free_list
{
683 /* A simple count that is incremented every time the head changes. */
686 /* Make sure it's aligned to 64 bits. This will make atomic operations
687 * faster on 32 bit platforms.
689 uint64_t u64
__attribute__ ((aligned (8)));
692 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
694 struct anv_block_state
{
700 /* Make sure it's aligned to 64 bits. This will make atomic operations
701 * faster on 32 bit platforms.
703 uint64_t u64
__attribute__ ((aligned (8)));
707 #define anv_block_pool_foreach_bo(bo, pool) \
708 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
709 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
712 #define ANV_MAX_BLOCK_POOL_BOS 20
714 struct anv_block_pool
{
715 struct anv_device
*device
;
718 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
719 * around the actual BO so that we grow the pool after the wrapper BO has
720 * been put in a relocation list. This is only used in the non-softpin
723 struct anv_bo wrapper_bo
;
725 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
731 /* The address where the start of the pool is pinned. The various bos that
732 * are created as the pool grows will have addresses in the range
733 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
735 uint64_t start_address
;
737 /* The offset from the start of the bo to the "center" of the block
738 * pool. Pointers to allocated blocks are given by
739 * bo.map + center_bo_offset + offsets.
741 uint32_t center_bo_offset
;
743 /* Current memory map of the block pool. This pointer may or may not
744 * point to the actual beginning of the block pool memory. If
745 * anv_block_pool_alloc_back has ever been called, then this pointer
746 * will point to the "center" position of the buffer and all offsets
747 * (negative or positive) given out by the block pool alloc functions
748 * will be valid relative to this pointer.
750 * In particular, map == bo.map + center_offset
752 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
753 * since it will handle the softpin case as well, where this points to NULL.
759 * Array of mmaps and gem handles owned by the block pool, reclaimed when
760 * the block pool is destroyed.
762 struct u_vector mmap_cleanups
;
764 struct anv_block_state state
;
766 struct anv_block_state back_state
;
769 /* Block pools are backed by a fixed-size 1GB memfd */
770 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
772 /* The center of the block pool is also the middle of the memfd. This may
773 * change in the future if we decide differently for some reason.
775 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
777 static inline uint32_t
778 anv_block_pool_size(struct anv_block_pool
*pool
)
780 return pool
->state
.end
+ pool
->back_state
.end
;
790 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
792 struct anv_fixed_size_state_pool
{
793 union anv_free_list free_list
;
794 struct anv_block_state block
;
797 #define ANV_MIN_STATE_SIZE_LOG2 6
798 #define ANV_MAX_STATE_SIZE_LOG2 21
800 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
802 struct anv_free_entry
{
804 struct anv_state state
;
807 struct anv_state_table
{
808 struct anv_device
*device
;
810 struct anv_free_entry
*map
;
812 struct anv_block_state state
;
813 struct u_vector cleanups
;
816 struct anv_state_pool
{
817 struct anv_block_pool block_pool
;
819 struct anv_state_table table
;
821 /* The size of blocks which will be allocated from the block pool */
824 /** Free list for "back" allocations */
825 union anv_free_list back_alloc_free_list
;
827 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
830 struct anv_state_stream_block
;
832 struct anv_state_stream
{
833 struct anv_state_pool
*state_pool
;
835 /* The size of blocks to allocate from the state pool */
838 /* Current block we're allocating from */
839 struct anv_state block
;
841 /* Offset into the current block at which to allocate the next state */
844 /* List of all blocks allocated from this pool */
845 struct anv_state_stream_block
*block_list
;
848 /* The block_pool functions exported for testing only. The block pool should
849 * only be used via a state pool (see below).
851 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
852 struct anv_device
*device
,
853 uint64_t start_address
,
854 uint32_t initial_size
);
855 void anv_block_pool_finish(struct anv_block_pool
*pool
);
856 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
857 uint32_t block_size
, uint32_t *padding
);
858 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
859 uint32_t block_size
);
860 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
862 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
863 struct anv_device
*device
,
864 uint64_t start_address
,
865 uint32_t block_size
);
866 void anv_state_pool_finish(struct anv_state_pool
*pool
);
867 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
868 uint32_t state_size
, uint32_t alignment
);
869 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
870 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
871 void anv_state_stream_init(struct anv_state_stream
*stream
,
872 struct anv_state_pool
*state_pool
,
873 uint32_t block_size
);
874 void anv_state_stream_finish(struct anv_state_stream
*stream
);
875 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
876 uint32_t size
, uint32_t alignment
);
878 VkResult
anv_state_table_init(struct anv_state_table
*table
,
879 struct anv_device
*device
,
880 uint32_t initial_entries
);
881 void anv_state_table_finish(struct anv_state_table
*table
);
882 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
884 void anv_free_list_push(union anv_free_list
*list
,
885 struct anv_state_table
*table
,
886 uint32_t idx
, uint32_t count
);
887 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
888 struct anv_state_table
*table
);
891 static inline struct anv_state
*
892 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
894 return &table
->map
[idx
].state
;
897 * Implements a pool of re-usable BOs. The interface is identical to that
898 * of block_pool except that each block is its own BO.
901 struct anv_device
*device
;
903 struct util_sparse_array_free_list free_list
[16];
906 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
907 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
908 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
909 struct anv_bo
**bo_out
);
910 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
912 struct anv_scratch_pool
{
913 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
914 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
917 void anv_scratch_pool_init(struct anv_device
*device
,
918 struct anv_scratch_pool
*pool
);
919 void anv_scratch_pool_finish(struct anv_device
*device
,
920 struct anv_scratch_pool
*pool
);
921 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
922 struct anv_scratch_pool
*pool
,
923 gl_shader_stage stage
,
924 unsigned per_thread_scratch
);
926 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
927 struct anv_bo_cache
{
928 struct util_sparse_array bo_map
;
929 pthread_mutex_t mutex
;
932 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
933 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
935 struct anv_memory_type
{
936 /* Standard bits passed on to the client */
937 VkMemoryPropertyFlags propertyFlags
;
940 /* Driver-internal book-keeping */
941 VkBufferUsageFlags valid_buffer_usage
;
944 struct anv_memory_heap
{
945 /* Standard bits passed on to the client */
947 VkMemoryHeapFlags flags
;
949 /* Driver-internal book-keeping */
952 bool supports_48bit_addresses
;
956 struct anv_physical_device
{
957 VK_LOADER_DATA _loader_data
;
959 struct anv_instance
* instance
;
970 struct gen_device_info info
;
971 /** Amount of "GPU memory" we want to advertise
973 * Clearly, this value is bogus since Intel is a UMA architecture. On
974 * gen7 platforms, we are limited by GTT size unless we want to implement
975 * fine-grained tracking and GTT splitting. On Broadwell and above we are
976 * practically unlimited. However, we will never report more than 3/4 of
977 * the total system ram to try and avoid running out of RAM.
979 bool supports_48bit_addresses
;
980 struct brw_compiler
* compiler
;
981 struct isl_device isl_dev
;
982 struct gen_perf_config
* perf
;
983 int cmd_parser_version
;
985 bool has_exec_capture
;
988 bool has_syncobj_wait
;
989 bool has_context_priority
;
991 bool has_context_isolation
;
992 bool has_mem_available
;
993 bool always_use_bindless
;
995 /** True if we can access buffers using A64 messages */
996 bool has_a64_buffer_access
;
997 /** True if we can use bindless access for images */
998 bool has_bindless_images
;
999 /** True if we can use bindless access for samplers */
1000 bool has_bindless_samplers
;
1002 bool always_flush_cache
;
1004 struct anv_device_extension_table supported_extensions
;
1005 struct anv_physical_device_dispatch_table dispatch
;
1008 uint32_t subslice_total
;
1011 uint32_t type_count
;
1012 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1013 uint32_t heap_count
;
1014 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1017 uint8_t driver_build_sha1
[20];
1018 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1019 uint8_t driver_uuid
[VK_UUID_SIZE
];
1020 uint8_t device_uuid
[VK_UUID_SIZE
];
1022 struct disk_cache
* disk_cache
;
1024 struct wsi_device wsi_device
;
1029 struct anv_app_info
{
1030 const char* app_name
;
1031 uint32_t app_version
;
1032 const char* engine_name
;
1033 uint32_t engine_version
;
1034 uint32_t api_version
;
1037 struct anv_instance
{
1038 VK_LOADER_DATA _loader_data
;
1040 VkAllocationCallbacks alloc
;
1042 struct anv_app_info app_info
;
1044 struct anv_instance_extension_table enabled_extensions
;
1045 struct anv_instance_dispatch_table dispatch
;
1046 struct anv_device_dispatch_table device_dispatch
;
1048 int physicalDeviceCount
;
1049 struct anv_physical_device physicalDevice
;
1051 bool pipeline_cache_enabled
;
1053 struct vk_debug_report_instance debug_report_callbacks
;
1055 struct driOptionCache dri_options
;
1056 struct driOptionCache available_dri_options
;
1059 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1060 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1062 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1063 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1066 struct anv_queue_submit
{
1067 struct anv_cmd_buffer
* cmd_buffer
;
1069 uint32_t fence_count
;
1070 uint32_t fence_array_length
;
1071 struct drm_i915_gem_exec_fence
* fences
;
1073 uint32_t temporary_semaphore_count
;
1074 uint32_t temporary_semaphore_array_length
;
1075 struct anv_semaphore_impl
* temporary_semaphores
;
1077 /* Semaphores to be signaled with a SYNC_FD. */
1078 struct anv_semaphore
** sync_fd_semaphores
;
1079 uint32_t sync_fd_semaphore_count
;
1080 uint32_t sync_fd_semaphore_array_length
;
1082 /* Allocated only with non shareable timelines. */
1083 struct anv_timeline
** wait_timelines
;
1084 uint32_t wait_timeline_count
;
1085 uint32_t wait_timeline_array_length
;
1086 uint64_t * wait_timeline_values
;
1088 struct anv_timeline
** signal_timelines
;
1089 uint32_t signal_timeline_count
;
1090 uint32_t signal_timeline_array_length
;
1091 uint64_t * signal_timeline_values
;
1094 bool need_out_fence
;
1097 uint32_t fence_bo_count
;
1098 uint32_t fence_bo_array_length
;
1099 /* An array of struct anv_bo pointers with lower bit used as a flag to
1100 * signal we will wait on that BO (see anv_(un)pack_ptr).
1102 uintptr_t * fence_bos
;
1104 const VkAllocationCallbacks
* alloc
;
1105 VkSystemAllocationScope alloc_scope
;
1107 struct anv_bo
* simple_bo
;
1108 uint32_t simple_bo_size
;
1110 struct list_head link
;
1114 VK_LOADER_DATA _loader_data
;
1116 struct anv_device
* device
;
1119 * A list of struct anv_queue_submit to be submitted to i915.
1121 struct list_head queued_submits
;
1123 VkDeviceQueueCreateFlags flags
;
1126 struct anv_pipeline_cache
{
1127 struct anv_device
* device
;
1128 pthread_mutex_t mutex
;
1130 struct hash_table
* nir_cache
;
1132 struct hash_table
* cache
;
1135 struct nir_xfb_info
;
1136 struct anv_pipeline_bind_map
;
1138 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1139 struct anv_device
*device
,
1140 bool cache_enabled
);
1141 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1143 struct anv_shader_bin
*
1144 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1145 const void *key
, uint32_t key_size
);
1146 struct anv_shader_bin
*
1147 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1148 const void *key_data
, uint32_t key_size
,
1149 const void *kernel_data
, uint32_t kernel_size
,
1150 const void *constant_data
,
1151 uint32_t constant_data_size
,
1152 const struct brw_stage_prog_data
*prog_data
,
1153 uint32_t prog_data_size
,
1154 const struct brw_compile_stats
*stats
,
1156 const struct nir_xfb_info
*xfb_info
,
1157 const struct anv_pipeline_bind_map
*bind_map
);
1159 struct anv_shader_bin
*
1160 anv_device_search_for_kernel(struct anv_device
*device
,
1161 struct anv_pipeline_cache
*cache
,
1162 const void *key_data
, uint32_t key_size
,
1163 bool *user_cache_bit
);
1165 struct anv_shader_bin
*
1166 anv_device_upload_kernel(struct anv_device
*device
,
1167 struct anv_pipeline_cache
*cache
,
1168 const void *key_data
, uint32_t key_size
,
1169 const void *kernel_data
, uint32_t kernel_size
,
1170 const void *constant_data
,
1171 uint32_t constant_data_size
,
1172 const struct brw_stage_prog_data
*prog_data
,
1173 uint32_t prog_data_size
,
1174 const struct brw_compile_stats
*stats
,
1176 const struct nir_xfb_info
*xfb_info
,
1177 const struct anv_pipeline_bind_map
*bind_map
);
1180 struct nir_shader_compiler_options
;
1183 anv_device_search_for_nir(struct anv_device
*device
,
1184 struct anv_pipeline_cache
*cache
,
1185 const struct nir_shader_compiler_options
*nir_options
,
1186 unsigned char sha1_key
[20],
1190 anv_device_upload_nir(struct anv_device
*device
,
1191 struct anv_pipeline_cache
*cache
,
1192 const struct nir_shader
*nir
,
1193 unsigned char sha1_key
[20]);
1196 VK_LOADER_DATA _loader_data
;
1198 VkAllocationCallbacks alloc
;
1200 struct anv_instance
* instance
;
1201 uint32_t chipset_id
;
1203 struct gen_device_info info
;
1204 struct isl_device isl_dev
;
1207 bool can_chain_batches
;
1208 bool robust_buffer_access
;
1209 struct anv_device_extension_table enabled_extensions
;
1210 struct anv_device_dispatch_table dispatch
;
1212 pthread_mutex_t vma_mutex
;
1213 struct util_vma_heap vma_lo
;
1214 struct util_vma_heap vma_hi
;
1215 uint64_t vma_lo_available
;
1216 uint64_t vma_hi_available
;
1218 /** List of all anv_device_memory objects */
1219 struct list_head memory_objects
;
1221 struct anv_bo_pool batch_bo_pool
;
1223 struct anv_bo_cache bo_cache
;
1225 struct anv_state_pool dynamic_state_pool
;
1226 struct anv_state_pool instruction_state_pool
;
1227 struct anv_state_pool binding_table_pool
;
1228 struct anv_state_pool surface_state_pool
;
1230 struct anv_bo
* workaround_bo
;
1231 struct anv_bo
* trivial_batch_bo
;
1232 struct anv_bo
* hiz_clear_bo
;
1234 struct anv_pipeline_cache default_pipeline_cache
;
1235 struct blorp_context blorp
;
1237 struct anv_state border_colors
;
1239 struct anv_state slice_hash
;
1241 struct anv_queue queue
;
1243 struct anv_scratch_pool scratch_pool
;
1245 pthread_mutex_t mutex
;
1246 pthread_cond_t queue_submit
;
1249 struct gen_batch_decode_ctx decoder_ctx
;
1251 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1252 * the cmd_buffer's list.
1254 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1256 int perf_fd
; /* -1 if no opened */
1257 uint64_t perf_metric
; /* 0 if unset */
1259 struct gen_aux_map_context
*aux_map_ctx
;
1262 static inline struct anv_state_pool
*
1263 anv_binding_table_pool(struct anv_device
*device
)
1265 if (device
->instance
->physicalDevice
.use_softpin
)
1266 return &device
->binding_table_pool
;
1268 return &device
->surface_state_pool
;
1271 static inline struct anv_state
1272 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1273 if (device
->instance
->physicalDevice
.use_softpin
)
1274 return anv_state_pool_alloc(&device
->binding_table_pool
,
1275 device
->binding_table_pool
.block_size
, 0);
1277 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1281 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1282 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1285 static inline uint32_t
1286 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1288 if (bo
->is_external
)
1289 return device
->isl_dev
.mocs
.external
;
1291 return device
->isl_dev
.mocs
.internal
;
1294 void anv_device_init_blorp(struct anv_device
*device
);
1295 void anv_device_finish_blorp(struct anv_device
*device
);
1297 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1298 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1299 const char *file
, int line
,
1300 const char *msg
, ...)
1301 anv_printflike(4, 5);
1302 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1303 const char *file
, int line
,
1304 const char *msg
, ...)
1305 anv_printflike(4, 5);
1306 #define anv_device_set_lost(dev, ...) \
1307 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1308 #define anv_queue_set_lost(queue, ...) \
1309 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1312 anv_device_is_lost(struct anv_device
*device
)
1314 return unlikely(p_atomic_read(&device
->_lost
));
1317 VkResult
anv_device_query_status(struct anv_device
*device
);
1320 enum anv_bo_alloc_flags
{
1321 /** Specifies that the BO must have a 32-bit address
1323 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1325 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1327 /** Specifies that the BO may be shared externally */
1328 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1330 /** Specifies that the BO should be mapped */
1331 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1333 /** Specifies that the BO should be snooped so we get coherency */
1334 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1336 /** Specifies that the BO should be captured in error states */
1337 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1339 /** Specifies that the BO will have an address assigned by the caller */
1340 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1342 /** Enables implicit synchronization on the BO
1344 * This is the opposite of EXEC_OBJECT_ASYNC.
1346 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1348 /** Enables implicit synchronization on the BO
1350 * This is equivalent to EXEC_OBJECT_WRITE.
1352 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1355 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1356 enum anv_bo_alloc_flags alloc_flags
,
1357 struct anv_bo
**bo
);
1358 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1359 void *host_ptr
, uint32_t size
,
1360 enum anv_bo_alloc_flags alloc_flags
,
1361 struct anv_bo
**bo_out
);
1362 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1363 enum anv_bo_alloc_flags alloc_flags
,
1364 struct anv_bo
**bo
);
1365 VkResult
anv_device_export_bo(struct anv_device
*device
,
1366 struct anv_bo
*bo
, int *fd_out
);
1367 void anv_device_release_bo(struct anv_device
*device
,
1370 static inline struct anv_bo
*
1371 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1373 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1376 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1377 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1380 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1381 void anv_queue_finish(struct anv_queue
*queue
);
1383 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1384 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1385 struct anv_batch
*batch
);
1387 uint64_t anv_gettime_ns(void);
1388 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1390 void* anv_gem_mmap(struct anv_device
*device
,
1391 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1392 void anv_gem_munmap(void *p
, uint64_t size
);
1393 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1394 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1395 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1396 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1397 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1398 int anv_gem_execbuffer(struct anv_device
*device
,
1399 struct drm_i915_gem_execbuffer2
*execbuf
);
1400 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1401 uint32_t stride
, uint32_t tiling
);
1402 int anv_gem_create_context(struct anv_device
*device
);
1403 bool anv_gem_has_context_priority(int fd
);
1404 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1405 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1407 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1409 int anv_gem_get_param(int fd
, uint32_t param
);
1410 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1411 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1412 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1413 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1414 uint32_t *active
, uint32_t *pending
);
1415 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1416 int anv_gem_reg_read(struct anv_device
*device
,
1417 uint32_t offset
, uint64_t *result
);
1418 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1419 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1420 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1421 uint32_t read_domains
, uint32_t write_domain
);
1422 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1423 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1424 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1425 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1426 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1427 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1429 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1430 uint32_t handle
, int fd
);
1431 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1432 bool anv_gem_supports_syncobj_wait(int fd
);
1433 int anv_gem_syncobj_wait(struct anv_device
*device
,
1434 uint32_t *handles
, uint32_t num_handles
,
1435 int64_t abs_timeout_ns
, bool wait_all
);
1437 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1438 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1440 struct anv_reloc_list
{
1441 uint32_t num_relocs
;
1442 uint32_t array_length
;
1443 struct drm_i915_gem_relocation_entry
* relocs
;
1444 struct anv_bo
** reloc_bos
;
1449 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1450 const VkAllocationCallbacks
*alloc
);
1451 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1452 const VkAllocationCallbacks
*alloc
);
1454 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1455 const VkAllocationCallbacks
*alloc
,
1456 uint32_t offset
, struct anv_bo
*target_bo
,
1457 uint32_t delta
, uint64_t *address_u64_out
);
1459 struct anv_batch_bo
{
1460 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1461 struct list_head link
;
1465 /* Bytes actually consumed in this batch BO */
1468 struct anv_reloc_list relocs
;
1472 const VkAllocationCallbacks
* alloc
;
1478 struct anv_reloc_list
* relocs
;
1480 /* This callback is called (with the associated user data) in the event
1481 * that the batch runs out of space.
1483 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1487 * Current error status of the command buffer. Used to track inconsistent
1488 * or incomplete command buffer states that are the consequence of run-time
1489 * errors such as out of memory scenarios. We want to track this in the
1490 * batch because the command buffer object is not visible to some parts
1496 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1497 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1498 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1499 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1501 static inline VkResult
1502 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1504 assert(error
!= VK_SUCCESS
);
1505 if (batch
->status
== VK_SUCCESS
)
1506 batch
->status
= error
;
1507 return batch
->status
;
1511 anv_batch_has_error(struct anv_batch
*batch
)
1513 return batch
->status
!= VK_SUCCESS
;
1516 struct anv_address
{
1521 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1524 anv_address_is_null(struct anv_address addr
)
1526 return addr
.bo
== NULL
&& addr
.offset
== 0;
1529 static inline uint64_t
1530 anv_address_physical(struct anv_address addr
)
1532 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1533 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1535 return gen_canonical_address(addr
.offset
);
1538 static inline struct anv_address
1539 anv_address_add(struct anv_address addr
, uint64_t offset
)
1541 addr
.offset
+= offset
;
1546 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1548 unsigned reloc_size
= 0;
1549 if (device
->info
.gen
>= 8) {
1550 reloc_size
= sizeof(uint64_t);
1551 *(uint64_t *)p
= gen_canonical_address(v
);
1553 reloc_size
= sizeof(uint32_t);
1557 if (flush
&& !device
->info
.has_llc
)
1558 gen_flush_range(p
, reloc_size
);
1561 static inline uint64_t
1562 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1563 const struct anv_address address
, uint32_t delta
)
1565 if (address
.bo
== NULL
) {
1566 return address
.offset
+ delta
;
1568 assert(batch
->start
<= location
&& location
< batch
->end
);
1570 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1574 #define __gen_address_type struct anv_address
1575 #define __gen_user_data struct anv_batch
1576 #define __gen_combine_address _anv_combine_address
1578 /* Wrapper macros needed to work around preprocessor argument issues. In
1579 * particular, arguments don't get pre-evaluated if they are concatenated.
1580 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1581 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1582 * We can work around this easily enough with these helpers.
1584 #define __anv_cmd_length(cmd) cmd ## _length
1585 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1586 #define __anv_cmd_header(cmd) cmd ## _header
1587 #define __anv_cmd_pack(cmd) cmd ## _pack
1588 #define __anv_reg_num(reg) reg ## _num
1590 #define anv_pack_struct(dst, struc, ...) do { \
1591 struct struc __template = { \
1594 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1595 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1598 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1599 void *__dst = anv_batch_emit_dwords(batch, n); \
1601 struct cmd __template = { \
1602 __anv_cmd_header(cmd), \
1603 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1606 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1611 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1615 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1616 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1619 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1620 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1621 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1624 #define anv_batch_emit(batch, cmd, name) \
1625 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1626 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1627 __builtin_expect(_dst != NULL, 1); \
1628 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1629 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1633 struct anv_device_memory
{
1634 struct list_head link
;
1637 struct anv_memory_type
* type
;
1638 VkDeviceSize map_size
;
1641 /* If set, we are holding reference to AHardwareBuffer
1642 * which we must release when memory is freed.
1644 struct AHardwareBuffer
* ahw
;
1646 /* If set, this memory comes from a host pointer. */
1651 * Header for Vertex URB Entry (VUE)
1653 struct anv_vue_header
{
1655 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1656 uint32_t ViewportIndex
;
1660 /** Struct representing a sampled image descriptor
1662 * This descriptor layout is used for sampled images, bare sampler, and
1663 * combined image/sampler descriptors.
1665 struct anv_sampled_image_descriptor
{
1666 /** Bindless image handle
1668 * This is expected to already be shifted such that the 20-bit
1669 * SURFACE_STATE table index is in the top 20 bits.
1673 /** Bindless sampler handle
1675 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1676 * to the dynamic state base address.
1681 struct anv_texture_swizzle_descriptor
{
1684 * See also nir_intrinsic_channel_select_intel
1688 /** Unused padding to ensure the struct is a multiple of 64 bits */
1692 /** Struct representing a storage image descriptor */
1693 struct anv_storage_image_descriptor
{
1694 /** Bindless image handles
1696 * These are expected to already be shifted such that the 20-bit
1697 * SURFACE_STATE table index is in the top 20 bits.
1699 uint32_t read_write
;
1700 uint32_t write_only
;
1703 /** Struct representing a address/range descriptor
1705 * The fields of this struct correspond directly to the data layout of
1706 * nir_address_format_64bit_bounded_global addresses. The last field is the
1707 * offset in the NIR address so it must be zero so that when you load the
1708 * descriptor you get a pointer to the start of the range.
1710 struct anv_address_range_descriptor
{
1716 enum anv_descriptor_data
{
1717 /** The descriptor contains a BTI reference to a surface state */
1718 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1719 /** The descriptor contains a BTI reference to a sampler state */
1720 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1721 /** The descriptor contains an actual buffer view */
1722 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1723 /** The descriptor contains auxiliary image layout data */
1724 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1725 /** The descriptor contains auxiliary image layout data */
1726 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1727 /** anv_address_range_descriptor with a buffer address and range */
1728 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1729 /** Bindless surface handle */
1730 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1731 /** Storage image handles */
1732 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1733 /** Storage image handles */
1734 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1737 struct anv_descriptor_set_binding_layout
{
1739 /* The type of the descriptors in this binding */
1740 VkDescriptorType type
;
1743 /* Flags provided when this binding was created */
1744 VkDescriptorBindingFlagsEXT flags
;
1746 /* Bitfield representing the type of data this descriptor contains */
1747 enum anv_descriptor_data data
;
1749 /* Maximum number of YCbCr texture/sampler planes */
1750 uint8_t max_plane_count
;
1752 /* Number of array elements in this binding (or size in bytes for inline
1755 uint16_t array_size
;
1757 /* Index into the flattend descriptor set */
1758 uint16_t descriptor_index
;
1760 /* Index into the dynamic state array for a dynamic buffer */
1761 int16_t dynamic_offset_index
;
1763 /* Index into the descriptor set buffer views */
1764 int16_t buffer_view_index
;
1766 /* Offset into the descriptor buffer where this descriptor lives */
1767 uint32_t descriptor_offset
;
1769 /* Immutable samplers (or NULL if no immutable samplers) */
1770 struct anv_sampler
**immutable_samplers
;
1773 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1775 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1776 VkDescriptorType type
);
1778 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1779 const struct anv_descriptor_set_binding_layout
*binding
,
1782 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1783 const struct anv_descriptor_set_binding_layout
*binding
,
1786 struct anv_descriptor_set_layout
{
1787 /* Descriptor set layouts can be destroyed at almost any time */
1790 /* Number of bindings in this descriptor set */
1791 uint16_t binding_count
;
1793 /* Total size of the descriptor set with room for all array entries */
1796 /* Shader stages affected by this descriptor set */
1797 uint16_t shader_stages
;
1799 /* Number of buffer views in this descriptor set */
1800 uint16_t buffer_view_count
;
1802 /* Number of dynamic offsets used by this descriptor set */
1803 uint16_t dynamic_offset_count
;
1805 /* For each shader stage, which offsets apply to that stage */
1806 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1808 /* Size of the descriptor buffer for this descriptor set */
1809 uint32_t descriptor_buffer_size
;
1811 /* Bindings in this descriptor set */
1812 struct anv_descriptor_set_binding_layout binding
[0];
1816 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1818 assert(layout
&& layout
->ref_cnt
>= 1);
1819 p_atomic_inc(&layout
->ref_cnt
);
1823 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1824 struct anv_descriptor_set_layout
*layout
)
1826 assert(layout
&& layout
->ref_cnt
>= 1);
1827 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1828 vk_free(&device
->alloc
, layout
);
1831 struct anv_descriptor
{
1832 VkDescriptorType type
;
1836 VkImageLayout layout
;
1837 struct anv_image_view
*image_view
;
1838 struct anv_sampler
*sampler
;
1842 struct anv_buffer
*buffer
;
1847 struct anv_buffer_view
*buffer_view
;
1851 struct anv_descriptor_set
{
1852 struct anv_descriptor_pool
*pool
;
1853 struct anv_descriptor_set_layout
*layout
;
1856 /* State relative to anv_descriptor_pool::bo */
1857 struct anv_state desc_mem
;
1858 /* Surface state for the descriptor buffer */
1859 struct anv_state desc_surface_state
;
1861 uint32_t buffer_view_count
;
1862 struct anv_buffer_view
*buffer_views
;
1864 /* Link to descriptor pool's desc_sets list . */
1865 struct list_head pool_link
;
1867 struct anv_descriptor descriptors
[0];
1870 struct anv_buffer_view
{
1871 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1872 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1874 struct anv_address address
;
1876 struct anv_state surface_state
;
1877 struct anv_state storage_surface_state
;
1878 struct anv_state writeonly_storage_surface_state
;
1880 struct brw_image_param storage_image_param
;
1883 struct anv_push_descriptor_set
{
1884 struct anv_descriptor_set set
;
1886 /* Put this field right behind anv_descriptor_set so it fills up the
1887 * descriptors[0] field. */
1888 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1890 /** True if the descriptor set buffer has been referenced by a draw or
1893 bool set_used_on_gpu
;
1895 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1898 struct anv_descriptor_pool
{
1904 struct util_vma_heap bo_heap
;
1906 struct anv_state_stream surface_state_stream
;
1907 void *surface_state_free_list
;
1909 struct list_head desc_sets
;
1914 enum anv_descriptor_template_entry_type
{
1915 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1916 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1917 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1920 struct anv_descriptor_template_entry
{
1921 /* The type of descriptor in this entry */
1922 VkDescriptorType type
;
1924 /* Binding in the descriptor set */
1927 /* Offset at which to write into the descriptor set binding */
1928 uint32_t array_element
;
1930 /* Number of elements to write into the descriptor set binding */
1931 uint32_t array_count
;
1933 /* Offset into the user provided data */
1936 /* Stride between elements into the user provided data */
1940 struct anv_descriptor_update_template
{
1941 VkPipelineBindPoint bind_point
;
1943 /* The descriptor set this template corresponds to. This value is only
1944 * valid if the template was created with the templateType
1945 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1949 /* Number of entries in this template */
1950 uint32_t entry_count
;
1952 /* Entries of the template */
1953 struct anv_descriptor_template_entry entries
[0];
1957 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1960 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1961 struct anv_descriptor_set
*set
,
1962 const VkDescriptorImageInfo
* const info
,
1963 VkDescriptorType type
,
1968 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1969 struct anv_descriptor_set
*set
,
1970 VkDescriptorType type
,
1971 struct anv_buffer_view
*buffer_view
,
1976 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1977 struct anv_descriptor_set
*set
,
1978 struct anv_state_stream
*alloc_stream
,
1979 VkDescriptorType type
,
1980 struct anv_buffer
*buffer
,
1983 VkDeviceSize offset
,
1984 VkDeviceSize range
);
1986 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1987 struct anv_descriptor_set
*set
,
1994 anv_descriptor_set_write_template(struct anv_device
*device
,
1995 struct anv_descriptor_set
*set
,
1996 struct anv_state_stream
*alloc_stream
,
1997 const struct anv_descriptor_update_template
*template,
2001 anv_descriptor_set_create(struct anv_device
*device
,
2002 struct anv_descriptor_pool
*pool
,
2003 struct anv_descriptor_set_layout
*layout
,
2004 struct anv_descriptor_set
**out_set
);
2007 anv_descriptor_set_destroy(struct anv_device
*device
,
2008 struct anv_descriptor_pool
*pool
,
2009 struct anv_descriptor_set
*set
);
2011 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2012 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2013 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2014 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2015 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2016 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2018 struct anv_pipeline_binding
{
2019 /** Index in the descriptor set
2021 * This is a flattened index; the descriptor set layout is already taken
2026 /** The descriptor set this surface corresponds to.
2028 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2029 * binding is not a normal descriptor set but something else.
2034 /** Plane in the binding index for images */
2037 /** Input attachment index (relative to the subpass) */
2038 uint8_t input_attachment_index
;
2040 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2041 uint8_t dynamic_offset_index
;
2044 /** For a storage image, whether it is write-only */
2047 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2048 * assuming POD zero-initialization.
2053 struct anv_push_range
{
2054 /** Index in the descriptor set */
2057 /** Descriptor set index */
2060 /** Dynamic offset index (for dynamic UBOs) */
2061 uint8_t dynamic_offset_index
;
2063 /** Start offset in units of 32B */
2066 /** Range in units of 32B */
2070 struct anv_pipeline_layout
{
2072 struct anv_descriptor_set_layout
*layout
;
2073 uint32_t dynamic_offset_start
;
2078 unsigned char sha1
[20];
2082 struct anv_device
* device
;
2085 VkBufferUsageFlags usage
;
2087 /* Set when bound */
2088 struct anv_address address
;
2091 static inline uint64_t
2092 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2094 assert(offset
<= buffer
->size
);
2095 if (range
== VK_WHOLE_SIZE
) {
2096 return buffer
->size
- offset
;
2098 assert(range
+ offset
>= range
);
2099 assert(range
+ offset
<= buffer
->size
);
2104 enum anv_cmd_dirty_bits
{
2105 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2106 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2107 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2108 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2109 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2110 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2111 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2112 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2113 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2114 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2115 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2116 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2117 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2118 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2120 typedef uint32_t anv_cmd_dirty_mask_t
;
2122 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2123 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2124 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2125 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2126 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2127 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2128 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2129 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2130 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2131 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2132 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2134 static inline enum anv_cmd_dirty_bits
2135 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2138 case VK_DYNAMIC_STATE_VIEWPORT
:
2139 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2140 case VK_DYNAMIC_STATE_SCISSOR
:
2141 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2142 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2143 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2144 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2145 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2146 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2147 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2148 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2149 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2150 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2151 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2152 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2153 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2154 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2155 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2156 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2157 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2159 assert(!"Unsupported dynamic state");
2165 enum anv_pipe_bits
{
2166 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2167 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2168 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2169 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2170 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2171 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2172 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2173 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2174 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2175 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2176 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2177 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2179 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2180 * a flush has happened but not a CS stall. The next time we do any sort
2181 * of invalidation we need to insert a CS stall at that time. Otherwise,
2182 * we would have to CS stall on every flush which could be bad.
2184 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2186 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2187 * target operations related to transfer commands with VkBuffer as
2188 * destination are ongoing. Some operations like copies on the command
2189 * streamer might need to be aware of this to trigger the appropriate stall
2190 * before they can proceed with the copy.
2192 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2195 #define ANV_PIPE_FLUSH_BITS ( \
2196 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2197 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2198 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2199 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2201 #define ANV_PIPE_STALL_BITS ( \
2202 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2203 ANV_PIPE_DEPTH_STALL_BIT | \
2204 ANV_PIPE_CS_STALL_BIT)
2206 #define ANV_PIPE_INVALIDATE_BITS ( \
2207 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2208 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2209 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2210 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2211 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2212 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2214 static inline enum anv_pipe_bits
2215 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2217 enum anv_pipe_bits pipe_bits
= 0;
2220 for_each_bit(b
, flags
) {
2221 switch ((VkAccessFlagBits
)(1 << b
)) {
2222 case VK_ACCESS_SHADER_WRITE_BIT
:
2223 /* We're transitioning a buffer that was previously used as write
2224 * destination through the data port. To make its content available
2225 * to future operations, flush the data cache.
2227 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2229 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2230 /* We're transitioning a buffer that was previously used as render
2231 * target. To make its content available to future operations, flush
2232 * the render target cache.
2234 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2236 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2237 /* We're transitioning a buffer that was previously used as depth
2238 * buffer. To make its content available to future operations, flush
2241 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2243 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2244 /* We're transitioning a buffer that was previously used as a
2245 * transfer write destination. Generic write operations include color
2246 * & depth operations as well as buffer operations like :
2247 * - vkCmdClearColorImage()
2248 * - vkCmdClearDepthStencilImage()
2249 * - vkCmdBlitImage()
2250 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2252 * Most of these operations are implemented using Blorp which writes
2253 * through the render target, so flush that cache to make it visible
2254 * to future operations. And for depth related operations we also
2255 * need to flush the depth cache.
2257 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2258 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2260 case VK_ACCESS_MEMORY_WRITE_BIT
:
2261 /* We're transitioning a buffer for generic write operations. Flush
2264 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2267 break; /* Nothing to do */
2274 static inline enum anv_pipe_bits
2275 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2277 enum anv_pipe_bits pipe_bits
= 0;
2280 for_each_bit(b
, flags
) {
2281 switch ((VkAccessFlagBits
)(1 << b
)) {
2282 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2283 /* Indirect draw commands take a buffer as input that we're going to
2284 * read from the command streamer to load some of the HW registers
2285 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2286 * command streamer stall so that all the cache flushes have
2287 * completed before the command streamer loads from memory.
2289 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2290 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2291 * through a vertex buffer, so invalidate that cache.
2293 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2294 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2295 * UBO from the buffer, so we need to invalidate constant cache.
2297 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2299 case VK_ACCESS_INDEX_READ_BIT
:
2300 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2301 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2302 * commands, so we invalidate the VF cache to make sure there is no
2303 * stale data when we start rendering.
2305 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2307 case VK_ACCESS_UNIFORM_READ_BIT
:
2308 /* We transitioning a buffer to be used as uniform data. Because
2309 * uniform is accessed through the data port & sampler, we need to
2310 * invalidate the texture cache (sampler) & constant cache (data
2311 * port) to avoid stale data.
2313 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2314 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2316 case VK_ACCESS_SHADER_READ_BIT
:
2317 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2318 case VK_ACCESS_TRANSFER_READ_BIT
:
2319 /* Transitioning a buffer to be read through the sampler, so
2320 * invalidate the texture cache, we don't want any stale data.
2322 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2324 case VK_ACCESS_MEMORY_READ_BIT
:
2325 /* Transitioning a buffer for generic read, invalidate all the
2328 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2330 case VK_ACCESS_MEMORY_WRITE_BIT
:
2331 /* Generic write, make sure all previously written things land in
2334 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2336 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2337 /* Transitioning a buffer for conditional rendering. We'll load the
2338 * content of this buffer into HW registers using the command
2339 * streamer, so we need to stall the command streamer to make sure
2340 * any in-flight flush operations have completed.
2342 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2345 break; /* Nothing to do */
2352 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2353 VK_IMAGE_ASPECT_COLOR_BIT | \
2354 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2355 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2356 VK_IMAGE_ASPECT_PLANE_2_BIT)
2357 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2358 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2359 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2360 VK_IMAGE_ASPECT_PLANE_2_BIT)
2362 struct anv_vertex_binding
{
2363 struct anv_buffer
* buffer
;
2364 VkDeviceSize offset
;
2367 struct anv_xfb_binding
{
2368 struct anv_buffer
* buffer
;
2369 VkDeviceSize offset
;
2373 struct anv_push_constants
{
2374 /** Push constant data provided by the client through vkPushConstants */
2375 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2377 /** Dynamic offsets for dynamic UBOs and SSBOs */
2378 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2381 /** Base workgroup ID
2383 * Used for vkCmdDispatchBase.
2385 uint32_t base_work_group_id
[3];
2389 * This is never set by software but is implicitly filled out when
2390 * uploading the push constants for compute shaders.
2392 uint32_t subgroup_id
;
2394 /** Pad out to a multiple of 32 bytes */
2399 struct anv_dynamic_state
{
2402 VkViewport viewports
[MAX_VIEWPORTS
];
2407 VkRect2D scissors
[MAX_SCISSORS
];
2418 float blend_constants
[4];
2428 } stencil_compare_mask
;
2433 } stencil_write_mask
;
2438 } stencil_reference
;
2446 extern const struct anv_dynamic_state default_dynamic_state
;
2448 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2449 const struct anv_dynamic_state
*src
,
2450 uint32_t copy_mask
);
2452 struct anv_surface_state
{
2453 struct anv_state state
;
2454 /** Address of the surface referred to by this state
2456 * This address is relative to the start of the BO.
2458 struct anv_address address
;
2459 /* Address of the aux surface, if any
2461 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2463 * With the exception of gen8, the bottom 12 bits of this address' offset
2464 * include extra aux information.
2466 struct anv_address aux_address
;
2467 /* Address of the clear color, if any
2469 * This address is relative to the start of the BO.
2471 struct anv_address clear_address
;
2475 * Attachment state when recording a renderpass instance.
2477 * The clear value is valid only if there exists a pending clear.
2479 struct anv_attachment_state
{
2480 enum isl_aux_usage aux_usage
;
2481 enum isl_aux_usage input_aux_usage
;
2482 struct anv_surface_state color
;
2483 struct anv_surface_state input
;
2485 VkImageLayout current_layout
;
2486 VkImageLayout current_stencil_layout
;
2487 VkImageAspectFlags pending_clear_aspects
;
2488 VkImageAspectFlags pending_load_aspects
;
2490 VkClearValue clear_value
;
2491 bool clear_color_is_zero_one
;
2492 bool clear_color_is_zero
;
2494 /* When multiview is active, attachments with a renderpass clear
2495 * operation have their respective layers cleared on the first
2496 * subpass that uses them, and only in that subpass. We keep track
2497 * of this using a bitfield to indicate which layers of an attachment
2498 * have not been cleared yet when multiview is active.
2500 uint32_t pending_clear_views
;
2501 struct anv_image_view
* image_view
;
2504 /** State tracking for particular pipeline bind point
2506 * This struct is the base struct for anv_cmd_graphics_state and
2507 * anv_cmd_compute_state. These are used to track state which is bound to a
2508 * particular type of pipeline. Generic state that applies per-stage such as
2509 * binding table offsets and push constants is tracked generically with a
2510 * per-stage array in anv_cmd_state.
2512 struct anv_cmd_pipeline_state
{
2513 struct anv_pipeline
*pipeline
;
2515 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2516 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2519 /** State tracking for graphics pipeline
2521 * This has anv_cmd_pipeline_state as a base struct to track things which get
2522 * bound to a graphics pipeline. Along with general pipeline bind point state
2523 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2524 * state which is graphics-specific.
2526 struct anv_cmd_graphics_state
{
2527 struct anv_cmd_pipeline_state base
;
2529 anv_cmd_dirty_mask_t dirty
;
2532 struct anv_dynamic_state dynamic
;
2535 struct anv_buffer
*index_buffer
;
2536 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2537 uint32_t index_offset
;
2541 /** State tracking for compute pipeline
2543 * This has anv_cmd_pipeline_state as a base struct to track things which get
2544 * bound to a compute pipeline. Along with general pipeline bind point state
2545 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2546 * state which is compute-specific.
2548 struct anv_cmd_compute_state
{
2549 struct anv_cmd_pipeline_state base
;
2551 bool pipeline_dirty
;
2553 struct anv_address num_workgroups
;
2556 /** State required while building cmd buffer */
2557 struct anv_cmd_state
{
2558 /* PIPELINE_SELECT.PipelineSelection */
2559 uint32_t current_pipeline
;
2560 const struct gen_l3_config
* current_l3_config
;
2561 uint32_t last_aux_map_state
;
2563 struct anv_cmd_graphics_state gfx
;
2564 struct anv_cmd_compute_state compute
;
2566 enum anv_pipe_bits pending_pipe_bits
;
2567 VkShaderStageFlags descriptors_dirty
;
2568 VkShaderStageFlags push_constants_dirty
;
2570 struct anv_framebuffer
* framebuffer
;
2571 struct anv_render_pass
* pass
;
2572 struct anv_subpass
* subpass
;
2573 VkRect2D render_area
;
2574 uint32_t restart_index
;
2575 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2577 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2578 VkShaderStageFlags push_constant_stages
;
2579 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2580 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2581 struct anv_state samplers
[MESA_SHADER_STAGES
];
2583 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2584 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2585 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2588 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2589 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2590 * and before invoking the secondary in ExecuteCommands.
2592 bool pma_fix_enabled
;
2595 * Whether or not we know for certain that HiZ is enabled for the current
2596 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2597 * enabled or not, this will be false.
2601 bool conditional_render_enabled
;
2604 * Last rendering scale argument provided to
2605 * genX(cmd_buffer_emit_hashing_mode)().
2607 unsigned current_hash_scale
;
2610 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2611 * valid only when recording a render pass instance.
2613 struct anv_attachment_state
* attachments
;
2616 * Surface states for color render targets. These are stored in a single
2617 * flat array. For depth-stencil attachments, the surface state is simply
2620 struct anv_state render_pass_states
;
2623 * A null surface state of the right size to match the framebuffer. This
2624 * is one of the states in render_pass_states.
2626 struct anv_state null_surface_state
;
2629 struct anv_cmd_pool
{
2630 VkAllocationCallbacks alloc
;
2631 struct list_head cmd_buffers
;
2634 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2636 enum anv_cmd_buffer_exec_mode
{
2637 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2638 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2639 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2640 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2641 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2644 struct anv_cmd_buffer
{
2645 VK_LOADER_DATA _loader_data
;
2647 struct anv_device
* device
;
2649 struct anv_cmd_pool
* pool
;
2650 struct list_head pool_link
;
2652 struct anv_batch batch
;
2654 /* Fields required for the actual chain of anv_batch_bo's.
2656 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2658 struct list_head batch_bos
;
2659 enum anv_cmd_buffer_exec_mode exec_mode
;
2661 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2662 * referenced by this command buffer
2664 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2666 struct u_vector seen_bbos
;
2668 /* A vector of int32_t's for every block of binding tables.
2670 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2672 struct u_vector bt_block_states
;
2673 struct anv_state bt_next
;
2675 struct anv_reloc_list surface_relocs
;
2676 /** Last seen surface state block pool center bo offset */
2677 uint32_t last_ss_pool_center
;
2679 /* Serial for tracking buffer completion */
2682 /* Stream objects for storing temporary data */
2683 struct anv_state_stream surface_state_stream
;
2684 struct anv_state_stream dynamic_state_stream
;
2686 VkCommandBufferUsageFlags usage_flags
;
2687 VkCommandBufferLevel level
;
2689 struct anv_cmd_state state
;
2691 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2692 uint64_t intel_perf_marker
;
2695 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2696 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2697 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2698 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2699 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2700 struct anv_cmd_buffer
*secondary
);
2701 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2702 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2703 struct anv_cmd_buffer
*cmd_buffer
,
2704 const VkSemaphore
*in_semaphores
,
2705 const uint64_t *in_wait_values
,
2706 uint32_t num_in_semaphores
,
2707 const VkSemaphore
*out_semaphores
,
2708 const uint64_t *out_signal_values
,
2709 uint32_t num_out_semaphores
,
2712 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2714 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2715 const void *data
, uint32_t size
, uint32_t alignment
);
2716 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2717 uint32_t *a
, uint32_t *b
,
2718 uint32_t dwords
, uint32_t alignment
);
2721 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2723 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2724 uint32_t entries
, uint32_t *state_offset
);
2726 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2728 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2729 uint32_t size
, uint32_t alignment
);
2732 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2734 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2735 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2736 bool depth_clamp_enable
);
2737 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2739 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2740 struct anv_render_pass
*pass
,
2741 struct anv_framebuffer
*framebuffer
,
2742 const VkClearValue
*clear_values
);
2744 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2747 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2748 gl_shader_stage stage
);
2750 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2752 const struct anv_image_view
*
2753 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2756 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2757 uint32_t num_entries
,
2758 uint32_t *state_offset
,
2759 struct anv_state
*bt_state
);
2761 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2763 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2765 enum anv_fence_type
{
2766 ANV_FENCE_TYPE_NONE
= 0,
2768 ANV_FENCE_TYPE_SYNCOBJ
,
2772 enum anv_bo_fence_state
{
2773 /** Indicates that this is a new (or newly reset fence) */
2774 ANV_BO_FENCE_STATE_RESET
,
2776 /** Indicates that this fence has been submitted to the GPU but is still
2777 * (as far as we know) in use by the GPU.
2779 ANV_BO_FENCE_STATE_SUBMITTED
,
2781 ANV_BO_FENCE_STATE_SIGNALED
,
2784 struct anv_fence_impl
{
2785 enum anv_fence_type type
;
2788 /** Fence implementation for BO fences
2790 * These fences use a BO and a set of CPU-tracked state flags. The BO
2791 * is added to the object list of the last execbuf call in a QueueSubmit
2792 * and is marked EXEC_WRITE. The state flags track when the BO has been
2793 * submitted to the kernel. We need to do this because Vulkan lets you
2794 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2795 * will say it's idle in this case.
2799 enum anv_bo_fence_state state
;
2802 /** DRM syncobj handle for syncobj-based fences */
2806 struct wsi_fence
*fence_wsi
;
2811 /* Permanent fence state. Every fence has some form of permanent state
2812 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2813 * cross-process fences) or it could just be a dummy for use internally.
2815 struct anv_fence_impl permanent
;
2817 /* Temporary fence state. A fence *may* have temporary state. That state
2818 * is added to the fence by an import operation and is reset back to
2819 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2820 * state cannot be signaled because the fence must already be signaled
2821 * before the temporary state can be exported from the fence in the other
2822 * process and imported here.
2824 struct anv_fence_impl temporary
;
2829 struct anv_state state
;
2832 enum anv_semaphore_type
{
2833 ANV_SEMAPHORE_TYPE_NONE
= 0,
2834 ANV_SEMAPHORE_TYPE_DUMMY
,
2835 ANV_SEMAPHORE_TYPE_BO
,
2836 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2837 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2838 ANV_SEMAPHORE_TYPE_TIMELINE
,
2841 struct anv_timeline_point
{
2842 struct list_head link
;
2846 /* Number of waiter on this point, when > 0 the point should not be garbage
2851 /* BO used for synchronization. */
2855 struct anv_timeline
{
2856 pthread_mutex_t mutex
;
2857 pthread_cond_t cond
;
2859 uint64_t highest_past
;
2860 uint64_t highest_pending
;
2862 struct list_head points
;
2863 struct list_head free_points
;
2866 struct anv_semaphore_impl
{
2867 enum anv_semaphore_type type
;
2870 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2871 * This BO will be added to the object list on any execbuf2 calls for
2872 * which this semaphore is used as a wait or signal fence. When used as
2873 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2877 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2878 * If the semaphore is in the unsignaled state due to either just being
2879 * created or because it has been used for a wait, fd will be -1.
2883 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2884 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2885 * import so we don't need to bother with a userspace cache.
2889 /* Non shareable timeline semaphore
2891 * Used when kernel don't have support for timeline semaphores.
2893 struct anv_timeline timeline
;
2897 struct anv_semaphore
{
2900 /* Permanent semaphore state. Every semaphore has some form of permanent
2901 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2902 * (for cross-process semaphores0 or it could just be a dummy for use
2905 struct anv_semaphore_impl permanent
;
2907 /* Temporary semaphore state. A semaphore *may* have temporary state.
2908 * That state is added to the semaphore by an import operation and is reset
2909 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2910 * semaphore with temporary state cannot be signaled because the semaphore
2911 * must already be signaled before the temporary state can be exported from
2912 * the semaphore in the other process and imported here.
2914 struct anv_semaphore_impl temporary
;
2917 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2918 struct anv_semaphore
*semaphore
);
2920 struct anv_shader_module
{
2921 unsigned char sha1
[20];
2926 static inline gl_shader_stage
2927 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2929 assert(__builtin_popcount(vk_stage
) == 1);
2930 return ffs(vk_stage
) - 1;
2933 static inline VkShaderStageFlagBits
2934 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2936 return (1 << mesa_stage
);
2939 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2941 #define anv_foreach_stage(stage, stage_bits) \
2942 for (gl_shader_stage stage, \
2943 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2944 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2945 __tmp &= ~(1 << (stage)))
2947 struct anv_pipeline_bind_map
{
2948 unsigned char surface_sha1
[20];
2949 unsigned char sampler_sha1
[20];
2950 unsigned char push_sha1
[20];
2952 uint32_t surface_count
;
2953 uint32_t sampler_count
;
2955 struct anv_pipeline_binding
* surface_to_descriptor
;
2956 struct anv_pipeline_binding
* sampler_to_descriptor
;
2958 struct anv_push_range push_ranges
[4];
2961 struct anv_shader_bin_key
{
2966 struct anv_shader_bin
{
2969 const struct anv_shader_bin_key
*key
;
2971 struct anv_state kernel
;
2972 uint32_t kernel_size
;
2974 struct anv_state constant_data
;
2975 uint32_t constant_data_size
;
2977 const struct brw_stage_prog_data
*prog_data
;
2978 uint32_t prog_data_size
;
2980 struct brw_compile_stats stats
[3];
2983 struct nir_xfb_info
*xfb_info
;
2985 struct anv_pipeline_bind_map bind_map
;
2988 struct anv_shader_bin
*
2989 anv_shader_bin_create(struct anv_device
*device
,
2990 const void *key
, uint32_t key_size
,
2991 const void *kernel
, uint32_t kernel_size
,
2992 const void *constant_data
, uint32_t constant_data_size
,
2993 const struct brw_stage_prog_data
*prog_data
,
2994 uint32_t prog_data_size
, const void *prog_data_param
,
2995 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2996 const struct nir_xfb_info
*xfb_info
,
2997 const struct anv_pipeline_bind_map
*bind_map
);
3000 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3003 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3005 assert(shader
&& shader
->ref_cnt
>= 1);
3006 p_atomic_inc(&shader
->ref_cnt
);
3010 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3012 assert(shader
&& shader
->ref_cnt
>= 1);
3013 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3014 anv_shader_bin_destroy(device
, shader
);
3017 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
3018 #define MAX_PIPELINE_EXECUTABLES 7
3020 struct anv_pipeline_executable
{
3021 gl_shader_stage stage
;
3023 struct brw_compile_stats stats
;
3029 struct anv_pipeline
{
3030 struct anv_device
* device
;
3031 struct anv_batch batch
;
3032 uint32_t batch_data
[512];
3033 struct anv_reloc_list batch_relocs
;
3034 anv_cmd_dirty_mask_t dynamic_state_mask
;
3035 struct anv_dynamic_state dynamic_state
;
3039 VkPipelineCreateFlags flags
;
3040 struct anv_subpass
* subpass
;
3042 bool needs_data_cache
;
3044 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3046 uint32_t num_executables
;
3047 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
3050 const struct gen_l3_config
* l3_config
;
3051 uint32_t total_size
;
3054 VkShaderStageFlags active_stages
;
3055 struct anv_state blend_state
;
3058 struct anv_pipeline_vertex_binding
{
3061 uint32_t instance_divisor
;
3066 bool primitive_restart
;
3069 uint32_t cs_right_mask
;
3072 bool depth_test_enable
;
3073 bool writes_stencil
;
3074 bool stencil_test_enable
;
3075 bool depth_clamp_enable
;
3076 bool depth_clip_enable
;
3077 bool sample_shading_enable
;
3079 bool depth_bounds_test_enable
;
3083 uint32_t depth_stencil_state
[3];
3089 uint32_t wm_depth_stencil
[3];
3093 uint32_t wm_depth_stencil
[4];
3096 uint32_t interface_descriptor_data
[8];
3100 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3101 gl_shader_stage stage
)
3103 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3106 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3107 static inline const struct brw_##prefix##_prog_data * \
3108 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3110 if (anv_pipeline_has_stage(pipeline, stage)) { \
3111 return (const struct brw_##prefix##_prog_data *) \
3112 pipeline->shaders[stage]->prog_data; \
3118 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3119 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3120 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3121 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3122 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3123 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3125 static inline const struct brw_vue_prog_data
*
3126 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3128 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3129 return &get_gs_prog_data(pipeline
)->base
;
3130 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3131 return &get_tes_prog_data(pipeline
)->base
;
3133 return &get_vs_prog_data(pipeline
)->base
;
3137 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3138 struct anv_pipeline_cache
*cache
,
3139 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3140 const VkAllocationCallbacks
*alloc
);
3143 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3144 struct anv_pipeline_cache
*cache
,
3145 const VkComputePipelineCreateInfo
*info
,
3146 const struct anv_shader_module
*module
,
3147 const char *entrypoint
,
3148 const VkSpecializationInfo
*spec_info
);
3150 struct anv_format_plane
{
3151 enum isl_format isl_format
:16;
3152 struct isl_swizzle swizzle
;
3154 /* Whether this plane contains chroma channels */
3157 /* For downscaling of YUV planes */
3158 uint8_t denominator_scales
[2];
3160 /* How to map sampled ycbcr planes to a single 4 component element. */
3161 struct isl_swizzle ycbcr_swizzle
;
3163 /* What aspect is associated to this plane */
3164 VkImageAspectFlags aspect
;
3169 struct anv_format_plane planes
[3];
3175 static inline uint32_t
3176 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3177 VkImageAspectFlags aspect_mask
)
3179 switch (aspect_mask
) {
3180 case VK_IMAGE_ASPECT_COLOR_BIT
:
3181 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3182 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3184 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3185 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3188 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3190 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3193 /* Purposefully assert with depth/stencil aspects. */
3194 unreachable("invalid image aspect");
3198 static inline VkImageAspectFlags
3199 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3202 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3203 if (util_bitcount(image_aspects
) > 1)
3204 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3205 return VK_IMAGE_ASPECT_COLOR_BIT
;
3207 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3208 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3209 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3210 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3213 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3214 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3216 const struct anv_format
*
3217 anv_get_format(VkFormat format
);
3219 static inline uint32_t
3220 anv_get_format_planes(VkFormat vk_format
)
3222 const struct anv_format
*format
= anv_get_format(vk_format
);
3224 return format
!= NULL
? format
->n_planes
: 0;
3227 struct anv_format_plane
3228 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3229 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3231 static inline enum isl_format
3232 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3233 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3235 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3238 static inline struct isl_swizzle
3239 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3241 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3242 * RGB as RGBA for texturing
3244 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3245 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3247 /* But it doesn't matter what we render to that channel */
3248 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3254 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3257 * Subsurface of an anv_image.
3259 struct anv_surface
{
3260 /** Valid only if isl_surf::size_B > 0. */
3261 struct isl_surf isl
;
3264 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3270 VkImageType type
; /**< VkImageCreateInfo::imageType */
3271 /* The original VkFormat provided by the client. This may not match any
3272 * of the actual surface formats.
3275 const struct anv_format
*format
;
3277 VkImageAspectFlags aspects
;
3280 uint32_t array_size
;
3281 uint32_t samples
; /**< VkImageCreateInfo::samples */
3283 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3284 VkImageUsageFlags stencil_usage
;
3285 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3286 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3288 /** True if this is needs to be bound to an appropriately tiled BO.
3290 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3291 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3292 * we require a dedicated allocation so that we can know to allocate a
3295 bool needs_set_tiling
;
3298 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3299 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3301 uint64_t drm_format_mod
;
3306 /* Whether the image is made of several underlying buffer objects rather a
3307 * single one with different offsets.
3311 /* All the formats that can be used when creating views of this image
3312 * are CCS_E compatible.
3314 bool ccs_e_compatible
;
3316 /* Image was created with external format. */
3317 bool external_format
;
3322 * For each foo, anv_image::planes[x].surface is valid if and only if
3323 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3324 * to figure the number associated with a given aspect.
3326 * The hardware requires that the depth buffer and stencil buffer be
3327 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3328 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3329 * allocate the depth and stencil buffers as separate surfaces in the same
3334 * -----------------------
3336 * ----------------------- |
3337 * | shadow surface0 | |
3338 * ----------------------- | Plane 0
3339 * | aux surface0 | |
3340 * ----------------------- |
3341 * | fast clear colors0 | \|/
3342 * -----------------------
3344 * ----------------------- |
3345 * | shadow surface1 | |
3346 * ----------------------- | Plane 1
3347 * | aux surface1 | |
3348 * ----------------------- |
3349 * | fast clear colors1 | \|/
3350 * -----------------------
3353 * -----------------------
3357 * Offset of the entire plane (whenever the image is disjoint this is
3365 struct anv_surface surface
;
3368 * A surface which shadows the main surface and may have different
3369 * tiling. This is used for sampling using a tiling that isn't supported
3370 * for other operations.
3372 struct anv_surface shadow_surface
;
3375 * For color images, this is the aux usage for this image when not used
3376 * as a color attachment.
3378 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3379 * image has a HiZ buffer.
3381 enum isl_aux_usage aux_usage
;
3383 struct anv_surface aux_surface
;
3386 * Offset of the fast clear state (used to compute the
3387 * fast_clear_state_offset of the following planes).
3389 uint32_t fast_clear_state_offset
;
3392 * BO associated with this plane, set when bound.
3394 struct anv_address address
;
3397 * Address of the main surface used to fill the aux map table. This is
3398 * used at destruction of the image since the Vulkan spec does not
3399 * guarantee that the address.bo field we still be valid at destruction.
3401 uint64_t aux_map_surface_address
;
3404 * When destroying the image, also free the bo.
3410 /* The ordering of this enum is important */
3411 enum anv_fast_clear_type
{
3412 /** Image does not have/support any fast-clear blocks */
3413 ANV_FAST_CLEAR_NONE
= 0,
3414 /** Image has/supports fast-clear but only to the default value */
3415 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3416 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3417 ANV_FAST_CLEAR_ANY
= 2,
3420 /* Returns the number of auxiliary buffer levels attached to an image. */
3421 static inline uint8_t
3422 anv_image_aux_levels(const struct anv_image
* const image
,
3423 VkImageAspectFlagBits aspect
)
3425 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3427 /* The Gen12 CCS aux surface is represented with only one level. */
3428 const uint8_t aux_logical_levels
=
3429 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3430 image
->planes
[plane
].surface
.isl
.levels
:
3431 image
->planes
[plane
].aux_surface
.isl
.levels
;
3433 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3434 aux_logical_levels
: 0;
3437 /* Returns the number of auxiliary buffer layers attached to an image. */
3438 static inline uint32_t
3439 anv_image_aux_layers(const struct anv_image
* const image
,
3440 VkImageAspectFlagBits aspect
,
3441 const uint8_t miplevel
)
3445 /* The miplevel must exist in the main buffer. */
3446 assert(miplevel
< image
->levels
);
3448 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3449 /* There are no layers with auxiliary data because the miplevel has no
3454 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3456 /* The Gen12 CCS aux surface is represented with only one layer. */
3457 const struct isl_extent4d
*aux_logical_level0_px
=
3458 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3459 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3460 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3462 return MAX2(aux_logical_level0_px
->array_len
,
3463 aux_logical_level0_px
->depth
>> miplevel
);
3467 static inline struct anv_address
3468 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3469 const struct anv_image
*image
,
3470 VkImageAspectFlagBits aspect
)
3472 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3474 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3475 return anv_address_add(image
->planes
[plane
].address
,
3476 image
->planes
[plane
].fast_clear_state_offset
);
3479 static inline struct anv_address
3480 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3481 const struct anv_image
*image
,
3482 VkImageAspectFlagBits aspect
)
3484 struct anv_address addr
=
3485 anv_image_get_clear_color_addr(device
, image
, aspect
);
3487 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3488 device
->isl_dev
.ss
.clear_color_state_size
:
3489 device
->isl_dev
.ss
.clear_value_size
;
3490 return anv_address_add(addr
, clear_color_state_size
);
3493 static inline struct anv_address
3494 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3495 const struct anv_image
*image
,
3496 VkImageAspectFlagBits aspect
,
3497 uint32_t level
, uint32_t array_layer
)
3499 assert(level
< anv_image_aux_levels(image
, aspect
));
3500 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3501 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3502 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3504 struct anv_address addr
=
3505 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3506 addr
.offset
+= 4; /* Go past the fast clear type */
3508 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3509 for (uint32_t l
= 0; l
< level
; l
++)
3510 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3512 addr
.offset
+= level
* image
->array_size
* 4;
3514 addr
.offset
+= array_layer
* 4;
3516 assert(addr
.offset
<
3517 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3521 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3523 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3524 const struct anv_image
*image
)
3526 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3529 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3530 * struct. There's documentation which suggests that this feature actually
3531 * reduces performance on BDW, but it has only been observed to help so
3532 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3533 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3535 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3538 return image
->samples
== 1;
3542 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3543 const struct anv_image
*image
,
3546 return device
->info
.has_aux_map
&&
3547 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3551 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3552 const struct anv_image
*image
,
3553 VkImageAspectFlagBits aspect
,
3554 enum isl_aux_usage aux_usage
,
3556 uint32_t base_layer
,
3557 uint32_t layer_count
);
3560 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3561 const struct anv_image
*image
,
3562 VkImageAspectFlagBits aspect
,
3563 enum isl_aux_usage aux_usage
,
3564 enum isl_format format
, struct isl_swizzle swizzle
,
3565 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3566 VkRect2D area
, union isl_color_value clear_color
);
3568 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3569 const struct anv_image
*image
,
3570 VkImageAspectFlags aspects
,
3571 enum isl_aux_usage depth_aux_usage
,
3573 uint32_t base_layer
, uint32_t layer_count
,
3575 float depth_value
, uint8_t stencil_value
);
3577 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3578 const struct anv_image
*src_image
,
3579 enum isl_aux_usage src_aux_usage
,
3580 uint32_t src_level
, uint32_t src_base_layer
,
3581 const struct anv_image
*dst_image
,
3582 enum isl_aux_usage dst_aux_usage
,
3583 uint32_t dst_level
, uint32_t dst_base_layer
,
3584 VkImageAspectFlagBits aspect
,
3585 uint32_t src_x
, uint32_t src_y
,
3586 uint32_t dst_x
, uint32_t dst_y
,
3587 uint32_t width
, uint32_t height
,
3588 uint32_t layer_count
,
3589 enum blorp_filter filter
);
3591 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3592 const struct anv_image
*image
,
3593 VkImageAspectFlagBits aspect
, uint32_t level
,
3594 uint32_t base_layer
, uint32_t layer_count
,
3595 enum isl_aux_op hiz_op
);
3597 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3598 const struct anv_image
*image
,
3599 VkImageAspectFlags aspects
,
3601 uint32_t base_layer
, uint32_t layer_count
,
3602 VkRect2D area
, uint8_t stencil_value
);
3604 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3605 const struct anv_image
*image
,
3606 enum isl_format format
,
3607 VkImageAspectFlagBits aspect
,
3608 uint32_t base_layer
, uint32_t layer_count
,
3609 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3612 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3613 const struct anv_image
*image
,
3614 enum isl_format format
,
3615 VkImageAspectFlagBits aspect
, uint32_t level
,
3616 uint32_t base_layer
, uint32_t layer_count
,
3617 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3621 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3622 const struct anv_image
*image
,
3623 VkImageAspectFlagBits aspect
,
3624 uint32_t base_level
, uint32_t level_count
,
3625 uint32_t base_layer
, uint32_t layer_count
);
3628 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3629 const struct anv_image
*image
,
3630 const VkImageAspectFlagBits aspect
,
3631 const VkImageLayout layout
);
3633 enum anv_fast_clear_type
3634 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3635 const struct anv_image
* const image
,
3636 const VkImageAspectFlagBits aspect
,
3637 const VkImageLayout layout
);
3639 /* This is defined as a macro so that it works for both
3640 * VkImageSubresourceRange and VkImageSubresourceLayers
3642 #define anv_get_layerCount(_image, _range) \
3643 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3644 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3646 static inline uint32_t
3647 anv_get_levelCount(const struct anv_image
*image
,
3648 const VkImageSubresourceRange
*range
)
3650 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3651 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3654 static inline VkImageAspectFlags
3655 anv_image_expand_aspects(const struct anv_image
*image
,
3656 VkImageAspectFlags aspects
)
3658 /* If the underlying image has color plane aspects and
3659 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3660 * the underlying image. */
3661 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3662 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3663 return image
->aspects
;
3669 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3670 VkImageAspectFlags aspects2
)
3672 if (aspects1
== aspects2
)
3675 /* Only 1 color aspects are compatibles. */
3676 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3677 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3678 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3684 struct anv_image_view
{
3685 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3687 VkImageAspectFlags aspect_mask
;
3689 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3693 uint32_t image_plane
;
3695 struct isl_view isl
;
3698 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3699 * image layout of SHADER_READ_ONLY_OPTIMAL or
3700 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3702 struct anv_surface_state optimal_sampler_surface_state
;
3705 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3706 * image layout of GENERAL.
3708 struct anv_surface_state general_sampler_surface_state
;
3711 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3712 * states for write-only and readable, using the real format for
3713 * write-only and the lowered format for readable.
3715 struct anv_surface_state storage_surface_state
;
3716 struct anv_surface_state writeonly_storage_surface_state
;
3718 struct brw_image_param storage_image_param
;
3722 enum anv_image_view_state_flags
{
3723 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3724 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3727 void anv_image_fill_surface_state(struct anv_device
*device
,
3728 const struct anv_image
*image
,
3729 VkImageAspectFlagBits aspect
,
3730 const struct isl_view
*view
,
3731 isl_surf_usage_flags_t view_usage
,
3732 enum isl_aux_usage aux_usage
,
3733 const union isl_color_value
*clear_color
,
3734 enum anv_image_view_state_flags flags
,
3735 struct anv_surface_state
*state_inout
,
3736 struct brw_image_param
*image_param_out
);
3738 struct anv_image_create_info
{
3739 const VkImageCreateInfo
*vk_info
;
3741 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3742 isl_tiling_flags_t isl_tiling_flags
;
3744 /** These flags will be added to any derived from VkImageCreateInfo. */
3745 isl_surf_usage_flags_t isl_extra_usage_flags
;
3748 bool external_format
;
3751 VkResult
anv_image_create(VkDevice _device
,
3752 const struct anv_image_create_info
*info
,
3753 const VkAllocationCallbacks
* alloc
,
3756 const struct anv_surface
*
3757 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3758 VkImageAspectFlags aspect_mask
);
3761 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3763 static inline struct VkExtent3D
3764 anv_sanitize_image_extent(const VkImageType imageType
,
3765 const struct VkExtent3D imageExtent
)
3767 switch (imageType
) {
3768 case VK_IMAGE_TYPE_1D
:
3769 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3770 case VK_IMAGE_TYPE_2D
:
3771 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3772 case VK_IMAGE_TYPE_3D
:
3775 unreachable("invalid image type");
3779 static inline struct VkOffset3D
3780 anv_sanitize_image_offset(const VkImageType imageType
,
3781 const struct VkOffset3D imageOffset
)
3783 switch (imageType
) {
3784 case VK_IMAGE_TYPE_1D
:
3785 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3786 case VK_IMAGE_TYPE_2D
:
3787 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3788 case VK_IMAGE_TYPE_3D
:
3791 unreachable("invalid image type");
3795 VkFormatFeatureFlags
3796 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3798 const struct anv_format
*anv_format
,
3799 VkImageTiling vk_tiling
);
3801 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3802 struct anv_state state
,
3803 enum isl_format format
,
3804 struct anv_address address
,
3805 uint32_t range
, uint32_t stride
);
3808 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3809 const struct anv_attachment_state
*att_state
,
3810 const struct anv_image_view
*iview
)
3812 const struct isl_format_layout
*view_fmtl
=
3813 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3815 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3816 if (view_fmtl->channels.c.bits) \
3817 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3819 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3820 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3821 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3822 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3824 #undef COPY_CLEAR_COLOR_CHANNEL
3828 struct anv_ycbcr_conversion
{
3829 const struct anv_format
* format
;
3830 VkSamplerYcbcrModelConversion ycbcr_model
;
3831 VkSamplerYcbcrRange ycbcr_range
;
3832 VkComponentSwizzle mapping
[4];
3833 VkChromaLocation chroma_offsets
[2];
3834 VkFilter chroma_filter
;
3835 bool chroma_reconstruction
;
3838 struct anv_sampler
{
3839 uint32_t state
[3][4];
3841 struct anv_ycbcr_conversion
*conversion
;
3843 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3844 * and with a 32-byte stride for use as bindless samplers.
3846 struct anv_state bindless_state
;
3849 struct anv_framebuffer
{
3854 uint32_t attachment_count
;
3855 struct anv_image_view
* attachments
[0];
3858 struct anv_subpass_attachment
{
3859 VkImageUsageFlagBits usage
;
3860 uint32_t attachment
;
3861 VkImageLayout layout
;
3863 /* Used only with attachment containing stencil data. */
3864 VkImageLayout stencil_layout
;
3867 struct anv_subpass
{
3868 uint32_t attachment_count
;
3871 * A pointer to all attachment references used in this subpass.
3872 * Only valid if ::attachment_count > 0.
3874 struct anv_subpass_attachment
* attachments
;
3875 uint32_t input_count
;
3876 struct anv_subpass_attachment
* input_attachments
;
3877 uint32_t color_count
;
3878 struct anv_subpass_attachment
* color_attachments
;
3879 struct anv_subpass_attachment
* resolve_attachments
;
3881 struct anv_subpass_attachment
* depth_stencil_attachment
;
3882 struct anv_subpass_attachment
* ds_resolve_attachment
;
3883 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3884 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3888 /** Subpass has a depth/stencil self-dependency */
3889 bool has_ds_self_dep
;
3891 /** Subpass has at least one color resolve attachment */
3892 bool has_color_resolve
;
3895 static inline unsigned
3896 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3898 return MAX2(1, util_bitcount(subpass
->view_mask
));
3901 struct anv_render_pass_attachment
{
3902 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3903 * its members individually.
3907 VkImageUsageFlags usage
;
3908 VkAttachmentLoadOp load_op
;
3909 VkAttachmentStoreOp store_op
;
3910 VkAttachmentLoadOp stencil_load_op
;
3911 VkImageLayout initial_layout
;
3912 VkImageLayout final_layout
;
3913 VkImageLayout first_subpass_layout
;
3915 VkImageLayout stencil_initial_layout
;
3916 VkImageLayout stencil_final_layout
;
3918 /* The subpass id in which the attachment will be used last. */
3919 uint32_t last_subpass_idx
;
3922 struct anv_render_pass
{
3923 uint32_t attachment_count
;
3924 uint32_t subpass_count
;
3925 /* An array of subpass_count+1 flushes, one per subpass boundary */
3926 enum anv_pipe_bits
* subpass_flushes
;
3927 struct anv_render_pass_attachment
* attachments
;
3928 struct anv_subpass subpasses
[0];
3931 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3933 struct anv_query_pool
{
3935 VkQueryPipelineStatisticFlags pipeline_statistics
;
3936 /** Stride between slots, in bytes */
3938 /** Number of slots in this query pool */
3943 int anv_get_instance_entrypoint_index(const char *name
);
3944 int anv_get_device_entrypoint_index(const char *name
);
3945 int anv_get_physical_device_entrypoint_index(const char *name
);
3947 const char *anv_get_instance_entry_name(int index
);
3948 const char *anv_get_physical_device_entry_name(int index
);
3949 const char *anv_get_device_entry_name(int index
);
3952 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3953 const struct anv_instance_extension_table
*instance
);
3955 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3956 const struct anv_instance_extension_table
*instance
);
3958 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3959 const struct anv_instance_extension_table
*instance
,
3960 const struct anv_device_extension_table
*device
);
3962 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3965 void anv_dump_image_to_ppm(struct anv_device
*device
,
3966 struct anv_image
*image
, unsigned miplevel
,
3967 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3968 const char *filename
);
3970 enum anv_dump_action
{
3971 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3974 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3975 void anv_dump_finish(void);
3977 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3979 static inline uint32_t
3980 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3982 /* This function must be called from within a subpass. */
3983 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3985 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3987 /* The id of this subpass shouldn't exceed the number of subpasses in this
3988 * render pass minus 1.
3990 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3994 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
3995 void anv_device_perf_init(struct anv_device
*device
);
3997 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3999 static inline struct __anv_type * \
4000 __anv_type ## _from_handle(__VkType _handle) \
4002 return (struct __anv_type *) _handle; \
4005 static inline __VkType \
4006 __anv_type ## _to_handle(struct __anv_type *_obj) \
4008 return (__VkType) _obj; \
4011 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4013 static inline struct __anv_type * \
4014 __anv_type ## _from_handle(__VkType _handle) \
4016 return (struct __anv_type *)(uintptr_t) _handle; \
4019 static inline __VkType \
4020 __anv_type ## _to_handle(struct __anv_type *_obj) \
4022 return (__VkType)(uintptr_t) _obj; \
4025 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4026 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4028 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4029 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4030 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4031 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4032 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4034 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4035 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4036 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4037 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4038 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4039 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4040 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4041 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4042 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4043 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4044 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4045 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4046 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4047 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4048 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4049 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4050 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4051 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4052 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4053 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4054 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4055 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4056 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4058 /* Gen-specific function declarations */
4060 # include "anv_genX.h"
4062 # define genX(x) gen7_##x
4063 # include "anv_genX.h"
4065 # define genX(x) gen75_##x
4066 # include "anv_genX.h"
4068 # define genX(x) gen8_##x
4069 # include "anv_genX.h"
4071 # define genX(x) gen9_##x
4072 # include "anv_genX.h"
4074 # define genX(x) gen10_##x
4075 # include "anv_genX.h"
4077 # define genX(x) gen11_##x
4078 # include "anv_genX.h"
4080 # define genX(x) gen12_##x
4081 # include "anv_genX.h"
4085 #endif /* ANV_PRIVATE_H */