projects / mesa.git / blob
? search:


d7a04438165d409e3756114159023716a7817e72
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "dev/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 /* Pre-declarations needed for WSI entrypoints */
56 struct wl_surface;
57 struct wl_display;
58 typedef struct xcb_connection_t xcb_connection_t;
59 typedef uint32_t xcb_visualid_t;
60 typedef uint32_t xcb_window_t;
61
62 struct anv_buffer;
63 struct anv_buffer_view;
64 struct anv_image_view;
65 struct anv_instance;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "anv_extensions.h"
76 #include "isl/isl.h"
77
78 #include "common/gen_debug.h"
79 #include "common/intel_log.h"
80 #include "wsi_common.h"
81
82 /* Allowing different clear colors requires us to perform a depth resolve at
83 * the end of certain render passes. This is because while slow clears store
84 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
85 * See the PRMs for examples describing when additional resolves would be
86 * necessary. To enable fast clears without requiring extra resolves, we set
87 * the clear value to a globally-defined one. We could allow different values
88 * if the user doesn't expect coherent data during or after a render passes
89 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
90 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
91 * 1.0f seems to be the only value used. The only application that doesn't set
92 * this value does so through the usage of an seemingly uninitialized clear
93 * value.
94 */
95 #define ANV_HZ_FC_VAL 1.0f
96
97 #define MAX_VBS 28
98 #define MAX_SETS 8
99 #define MAX_RTS 8
100 #define MAX_VIEWPORTS 16
101 #define MAX_SCISSORS 16
102 #define MAX_PUSH_CONSTANTS_SIZE 128
103 #define MAX_DYNAMIC_BUFFERS 16
104 #define MAX_IMAGES 8
105 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
106
107 /* The kernel relocation API has a limitation of a 32-bit delta value
108 * applied to the address before it is written which, in spite of it being
109 * unsigned, is treated as signed . Because of the way that this maps to
110 * the Vulkan API, we cannot handle an offset into a buffer that does not
111 * fit into a signed 32 bits. The only mechanism we have for dealing with
112 * this at the moment is to limit all VkDeviceMemory objects to a maximum
113 * of 2GB each. The Vulkan spec allows us to do this:
114 *
115 * "Some platforms may have a limit on the maximum size of a single
116 * allocation. For example, certain systems may fail to create
117 * allocations with a size greater than or equal to 4GB. Such a limit is
118 * implementation-dependent, and if such a failure occurs then the error
119 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
120 *
121 * We don't use vk_error here because it's not an error so much as an
122 * indication to the application that the allocation is too large.
123 */
124 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
125
126 #define ANV_SVGS_VB_INDEX MAX_VBS
127 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
128
129 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
130
131 static inline uint32_t
132 align_down_npot_u32(uint32_t v, uint32_t a)
133 {
134 return v - (v % a);
135 }
136
137 static inline uint32_t
138 align_u32(uint32_t v, uint32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 static inline uint64_t
145 align_u64(uint64_t v, uint64_t a)
146 {
147 assert(a != 0 && a == (a & -a));
148 return (v + a - 1) & ~(a - 1);
149 }
150
151 static inline int32_t
152 align_i32(int32_t v, int32_t a)
153 {
154 assert(a != 0 && a == (a & -a));
155 return (v + a - 1) & ~(a - 1);
156 }
157
158 /** Alignment must be a power of 2. */
159 static inline bool
160 anv_is_aligned(uintmax_t n, uintmax_t a)
161 {
162 assert(a == (a & -a));
163 return (n & (a - 1)) == 0;
164 }
165
166 static inline uint32_t
167 anv_minify(uint32_t n, uint32_t levels)
168 {
169 if (unlikely(n == 0))
170 return 0;
171 else
172 return MAX2(n >> levels, 1);
173 }
174
175 static inline float
176 anv_clamp_f(float f, float min, float max)
177 {
178 assert(min < max);
179
180 if (f > max)
181 return max;
182 else if (f < min)
183 return min;
184 else
185 return f;
186 }
187
188 static inline bool
189 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
190 {
191 if (*inout_mask & clear_mask) {
192 *inout_mask &= ~clear_mask;
193 return true;
194 } else {
195 return false;
196 }
197 }
198
199 static inline union isl_color_value
200 vk_to_isl_color(VkClearColorValue color)
201 {
202 return (union isl_color_value) {
203 .u32 = {
204 color.uint32[0],
205 color.uint32[1],
206 color.uint32[2],
207 color.uint32[3],
208 },
209 };
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
223 * to be added here in order to utilize mapping in debug/error/perf macros.
224 */
225 #define REPORT_OBJECT_TYPE(o) \
226 __builtin_choose_expr ( \
227 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
228 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
229 __builtin_choose_expr ( \
230 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
231 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
232 __builtin_choose_expr ( \
233 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
234 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
235 __builtin_choose_expr ( \
236 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
237 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
238 __builtin_choose_expr ( \
239 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
240 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
241 __builtin_choose_expr ( \
242 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
243 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
244 __builtin_choose_expr ( \
245 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
246 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
247 __builtin_choose_expr ( \
248 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
249 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
250 __builtin_choose_expr ( \
251 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
252 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
253 __builtin_choose_expr ( \
254 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
255 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
256 __builtin_choose_expr ( \
257 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
258 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
259 __builtin_choose_expr ( \
260 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
261 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
262 __builtin_choose_expr ( \
263 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
264 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
265 __builtin_choose_expr ( \
266 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
267 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
268 __builtin_choose_expr ( \
269 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
270 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
271 __builtin_choose_expr ( \
272 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
273 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
274 __builtin_choose_expr ( \
275 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
276 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
277 __builtin_choose_expr ( \
278 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
279 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
280 __builtin_choose_expr ( \
281 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
282 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
283 __builtin_choose_expr ( \
284 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
285 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
286 __builtin_choose_expr ( \
287 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
288 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
289 __builtin_choose_expr ( \
290 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
291 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
292 __builtin_choose_expr ( \
293 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
294 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
295 __builtin_choose_expr ( \
296 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
297 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
298 __builtin_choose_expr ( \
299 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
300 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
301 __builtin_choose_expr ( \
302 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
303 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), void*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
319 /* The void expression results in a compile-time error \
320 when assigning the result to something. */ \
321 (void)0)))))))))))))))))))))))))))))))
322
323 /* Whenever we generate an error, pass it through this function. Useful for
324 * debugging, where we can break on it. Only call at error site, not when
325 * propagating errors. Might be useful to plug in a stack trace here.
326 */
327
328 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
329 VkDebugReportObjectTypeEXT type, VkResult error,
330 const char *file, int line, const char *format, ...);
331
332 #ifdef DEBUG
333 #define vk_error(error) __vk_errorf(NULL, NULL,\
334 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
335 error, __FILE__, __LINE__, NULL)
336 #define vk_errorf(instance, obj, error, format, ...)\
337 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
338 __FILE__, __LINE__, format, ## __VA_ARGS__)
339 #else
340 #define vk_error(error) error
341 #define vk_errorf(instance, obj, error, format, ...) error
342 #endif
343
344 /**
345 * Warn on ignored extension structs.
346 *
347 * The Vulkan spec requires us to ignore unsupported or unknown structs in
348 * a pNext chain. In debug mode, emitting warnings for ignored structs may
349 * help us discover structs that we should not have ignored.
350 *
351 *
352 * From the Vulkan 1.0.38 spec:
353 *
354 * Any component of the implementation (the loader, any enabled layers,
355 * and drivers) must skip over, without processing (other than reading the
356 * sType and pNext members) any chained structures with sType values not
357 * defined by extensions supported by that component.
358 */
359 #define anv_debug_ignored_stype(sType) \
360 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
361
362 void __anv_perf_warn(struct anv_instance *instance, const void *object,
363 VkDebugReportObjectTypeEXT type, const char *file,
364 int line, const char *format, ...)
365 anv_printflike(6, 7);
366 void anv_loge(const char *format, ...) anv_printflike(1, 2);
367 void anv_loge_v(const char *format, va_list va);
368
369 /**
370 * Print a FINISHME message, including its source location.
371 */
372 #define anv_finishme(format, ...) \
373 do { \
374 static bool reported = false; \
375 if (!reported) { \
376 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
377 ##__VA_ARGS__); \
378 reported = true; \
379 } \
380 } while (0)
381
382 /**
383 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
384 */
385 #define anv_perf_warn(instance, obj, format, ...) \
386 do { \
387 static bool reported = false; \
388 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
389 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
390 format, ##__VA_ARGS__); \
391 reported = true; \
392 } \
393 } while (0)
394
395 /* A non-fatal assert. Useful for debugging. */
396 #ifdef DEBUG
397 #define anv_assert(x) ({ \
398 if (unlikely(!(x))) \
399 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
400 })
401 #else
402 #define anv_assert(x)
403 #endif
404
405 /* A multi-pointer allocator
406 *
407 * When copying data structures from the user (such as a render pass), it's
408 * common to need to allocate data for a bunch of different things. Instead
409 * of doing several allocations and having to handle all of the error checking
410 * that entails, it can be easier to do a single allocation. This struct
411 * helps facilitate that. The intended usage looks like this:
412 *
413 * ANV_MULTIALLOC(ma)
414 * anv_multialloc_add(&ma, &main_ptr, 1);
415 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
416 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
417 *
418 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
419 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
420 */
421 struct anv_multialloc {
422 size_t size;
423 size_t align;
424
425 uint32_t ptr_count;
426 void **ptrs[8];
427 };
428
429 #define ANV_MULTIALLOC_INIT \
430 ((struct anv_multialloc) { 0, })
431
432 #define ANV_MULTIALLOC(_name) \
433 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
434
435 __attribute__((always_inline))
436 static inline void
437 _anv_multialloc_add(struct anv_multialloc *ma,
438 void **ptr, size_t size, size_t align)
439 {
440 size_t offset = align_u64(ma->size, align);
441 ma->size = offset + size;
442 ma->align = MAX2(ma->align, align);
443
444 /* Store the offset in the pointer. */
445 *ptr = (void *)(uintptr_t)offset;
446
447 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
448 ma->ptrs[ma->ptr_count++] = ptr;
449 }
450
451 #define anv_multialloc_add_size(_ma, _ptr, _size) \
452 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
453
454 #define anv_multialloc_add(_ma, _ptr, _count) \
455 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
456
457 __attribute__((always_inline))
458 static inline void *
459 anv_multialloc_alloc(struct anv_multialloc *ma,
460 const VkAllocationCallbacks *alloc,
461 VkSystemAllocationScope scope)
462 {
463 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
464 if (!ptr)
465 return NULL;
466
467 /* Fill out each of the pointers with their final value.
468 *
469 * for (uint32_t i = 0; i < ma->ptr_count; i++)
470 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
471 *
472 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
473 * constant, GCC is incapable of figuring this out and unrolling the loop
474 * so we have to give it a little help.
475 */
476 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
477 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
478 if ((_i) < ma->ptr_count) \
479 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
480 _ANV_MULTIALLOC_UPDATE_POINTER(0);
481 _ANV_MULTIALLOC_UPDATE_POINTER(1);
482 _ANV_MULTIALLOC_UPDATE_POINTER(2);
483 _ANV_MULTIALLOC_UPDATE_POINTER(3);
484 _ANV_MULTIALLOC_UPDATE_POINTER(4);
485 _ANV_MULTIALLOC_UPDATE_POINTER(5);
486 _ANV_MULTIALLOC_UPDATE_POINTER(6);
487 _ANV_MULTIALLOC_UPDATE_POINTER(7);
488 #undef _ANV_MULTIALLOC_UPDATE_POINTER
489
490 return ptr;
491 }
492
493 __attribute__((always_inline))
494 static inline void *
495 anv_multialloc_alloc2(struct anv_multialloc *ma,
496 const VkAllocationCallbacks *parent_alloc,
497 const VkAllocationCallbacks *alloc,
498 VkSystemAllocationScope scope)
499 {
500 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
501 }
502
503 struct anv_bo {
504 uint32_t gem_handle;
505
506 /* Index into the current validation list. This is used by the
507 * validation list building alrogithm to track which buffers are already
508 * in the validation list so that we can ensure uniqueness.
509 */
510 uint32_t index;
511
512 /* Last known offset. This value is provided by the kernel when we
513 * execbuf and is used as the presumed offset for the next bunch of
514 * relocations.
515 */
516 uint64_t offset;
517
518 uint64_t size;
519 void *map;
520
521 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
522 uint32_t flags;
523 };
524
525 static inline void
526 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
527 {
528 bo->gem_handle = gem_handle;
529 bo->index = 0;
530 bo->offset = -1;
531 bo->size = size;
532 bo->map = NULL;
533 bo->flags = 0;
534 }
535
536 /* Represents a lock-free linked list of "free" things. This is used by
537 * both the block pool and the state pools. Unfortunately, in order to
538 * solve the ABA problem, we can't use a single uint32_t head.
539 */
540 union anv_free_list {
541 struct {
542 int32_t offset;
543
544 /* A simple count that is incremented every time the head changes. */
545 uint32_t count;
546 };
547 uint64_t u64;
548 };
549
550 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
551
552 struct anv_block_state {
553 union {
554 struct {
555 uint32_t next;
556 uint32_t end;
557 };
558 uint64_t u64;
559 };
560 };
561
562 struct anv_block_pool {
563 struct anv_device *device;
564
565 uint64_t bo_flags;
566
567 struct anv_bo bo;
568
569 /* The offset from the start of the bo to the "center" of the block
570 * pool. Pointers to allocated blocks are given by
571 * bo.map + center_bo_offset + offsets.
572 */
573 uint32_t center_bo_offset;
574
575 /* Current memory map of the block pool. This pointer may or may not
576 * point to the actual beginning of the block pool memory. If
577 * anv_block_pool_alloc_back has ever been called, then this pointer
578 * will point to the "center" position of the buffer and all offsets
579 * (negative or positive) given out by the block pool alloc functions
580 * will be valid relative to this pointer.
581 *
582 * In particular, map == bo.map + center_offset
583 */
584 void *map;
585 int fd;
586
587 /**
588 * Array of mmaps and gem handles owned by the block pool, reclaimed when
589 * the block pool is destroyed.
590 */
591 struct u_vector mmap_cleanups;
592
593 struct anv_block_state state;
594
595 struct anv_block_state back_state;
596 };
597
598 /* Block pools are backed by a fixed-size 1GB memfd */
599 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
600
601 /* The center of the block pool is also the middle of the memfd. This may
602 * change in the future if we decide differently for some reason.
603 */
604 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
605
606 static inline uint32_t
607 anv_block_pool_size(struct anv_block_pool *pool)
608 {
609 return pool->state.end + pool->back_state.end;
610 }
611
612 struct anv_state {
613 int32_t offset;
614 uint32_t alloc_size;
615 void *map;
616 };
617
618 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
619
620 struct anv_fixed_size_state_pool {
621 union anv_free_list free_list;
622 struct anv_block_state block;
623 };
624
625 #define ANV_MIN_STATE_SIZE_LOG2 6
626 #define ANV_MAX_STATE_SIZE_LOG2 20
627
628 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
629
630 struct anv_state_pool {
631 struct anv_block_pool block_pool;
632
633 /* The size of blocks which will be allocated from the block pool */
634 uint32_t block_size;
635
636 /** Free list for "back" allocations */
637 union anv_free_list back_alloc_free_list;
638
639 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
640 };
641
642 struct anv_state_stream_block;
643
644 struct anv_state_stream {
645 struct anv_state_pool *state_pool;
646
647 /* The size of blocks to allocate from the state pool */
648 uint32_t block_size;
649
650 /* Current block we're allocating from */
651 struct anv_state block;
652
653 /* Offset into the current block at which to allocate the next state */
654 uint32_t next;
655
656 /* List of all blocks allocated from this pool */
657 struct anv_state_stream_block *block_list;
658 };
659
660 /* The block_pool functions exported for testing only. The block pool should
661 * only be used via a state pool (see below).
662 */
663 VkResult anv_block_pool_init(struct anv_block_pool *pool,
664 struct anv_device *device,
665 uint32_t initial_size,
666 uint64_t bo_flags);
667 void anv_block_pool_finish(struct anv_block_pool *pool);
668 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
669 uint32_t block_size);
670 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
671 uint32_t block_size);
672
673 VkResult anv_state_pool_init(struct anv_state_pool *pool,
674 struct anv_device *device,
675 uint32_t block_size,
676 uint64_t bo_flags);
677 void anv_state_pool_finish(struct anv_state_pool *pool);
678 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
679 uint32_t state_size, uint32_t alignment);
680 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
681 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
682 void anv_state_stream_init(struct anv_state_stream *stream,
683 struct anv_state_pool *state_pool,
684 uint32_t block_size);
685 void anv_state_stream_finish(struct anv_state_stream *stream);
686 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
687 uint32_t size, uint32_t alignment);
688
689 /**
690 * Implements a pool of re-usable BOs. The interface is identical to that
691 * of block_pool except that each block is its own BO.
692 */
693 struct anv_bo_pool {
694 struct anv_device *device;
695
696 uint64_t bo_flags;
697
698 void *free_list[16];
699 };
700
701 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
702 uint64_t bo_flags);
703 void anv_bo_pool_finish(struct anv_bo_pool *pool);
704 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
705 uint32_t size);
706 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
707
708 struct anv_scratch_bo {
709 bool exists;
710 struct anv_bo bo;
711 };
712
713 struct anv_scratch_pool {
714 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
715 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
716 };
717
718 void anv_scratch_pool_init(struct anv_device *device,
719 struct anv_scratch_pool *pool);
720 void anv_scratch_pool_finish(struct anv_device *device,
721 struct anv_scratch_pool *pool);
722 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
723 struct anv_scratch_pool *pool,
724 gl_shader_stage stage,
725 unsigned per_thread_scratch);
726
727 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
728 struct anv_bo_cache {
729 struct hash_table *bo_map;
730 pthread_mutex_t mutex;
731 };
732
733 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
734 void anv_bo_cache_finish(struct anv_bo_cache *cache);
735 VkResult anv_bo_cache_alloc(struct anv_device *device,
736 struct anv_bo_cache *cache,
737 uint64_t size, struct anv_bo **bo);
738 VkResult anv_bo_cache_import(struct anv_device *device,
739 struct anv_bo_cache *cache,
740 int fd, struct anv_bo **bo);
741 VkResult anv_bo_cache_export(struct anv_device *device,
742 struct anv_bo_cache *cache,
743 struct anv_bo *bo_in, int *fd_out);
744 void anv_bo_cache_release(struct anv_device *device,
745 struct anv_bo_cache *cache,
746 struct anv_bo *bo);
747
748 struct anv_memory_type {
749 /* Standard bits passed on to the client */
750 VkMemoryPropertyFlags propertyFlags;
751 uint32_t heapIndex;
752
753 /* Driver-internal book-keeping */
754 VkBufferUsageFlags valid_buffer_usage;
755 };
756
757 struct anv_memory_heap {
758 /* Standard bits passed on to the client */
759 VkDeviceSize size;
760 VkMemoryHeapFlags flags;
761
762 /* Driver-internal book-keeping */
763 bool supports_48bit_addresses;
764 };
765
766 struct anv_physical_device {
767 VK_LOADER_DATA _loader_data;
768
769 struct anv_instance * instance;
770 uint32_t chipset_id;
771 bool no_hw;
772 char path[20];
773 const char * name;
774 struct gen_device_info info;
775 /** Amount of "GPU memory" we want to advertise
776 *
777 * Clearly, this value is bogus since Intel is a UMA architecture. On
778 * gen7 platforms, we are limited by GTT size unless we want to implement
779 * fine-grained tracking and GTT splitting. On Broadwell and above we are
780 * practically unlimited. However, we will never report more than 3/4 of
781 * the total system ram to try and avoid running out of RAM.
782 */
783 bool supports_48bit_addresses;
784 struct brw_compiler * compiler;
785 struct isl_device isl_dev;
786 int cmd_parser_version;
787 bool has_exec_async;
788 bool has_exec_capture;
789 bool has_exec_fence;
790 bool has_syncobj;
791 bool has_syncobj_wait;
792 bool has_context_priority;
793
794 struct anv_device_extension_table supported_extensions;
795
796 uint32_t eu_total;
797 uint32_t subslice_total;
798
799 struct {
800 uint32_t type_count;
801 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
802 uint32_t heap_count;
803 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
804 } memory;
805
806 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
807 uint8_t driver_uuid[VK_UUID_SIZE];
808 uint8_t device_uuid[VK_UUID_SIZE];
809
810 struct wsi_device wsi_device;
811 int local_fd;
812 };
813
814 struct anv_instance {
815 VK_LOADER_DATA _loader_data;
816
817 VkAllocationCallbacks alloc;
818
819 uint32_t apiVersion;
820 struct anv_instance_extension_table enabled_extensions;
821 struct anv_dispatch_table dispatch;
822
823 int physicalDeviceCount;
824 struct anv_physical_device physicalDevice;
825
826 struct vk_debug_report_instance debug_report_callbacks;
827 };
828
829 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
830 void anv_finish_wsi(struct anv_physical_device *physical_device);
831
832 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
833 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
834 const char *name);
835
836 struct anv_queue {
837 VK_LOADER_DATA _loader_data;
838
839 struct anv_device * device;
840
841 struct anv_state_pool * pool;
842
843 VkDeviceQueueCreateFlags flags;
844 };
845
846 struct anv_pipeline_cache {
847 struct anv_device * device;
848 pthread_mutex_t mutex;
849
850 struct hash_table * cache;
851 };
852
853 struct anv_pipeline_bind_map;
854
855 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
856 struct anv_device *device,
857 bool cache_enabled);
858 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
859
860 struct anv_shader_bin *
861 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
862 const void *key, uint32_t key_size);
863 struct anv_shader_bin *
864 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
865 const void *key_data, uint32_t key_size,
866 const void *kernel_data, uint32_t kernel_size,
867 const struct brw_stage_prog_data *prog_data,
868 uint32_t prog_data_size,
869 const struct anv_pipeline_bind_map *bind_map);
870
871 struct anv_device {
872 VK_LOADER_DATA _loader_data;
873
874 VkAllocationCallbacks alloc;
875
876 struct anv_instance * instance;
877 uint32_t chipset_id;
878 bool no_hw;
879 struct gen_device_info info;
880 struct isl_device isl_dev;
881 int context_id;
882 int fd;
883 bool can_chain_batches;
884 bool robust_buffer_access;
885 struct anv_device_extension_table enabled_extensions;
886 struct anv_dispatch_table dispatch;
887
888 struct anv_bo_pool batch_bo_pool;
889
890 struct anv_bo_cache bo_cache;
891
892 struct anv_state_pool dynamic_state_pool;
893 struct anv_state_pool instruction_state_pool;
894 struct anv_state_pool surface_state_pool;
895
896 struct anv_bo workaround_bo;
897 struct anv_bo trivial_batch_bo;
898
899 struct anv_pipeline_cache blorp_shader_cache;
900 struct blorp_context blorp;
901
902 struct anv_state border_colors;
903
904 struct anv_queue queue;
905
906 struct anv_scratch_pool scratch_pool;
907
908 uint32_t default_mocs;
909
910 pthread_mutex_t mutex;
911 pthread_cond_t queue_submit;
912 bool lost;
913 };
914
915 static void inline
916 anv_state_flush(struct anv_device *device, struct anv_state state)
917 {
918 if (device->info.has_llc)
919 return;
920
921 gen_flush_range(state.map, state.alloc_size);
922 }
923
924 void anv_device_init_blorp(struct anv_device *device);
925 void anv_device_finish_blorp(struct anv_device *device);
926
927 VkResult anv_device_execbuf(struct anv_device *device,
928 struct drm_i915_gem_execbuffer2 *execbuf,
929 struct anv_bo **execbuf_bos);
930 VkResult anv_device_query_status(struct anv_device *device);
931 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
932 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
933 int64_t timeout);
934
935 void* anv_gem_mmap(struct anv_device *device,
936 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
937 void anv_gem_munmap(void *p, uint64_t size);
938 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
939 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
940 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
941 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
942 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
943 int anv_gem_execbuffer(struct anv_device *device,
944 struct drm_i915_gem_execbuffer2 *execbuf);
945 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
946 uint32_t stride, uint32_t tiling);
947 int anv_gem_create_context(struct anv_device *device);
948 bool anv_gem_has_context_priority(int fd);
949 int anv_gem_destroy_context(struct anv_device *device, int context);
950 int anv_gem_set_context_param(int fd, int context, uint32_t param,
951 uint64_t value);
952 int anv_gem_get_context_param(int fd, int context, uint32_t param,
953 uint64_t *value);
954 int anv_gem_get_param(int fd, uint32_t param);
955 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
956 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
957 int anv_gem_get_aperture(int fd, uint64_t *size);
958 bool anv_gem_supports_48b_addresses(int fd);
959 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
960 uint32_t *active, uint32_t *pending);
961 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
962 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
963 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
964 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
965 uint32_t read_domains, uint32_t write_domain);
966 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
967 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
968 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
969 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
970 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
971 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
972 uint32_t handle);
973 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
974 uint32_t handle, int fd);
975 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
976 bool anv_gem_supports_syncobj_wait(int fd);
977 int anv_gem_syncobj_wait(struct anv_device *device,
978 uint32_t *handles, uint32_t num_handles,
979 int64_t abs_timeout_ns, bool wait_all);
980
981 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
982
983 struct anv_reloc_list {
984 uint32_t num_relocs;
985 uint32_t array_length;
986 struct drm_i915_gem_relocation_entry * relocs;
987 struct anv_bo ** reloc_bos;
988 };
989
990 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
991 const VkAllocationCallbacks *alloc);
992 void anv_reloc_list_finish(struct anv_reloc_list *list,
993 const VkAllocationCallbacks *alloc);
994
995 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
996 const VkAllocationCallbacks *alloc,
997 uint32_t offset, struct anv_bo *target_bo,
998 uint32_t delta);
999
1000 struct anv_batch_bo {
1001 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1002 struct list_head link;
1003
1004 struct anv_bo bo;
1005
1006 /* Bytes actually consumed in this batch BO */
1007 uint32_t length;
1008
1009 struct anv_reloc_list relocs;
1010 };
1011
1012 struct anv_batch {
1013 const VkAllocationCallbacks * alloc;
1014
1015 void * start;
1016 void * end;
1017 void * next;
1018
1019 struct anv_reloc_list * relocs;
1020
1021 /* This callback is called (with the associated user data) in the event
1022 * that the batch runs out of space.
1023 */
1024 VkResult (*extend_cb)(struct anv_batch *, void *);
1025 void * user_data;
1026
1027 /**
1028 * Current error status of the command buffer. Used to track inconsistent
1029 * or incomplete command buffer states that are the consequence of run-time
1030 * errors such as out of memory scenarios. We want to track this in the
1031 * batch because the command buffer object is not visible to some parts
1032 * of the driver.
1033 */
1034 VkResult status;
1035 };
1036
1037 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1038 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1039 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1040 void *location, struct anv_bo *bo, uint32_t offset);
1041 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1042 struct anv_batch *batch);
1043
1044 static inline VkResult
1045 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1046 {
1047 assert(error != VK_SUCCESS);
1048 if (batch->status == VK_SUCCESS)
1049 batch->status = error;
1050 return batch->status;
1051 }
1052
1053 static inline bool
1054 anv_batch_has_error(struct anv_batch *batch)
1055 {
1056 return batch->status != VK_SUCCESS;
1057 }
1058
1059 struct anv_address {
1060 struct anv_bo *bo;
1061 uint32_t offset;
1062 };
1063
1064 static inline uint64_t
1065 _anv_combine_address(struct anv_batch *batch, void *location,
1066 const struct anv_address address, uint32_t delta)
1067 {
1068 if (address.bo == NULL) {
1069 return address.offset + delta;
1070 } else {
1071 assert(batch->start <= location && location < batch->end);
1072
1073 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1074 }
1075 }
1076
1077 #define __gen_address_type struct anv_address
1078 #define __gen_user_data struct anv_batch
1079 #define __gen_combine_address _anv_combine_address
1080
1081 /* Wrapper macros needed to work around preprocessor argument issues. In
1082 * particular, arguments don't get pre-evaluated if they are concatenated.
1083 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1084 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1085 * We can work around this easily enough with these helpers.
1086 */
1087 #define __anv_cmd_length(cmd) cmd ## _length
1088 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1089 #define __anv_cmd_header(cmd) cmd ## _header
1090 #define __anv_cmd_pack(cmd) cmd ## _pack
1091 #define __anv_reg_num(reg) reg ## _num
1092
1093 #define anv_pack_struct(dst, struc, ...) do { \
1094 struct struc __template = { \
1095 __VA_ARGS__ \
1096 }; \
1097 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1098 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1099 } while (0)
1100
1101 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1102 void *__dst = anv_batch_emit_dwords(batch, n); \
1103 if (__dst) { \
1104 struct cmd __template = { \
1105 __anv_cmd_header(cmd), \
1106 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1107 __VA_ARGS__ \
1108 }; \
1109 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1110 } \
1111 __dst; \
1112 })
1113
1114 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1115 do { \
1116 uint32_t *dw; \
1117 \
1118 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1119 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1120 if (!dw) \
1121 break; \
1122 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1123 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1124 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1125 } while (0)
1126
1127 #define anv_batch_emit(batch, cmd, name) \
1128 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1129 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1130 __builtin_expect(_dst != NULL, 1); \
1131 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1132 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1133 _dst = NULL; \
1134 }))
1135
1136 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1137 .GraphicsDataTypeGFDT = 0, \
1138 .LLCCacheabilityControlLLCCC = 0, \
1139 .L3CacheabilityControlL3CC = 1, \
1140 }
1141
1142 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1143 .LLCeLLCCacheabilityControlLLCCC = 0, \
1144 .L3CacheabilityControlL3CC = 1, \
1145 }
1146
1147 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1148 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1149 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1150 .AgeforQUADLRU = 0 \
1151 }
1152
1153 /* Skylake: MOCS is now an index into an array of 62 different caching
1154 * configurations programmed by the kernel.
1155 */
1156
1157 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1158 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1159 .IndextoMOCSTables = 2 \
1160 }
1161
1162 #define GEN9_MOCS_PTE { \
1163 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1164 .IndextoMOCSTables = 1 \
1165 }
1166
1167 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1168 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1169 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1170 .IndextoMOCSTables = 2 \
1171 }
1172
1173 #define GEN10_MOCS_PTE { \
1174 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1175 .IndextoMOCSTables = 1 \
1176 }
1177
1178 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1179 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1180 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1181 .IndextoMOCSTables = 2 \
1182 }
1183
1184 #define GEN11_MOCS_PTE { \
1185 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1186 .IndextoMOCSTables = 1 \
1187 }
1188
1189 struct anv_device_memory {
1190 struct anv_bo * bo;
1191 struct anv_memory_type * type;
1192 VkDeviceSize map_size;
1193 void * map;
1194 };
1195
1196 /**
1197 * Header for Vertex URB Entry (VUE)
1198 */
1199 struct anv_vue_header {
1200 uint32_t Reserved;
1201 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1202 uint32_t ViewportIndex;
1203 float PointWidth;
1204 };
1205
1206 struct anv_descriptor_set_binding_layout {
1207 #ifndef NDEBUG
1208 /* The type of the descriptors in this binding */
1209 VkDescriptorType type;
1210 #endif
1211
1212 /* Number of array elements in this binding */
1213 uint16_t array_size;
1214
1215 /* Index into the flattend descriptor set */
1216 uint16_t descriptor_index;
1217
1218 /* Index into the dynamic state array for a dynamic buffer */
1219 int16_t dynamic_offset_index;
1220
1221 /* Index into the descriptor set buffer views */
1222 int16_t buffer_index;
1223
1224 struct {
1225 /* Index into the binding table for the associated surface */
1226 int16_t surface_index;
1227
1228 /* Index into the sampler table for the associated sampler */
1229 int16_t sampler_index;
1230
1231 /* Index into the image table for the associated image */
1232 int16_t image_index;
1233 } stage[MESA_SHADER_STAGES];
1234
1235 /* Immutable samplers (or NULL if no immutable samplers) */
1236 struct anv_sampler **immutable_samplers;
1237 };
1238
1239 struct anv_descriptor_set_layout {
1240 /* Descriptor set layouts can be destroyed at almost any time */
1241 uint32_t ref_cnt;
1242
1243 /* Number of bindings in this descriptor set */
1244 uint16_t binding_count;
1245
1246 /* Total size of the descriptor set with room for all array entries */
1247 uint16_t size;
1248
1249 /* Shader stages affected by this descriptor set */
1250 uint16_t shader_stages;
1251
1252 /* Number of buffers in this descriptor set */
1253 uint16_t buffer_count;
1254
1255 /* Number of dynamic offsets used by this descriptor set */
1256 uint16_t dynamic_offset_count;
1257
1258 /* Bindings in this descriptor set */
1259 struct anv_descriptor_set_binding_layout binding[0];
1260 };
1261
1262 static inline void
1263 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1264 {
1265 assert(layout && layout->ref_cnt >= 1);
1266 p_atomic_inc(&layout->ref_cnt);
1267 }
1268
1269 static inline void
1270 anv_descriptor_set_layout_unref(struct anv_device *device,
1271 struct anv_descriptor_set_layout *layout)
1272 {
1273 assert(layout && layout->ref_cnt >= 1);
1274 if (p_atomic_dec_zero(&layout->ref_cnt))
1275 vk_free(&device->alloc, layout);
1276 }
1277
1278 struct anv_descriptor {
1279 VkDescriptorType type;
1280
1281 union {
1282 struct {
1283 VkImageLayout layout;
1284 struct anv_image_view *image_view;
1285 struct anv_sampler *sampler;
1286 };
1287
1288 struct {
1289 struct anv_buffer *buffer;
1290 uint64_t offset;
1291 uint64_t range;
1292 };
1293
1294 struct anv_buffer_view *buffer_view;
1295 };
1296 };
1297
1298 struct anv_descriptor_set {
1299 struct anv_descriptor_set_layout *layout;
1300 uint32_t size;
1301 uint32_t buffer_count;
1302 struct anv_buffer_view *buffer_views;
1303 struct anv_descriptor descriptors[0];
1304 };
1305
1306 struct anv_buffer_view {
1307 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1308 struct anv_bo *bo;
1309 uint32_t offset; /**< Offset into bo. */
1310 uint64_t range; /**< VkBufferViewCreateInfo::range */
1311
1312 struct anv_state surface_state;
1313 struct anv_state storage_surface_state;
1314 struct anv_state writeonly_storage_surface_state;
1315
1316 struct brw_image_param storage_image_param;
1317 };
1318
1319 struct anv_push_descriptor_set {
1320 struct anv_descriptor_set set;
1321
1322 /* Put this field right behind anv_descriptor_set so it fills up the
1323 * descriptors[0] field. */
1324 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1325 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1326 };
1327
1328 struct anv_descriptor_pool {
1329 uint32_t size;
1330 uint32_t next;
1331 uint32_t free_list;
1332
1333 struct anv_state_stream surface_state_stream;
1334 void *surface_state_free_list;
1335
1336 char data[0];
1337 };
1338
1339 enum anv_descriptor_template_entry_type {
1340 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1341 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1342 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1343 };
1344
1345 struct anv_descriptor_template_entry {
1346 /* The type of descriptor in this entry */
1347 VkDescriptorType type;
1348
1349 /* Binding in the descriptor set */
1350 uint32_t binding;
1351
1352 /* Offset at which to write into the descriptor set binding */
1353 uint32_t array_element;
1354
1355 /* Number of elements to write into the descriptor set binding */
1356 uint32_t array_count;
1357
1358 /* Offset into the user provided data */
1359 size_t offset;
1360
1361 /* Stride between elements into the user provided data */
1362 size_t stride;
1363 };
1364
1365 struct anv_descriptor_update_template {
1366 VkPipelineBindPoint bind_point;
1367
1368 /* The descriptor set this template corresponds to. This value is only
1369 * valid if the template was created with the templateType
1370 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1371 */
1372 uint8_t set;
1373
1374 /* Number of entries in this template */
1375 uint32_t entry_count;
1376
1377 /* Entries of the template */
1378 struct anv_descriptor_template_entry entries[0];
1379 };
1380
1381 size_t
1382 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1383
1384 size_t
1385 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1386
1387 void
1388 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1389 const struct gen_device_info * const devinfo,
1390 const VkDescriptorImageInfo * const info,
1391 VkDescriptorType type,
1392 uint32_t binding,
1393 uint32_t element);
1394
1395 void
1396 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1397 VkDescriptorType type,
1398 struct anv_buffer_view *buffer_view,
1399 uint32_t binding,
1400 uint32_t element);
1401
1402 void
1403 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1404 struct anv_device *device,
1405 struct anv_state_stream *alloc_stream,
1406 VkDescriptorType type,
1407 struct anv_buffer *buffer,
1408 uint32_t binding,
1409 uint32_t element,
1410 VkDeviceSize offset,
1411 VkDeviceSize range);
1412
1413 void
1414 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1415 struct anv_device *device,
1416 struct anv_state_stream *alloc_stream,
1417 const struct anv_descriptor_update_template *template,
1418 const void *data);
1419
1420 VkResult
1421 anv_descriptor_set_create(struct anv_device *device,
1422 struct anv_descriptor_pool *pool,
1423 struct anv_descriptor_set_layout *layout,
1424 struct anv_descriptor_set **out_set);
1425
1426 void
1427 anv_descriptor_set_destroy(struct anv_device *device,
1428 struct anv_descriptor_pool *pool,
1429 struct anv_descriptor_set *set);
1430
1431 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1432
1433 struct anv_pipeline_binding {
1434 /* The descriptor set this surface corresponds to. The special value of
1435 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1436 * to a color attachment and not a regular descriptor.
1437 */
1438 uint8_t set;
1439
1440 /* Binding in the descriptor set */
1441 uint32_t binding;
1442
1443 /* Index in the binding */
1444 uint32_t index;
1445
1446 /* Plane in the binding index */
1447 uint8_t plane;
1448
1449 /* Input attachment index (relative to the subpass) */
1450 uint8_t input_attachment_index;
1451
1452 /* For a storage image, whether it is write-only */
1453 bool write_only;
1454 };
1455
1456 struct anv_pipeline_layout {
1457 struct {
1458 struct anv_descriptor_set_layout *layout;
1459 uint32_t dynamic_offset_start;
1460 } set[MAX_SETS];
1461
1462 uint32_t num_sets;
1463
1464 struct {
1465 bool has_dynamic_offsets;
1466 } stage[MESA_SHADER_STAGES];
1467
1468 unsigned char sha1[20];
1469 };
1470
1471 struct anv_buffer {
1472 struct anv_device * device;
1473 VkDeviceSize size;
1474
1475 VkBufferUsageFlags usage;
1476
1477 /* Set when bound */
1478 struct anv_bo * bo;
1479 VkDeviceSize offset;
1480 };
1481
1482 static inline uint64_t
1483 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1484 {
1485 assert(offset <= buffer->size);
1486 if (range == VK_WHOLE_SIZE) {
1487 return buffer->size - offset;
1488 } else {
1489 assert(range <= buffer->size);
1490 return range;
1491 }
1492 }
1493
1494 enum anv_cmd_dirty_bits {
1495 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1496 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1497 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1498 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1499 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1500 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1501 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1502 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1503 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1504 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1505 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1506 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1507 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1508 };
1509 typedef uint32_t anv_cmd_dirty_mask_t;
1510
1511 enum anv_pipe_bits {
1512 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1513 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1514 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1515 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1516 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1517 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1518 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1519 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1520 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1521 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1522 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1523
1524 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1525 * a flush has happened but not a CS stall. The next time we do any sort
1526 * of invalidation we need to insert a CS stall at that time. Otherwise,
1527 * we would have to CS stall on every flush which could be bad.
1528 */
1529 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1530 };
1531
1532 #define ANV_PIPE_FLUSH_BITS ( \
1533 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1534 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1535 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1536
1537 #define ANV_PIPE_STALL_BITS ( \
1538 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1539 ANV_PIPE_DEPTH_STALL_BIT | \
1540 ANV_PIPE_CS_STALL_BIT)
1541
1542 #define ANV_PIPE_INVALIDATE_BITS ( \
1543 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1544 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1545 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1546 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1547 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1548 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1549
1550 static inline enum anv_pipe_bits
1551 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1552 {
1553 enum anv_pipe_bits pipe_bits = 0;
1554
1555 unsigned b;
1556 for_each_bit(b, flags) {
1557 switch ((VkAccessFlagBits)(1 << b)) {
1558 case VK_ACCESS_SHADER_WRITE_BIT:
1559 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1560 break;
1561 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1562 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1563 break;
1564 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1565 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1566 break;
1567 case VK_ACCESS_TRANSFER_WRITE_BIT:
1568 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1569 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1570 break;
1571 default:
1572 break; /* Nothing to do */
1573 }
1574 }
1575
1576 return pipe_bits;
1577 }
1578
1579 static inline enum anv_pipe_bits
1580 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1581 {
1582 enum anv_pipe_bits pipe_bits = 0;
1583
1584 unsigned b;
1585 for_each_bit(b, flags) {
1586 switch ((VkAccessFlagBits)(1 << b)) {
1587 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1588 case VK_ACCESS_INDEX_READ_BIT:
1589 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1590 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1591 break;
1592 case VK_ACCESS_UNIFORM_READ_BIT:
1593 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1594 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1595 break;
1596 case VK_ACCESS_SHADER_READ_BIT:
1597 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1598 case VK_ACCESS_TRANSFER_READ_BIT:
1599 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1600 break;
1601 default:
1602 break; /* Nothing to do */
1603 }
1604 }
1605
1606 return pipe_bits;
1607 }
1608
1609 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1610 VK_IMAGE_ASPECT_COLOR_BIT | \
1611 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1612 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1613 VK_IMAGE_ASPECT_PLANE_2_BIT)
1614 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1615 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1616 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1617 VK_IMAGE_ASPECT_PLANE_2_BIT)
1618
1619 struct anv_vertex_binding {
1620 struct anv_buffer * buffer;
1621 VkDeviceSize offset;
1622 };
1623
1624 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1625 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1626
1627 struct anv_push_constants {
1628 /* Current allocated size of this push constants data structure.
1629 * Because a decent chunk of it may not be used (images on SKL, for
1630 * instance), we won't actually allocate the entire structure up-front.
1631 */
1632 uint32_t size;
1633
1634 /* Push constant data provided by the client through vkPushConstants */
1635 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1636
1637 /* Used for vkCmdDispatchBase */
1638 uint32_t base_work_group_id[3];
1639
1640 /* Image data for image_load_store on pre-SKL */
1641 struct brw_image_param images[MAX_IMAGES];
1642 };
1643
1644 struct anv_dynamic_state {
1645 struct {
1646 uint32_t count;
1647 VkViewport viewports[MAX_VIEWPORTS];
1648 } viewport;
1649
1650 struct {
1651 uint32_t count;
1652 VkRect2D scissors[MAX_SCISSORS];
1653 } scissor;
1654
1655 float line_width;
1656
1657 struct {
1658 float bias;
1659 float clamp;
1660 float slope;
1661 } depth_bias;
1662
1663 float blend_constants[4];
1664
1665 struct {
1666 float min;
1667 float max;
1668 } depth_bounds;
1669
1670 struct {
1671 uint32_t front;
1672 uint32_t back;
1673 } stencil_compare_mask;
1674
1675 struct {
1676 uint32_t front;
1677 uint32_t back;
1678 } stencil_write_mask;
1679
1680 struct {
1681 uint32_t front;
1682 uint32_t back;
1683 } stencil_reference;
1684 };
1685
1686 extern const struct anv_dynamic_state default_dynamic_state;
1687
1688 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1689 const struct anv_dynamic_state *src,
1690 uint32_t copy_mask);
1691
1692 struct anv_surface_state {
1693 struct anv_state state;
1694 /** Address of the surface referred to by this state
1695 *
1696 * This address is relative to the start of the BO.
1697 */
1698 uint64_t address;
1699 /* Address of the aux surface, if any
1700 *
1701 * This field is 0 if and only if no aux surface exists.
1702 *
1703 * This address is relative to the start of the BO. With the exception of
1704 * gen8, the bottom 12 bits of this address include extra aux information.
1705 */
1706 uint64_t aux_address;
1707 };
1708
1709 /**
1710 * Attachment state when recording a renderpass instance.
1711 *
1712 * The clear value is valid only if there exists a pending clear.
1713 */
1714 struct anv_attachment_state {
1715 enum isl_aux_usage aux_usage;
1716 enum isl_aux_usage input_aux_usage;
1717 struct anv_surface_state color;
1718 struct anv_surface_state input;
1719
1720 VkImageLayout current_layout;
1721 VkImageAspectFlags pending_clear_aspects;
1722 VkImageAspectFlags pending_load_aspects;
1723 bool fast_clear;
1724 VkClearValue clear_value;
1725 bool clear_color_is_zero_one;
1726 bool clear_color_is_zero;
1727
1728 /* When multiview is active, attachments with a renderpass clear
1729 * operation have their respective layers cleared on the first
1730 * subpass that uses them, and only in that subpass. We keep track
1731 * of this using a bitfield to indicate which layers of an attachment
1732 * have not been cleared yet when multiview is active.
1733 */
1734 uint32_t pending_clear_views;
1735 };
1736
1737 /** State tracking for particular pipeline bind point
1738 *
1739 * This struct is the base struct for anv_cmd_graphics_state and
1740 * anv_cmd_compute_state. These are used to track state which is bound to a
1741 * particular type of pipeline. Generic state that applies per-stage such as
1742 * binding table offsets and push constants is tracked generically with a
1743 * per-stage array in anv_cmd_state.
1744 */
1745 struct anv_cmd_pipeline_state {
1746 struct anv_pipeline *pipeline;
1747 struct anv_pipeline_layout *layout;
1748
1749 struct anv_descriptor_set *descriptors[MAX_SETS];
1750 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1751
1752 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
1753 };
1754
1755 /** State tracking for graphics pipeline
1756 *
1757 * This has anv_cmd_pipeline_state as a base struct to track things which get
1758 * bound to a graphics pipeline. Along with general pipeline bind point state
1759 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1760 * state which is graphics-specific.
1761 */
1762 struct anv_cmd_graphics_state {
1763 struct anv_cmd_pipeline_state base;
1764
1765 anv_cmd_dirty_mask_t dirty;
1766 uint32_t vb_dirty;
1767
1768 struct anv_dynamic_state dynamic;
1769
1770 struct {
1771 struct anv_buffer *index_buffer;
1772 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1773 uint32_t index_offset;
1774 } gen7;
1775 };
1776
1777 /** State tracking for compute pipeline
1778 *
1779 * This has anv_cmd_pipeline_state as a base struct to track things which get
1780 * bound to a compute pipeline. Along with general pipeline bind point state
1781 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1782 * state which is compute-specific.
1783 */
1784 struct anv_cmd_compute_state {
1785 struct anv_cmd_pipeline_state base;
1786
1787 bool pipeline_dirty;
1788
1789 struct anv_address num_workgroups;
1790 };
1791
1792 /** State required while building cmd buffer */
1793 struct anv_cmd_state {
1794 /* PIPELINE_SELECT.PipelineSelection */
1795 uint32_t current_pipeline;
1796 const struct gen_l3_config * current_l3_config;
1797
1798 struct anv_cmd_graphics_state gfx;
1799 struct anv_cmd_compute_state compute;
1800
1801 enum anv_pipe_bits pending_pipe_bits;
1802 VkShaderStageFlags descriptors_dirty;
1803 VkShaderStageFlags push_constants_dirty;
1804
1805 struct anv_framebuffer * framebuffer;
1806 struct anv_render_pass * pass;
1807 struct anv_subpass * subpass;
1808 VkRect2D render_area;
1809 uint32_t restart_index;
1810 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1811 VkShaderStageFlags push_constant_stages;
1812 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1813 struct anv_state binding_tables[MESA_SHADER_STAGES];
1814 struct anv_state samplers[MESA_SHADER_STAGES];
1815
1816 /**
1817 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1818 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1819 * and before invoking the secondary in ExecuteCommands.
1820 */
1821 bool pma_fix_enabled;
1822
1823 /**
1824 * Whether or not we know for certain that HiZ is enabled for the current
1825 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1826 * enabled or not, this will be false.
1827 */
1828 bool hiz_enabled;
1829
1830 /**
1831 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1832 * valid only when recording a render pass instance.
1833 */
1834 struct anv_attachment_state * attachments;
1835
1836 /**
1837 * Surface states for color render targets. These are stored in a single
1838 * flat array. For depth-stencil attachments, the surface state is simply
1839 * left blank.
1840 */
1841 struct anv_state render_pass_states;
1842
1843 /**
1844 * A null surface state of the right size to match the framebuffer. This
1845 * is one of the states in render_pass_states.
1846 */
1847 struct anv_state null_surface_state;
1848 };
1849
1850 struct anv_cmd_pool {
1851 VkAllocationCallbacks alloc;
1852 struct list_head cmd_buffers;
1853 };
1854
1855 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1856
1857 enum anv_cmd_buffer_exec_mode {
1858 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1859 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1860 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1861 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1862 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1863 };
1864
1865 struct anv_cmd_buffer {
1866 VK_LOADER_DATA _loader_data;
1867
1868 struct anv_device * device;
1869
1870 struct anv_cmd_pool * pool;
1871 struct list_head pool_link;
1872
1873 struct anv_batch batch;
1874
1875 /* Fields required for the actual chain of anv_batch_bo's.
1876 *
1877 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1878 */
1879 struct list_head batch_bos;
1880 enum anv_cmd_buffer_exec_mode exec_mode;
1881
1882 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1883 * referenced by this command buffer
1884 *
1885 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1886 */
1887 struct u_vector seen_bbos;
1888
1889 /* A vector of int32_t's for every block of binding tables.
1890 *
1891 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1892 */
1893 struct u_vector bt_block_states;
1894 uint32_t bt_next;
1895
1896 struct anv_reloc_list surface_relocs;
1897 /** Last seen surface state block pool center bo offset */
1898 uint32_t last_ss_pool_center;
1899
1900 /* Serial for tracking buffer completion */
1901 uint32_t serial;
1902
1903 /* Stream objects for storing temporary data */
1904 struct anv_state_stream surface_state_stream;
1905 struct anv_state_stream dynamic_state_stream;
1906
1907 VkCommandBufferUsageFlags usage_flags;
1908 VkCommandBufferLevel level;
1909
1910 struct anv_cmd_state state;
1911 };
1912
1913 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1914 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1915 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1916 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1917 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1918 struct anv_cmd_buffer *secondary);
1919 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1920 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1921 struct anv_cmd_buffer *cmd_buffer,
1922 const VkSemaphore *in_semaphores,
1923 uint32_t num_in_semaphores,
1924 const VkSemaphore *out_semaphores,
1925 uint32_t num_out_semaphores,
1926 VkFence fence);
1927
1928 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1929
1930 VkResult
1931 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1932 gl_shader_stage stage, uint32_t size);
1933 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1934 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1935 (offsetof(struct anv_push_constants, field) + \
1936 sizeof(cmd_buffer->state.push_constants[0]->field)))
1937
1938 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1939 const void *data, uint32_t size, uint32_t alignment);
1940 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1941 uint32_t *a, uint32_t *b,
1942 uint32_t dwords, uint32_t alignment);
1943
1944 struct anv_address
1945 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1946 struct anv_state
1947 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1948 uint32_t entries, uint32_t *state_offset);
1949 struct anv_state
1950 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1951 struct anv_state
1952 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1953 uint32_t size, uint32_t alignment);
1954
1955 VkResult
1956 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1957
1958 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1959 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1960 bool depth_clamp_enable);
1961 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1962
1963 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1964 struct anv_render_pass *pass,
1965 struct anv_framebuffer *framebuffer,
1966 const VkClearValue *clear_values);
1967
1968 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1969
1970 struct anv_state
1971 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1972 gl_shader_stage stage);
1973 struct anv_state
1974 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1975
1976 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1977
1978 const struct anv_image_view *
1979 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1980
1981 VkResult
1982 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1983 uint32_t num_entries,
1984 uint32_t *state_offset,
1985 struct anv_state *bt_state);
1986
1987 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1988
1989 enum anv_fence_type {
1990 ANV_FENCE_TYPE_NONE = 0,
1991 ANV_FENCE_TYPE_BO,
1992 ANV_FENCE_TYPE_SYNCOBJ,
1993 };
1994
1995 enum anv_bo_fence_state {
1996 /** Indicates that this is a new (or newly reset fence) */
1997 ANV_BO_FENCE_STATE_RESET,
1998
1999 /** Indicates that this fence has been submitted to the GPU but is still
2000 * (as far as we know) in use by the GPU.
2001 */
2002 ANV_BO_FENCE_STATE_SUBMITTED,
2003
2004 ANV_BO_FENCE_STATE_SIGNALED,
2005 };
2006
2007 struct anv_fence_impl {
2008 enum anv_fence_type type;
2009
2010 union {
2011 /** Fence implementation for BO fences
2012 *
2013 * These fences use a BO and a set of CPU-tracked state flags. The BO
2014 * is added to the object list of the last execbuf call in a QueueSubmit
2015 * and is marked EXEC_WRITE. The state flags track when the BO has been
2016 * submitted to the kernel. We need to do this because Vulkan lets you
2017 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2018 * will say it's idle in this case.
2019 */
2020 struct {
2021 struct anv_bo bo;
2022 enum anv_bo_fence_state state;
2023 } bo;
2024
2025 /** DRM syncobj handle for syncobj-based fences */
2026 uint32_t syncobj;
2027 };
2028 };
2029
2030 struct anv_fence {
2031 /* Permanent fence state. Every fence has some form of permanent state
2032 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2033 * cross-process fences) or it could just be a dummy for use internally.
2034 */
2035 struct anv_fence_impl permanent;
2036
2037 /* Temporary fence state. A fence *may* have temporary state. That state
2038 * is added to the fence by an import operation and is reset back to
2039 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2040 * state cannot be signaled because the fence must already be signaled
2041 * before the temporary state can be exported from the fence in the other
2042 * process and imported here.
2043 */
2044 struct anv_fence_impl temporary;
2045 };
2046
2047 struct anv_event {
2048 uint64_t semaphore;
2049 struct anv_state state;
2050 };
2051
2052 enum anv_semaphore_type {
2053 ANV_SEMAPHORE_TYPE_NONE = 0,
2054 ANV_SEMAPHORE_TYPE_DUMMY,
2055 ANV_SEMAPHORE_TYPE_BO,
2056 ANV_SEMAPHORE_TYPE_SYNC_FILE,
2057 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
2058 };
2059
2060 struct anv_semaphore_impl {
2061 enum anv_semaphore_type type;
2062
2063 union {
2064 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2065 * This BO will be added to the object list on any execbuf2 calls for
2066 * which this semaphore is used as a wait or signal fence. When used as
2067 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2068 */
2069 struct anv_bo *bo;
2070
2071 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2072 * If the semaphore is in the unsignaled state due to either just being
2073 * created or because it has been used for a wait, fd will be -1.
2074 */
2075 int fd;
2076
2077 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2078 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2079 * import so we don't need to bother with a userspace cache.
2080 */
2081 uint32_t syncobj;
2082 };
2083 };
2084
2085 struct anv_semaphore {
2086 /* Permanent semaphore state. Every semaphore has some form of permanent
2087 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2088 * (for cross-process semaphores0 or it could just be a dummy for use
2089 * internally.
2090 */
2091 struct anv_semaphore_impl permanent;
2092
2093 /* Temporary semaphore state. A semaphore *may* have temporary state.
2094 * That state is added to the semaphore by an import operation and is reset
2095 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2096 * semaphore with temporary state cannot be signaled because the semaphore
2097 * must already be signaled before the temporary state can be exported from
2098 * the semaphore in the other process and imported here.
2099 */
2100 struct anv_semaphore_impl temporary;
2101 };
2102
2103 void anv_semaphore_reset_temporary(struct anv_device *device,
2104 struct anv_semaphore *semaphore);
2105
2106 struct anv_shader_module {
2107 unsigned char sha1[20];
2108 uint32_t size;
2109 char data[0];
2110 };
2111
2112 static inline gl_shader_stage
2113 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2114 {
2115 assert(__builtin_popcount(vk_stage) == 1);
2116 return ffs(vk_stage) - 1;
2117 }
2118
2119 static inline VkShaderStageFlagBits
2120 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2121 {
2122 return (1 << mesa_stage);
2123 }
2124
2125 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2126
2127 #define anv_foreach_stage(stage, stage_bits) \
2128 for (gl_shader_stage stage, \
2129 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2130 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2131 __tmp &= ~(1 << (stage)))
2132
2133 struct anv_pipeline_bind_map {
2134 uint32_t surface_count;
2135 uint32_t sampler_count;
2136 uint32_t image_count;
2137
2138 struct anv_pipeline_binding * surface_to_descriptor;
2139 struct anv_pipeline_binding * sampler_to_descriptor;
2140 };
2141
2142 struct anv_shader_bin_key {
2143 uint32_t size;
2144 uint8_t data[0];
2145 };
2146
2147 struct anv_shader_bin {
2148 uint32_t ref_cnt;
2149
2150 const struct anv_shader_bin_key *key;
2151
2152 struct anv_state kernel;
2153 uint32_t kernel_size;
2154
2155 const struct brw_stage_prog_data *prog_data;
2156 uint32_t prog_data_size;
2157
2158 struct anv_pipeline_bind_map bind_map;
2159 };
2160
2161 struct anv_shader_bin *
2162 anv_shader_bin_create(struct anv_device *device,
2163 const void *key, uint32_t key_size,
2164 const void *kernel, uint32_t kernel_size,
2165 const struct brw_stage_prog_data *prog_data,
2166 uint32_t prog_data_size, const void *prog_data_param,
2167 const struct anv_pipeline_bind_map *bind_map);
2168
2169 void
2170 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2171
2172 static inline void
2173 anv_shader_bin_ref(struct anv_shader_bin *shader)
2174 {
2175 assert(shader && shader->ref_cnt >= 1);
2176 p_atomic_inc(&shader->ref_cnt);
2177 }
2178
2179 static inline void
2180 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2181 {
2182 assert(shader && shader->ref_cnt >= 1);
2183 if (p_atomic_dec_zero(&shader->ref_cnt))
2184 anv_shader_bin_destroy(device, shader);
2185 }
2186
2187 struct anv_pipeline {
2188 struct anv_device * device;
2189 struct anv_batch batch;
2190 uint32_t batch_data[512];
2191 struct anv_reloc_list batch_relocs;
2192 uint32_t dynamic_state_mask;
2193 struct anv_dynamic_state dynamic_state;
2194
2195 struct anv_subpass * subpass;
2196
2197 bool needs_data_cache;
2198
2199 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2200
2201 struct {
2202 const struct gen_l3_config * l3_config;
2203 uint32_t total_size;
2204 } urb;
2205
2206 VkShaderStageFlags active_stages;
2207 struct anv_state blend_state;
2208
2209 uint32_t vb_used;
2210 uint32_t binding_stride[MAX_VBS];
2211 bool instancing_enable[MAX_VBS];
2212 bool primitive_restart;
2213 uint32_t topology;
2214
2215 uint32_t cs_right_mask;
2216
2217 bool writes_depth;
2218 bool depth_test_enable;
2219 bool writes_stencil;
2220 bool stencil_test_enable;
2221 bool depth_clamp_enable;
2222 bool sample_shading_enable;
2223 bool kill_pixel;
2224
2225 struct {
2226 uint32_t sf[7];
2227 uint32_t depth_stencil_state[3];
2228 } gen7;
2229
2230 struct {
2231 uint32_t sf[4];
2232 uint32_t raster[5];
2233 uint32_t wm_depth_stencil[3];
2234 } gen8;
2235
2236 struct {
2237 uint32_t wm_depth_stencil[4];
2238 } gen9;
2239
2240 uint32_t interface_descriptor_data[8];
2241 };
2242
2243 static inline bool
2244 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2245 gl_shader_stage stage)
2246 {
2247 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2248 }
2249
2250 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2251 static inline const struct brw_##prefix##_prog_data * \
2252 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2253 { \
2254 if (anv_pipeline_has_stage(pipeline, stage)) { \
2255 return (const struct brw_##prefix##_prog_data *) \
2256 pipeline->shaders[stage]->prog_data; \
2257 } else { \
2258 return NULL; \
2259 } \
2260 }
2261
2262 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2263 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2264 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2265 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2266 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2267 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2268
2269 static inline const struct brw_vue_prog_data *
2270 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2271 {
2272 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2273 return &get_gs_prog_data(pipeline)->base;
2274 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2275 return &get_tes_prog_data(pipeline)->base;
2276 else
2277 return &get_vs_prog_data(pipeline)->base;
2278 }
2279
2280 VkResult
2281 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2282 struct anv_pipeline_cache *cache,
2283 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2284 const VkAllocationCallbacks *alloc);
2285
2286 VkResult
2287 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2288 struct anv_pipeline_cache *cache,
2289 const VkComputePipelineCreateInfo *info,
2290 struct anv_shader_module *module,
2291 const char *entrypoint,
2292 const VkSpecializationInfo *spec_info);
2293
2294 struct anv_format_plane {
2295 enum isl_format isl_format:16;
2296 struct isl_swizzle swizzle;
2297
2298 /* Whether this plane contains chroma channels */
2299 bool has_chroma;
2300
2301 /* For downscaling of YUV planes */
2302 uint8_t denominator_scales[2];
2303
2304 /* How to map sampled ycbcr planes to a single 4 component element. */
2305 struct isl_swizzle ycbcr_swizzle;
2306 };
2307
2308
2309 struct anv_format {
2310 struct anv_format_plane planes[3];
2311 uint8_t n_planes;
2312 bool can_ycbcr;
2313 };
2314
2315 static inline uint32_t
2316 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2317 VkImageAspectFlags aspect_mask)
2318 {
2319 switch (aspect_mask) {
2320 case VK_IMAGE_ASPECT_COLOR_BIT:
2321 case VK_IMAGE_ASPECT_DEPTH_BIT:
2322 case VK_IMAGE_ASPECT_PLANE_0_BIT:
2323 return 0;
2324 case VK_IMAGE_ASPECT_STENCIL_BIT:
2325 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2326 return 0;
2327 /* Fall-through */
2328 case VK_IMAGE_ASPECT_PLANE_1_BIT:
2329 return 1;
2330 case VK_IMAGE_ASPECT_PLANE_2_BIT:
2331 return 2;
2332 default:
2333 /* Purposefully assert with depth/stencil aspects. */
2334 unreachable("invalid image aspect");
2335 }
2336 }
2337
2338 static inline uint32_t
2339 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2340 {
2341 uint32_t planes = 0;
2342
2343 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2344 VK_IMAGE_ASPECT_DEPTH_BIT |
2345 VK_IMAGE_ASPECT_STENCIL_BIT |
2346 VK_IMAGE_ASPECT_PLANE_0_BIT))
2347 planes++;
2348 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT)
2349 planes++;
2350 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT)
2351 planes++;
2352
2353 return planes;
2354 }
2355
2356 static inline VkImageAspectFlags
2357 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2358 uint32_t plane)
2359 {
2360 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2361 if (_mesa_bitcount(image_aspects) > 1)
2362 return VK_IMAGE_ASPECT_PLANE_0_BIT << plane;
2363 return VK_IMAGE_ASPECT_COLOR_BIT;
2364 }
2365 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2366 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2367 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2368 return VK_IMAGE_ASPECT_STENCIL_BIT;
2369 }
2370
2371 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2372 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2373
2374 const struct anv_format *
2375 anv_get_format(VkFormat format);
2376
2377 static inline uint32_t
2378 anv_get_format_planes(VkFormat vk_format)
2379 {
2380 const struct anv_format *format = anv_get_format(vk_format);
2381
2382 return format != NULL ? format->n_planes : 0;
2383 }
2384
2385 struct anv_format_plane
2386 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2387 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2388
2389 static inline enum isl_format
2390 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2391 VkImageAspectFlags aspect, VkImageTiling tiling)
2392 {
2393 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2394 }
2395
2396 static inline struct isl_swizzle
2397 anv_swizzle_for_render(struct isl_swizzle swizzle)
2398 {
2399 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2400 * RGB as RGBA for texturing
2401 */
2402 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2403 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2404
2405 /* But it doesn't matter what we render to that channel */
2406 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2407
2408 return swizzle;
2409 }
2410
2411 void
2412 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2413
2414 /**
2415 * Subsurface of an anv_image.
2416 */
2417 struct anv_surface {
2418 /** Valid only if isl_surf::size > 0. */
2419 struct isl_surf isl;
2420
2421 /**
2422 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2423 */
2424 uint32_t offset;
2425 };
2426
2427 struct anv_image {
2428 VkImageType type;
2429 /* The original VkFormat provided by the client. This may not match any
2430 * of the actual surface formats.
2431 */
2432 VkFormat vk_format;
2433 const struct anv_format *format;
2434
2435 VkImageAspectFlags aspects;
2436 VkExtent3D extent;
2437 uint32_t levels;
2438 uint32_t array_size;
2439 uint32_t samples; /**< VkImageCreateInfo::samples */
2440 uint32_t n_planes;
2441 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2442 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2443
2444 /** True if this is needs to be bound to an appropriately tiled BO.
2445 *
2446 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2447 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2448 * we require a dedicated allocation so that we can know to allocate a
2449 * tiled buffer.
2450 */
2451 bool needs_set_tiling;
2452
2453 /**
2454 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2455 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2456 */
2457 uint64_t drm_format_mod;
2458
2459 VkDeviceSize size;
2460 uint32_t alignment;
2461
2462 /* Whether the image is made of several underlying buffer objects rather a
2463 * single one with different offsets.
2464 */
2465 bool disjoint;
2466
2467 /**
2468 * Image subsurfaces
2469 *
2470 * For each foo, anv_image::planes[x].surface is valid if and only if
2471 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2472 * to figure the number associated with a given aspect.
2473 *
2474 * The hardware requires that the depth buffer and stencil buffer be
2475 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2476 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2477 * allocate the depth and stencil buffers as separate surfaces in the same
2478 * bo.
2479 *
2480 * Memory layout :
2481 *
2482 * -----------------------
2483 * | surface0 | /|\
2484 * ----------------------- |
2485 * | shadow surface0 | |
2486 * ----------------------- | Plane 0
2487 * | aux surface0 | |
2488 * ----------------------- |
2489 * | fast clear colors0 | \|/
2490 * -----------------------
2491 * | surface1 | /|\
2492 * ----------------------- |
2493 * | shadow surface1 | |
2494 * ----------------------- | Plane 1
2495 * | aux surface1 | |
2496 * ----------------------- |
2497 * | fast clear colors1 | \|/
2498 * -----------------------
2499 * | ... |
2500 * | |
2501 * -----------------------
2502 */
2503 struct {
2504 /**
2505 * Offset of the entire plane (whenever the image is disjoint this is
2506 * set to 0).
2507 */
2508 uint32_t offset;
2509
2510 VkDeviceSize size;
2511 uint32_t alignment;
2512
2513 struct anv_surface surface;
2514
2515 /**
2516 * A surface which shadows the main surface and may have different
2517 * tiling. This is used for sampling using a tiling that isn't supported
2518 * for other operations.
2519 */
2520 struct anv_surface shadow_surface;
2521
2522 /**
2523 * For color images, this is the aux usage for this image when not used
2524 * as a color attachment.
2525 *
2526 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2527 * image has a HiZ buffer.
2528 */
2529 enum isl_aux_usage aux_usage;
2530
2531 struct anv_surface aux_surface;
2532
2533 /**
2534 * Offset of the fast clear state (used to compute the
2535 * fast_clear_state_offset of the following planes).
2536 */
2537 uint32_t fast_clear_state_offset;
2538
2539 /**
2540 * BO associated with this plane, set when bound.
2541 */
2542 struct anv_bo *bo;
2543 VkDeviceSize bo_offset;
2544
2545 /**
2546 * When destroying the image, also free the bo.
2547 * */
2548 bool bo_is_owned;
2549 } planes[3];
2550 };
2551
2552 /* The ordering of this enum is important */
2553 enum anv_fast_clear_type {
2554 /** Image does not have/support any fast-clear blocks */
2555 ANV_FAST_CLEAR_NONE = 0,
2556 /** Image has/supports fast-clear but only to the default value */
2557 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
2558 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2559 ANV_FAST_CLEAR_ANY = 2,
2560 };
2561
2562 /* Returns the number of auxiliary buffer levels attached to an image. */
2563 static inline uint8_t
2564 anv_image_aux_levels(const struct anv_image * const image,
2565 VkImageAspectFlagBits aspect)
2566 {
2567 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2568 return image->planes[plane].aux_surface.isl.size > 0 ?
2569 image->planes[plane].aux_surface.isl.levels : 0;
2570 }
2571
2572 /* Returns the number of auxiliary buffer layers attached to an image. */
2573 static inline uint32_t
2574 anv_image_aux_layers(const struct anv_image * const image,
2575 VkImageAspectFlagBits aspect,
2576 const uint8_t miplevel)
2577 {
2578 assert(image);
2579
2580 /* The miplevel must exist in the main buffer. */
2581 assert(miplevel < image->levels);
2582
2583 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2584 /* There are no layers with auxiliary data because the miplevel has no
2585 * auxiliary data.
2586 */
2587 return 0;
2588 } else {
2589 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2590 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2591 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2592 }
2593 }
2594
2595 static inline struct anv_address
2596 anv_image_get_clear_color_addr(const struct anv_device *device,
2597 const struct anv_image *image,
2598 VkImageAspectFlagBits aspect)
2599 {
2600 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
2601
2602 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2603 return (struct anv_address) {
2604 .bo = image->planes[plane].bo,
2605 .offset = image->planes[plane].bo_offset +
2606 image->planes[plane].fast_clear_state_offset,
2607 };
2608 }
2609
2610 static inline struct anv_address
2611 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
2612 const struct anv_image *image,
2613 VkImageAspectFlagBits aspect)
2614 {
2615 struct anv_address addr =
2616 anv_image_get_clear_color_addr(device, image, aspect);
2617
2618 const unsigned clear_color_state_size = device->info.gen >= 10 ?
2619 device->isl_dev.ss.clear_color_state_size :
2620 device->isl_dev.ss.clear_value_size;
2621 addr.offset += clear_color_state_size;
2622 return addr;
2623 }
2624
2625 static inline struct anv_address
2626 anv_image_get_compression_state_addr(const struct anv_device *device,
2627 const struct anv_image *image,
2628 VkImageAspectFlagBits aspect,
2629 uint32_t level, uint32_t array_layer)
2630 {
2631 assert(level < anv_image_aux_levels(image, aspect));
2632 assert(array_layer < anv_image_aux_layers(image, aspect, level));
2633 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2634 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
2635
2636 struct anv_address addr =
2637 anv_image_get_fast_clear_type_addr(device, image, aspect);
2638 addr.offset += 4; /* Go past the fast clear type */
2639
2640 if (image->type == VK_IMAGE_TYPE_3D) {
2641 for (uint32_t l = 0; l < level; l++)
2642 addr.offset += anv_minify(image->extent.depth, l) * 4;
2643 } else {
2644 addr.offset += level * image->array_size * 4;
2645 }
2646 addr.offset += array_layer * 4;
2647
2648 return addr;
2649 }
2650
2651 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2652 static inline bool
2653 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2654 const struct anv_image *image)
2655 {
2656 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2657 return false;
2658
2659 if (devinfo->gen < 8)
2660 return false;
2661
2662 return image->samples == 1;
2663 }
2664
2665 void
2666 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
2667 const struct anv_image *image,
2668 VkImageAspectFlagBits aspect,
2669 enum isl_aux_usage aux_usage,
2670 uint32_t level,
2671 uint32_t base_layer,
2672 uint32_t layer_count);
2673
2674 void
2675 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
2676 const struct anv_image *image,
2677 VkImageAspectFlagBits aspect,
2678 enum isl_aux_usage aux_usage,
2679 enum isl_format format, struct isl_swizzle swizzle,
2680 uint32_t level, uint32_t base_layer, uint32_t layer_count,
2681 VkRect2D area, union isl_color_value clear_color);
2682 void
2683 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
2684 const struct anv_image *image,
2685 VkImageAspectFlags aspects,
2686 enum isl_aux_usage depth_aux_usage,
2687 uint32_t level,
2688 uint32_t base_layer, uint32_t layer_count,
2689 VkRect2D area,
2690 float depth_value, uint8_t stencil_value);
2691 void
2692 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
2693 const struct anv_image *image,
2694 VkImageAspectFlagBits aspect, uint32_t level,
2695 uint32_t base_layer, uint32_t layer_count,
2696 enum isl_aux_op hiz_op);
2697 void
2698 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
2699 const struct anv_image *image,
2700 VkImageAspectFlags aspects,
2701 uint32_t level,
2702 uint32_t base_layer, uint32_t layer_count,
2703 VkRect2D area, uint8_t stencil_value);
2704 void
2705 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
2706 const struct anv_image *image,
2707 VkImageAspectFlagBits aspect,
2708 uint32_t base_layer, uint32_t layer_count,
2709 enum isl_aux_op mcs_op, bool predicate);
2710 void
2711 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
2712 const struct anv_image *image,
2713 VkImageAspectFlagBits aspect, uint32_t level,
2714 uint32_t base_layer, uint32_t layer_count,
2715 enum isl_aux_op ccs_op, bool predicate);
2716
2717 void
2718 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2719 const struct anv_image *image,
2720 uint32_t base_level, uint32_t level_count,
2721 uint32_t base_layer, uint32_t layer_count);
2722
2723 enum isl_aux_usage
2724 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2725 const struct anv_image *image,
2726 const VkImageAspectFlagBits aspect,
2727 const VkImageLayout layout);
2728
2729 enum anv_fast_clear_type
2730 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
2731 const struct anv_image * const image,
2732 const VkImageAspectFlagBits aspect,
2733 const VkImageLayout layout);
2734
2735 /* This is defined as a macro so that it works for both
2736 * VkImageSubresourceRange and VkImageSubresourceLayers
2737 */
2738 #define anv_get_layerCount(_image, _range) \
2739 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2740 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2741
2742 static inline uint32_t
2743 anv_get_levelCount(const struct anv_image *image,
2744 const VkImageSubresourceRange *range)
2745 {
2746 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2747 image->levels - range->baseMipLevel : range->levelCount;
2748 }
2749
2750 static inline VkImageAspectFlags
2751 anv_image_expand_aspects(const struct anv_image *image,
2752 VkImageAspectFlags aspects)
2753 {
2754 /* If the underlying image has color plane aspects and
2755 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2756 * the underlying image. */
2757 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2758 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2759 return image->aspects;
2760
2761 return aspects;
2762 }
2763
2764 static inline bool
2765 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2766 VkImageAspectFlags aspects2)
2767 {
2768 if (aspects1 == aspects2)
2769 return true;
2770
2771 /* Only 1 color aspects are compatibles. */
2772 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2773 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2774 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2775 return true;
2776
2777 return false;
2778 }
2779
2780 struct anv_image_view {
2781 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2782
2783 VkImageAspectFlags aspect_mask;
2784 VkFormat vk_format;
2785 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2786
2787 unsigned n_planes;
2788 struct {
2789 uint32_t image_plane;
2790
2791 struct isl_view isl;
2792
2793 /**
2794 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2795 * image layout of SHADER_READ_ONLY_OPTIMAL or
2796 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2797 */
2798 struct anv_surface_state optimal_sampler_surface_state;
2799
2800 /**
2801 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2802 * image layout of GENERAL.
2803 */
2804 struct anv_surface_state general_sampler_surface_state;
2805
2806 /**
2807 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2808 * states for write-only and readable, using the real format for
2809 * write-only and the lowered format for readable.
2810 */
2811 struct anv_surface_state storage_surface_state;
2812 struct anv_surface_state writeonly_storage_surface_state;
2813
2814 struct brw_image_param storage_image_param;
2815 } planes[3];
2816 };
2817
2818 enum anv_image_view_state_flags {
2819 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2820 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2821 };
2822
2823 void anv_image_fill_surface_state(struct anv_device *device,
2824 const struct anv_image *image,
2825 VkImageAspectFlagBits aspect,
2826 const struct isl_view *view,
2827 isl_surf_usage_flags_t view_usage,
2828 enum isl_aux_usage aux_usage,
2829 const union isl_color_value *clear_color,
2830 enum anv_image_view_state_flags flags,
2831 struct anv_surface_state *state_inout,
2832 struct brw_image_param *image_param_out);
2833
2834 struct anv_image_create_info {
2835 const VkImageCreateInfo *vk_info;
2836
2837 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2838 isl_tiling_flags_t isl_tiling_flags;
2839
2840 /** These flags will be added to any derived from VkImageCreateInfo. */
2841 isl_surf_usage_flags_t isl_extra_usage_flags;
2842
2843 uint32_t stride;
2844 };
2845
2846 VkResult anv_image_create(VkDevice _device,
2847 const struct anv_image_create_info *info,
2848 const VkAllocationCallbacks* alloc,
2849 VkImage *pImage);
2850
2851 #ifdef ANDROID
2852 VkResult anv_image_from_gralloc(VkDevice device_h,
2853 const VkImageCreateInfo *base_info,
2854 const VkNativeBufferANDROID *gralloc_info,
2855 const VkAllocationCallbacks *alloc,
2856 VkImage *pImage);
2857 #endif
2858
2859 const struct anv_surface *
2860 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2861 VkImageAspectFlags aspect_mask);
2862
2863 enum isl_format
2864 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2865
2866 static inline struct VkExtent3D
2867 anv_sanitize_image_extent(const VkImageType imageType,
2868 const struct VkExtent3D imageExtent)
2869 {
2870 switch (imageType) {
2871 case VK_IMAGE_TYPE_1D:
2872 return (VkExtent3D) { imageExtent.width, 1, 1 };
2873 case VK_IMAGE_TYPE_2D:
2874 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2875 case VK_IMAGE_TYPE_3D:
2876 return imageExtent;
2877 default:
2878 unreachable("invalid image type");
2879 }
2880 }
2881
2882 static inline struct VkOffset3D
2883 anv_sanitize_image_offset(const VkImageType imageType,
2884 const struct VkOffset3D imageOffset)
2885 {
2886 switch (imageType) {
2887 case VK_IMAGE_TYPE_1D:
2888 return (VkOffset3D) { imageOffset.x, 0, 0 };
2889 case VK_IMAGE_TYPE_2D:
2890 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2891 case VK_IMAGE_TYPE_3D:
2892 return imageOffset;
2893 default:
2894 unreachable("invalid image type");
2895 }
2896 }
2897
2898
2899 void anv_fill_buffer_surface_state(struct anv_device *device,
2900 struct anv_state state,
2901 enum isl_format format,
2902 uint32_t offset, uint32_t range,
2903 uint32_t stride);
2904
2905
2906 struct anv_ycbcr_conversion {
2907 const struct anv_format * format;
2908 VkSamplerYcbcrModelConversion ycbcr_model;
2909 VkSamplerYcbcrRange ycbcr_range;
2910 VkComponentSwizzle mapping[4];
2911 VkChromaLocation chroma_offsets[2];
2912 VkFilter chroma_filter;
2913 bool chroma_reconstruction;
2914 };
2915
2916 struct anv_sampler {
2917 uint32_t state[3][4];
2918 uint32_t n_planes;
2919 struct anv_ycbcr_conversion *conversion;
2920 };
2921
2922 struct anv_framebuffer {
2923 uint32_t width;
2924 uint32_t height;
2925 uint32_t layers;
2926
2927 uint32_t attachment_count;
2928 struct anv_image_view * attachments[0];
2929 };
2930
2931 struct anv_subpass_attachment {
2932 VkImageUsageFlagBits usage;
2933 uint32_t attachment;
2934 VkImageLayout layout;
2935 };
2936
2937 struct anv_subpass {
2938 uint32_t attachment_count;
2939
2940 /**
2941 * A pointer to all attachment references used in this subpass.
2942 * Only valid if ::attachment_count > 0.
2943 */
2944 struct anv_subpass_attachment * attachments;
2945 uint32_t input_count;
2946 struct anv_subpass_attachment * input_attachments;
2947 uint32_t color_count;
2948 struct anv_subpass_attachment * color_attachments;
2949 struct anv_subpass_attachment * resolve_attachments;
2950
2951 struct anv_subpass_attachment depth_stencil_attachment;
2952
2953 uint32_t view_mask;
2954
2955 /** Subpass has a depth/stencil self-dependency */
2956 bool has_ds_self_dep;
2957
2958 /** Subpass has at least one resolve attachment */
2959 bool has_resolve;
2960 };
2961
2962 static inline unsigned
2963 anv_subpass_view_count(const struct anv_subpass *subpass)
2964 {
2965 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2966 }
2967
2968 struct anv_render_pass_attachment {
2969 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2970 * its members individually.
2971 */
2972 VkFormat format;
2973 uint32_t samples;
2974 VkImageUsageFlags usage;
2975 VkAttachmentLoadOp load_op;
2976 VkAttachmentStoreOp store_op;
2977 VkAttachmentLoadOp stencil_load_op;
2978 VkImageLayout initial_layout;
2979 VkImageLayout final_layout;
2980 VkImageLayout first_subpass_layout;
2981
2982 /* The subpass id in which the attachment will be used last. */
2983 uint32_t last_subpass_idx;
2984 };
2985
2986 struct anv_render_pass {
2987 uint32_t attachment_count;
2988 uint32_t subpass_count;
2989 /* An array of subpass_count+1 flushes, one per subpass boundary */
2990 enum anv_pipe_bits * subpass_flushes;
2991 struct anv_render_pass_attachment * attachments;
2992 struct anv_subpass subpasses[0];
2993 };
2994
2995 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2996
2997 struct anv_query_pool {
2998 VkQueryType type;
2999 VkQueryPipelineStatisticFlags pipeline_statistics;
3000 /** Stride between slots, in bytes */
3001 uint32_t stride;
3002 /** Number of slots in this query pool */
3003 uint32_t slots;
3004 struct anv_bo bo;
3005 };
3006
3007 int anv_get_entrypoint_index(const char *name);
3008
3009 bool
3010 anv_entrypoint_is_enabled(int index, uint32_t core_version,
3011 const struct anv_instance_extension_table *instance,
3012 const struct anv_device_extension_table *device);
3013
3014 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
3015 const char *name);
3016
3017 void anv_dump_image_to_ppm(struct anv_device *device,
3018 struct anv_image *image, unsigned miplevel,
3019 unsigned array_layer, VkImageAspectFlagBits aspect,
3020 const char *filename);
3021
3022 enum anv_dump_action {
3023 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
3024 };
3025
3026 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
3027 void anv_dump_finish(void);
3028
3029 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
3030 struct anv_framebuffer *fb);
3031
3032 static inline uint32_t
3033 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
3034 {
3035 /* This function must be called from within a subpass. */
3036 assert(cmd_state->pass && cmd_state->subpass);
3037
3038 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
3039
3040 /* The id of this subpass shouldn't exceed the number of subpasses in this
3041 * render pass minus 1.
3042 */
3043 assert(subpass_id < cmd_state->pass->subpass_count);
3044 return subpass_id;
3045 }
3046
3047 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3048 \
3049 static inline struct __anv_type * \
3050 __anv_type ## _from_handle(__VkType _handle) \
3051 { \
3052 return (struct __anv_type *) _handle; \
3053 } \
3054 \
3055 static inline __VkType \
3056 __anv_type ## _to_handle(struct __anv_type *_obj) \
3057 { \
3058 return (__VkType) _obj; \
3059 }
3060
3061 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3062 \
3063 static inline struct __anv_type * \
3064 __anv_type ## _from_handle(__VkType _handle) \
3065 { \
3066 return (struct __anv_type *)(uintptr_t) _handle; \
3067 } \
3068 \
3069 static inline __VkType \
3070 __anv_type ## _to_handle(struct __anv_type *_obj) \
3071 { \
3072 return (__VkType)(uintptr_t) _obj; \
3073 }
3074
3075 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3076 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3077
3078 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
3079 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
3080 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
3081 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
3082 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
3083
3084 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
3085 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
3086 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
3087 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
3088 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
3089 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
3090 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
3091 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
3092 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
3093 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
3094 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
3095 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
3096 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
3097 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
3098 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
3099 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
3100 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
3101 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
3102 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
3103 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
3104 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
3105 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
3106 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversion)
3107
3108 /* Gen-specific function declarations */
3109 #ifdef genX
3110 # include "anv_genX.h"
3111 #else
3112 # define genX(x) gen7_##x
3113 # include "anv_genX.h"
3114 # undef genX
3115 # define genX(x) gen75_##x
3116 # include "anv_genX.h"
3117 # undef genX
3118 # define genX(x) gen8_##x
3119 # include "anv_genX.h"
3120 # undef genX
3121 # define genX(x) gen9_##x
3122 # include "anv_genX.h"
3123 # undef genX
3124 # define genX(x) gen10_##x
3125 # include "anv_genX.h"
3126 # undef genX
3127 # define genX(x) gen11_##x
3128 # include "anv_genX.h"
3129 # undef genX
3130 #endif
3131
3132 #endif /* ANV_PRIVATE_H */