2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
61 #include "vk_debug_report.h"
63 /* Pre-declarations needed for WSI entrypoints */
66 typedef struct xcb_connection_t xcb_connection_t
;
67 typedef uint32_t xcb_visualid_t
;
68 typedef uint32_t xcb_window_t
;
71 struct anv_buffer_view
;
72 struct anv_image_view
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
81 #include "anv_android.h"
82 #include "anv_entrypoints.h"
83 #include "anv_extensions.h"
86 #include "dev/gen_debug.h"
87 #include "common/intel_log.h"
88 #include "wsi_common.h"
90 /* anv Virtual Memory Layout
91 * =========================
93 * When the anv driver is determining the virtual graphics addresses of memory
94 * objects itself using the softpin mechanism, the following memory ranges
97 * Three special considerations to notice:
99 * (1) the dynamic state pool is located within the same 4 GiB as the low
100 * heap. This is to work around a VF cache issue described in a comment in
101 * anv_physical_device_init_heaps.
103 * (2) the binding table pool is located at lower addresses than the surface
104 * state pool, within a 4 GiB range. This allows surface state base addresses
105 * to cover both binding tables (16 bit offsets) and surface states (32 bit
108 * (3) the last 4 GiB of the address space is withheld from the high
109 * heap. Various hardware units will read past the end of an object for
110 * various reasons. This healthy margin prevents reads from wrapping around
113 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
114 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
115 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
116 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
117 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
118 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
119 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
120 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
121 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
122 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
123 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
125 #define LOW_HEAP_SIZE \
126 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
127 #define DYNAMIC_STATE_POOL_SIZE \
128 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
129 #define BINDING_TABLE_POOL_SIZE \
130 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
131 #define SURFACE_STATE_POOL_SIZE \
132 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
133 #define INSTRUCTION_STATE_POOL_SIZE \
134 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
136 /* Allowing different clear colors requires us to perform a depth resolve at
137 * the end of certain render passes. This is because while slow clears store
138 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
139 * See the PRMs for examples describing when additional resolves would be
140 * necessary. To enable fast clears without requiring extra resolves, we set
141 * the clear value to a globally-defined one. We could allow different values
142 * if the user doesn't expect coherent data during or after a render passes
143 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
144 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
145 * 1.0f seems to be the only value used. The only application that doesn't set
146 * this value does so through the usage of an seemingly uninitialized clear
149 #define ANV_HZ_FC_VAL 1.0f
152 #define MAX_XFB_BUFFERS 4
153 #define MAX_XFB_STREAMS 4
156 #define MAX_VIEWPORTS 16
157 #define MAX_SCISSORS 16
158 #define MAX_PUSH_CONSTANTS_SIZE 128
159 #define MAX_DYNAMIC_BUFFERS 16
160 #define MAX_IMAGES 64
161 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
162 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
163 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
165 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
167 * "The surface state model is used when a Binding Table Index (specified
168 * in the message descriptor) of less than 240 is specified. In this model,
169 * the Binding Table Index is used to index into the binding table, and the
170 * binding table entry contains a pointer to the SURFACE_STATE."
172 * Binding table values above 240 are used for various things in the hardware
173 * such as stateless, stateless with incoherent cache, SLM, and bindless.
175 #define MAX_BINDING_TABLE_SIZE 240
177 /* The kernel relocation API has a limitation of a 32-bit delta value
178 * applied to the address before it is written which, in spite of it being
179 * unsigned, is treated as signed . Because of the way that this maps to
180 * the Vulkan API, we cannot handle an offset into a buffer that does not
181 * fit into a signed 32 bits. The only mechanism we have for dealing with
182 * this at the moment is to limit all VkDeviceMemory objects to a maximum
183 * of 2GB each. The Vulkan spec allows us to do this:
185 * "Some platforms may have a limit on the maximum size of a single
186 * allocation. For example, certain systems may fail to create
187 * allocations with a size greater than or equal to 4GB. Such a limit is
188 * implementation-dependent, and if such a failure occurs then the error
189 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
191 * We don't use vk_error here because it's not an error so much as an
192 * indication to the application that the allocation is too large.
194 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
196 #define ANV_SVGS_VB_INDEX MAX_VBS
197 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
199 /* We reserve this MI ALU register for the purpose of handling predication.
200 * Other code which uses the MI ALU should leave it alone.
202 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
204 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
206 static inline uint32_t
207 align_down_npot_u32(uint32_t v
, uint32_t a
)
212 static inline uint32_t
213 align_u32(uint32_t v
, uint32_t a
)
215 assert(a
!= 0 && a
== (a
& -a
));
216 return (v
+ a
- 1) & ~(a
- 1);
219 static inline uint64_t
220 align_u64(uint64_t v
, uint64_t a
)
222 assert(a
!= 0 && a
== (a
& -a
));
223 return (v
+ a
- 1) & ~(a
- 1);
226 static inline int32_t
227 align_i32(int32_t v
, int32_t a
)
229 assert(a
!= 0 && a
== (a
& -a
));
230 return (v
+ a
- 1) & ~(a
- 1);
233 /** Alignment must be a power of 2. */
235 anv_is_aligned(uintmax_t n
, uintmax_t a
)
237 assert(a
== (a
& -a
));
238 return (n
& (a
- 1)) == 0;
241 static inline uint32_t
242 anv_minify(uint32_t n
, uint32_t levels
)
244 if (unlikely(n
== 0))
247 return MAX2(n
>> levels
, 1);
251 anv_clamp_f(float f
, float min
, float max
)
264 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
266 if (*inout_mask
& clear_mask
) {
267 *inout_mask
&= ~clear_mask
;
274 static inline union isl_color_value
275 vk_to_isl_color(VkClearColorValue color
)
277 return (union isl_color_value
) {
287 #define for_each_bit(b, dword) \
288 for (uint32_t __dword = (dword); \
289 (b) = __builtin_ffs(__dword) - 1, __dword; \
290 __dword &= ~(1 << (b)))
292 #define typed_memcpy(dest, src, count) ({ \
293 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
294 memcpy((dest), (src), (count) * sizeof(*(src))); \
297 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
298 * to be added here in order to utilize mapping in debug/error/perf macros.
300 #define REPORT_OBJECT_TYPE(o) \
301 __builtin_choose_expr ( \
302 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
303 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
376 __builtin_choose_expr ( \
377 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
378 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
379 __builtin_choose_expr ( \
380 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
381 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
382 __builtin_choose_expr ( \
383 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
384 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
385 __builtin_choose_expr ( \
386 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
387 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
388 __builtin_choose_expr ( \
389 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
390 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
391 __builtin_choose_expr ( \
392 __builtin_types_compatible_p (__typeof (o), void*), \
393 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
394 /* The void expression results in a compile-time error \
395 when assigning the result to something. */ \
396 (void)0)))))))))))))))))))))))))))))))
398 /* Whenever we generate an error, pass it through this function. Useful for
399 * debugging, where we can break on it. Only call at error site, not when
400 * propagating errors. Might be useful to plug in a stack trace here.
403 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
404 VkDebugReportObjectTypeEXT type
, VkResult error
,
405 const char *file
, int line
, const char *format
,
408 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
409 VkDebugReportObjectTypeEXT type
, VkResult error
,
410 const char *file
, int line
, const char *format
, ...);
413 #define vk_error(error) __vk_errorf(NULL, NULL,\
414 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
415 error, __FILE__, __LINE__, NULL)
416 #define vk_errorv(instance, obj, error, format, args)\
417 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
418 __FILE__, __LINE__, format, args)
419 #define vk_errorf(instance, obj, error, format, ...)\
420 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
421 __FILE__, __LINE__, format, ## __VA_ARGS__)
423 #define vk_error(error) error
424 #define vk_errorf(instance, obj, error, format, ...) error
428 * Warn on ignored extension structs.
430 * The Vulkan spec requires us to ignore unsupported or unknown structs in
431 * a pNext chain. In debug mode, emitting warnings for ignored structs may
432 * help us discover structs that we should not have ignored.
435 * From the Vulkan 1.0.38 spec:
437 * Any component of the implementation (the loader, any enabled layers,
438 * and drivers) must skip over, without processing (other than reading the
439 * sType and pNext members) any chained structures with sType values not
440 * defined by extensions supported by that component.
442 #define anv_debug_ignored_stype(sType) \
443 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
445 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
446 VkDebugReportObjectTypeEXT type
, const char *file
,
447 int line
, const char *format
, ...)
448 anv_printflike(6, 7);
449 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
450 void anv_loge_v(const char *format
, va_list va
);
453 * Print a FINISHME message, including its source location.
455 #define anv_finishme(format, ...) \
457 static bool reported = false; \
459 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
466 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
468 #define anv_perf_warn(instance, obj, format, ...) \
470 static bool reported = false; \
471 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
472 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
473 format, ##__VA_ARGS__); \
478 /* A non-fatal assert. Useful for debugging. */
480 #define anv_assert(x) ({ \
481 if (unlikely(!(x))) \
482 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
485 #define anv_assert(x)
488 /* A multi-pointer allocator
490 * When copying data structures from the user (such as a render pass), it's
491 * common to need to allocate data for a bunch of different things. Instead
492 * of doing several allocations and having to handle all of the error checking
493 * that entails, it can be easier to do a single allocation. This struct
494 * helps facilitate that. The intended usage looks like this:
497 * anv_multialloc_add(&ma, &main_ptr, 1);
498 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
499 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
501 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
502 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
504 struct anv_multialloc
{
512 #define ANV_MULTIALLOC_INIT \
513 ((struct anv_multialloc) { 0, })
515 #define ANV_MULTIALLOC(_name) \
516 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
518 __attribute__((always_inline
))
520 _anv_multialloc_add(struct anv_multialloc
*ma
,
521 void **ptr
, size_t size
, size_t align
)
523 size_t offset
= align_u64(ma
->size
, align
);
524 ma
->size
= offset
+ size
;
525 ma
->align
= MAX2(ma
->align
, align
);
527 /* Store the offset in the pointer. */
528 *ptr
= (void *)(uintptr_t)offset
;
530 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
531 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
534 #define anv_multialloc_add_size(_ma, _ptr, _size) \
535 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
537 #define anv_multialloc_add(_ma, _ptr, _count) \
538 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
540 __attribute__((always_inline
))
542 anv_multialloc_alloc(struct anv_multialloc
*ma
,
543 const VkAllocationCallbacks
*alloc
,
544 VkSystemAllocationScope scope
)
546 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
550 /* Fill out each of the pointers with their final value.
552 * for (uint32_t i = 0; i < ma->ptr_count; i++)
553 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
555 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
556 * constant, GCC is incapable of figuring this out and unrolling the loop
557 * so we have to give it a little help.
559 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
560 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
561 if ((_i) < ma->ptr_count) \
562 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
563 _ANV_MULTIALLOC_UPDATE_POINTER(0);
564 _ANV_MULTIALLOC_UPDATE_POINTER(1);
565 _ANV_MULTIALLOC_UPDATE_POINTER(2);
566 _ANV_MULTIALLOC_UPDATE_POINTER(3);
567 _ANV_MULTIALLOC_UPDATE_POINTER(4);
568 _ANV_MULTIALLOC_UPDATE_POINTER(5);
569 _ANV_MULTIALLOC_UPDATE_POINTER(6);
570 _ANV_MULTIALLOC_UPDATE_POINTER(7);
571 #undef _ANV_MULTIALLOC_UPDATE_POINTER
576 __attribute__((always_inline
))
578 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
579 const VkAllocationCallbacks
*parent_alloc
,
580 const VkAllocationCallbacks
*alloc
,
581 VkSystemAllocationScope scope
)
583 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
586 /* Extra ANV-defined BO flags which won't be passed to the kernel */
587 #define ANV_BO_EXTERNAL (1ull << 31)
588 #define ANV_BO_FLAG_MASK (1ull << 31)
593 /* Index into the current validation list. This is used by the
594 * validation list building alrogithm to track which buffers are already
595 * in the validation list so that we can ensure uniqueness.
599 /* Last known offset. This value is provided by the kernel when we
600 * execbuf and is used as the presumed offset for the next bunch of
608 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
613 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
615 bo
->gem_handle
= gem_handle
;
623 /* Represents a lock-free linked list of "free" things. This is used by
624 * both the block pool and the state pools. Unfortunately, in order to
625 * solve the ABA problem, we can't use a single uint32_t head.
627 union anv_free_list
{
631 /* A simple count that is incremented every time the head changes. */
637 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
639 struct anv_block_state
{
649 #define anv_block_pool_foreach_bo(bo, pool) \
650 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
652 #define ANV_MAX_BLOCK_POOL_BOS 20
654 struct anv_block_pool
{
655 struct anv_device
*device
;
659 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
665 /* The address where the start of the pool is pinned. The various bos that
666 * are created as the pool grows will have addresses in the range
667 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
669 uint64_t start_address
;
671 /* The offset from the start of the bo to the "center" of the block
672 * pool. Pointers to allocated blocks are given by
673 * bo.map + center_bo_offset + offsets.
675 uint32_t center_bo_offset
;
677 /* Current memory map of the block pool. This pointer may or may not
678 * point to the actual beginning of the block pool memory. If
679 * anv_block_pool_alloc_back has ever been called, then this pointer
680 * will point to the "center" position of the buffer and all offsets
681 * (negative or positive) given out by the block pool alloc functions
682 * will be valid relative to this pointer.
684 * In particular, map == bo.map + center_offset
686 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
687 * since it will handle the softpin case as well, where this points to NULL.
693 * Array of mmaps and gem handles owned by the block pool, reclaimed when
694 * the block pool is destroyed.
696 struct u_vector mmap_cleanups
;
698 struct anv_block_state state
;
700 struct anv_block_state back_state
;
703 /* Block pools are backed by a fixed-size 1GB memfd */
704 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
706 /* The center of the block pool is also the middle of the memfd. This may
707 * change in the future if we decide differently for some reason.
709 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
711 static inline uint32_t
712 anv_block_pool_size(struct anv_block_pool
*pool
)
714 return pool
->state
.end
+ pool
->back_state
.end
;
724 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
726 struct anv_fixed_size_state_pool
{
727 union anv_free_list free_list
;
728 struct anv_block_state block
;
731 #define ANV_MIN_STATE_SIZE_LOG2 6
732 #define ANV_MAX_STATE_SIZE_LOG2 21
734 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
736 struct anv_free_entry
{
738 struct anv_state state
;
741 struct anv_state_table
{
742 struct anv_device
*device
;
744 struct anv_free_entry
*map
;
746 struct anv_block_state state
;
747 struct u_vector cleanups
;
750 struct anv_state_pool
{
751 struct anv_block_pool block_pool
;
753 struct anv_state_table table
;
755 /* The size of blocks which will be allocated from the block pool */
758 /** Free list for "back" allocations */
759 union anv_free_list back_alloc_free_list
;
761 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
764 struct anv_state_stream_block
;
766 struct anv_state_stream
{
767 struct anv_state_pool
*state_pool
;
769 /* The size of blocks to allocate from the state pool */
772 /* Current block we're allocating from */
773 struct anv_state block
;
775 /* Offset into the current block at which to allocate the next state */
778 /* List of all blocks allocated from this pool */
779 struct anv_state_stream_block
*block_list
;
782 /* The block_pool functions exported for testing only. The block pool should
783 * only be used via a state pool (see below).
785 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
786 struct anv_device
*device
,
787 uint64_t start_address
,
788 uint32_t initial_size
,
790 void anv_block_pool_finish(struct anv_block_pool
*pool
);
791 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
792 uint32_t block_size
, uint32_t *padding
);
793 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
794 uint32_t block_size
);
795 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
797 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
798 struct anv_device
*device
,
799 uint64_t start_address
,
802 void anv_state_pool_finish(struct anv_state_pool
*pool
);
803 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
804 uint32_t state_size
, uint32_t alignment
);
805 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
806 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
807 void anv_state_stream_init(struct anv_state_stream
*stream
,
808 struct anv_state_pool
*state_pool
,
809 uint32_t block_size
);
810 void anv_state_stream_finish(struct anv_state_stream
*stream
);
811 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
812 uint32_t size
, uint32_t alignment
);
814 VkResult
anv_state_table_init(struct anv_state_table
*table
,
815 struct anv_device
*device
,
816 uint32_t initial_entries
);
817 void anv_state_table_finish(struct anv_state_table
*table
);
818 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
820 void anv_free_list_push(union anv_free_list
*list
,
821 struct anv_state_table
*table
,
822 uint32_t idx
, uint32_t count
);
823 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
824 struct anv_state_table
*table
);
827 static inline struct anv_state
*
828 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
830 return &table
->map
[idx
].state
;
833 * Implements a pool of re-usable BOs. The interface is identical to that
834 * of block_pool except that each block is its own BO.
837 struct anv_device
*device
;
844 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
846 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
847 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
849 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
851 struct anv_scratch_bo
{
856 struct anv_scratch_pool
{
857 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
858 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
861 void anv_scratch_pool_init(struct anv_device
*device
,
862 struct anv_scratch_pool
*pool
);
863 void anv_scratch_pool_finish(struct anv_device
*device
,
864 struct anv_scratch_pool
*pool
);
865 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
866 struct anv_scratch_pool
*pool
,
867 gl_shader_stage stage
,
868 unsigned per_thread_scratch
);
870 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
871 struct anv_bo_cache
{
872 struct hash_table
*bo_map
;
873 pthread_mutex_t mutex
;
876 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
877 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
878 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
879 struct anv_bo_cache
*cache
,
880 uint64_t size
, uint64_t bo_flags
,
882 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
883 struct anv_bo_cache
*cache
,
884 void *host_ptr
, uint32_t size
,
885 uint64_t bo_flags
, struct anv_bo
**bo_out
);
886 VkResult
anv_bo_cache_import(struct anv_device
*device
,
887 struct anv_bo_cache
*cache
,
888 int fd
, uint64_t bo_flags
,
890 VkResult
anv_bo_cache_export(struct anv_device
*device
,
891 struct anv_bo_cache
*cache
,
892 struct anv_bo
*bo_in
, int *fd_out
);
893 void anv_bo_cache_release(struct anv_device
*device
,
894 struct anv_bo_cache
*cache
,
897 struct anv_memory_type
{
898 /* Standard bits passed on to the client */
899 VkMemoryPropertyFlags propertyFlags
;
902 /* Driver-internal book-keeping */
903 VkBufferUsageFlags valid_buffer_usage
;
906 struct anv_memory_heap
{
907 /* Standard bits passed on to the client */
909 VkMemoryHeapFlags flags
;
911 /* Driver-internal book-keeping */
914 bool supports_48bit_addresses
;
918 struct anv_physical_device
{
919 VK_LOADER_DATA _loader_data
;
921 struct anv_instance
* instance
;
932 struct gen_device_info info
;
933 /** Amount of "GPU memory" we want to advertise
935 * Clearly, this value is bogus since Intel is a UMA architecture. On
936 * gen7 platforms, we are limited by GTT size unless we want to implement
937 * fine-grained tracking and GTT splitting. On Broadwell and above we are
938 * practically unlimited. However, we will never report more than 3/4 of
939 * the total system ram to try and avoid running out of RAM.
941 bool supports_48bit_addresses
;
942 struct brw_compiler
* compiler
;
943 struct isl_device isl_dev
;
944 int cmd_parser_version
;
946 bool has_exec_capture
;
949 bool has_syncobj_wait
;
950 bool has_context_priority
;
952 bool has_context_isolation
;
953 bool has_mem_available
;
954 bool always_use_bindless
;
956 /** True if we can access buffers using A64 messages */
957 bool has_a64_buffer_access
;
958 /** True if we can use bindless access for images */
959 bool has_bindless_images
;
960 /** True if we can use bindless access for samplers */
961 bool has_bindless_samplers
;
963 struct anv_device_extension_table supported_extensions
;
966 uint32_t subslice_total
;
970 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
972 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
975 uint8_t driver_build_sha1
[20];
976 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
977 uint8_t driver_uuid
[VK_UUID_SIZE
];
978 uint8_t device_uuid
[VK_UUID_SIZE
];
980 struct disk_cache
* disk_cache
;
982 struct wsi_device wsi_device
;
987 struct anv_app_info
{
988 const char* app_name
;
989 uint32_t app_version
;
990 const char* engine_name
;
991 uint32_t engine_version
;
992 uint32_t api_version
;
995 struct anv_instance
{
996 VK_LOADER_DATA _loader_data
;
998 VkAllocationCallbacks alloc
;
1000 struct anv_app_info app_info
;
1002 struct anv_instance_extension_table enabled_extensions
;
1003 struct anv_instance_dispatch_table dispatch
;
1004 struct anv_device_dispatch_table device_dispatch
;
1006 int physicalDeviceCount
;
1007 struct anv_physical_device physicalDevice
;
1009 bool pipeline_cache_enabled
;
1011 struct vk_debug_report_instance debug_report_callbacks
;
1014 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1015 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1017 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1018 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1022 VK_LOADER_DATA _loader_data
;
1024 struct anv_device
* device
;
1026 VkDeviceQueueCreateFlags flags
;
1029 struct anv_pipeline_cache
{
1030 struct anv_device
* device
;
1031 pthread_mutex_t mutex
;
1033 struct hash_table
* nir_cache
;
1035 struct hash_table
* cache
;
1038 struct nir_xfb_info
;
1039 struct anv_pipeline_bind_map
;
1041 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1042 struct anv_device
*device
,
1043 bool cache_enabled
);
1044 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1046 struct anv_shader_bin
*
1047 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1048 const void *key
, uint32_t key_size
);
1049 struct anv_shader_bin
*
1050 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1051 const void *key_data
, uint32_t key_size
,
1052 const void *kernel_data
, uint32_t kernel_size
,
1053 const void *constant_data
,
1054 uint32_t constant_data_size
,
1055 const struct brw_stage_prog_data
*prog_data
,
1056 uint32_t prog_data_size
,
1057 const struct brw_compile_stats
*stats
,
1059 const struct nir_xfb_info
*xfb_info
,
1060 const struct anv_pipeline_bind_map
*bind_map
);
1062 struct anv_shader_bin
*
1063 anv_device_search_for_kernel(struct anv_device
*device
,
1064 struct anv_pipeline_cache
*cache
,
1065 const void *key_data
, uint32_t key_size
,
1066 bool *user_cache_bit
);
1068 struct anv_shader_bin
*
1069 anv_device_upload_kernel(struct anv_device
*device
,
1070 struct anv_pipeline_cache
*cache
,
1071 const void *key_data
, uint32_t key_size
,
1072 const void *kernel_data
, uint32_t kernel_size
,
1073 const void *constant_data
,
1074 uint32_t constant_data_size
,
1075 const struct brw_stage_prog_data
*prog_data
,
1076 uint32_t prog_data_size
,
1077 const struct brw_compile_stats
*stats
,
1079 const struct nir_xfb_info
*xfb_info
,
1080 const struct anv_pipeline_bind_map
*bind_map
);
1083 struct nir_shader_compiler_options
;
1086 anv_device_search_for_nir(struct anv_device
*device
,
1087 struct anv_pipeline_cache
*cache
,
1088 const struct nir_shader_compiler_options
*nir_options
,
1089 unsigned char sha1_key
[20],
1093 anv_device_upload_nir(struct anv_device
*device
,
1094 struct anv_pipeline_cache
*cache
,
1095 const struct nir_shader
*nir
,
1096 unsigned char sha1_key
[20]);
1099 VK_LOADER_DATA _loader_data
;
1101 VkAllocationCallbacks alloc
;
1103 struct anv_instance
* instance
;
1104 uint32_t chipset_id
;
1106 struct gen_device_info info
;
1107 struct isl_device isl_dev
;
1110 bool can_chain_batches
;
1111 bool robust_buffer_access
;
1112 struct anv_device_extension_table enabled_extensions
;
1113 struct anv_device_dispatch_table dispatch
;
1115 pthread_mutex_t vma_mutex
;
1116 struct util_vma_heap vma_lo
;
1117 struct util_vma_heap vma_hi
;
1118 uint64_t vma_lo_available
;
1119 uint64_t vma_hi_available
;
1121 /** List of all anv_device_memory objects */
1122 struct list_head memory_objects
;
1124 struct anv_bo_pool batch_bo_pool
;
1126 struct anv_bo_cache bo_cache
;
1128 struct anv_state_pool dynamic_state_pool
;
1129 struct anv_state_pool instruction_state_pool
;
1130 struct anv_state_pool binding_table_pool
;
1131 struct anv_state_pool surface_state_pool
;
1133 struct anv_bo workaround_bo
;
1134 struct anv_bo trivial_batch_bo
;
1135 struct anv_bo hiz_clear_bo
;
1137 struct anv_pipeline_cache default_pipeline_cache
;
1138 struct blorp_context blorp
;
1140 struct anv_state border_colors
;
1142 struct anv_state slice_hash
;
1144 struct anv_queue queue
;
1146 struct anv_scratch_pool scratch_pool
;
1148 uint32_t default_mocs
;
1149 uint32_t external_mocs
;
1151 pthread_mutex_t mutex
;
1152 pthread_cond_t queue_submit
;
1155 struct gen_batch_decode_ctx decoder_ctx
;
1157 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1158 * the cmd_buffer's list.
1160 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1163 static inline struct anv_state_pool
*
1164 anv_binding_table_pool(struct anv_device
*device
)
1166 if (device
->instance
->physicalDevice
.use_softpin
)
1167 return &device
->binding_table_pool
;
1169 return &device
->surface_state_pool
;
1172 static inline struct anv_state
1173 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1174 if (device
->instance
->physicalDevice
.use_softpin
)
1175 return anv_state_pool_alloc(&device
->binding_table_pool
,
1176 device
->binding_table_pool
.block_size
, 0);
1178 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1182 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1183 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1186 static inline uint32_t
1187 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1189 if (bo
->flags
& ANV_BO_EXTERNAL
)
1190 return device
->external_mocs
;
1192 return device
->default_mocs
;
1195 void anv_device_init_blorp(struct anv_device
*device
);
1196 void anv_device_finish_blorp(struct anv_device
*device
);
1198 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1199 const char *file
, int line
,
1200 const char *msg
, ...);
1201 #define anv_device_set_lost(dev, ...) \
1202 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1205 anv_device_is_lost(struct anv_device
*device
)
1207 return unlikely(device
->_lost
);
1210 VkResult
anv_device_execbuf(struct anv_device
*device
,
1211 struct drm_i915_gem_execbuffer2
*execbuf
,
1212 struct anv_bo
**execbuf_bos
);
1213 VkResult
anv_device_query_status(struct anv_device
*device
);
1214 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1215 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1218 void* anv_gem_mmap(struct anv_device
*device
,
1219 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1220 void anv_gem_munmap(void *p
, uint64_t size
);
1221 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1222 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1223 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1224 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1225 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1226 int anv_gem_execbuffer(struct anv_device
*device
,
1227 struct drm_i915_gem_execbuffer2
*execbuf
);
1228 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1229 uint32_t stride
, uint32_t tiling
);
1230 int anv_gem_create_context(struct anv_device
*device
);
1231 bool anv_gem_has_context_priority(int fd
);
1232 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1233 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1235 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1237 int anv_gem_get_param(int fd
, uint32_t param
);
1238 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1239 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1240 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1241 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1242 uint32_t *active
, uint32_t *pending
);
1243 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1244 int anv_gem_reg_read(struct anv_device
*device
,
1245 uint32_t offset
, uint64_t *result
);
1246 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1247 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1248 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1249 uint32_t read_domains
, uint32_t write_domain
);
1250 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1251 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1252 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1253 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1254 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1255 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1257 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1258 uint32_t handle
, int fd
);
1259 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1260 bool anv_gem_supports_syncobj_wait(int fd
);
1261 int anv_gem_syncobj_wait(struct anv_device
*device
,
1262 uint32_t *handles
, uint32_t num_handles
,
1263 int64_t abs_timeout_ns
, bool wait_all
);
1265 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1266 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1268 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1270 struct anv_reloc_list
{
1271 uint32_t num_relocs
;
1272 uint32_t array_length
;
1273 struct drm_i915_gem_relocation_entry
* relocs
;
1274 struct anv_bo
** reloc_bos
;
1278 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1279 const VkAllocationCallbacks
*alloc
);
1280 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1281 const VkAllocationCallbacks
*alloc
);
1283 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1284 const VkAllocationCallbacks
*alloc
,
1285 uint32_t offset
, struct anv_bo
*target_bo
,
1288 struct anv_batch_bo
{
1289 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1290 struct list_head link
;
1294 /* Bytes actually consumed in this batch BO */
1297 struct anv_reloc_list relocs
;
1301 const VkAllocationCallbacks
* alloc
;
1307 struct anv_reloc_list
* relocs
;
1309 /* This callback is called (with the associated user data) in the event
1310 * that the batch runs out of space.
1312 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1316 * Current error status of the command buffer. Used to track inconsistent
1317 * or incomplete command buffer states that are the consequence of run-time
1318 * errors such as out of memory scenarios. We want to track this in the
1319 * batch because the command buffer object is not visible to some parts
1325 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1326 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1327 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1328 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1329 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1330 struct anv_batch
*batch
);
1332 static inline VkResult
1333 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1335 assert(error
!= VK_SUCCESS
);
1336 if (batch
->status
== VK_SUCCESS
)
1337 batch
->status
= error
;
1338 return batch
->status
;
1342 anv_batch_has_error(struct anv_batch
*batch
)
1344 return batch
->status
!= VK_SUCCESS
;
1347 struct anv_address
{
1352 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1355 anv_address_is_null(struct anv_address addr
)
1357 return addr
.bo
== NULL
&& addr
.offset
== 0;
1360 static inline uint64_t
1361 anv_address_physical(struct anv_address addr
)
1363 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1364 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1366 return gen_canonical_address(addr
.offset
);
1369 static inline struct anv_address
1370 anv_address_add(struct anv_address addr
, uint64_t offset
)
1372 addr
.offset
+= offset
;
1377 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1379 unsigned reloc_size
= 0;
1380 if (device
->info
.gen
>= 8) {
1381 reloc_size
= sizeof(uint64_t);
1382 *(uint64_t *)p
= gen_canonical_address(v
);
1384 reloc_size
= sizeof(uint32_t);
1388 if (flush
&& !device
->info
.has_llc
)
1389 gen_flush_range(p
, reloc_size
);
1392 static inline uint64_t
1393 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1394 const struct anv_address address
, uint32_t delta
)
1396 if (address
.bo
== NULL
) {
1397 return address
.offset
+ delta
;
1399 assert(batch
->start
<= location
&& location
< batch
->end
);
1401 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1405 #define __gen_address_type struct anv_address
1406 #define __gen_user_data struct anv_batch
1407 #define __gen_combine_address _anv_combine_address
1409 /* Wrapper macros needed to work around preprocessor argument issues. In
1410 * particular, arguments don't get pre-evaluated if they are concatenated.
1411 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1412 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1413 * We can work around this easily enough with these helpers.
1415 #define __anv_cmd_length(cmd) cmd ## _length
1416 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1417 #define __anv_cmd_header(cmd) cmd ## _header
1418 #define __anv_cmd_pack(cmd) cmd ## _pack
1419 #define __anv_reg_num(reg) reg ## _num
1421 #define anv_pack_struct(dst, struc, ...) do { \
1422 struct struc __template = { \
1425 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1426 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1429 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1430 void *__dst = anv_batch_emit_dwords(batch, n); \
1432 struct cmd __template = { \
1433 __anv_cmd_header(cmd), \
1434 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1437 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1442 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1446 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1447 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1450 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1451 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1452 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1455 #define anv_batch_emit(batch, cmd, name) \
1456 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1457 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1458 __builtin_expect(_dst != NULL, 1); \
1459 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1460 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1464 /* MEMORY_OBJECT_CONTROL_STATE:
1465 * .GraphicsDataTypeGFDT = 0,
1466 * .LLCCacheabilityControlLLCCC = 0,
1467 * .L3CacheabilityControlL3CC = 1,
1471 /* MEMORY_OBJECT_CONTROL_STATE:
1472 * .LLCeLLCCacheabilityControlLLCCC = 0,
1473 * .L3CacheabilityControlL3CC = 1,
1475 #define GEN75_MOCS 1
1477 /* MEMORY_OBJECT_CONTROL_STATE:
1478 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1479 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1480 * .AgeforQUADLRU = 0
1482 #define GEN8_MOCS 0x78
1484 /* MEMORY_OBJECT_CONTROL_STATE:
1485 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1486 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1487 * .AgeforQUADLRU = 0
1489 #define GEN8_EXTERNAL_MOCS 0x18
1491 /* Skylake: MOCS is now an index into an array of 62 different caching
1492 * configurations programmed by the kernel.
1495 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1496 #define GEN9_MOCS (2 << 1)
1498 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1499 #define GEN9_EXTERNAL_MOCS (1 << 1)
1501 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1502 #define GEN10_MOCS GEN9_MOCS
1503 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1505 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1506 #define GEN11_MOCS GEN9_MOCS
1507 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1509 /* TigerLake MOCS */
1510 #define GEN12_MOCS GEN9_MOCS
1511 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1512 #define GEN12_EXTERNAL_MOCS (3 << 1)
1514 struct anv_device_memory
{
1515 struct list_head link
;
1518 struct anv_memory_type
* type
;
1519 VkDeviceSize map_size
;
1522 /* If set, we are holding reference to AHardwareBuffer
1523 * which we must release when memory is freed.
1525 struct AHardwareBuffer
* ahw
;
1527 /* If set, this memory comes from a host pointer. */
1532 * Header for Vertex URB Entry (VUE)
1534 struct anv_vue_header
{
1536 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1537 uint32_t ViewportIndex
;
1541 /** Struct representing a sampled image descriptor
1543 * This descriptor layout is used for sampled images, bare sampler, and
1544 * combined image/sampler descriptors.
1546 struct anv_sampled_image_descriptor
{
1547 /** Bindless image handle
1549 * This is expected to already be shifted such that the 20-bit
1550 * SURFACE_STATE table index is in the top 20 bits.
1554 /** Bindless sampler handle
1556 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1557 * to the dynamic state base address.
1562 struct anv_texture_swizzle_descriptor
{
1565 * See also nir_intrinsic_channel_select_intel
1569 /** Unused padding to ensure the struct is a multiple of 64 bits */
1573 /** Struct representing a storage image descriptor */
1574 struct anv_storage_image_descriptor
{
1575 /** Bindless image handles
1577 * These are expected to already be shifted such that the 20-bit
1578 * SURFACE_STATE table index is in the top 20 bits.
1580 uint32_t read_write
;
1581 uint32_t write_only
;
1584 /** Struct representing a address/range descriptor
1586 * The fields of this struct correspond directly to the data layout of
1587 * nir_address_format_64bit_bounded_global addresses. The last field is the
1588 * offset in the NIR address so it must be zero so that when you load the
1589 * descriptor you get a pointer to the start of the range.
1591 struct anv_address_range_descriptor
{
1597 enum anv_descriptor_data
{
1598 /** The descriptor contains a BTI reference to a surface state */
1599 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1600 /** The descriptor contains a BTI reference to a sampler state */
1601 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1602 /** The descriptor contains an actual buffer view */
1603 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1604 /** The descriptor contains auxiliary image layout data */
1605 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1606 /** The descriptor contains auxiliary image layout data */
1607 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1608 /** anv_address_range_descriptor with a buffer address and range */
1609 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1610 /** Bindless surface handle */
1611 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1612 /** Storage image handles */
1613 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1614 /** Storage image handles */
1615 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1618 struct anv_descriptor_set_binding_layout
{
1620 /* The type of the descriptors in this binding */
1621 VkDescriptorType type
;
1624 /* Flags provided when this binding was created */
1625 VkDescriptorBindingFlagsEXT flags
;
1627 /* Bitfield representing the type of data this descriptor contains */
1628 enum anv_descriptor_data data
;
1630 /* Maximum number of YCbCr texture/sampler planes */
1631 uint8_t max_plane_count
;
1633 /* Number of array elements in this binding (or size in bytes for inline
1636 uint16_t array_size
;
1638 /* Index into the flattend descriptor set */
1639 uint16_t descriptor_index
;
1641 /* Index into the dynamic state array for a dynamic buffer */
1642 int16_t dynamic_offset_index
;
1644 /* Index into the descriptor set buffer views */
1645 int16_t buffer_view_index
;
1647 /* Offset into the descriptor buffer where this descriptor lives */
1648 uint32_t descriptor_offset
;
1650 /* Immutable samplers (or NULL if no immutable samplers) */
1651 struct anv_sampler
**immutable_samplers
;
1654 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1656 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1657 VkDescriptorType type
);
1659 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1660 const struct anv_descriptor_set_binding_layout
*binding
,
1663 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1664 const struct anv_descriptor_set_binding_layout
*binding
,
1667 struct anv_descriptor_set_layout
{
1668 /* Descriptor set layouts can be destroyed at almost any time */
1671 /* Number of bindings in this descriptor set */
1672 uint16_t binding_count
;
1674 /* Total size of the descriptor set with room for all array entries */
1677 /* Shader stages affected by this descriptor set */
1678 uint16_t shader_stages
;
1680 /* Number of buffer views in this descriptor set */
1681 uint16_t buffer_view_count
;
1683 /* Number of dynamic offsets used by this descriptor set */
1684 uint16_t dynamic_offset_count
;
1686 /* Size of the descriptor buffer for this descriptor set */
1687 uint32_t descriptor_buffer_size
;
1689 /* Bindings in this descriptor set */
1690 struct anv_descriptor_set_binding_layout binding
[0];
1694 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1696 assert(layout
&& layout
->ref_cnt
>= 1);
1697 p_atomic_inc(&layout
->ref_cnt
);
1701 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1702 struct anv_descriptor_set_layout
*layout
)
1704 assert(layout
&& layout
->ref_cnt
>= 1);
1705 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1706 vk_free(&device
->alloc
, layout
);
1709 struct anv_descriptor
{
1710 VkDescriptorType type
;
1714 VkImageLayout layout
;
1715 struct anv_image_view
*image_view
;
1716 struct anv_sampler
*sampler
;
1720 struct anv_buffer
*buffer
;
1725 struct anv_buffer_view
*buffer_view
;
1729 struct anv_descriptor_set
{
1730 struct anv_descriptor_pool
*pool
;
1731 struct anv_descriptor_set_layout
*layout
;
1734 /* State relative to anv_descriptor_pool::bo */
1735 struct anv_state desc_mem
;
1736 /* Surface state for the descriptor buffer */
1737 struct anv_state desc_surface_state
;
1739 uint32_t buffer_view_count
;
1740 struct anv_buffer_view
*buffer_views
;
1742 /* Link to descriptor pool's desc_sets list . */
1743 struct list_head pool_link
;
1745 struct anv_descriptor descriptors
[0];
1748 struct anv_buffer_view
{
1749 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1750 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1752 struct anv_address address
;
1754 struct anv_state surface_state
;
1755 struct anv_state storage_surface_state
;
1756 struct anv_state writeonly_storage_surface_state
;
1758 struct brw_image_param storage_image_param
;
1761 struct anv_push_descriptor_set
{
1762 struct anv_descriptor_set set
;
1764 /* Put this field right behind anv_descriptor_set so it fills up the
1765 * descriptors[0] field. */
1766 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1768 /** True if the descriptor set buffer has been referenced by a draw or
1771 bool set_used_on_gpu
;
1773 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1776 struct anv_descriptor_pool
{
1782 struct util_vma_heap bo_heap
;
1784 struct anv_state_stream surface_state_stream
;
1785 void *surface_state_free_list
;
1787 struct list_head desc_sets
;
1792 enum anv_descriptor_template_entry_type
{
1793 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1794 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1795 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1798 struct anv_descriptor_template_entry
{
1799 /* The type of descriptor in this entry */
1800 VkDescriptorType type
;
1802 /* Binding in the descriptor set */
1805 /* Offset at which to write into the descriptor set binding */
1806 uint32_t array_element
;
1808 /* Number of elements to write into the descriptor set binding */
1809 uint32_t array_count
;
1811 /* Offset into the user provided data */
1814 /* Stride between elements into the user provided data */
1818 struct anv_descriptor_update_template
{
1819 VkPipelineBindPoint bind_point
;
1821 /* The descriptor set this template corresponds to. This value is only
1822 * valid if the template was created with the templateType
1823 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1827 /* Number of entries in this template */
1828 uint32_t entry_count
;
1830 /* Entries of the template */
1831 struct anv_descriptor_template_entry entries
[0];
1835 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1838 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1839 struct anv_descriptor_set
*set
,
1840 const VkDescriptorImageInfo
* const info
,
1841 VkDescriptorType type
,
1846 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1847 struct anv_descriptor_set
*set
,
1848 VkDescriptorType type
,
1849 struct anv_buffer_view
*buffer_view
,
1854 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1855 struct anv_descriptor_set
*set
,
1856 struct anv_state_stream
*alloc_stream
,
1857 VkDescriptorType type
,
1858 struct anv_buffer
*buffer
,
1861 VkDeviceSize offset
,
1862 VkDeviceSize range
);
1864 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1865 struct anv_descriptor_set
*set
,
1872 anv_descriptor_set_write_template(struct anv_device
*device
,
1873 struct anv_descriptor_set
*set
,
1874 struct anv_state_stream
*alloc_stream
,
1875 const struct anv_descriptor_update_template
*template,
1879 anv_descriptor_set_create(struct anv_device
*device
,
1880 struct anv_descriptor_pool
*pool
,
1881 struct anv_descriptor_set_layout
*layout
,
1882 struct anv_descriptor_set
**out_set
);
1885 anv_descriptor_set_destroy(struct anv_device
*device
,
1886 struct anv_descriptor_pool
*pool
,
1887 struct anv_descriptor_set
*set
);
1889 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1890 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1891 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1892 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1894 struct anv_pipeline_binding
{
1895 /* The descriptor set this surface corresponds to. The special value of
1896 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1897 * to a color attachment and not a regular descriptor.
1901 /* Binding in the descriptor set */
1904 /* Index in the binding */
1907 /* Plane in the binding index */
1910 /* Input attachment index (relative to the subpass) */
1911 uint8_t input_attachment_index
;
1913 /* For a storage image, whether it is write-only */
1917 struct anv_pipeline_layout
{
1919 struct anv_descriptor_set_layout
*layout
;
1920 uint32_t dynamic_offset_start
;
1925 unsigned char sha1
[20];
1929 struct anv_device
* device
;
1932 VkBufferUsageFlags usage
;
1934 /* Set when bound */
1935 struct anv_address address
;
1938 static inline uint64_t
1939 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1941 assert(offset
<= buffer
->size
);
1942 if (range
== VK_WHOLE_SIZE
) {
1943 return buffer
->size
- offset
;
1945 assert(range
+ offset
>= range
);
1946 assert(range
+ offset
<= buffer
->size
);
1951 enum anv_cmd_dirty_bits
{
1952 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1953 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1954 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1955 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1956 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1957 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1958 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1959 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1960 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1961 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1962 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1963 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1964 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1965 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
1967 typedef uint32_t anv_cmd_dirty_mask_t
;
1969 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
1970 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
1971 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
1972 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
1973 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
1974 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
1975 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
1976 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
1977 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
1978 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
1979 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
1981 static inline enum anv_cmd_dirty_bits
1982 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
1985 case VK_DYNAMIC_STATE_VIEWPORT
:
1986 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
1987 case VK_DYNAMIC_STATE_SCISSOR
:
1988 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1989 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1990 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
1991 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1992 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1993 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1994 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
1995 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1996 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
1997 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1998 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
1999 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2000 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2001 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2002 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2003 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2004 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2006 assert(!"Unsupported dynamic state");
2012 enum anv_pipe_bits
{
2013 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2014 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2015 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2016 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2017 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2018 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2019 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2020 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2021 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2022 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2023 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2025 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2026 * a flush has happened but not a CS stall. The next time we do any sort
2027 * of invalidation we need to insert a CS stall at that time. Otherwise,
2028 * we would have to CS stall on every flush which could be bad.
2030 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2032 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2033 * target operations related to transfer commands with VkBuffer as
2034 * destination are ongoing. Some operations like copies on the command
2035 * streamer might need to be aware of this to trigger the appropriate stall
2036 * before they can proceed with the copy.
2038 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2041 #define ANV_PIPE_FLUSH_BITS ( \
2042 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2043 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2044 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
2046 #define ANV_PIPE_STALL_BITS ( \
2047 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2048 ANV_PIPE_DEPTH_STALL_BIT | \
2049 ANV_PIPE_CS_STALL_BIT)
2051 #define ANV_PIPE_INVALIDATE_BITS ( \
2052 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2053 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2054 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2055 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2056 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2057 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2059 static inline enum anv_pipe_bits
2060 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2062 enum anv_pipe_bits pipe_bits
= 0;
2065 for_each_bit(b
, flags
) {
2066 switch ((VkAccessFlagBits
)(1 << b
)) {
2067 case VK_ACCESS_SHADER_WRITE_BIT
:
2068 /* We're transitioning a buffer that was previously used as write
2069 * destination through the data port. To make its content available
2070 * to future operations, flush the data cache.
2072 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2074 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2075 /* We're transitioning a buffer that was previously used as render
2076 * target. To make its content available to future operations, flush
2077 * the render target cache.
2079 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2081 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2082 /* We're transitioning a buffer that was previously used as depth
2083 * buffer. To make its content available to future operations, flush
2086 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2088 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2089 /* We're transitioning a buffer that was previously used as a
2090 * transfer write destination. Generic write operations include color
2091 * & depth operations as well as buffer operations like :
2092 * - vkCmdClearColorImage()
2093 * - vkCmdClearDepthStencilImage()
2094 * - vkCmdBlitImage()
2095 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2097 * Most of these operations are implemented using Blorp which writes
2098 * through the render target, so flush that cache to make it visible
2099 * to future operations. And for depth related operations we also
2100 * need to flush the depth cache.
2102 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2103 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2105 case VK_ACCESS_MEMORY_WRITE_BIT
:
2106 /* We're transitioning a buffer for generic write operations. Flush
2109 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2112 break; /* Nothing to do */
2119 static inline enum anv_pipe_bits
2120 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2122 enum anv_pipe_bits pipe_bits
= 0;
2125 for_each_bit(b
, flags
) {
2126 switch ((VkAccessFlagBits
)(1 << b
)) {
2127 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2128 /* Indirect draw commands take a buffer as input that we're going to
2129 * read from the command streamer to load some of the HW registers
2130 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2131 * command streamer stall so that all the cache flushes have
2132 * completed before the command streamer loads from memory.
2134 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2135 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2136 * through a vertex buffer, so invalidate that cache.
2138 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2139 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2140 * UBO from the buffer, so we need to invalidate constant cache.
2142 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2144 case VK_ACCESS_INDEX_READ_BIT
:
2145 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2146 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2147 * commands, so we invalidate the VF cache to make sure there is no
2148 * stale data when we start rendering.
2150 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2152 case VK_ACCESS_UNIFORM_READ_BIT
:
2153 /* We transitioning a buffer to be used as uniform data. Because
2154 * uniform is accessed through the data port & sampler, we need to
2155 * invalidate the texture cache (sampler) & constant cache (data
2156 * port) to avoid stale data.
2158 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2159 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2161 case VK_ACCESS_SHADER_READ_BIT
:
2162 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2163 case VK_ACCESS_TRANSFER_READ_BIT
:
2164 /* Transitioning a buffer to be read through the sampler, so
2165 * invalidate the texture cache, we don't want any stale data.
2167 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2169 case VK_ACCESS_MEMORY_READ_BIT
:
2170 /* Transitioning a buffer for generic read, invalidate all the
2173 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2175 case VK_ACCESS_MEMORY_WRITE_BIT
:
2176 /* Generic write, make sure all previously written things land in
2179 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2181 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2182 /* Transitioning a buffer for conditional rendering. We'll load the
2183 * content of this buffer into HW registers using the command
2184 * streamer, so we need to stall the command streamer to make sure
2185 * any in-flight flush operations have completed.
2187 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2190 break; /* Nothing to do */
2197 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2198 VK_IMAGE_ASPECT_COLOR_BIT | \
2199 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2200 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2201 VK_IMAGE_ASPECT_PLANE_2_BIT)
2202 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2203 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2204 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2205 VK_IMAGE_ASPECT_PLANE_2_BIT)
2207 struct anv_vertex_binding
{
2208 struct anv_buffer
* buffer
;
2209 VkDeviceSize offset
;
2212 struct anv_xfb_binding
{
2213 struct anv_buffer
* buffer
;
2214 VkDeviceSize offset
;
2218 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2219 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2220 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2222 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2223 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2224 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2226 struct anv_push_constants
{
2227 /* Push constant data provided by the client through vkPushConstants */
2228 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2230 /* Used for vkCmdDispatchBase */
2231 uint32_t base_work_group_id
[3];
2234 struct anv_dynamic_state
{
2237 VkViewport viewports
[MAX_VIEWPORTS
];
2242 VkRect2D scissors
[MAX_SCISSORS
];
2253 float blend_constants
[4];
2263 } stencil_compare_mask
;
2268 } stencil_write_mask
;
2273 } stencil_reference
;
2281 extern const struct anv_dynamic_state default_dynamic_state
;
2283 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2284 const struct anv_dynamic_state
*src
,
2285 uint32_t copy_mask
);
2287 struct anv_surface_state
{
2288 struct anv_state state
;
2289 /** Address of the surface referred to by this state
2291 * This address is relative to the start of the BO.
2293 struct anv_address address
;
2294 /* Address of the aux surface, if any
2296 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2298 * With the exception of gen8, the bottom 12 bits of this address' offset
2299 * include extra aux information.
2301 struct anv_address aux_address
;
2302 /* Address of the clear color, if any
2304 * This address is relative to the start of the BO.
2306 struct anv_address clear_address
;
2310 * Attachment state when recording a renderpass instance.
2312 * The clear value is valid only if there exists a pending clear.
2314 struct anv_attachment_state
{
2315 enum isl_aux_usage aux_usage
;
2316 enum isl_aux_usage input_aux_usage
;
2317 struct anv_surface_state color
;
2318 struct anv_surface_state input
;
2320 VkImageLayout current_layout
;
2321 VkImageAspectFlags pending_clear_aspects
;
2322 VkImageAspectFlags pending_load_aspects
;
2324 VkClearValue clear_value
;
2325 bool clear_color_is_zero_one
;
2326 bool clear_color_is_zero
;
2328 /* When multiview is active, attachments with a renderpass clear
2329 * operation have their respective layers cleared on the first
2330 * subpass that uses them, and only in that subpass. We keep track
2331 * of this using a bitfield to indicate which layers of an attachment
2332 * have not been cleared yet when multiview is active.
2334 uint32_t pending_clear_views
;
2335 struct anv_image_view
* image_view
;
2338 /** State tracking for particular pipeline bind point
2340 * This struct is the base struct for anv_cmd_graphics_state and
2341 * anv_cmd_compute_state. These are used to track state which is bound to a
2342 * particular type of pipeline. Generic state that applies per-stage such as
2343 * binding table offsets and push constants is tracked generically with a
2344 * per-stage array in anv_cmd_state.
2346 struct anv_cmd_pipeline_state
{
2347 struct anv_pipeline
*pipeline
;
2348 struct anv_pipeline_layout
*layout
;
2350 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2351 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2353 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2356 /** State tracking for graphics pipeline
2358 * This has anv_cmd_pipeline_state as a base struct to track things which get
2359 * bound to a graphics pipeline. Along with general pipeline bind point state
2360 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2361 * state which is graphics-specific.
2363 struct anv_cmd_graphics_state
{
2364 struct anv_cmd_pipeline_state base
;
2366 anv_cmd_dirty_mask_t dirty
;
2369 struct anv_dynamic_state dynamic
;
2372 struct anv_buffer
*index_buffer
;
2373 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2374 uint32_t index_offset
;
2378 /** State tracking for compute pipeline
2380 * This has anv_cmd_pipeline_state as a base struct to track things which get
2381 * bound to a compute pipeline. Along with general pipeline bind point state
2382 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2383 * state which is compute-specific.
2385 struct anv_cmd_compute_state
{
2386 struct anv_cmd_pipeline_state base
;
2388 bool pipeline_dirty
;
2390 struct anv_address num_workgroups
;
2393 /** State required while building cmd buffer */
2394 struct anv_cmd_state
{
2395 /* PIPELINE_SELECT.PipelineSelection */
2396 uint32_t current_pipeline
;
2397 const struct gen_l3_config
* current_l3_config
;
2399 struct anv_cmd_graphics_state gfx
;
2400 struct anv_cmd_compute_state compute
;
2402 enum anv_pipe_bits pending_pipe_bits
;
2403 VkShaderStageFlags descriptors_dirty
;
2404 VkShaderStageFlags push_constants_dirty
;
2406 struct anv_framebuffer
* framebuffer
;
2407 struct anv_render_pass
* pass
;
2408 struct anv_subpass
* subpass
;
2409 VkRect2D render_area
;
2410 uint32_t restart_index
;
2411 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2413 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2414 VkShaderStageFlags push_constant_stages
;
2415 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2416 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2417 struct anv_state samplers
[MESA_SHADER_STAGES
];
2420 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2421 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2422 * and before invoking the secondary in ExecuteCommands.
2424 bool pma_fix_enabled
;
2427 * Whether or not we know for certain that HiZ is enabled for the current
2428 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2429 * enabled or not, this will be false.
2433 bool conditional_render_enabled
;
2436 * Last rendering scale argument provided to
2437 * genX(cmd_buffer_emit_hashing_mode)().
2439 unsigned current_hash_scale
;
2442 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2443 * valid only when recording a render pass instance.
2445 struct anv_attachment_state
* attachments
;
2448 * Surface states for color render targets. These are stored in a single
2449 * flat array. For depth-stencil attachments, the surface state is simply
2452 struct anv_state render_pass_states
;
2455 * A null surface state of the right size to match the framebuffer. This
2456 * is one of the states in render_pass_states.
2458 struct anv_state null_surface_state
;
2461 struct anv_cmd_pool
{
2462 VkAllocationCallbacks alloc
;
2463 struct list_head cmd_buffers
;
2466 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2468 enum anv_cmd_buffer_exec_mode
{
2469 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2470 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2471 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2472 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2473 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2476 struct anv_cmd_buffer
{
2477 VK_LOADER_DATA _loader_data
;
2479 struct anv_device
* device
;
2481 struct anv_cmd_pool
* pool
;
2482 struct list_head pool_link
;
2484 struct anv_batch batch
;
2486 /* Fields required for the actual chain of anv_batch_bo's.
2488 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2490 struct list_head batch_bos
;
2491 enum anv_cmd_buffer_exec_mode exec_mode
;
2493 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2494 * referenced by this command buffer
2496 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2498 struct u_vector seen_bbos
;
2500 /* A vector of int32_t's for every block of binding tables.
2502 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2504 struct u_vector bt_block_states
;
2507 struct anv_reloc_list surface_relocs
;
2508 /** Last seen surface state block pool center bo offset */
2509 uint32_t last_ss_pool_center
;
2511 /* Serial for tracking buffer completion */
2514 /* Stream objects for storing temporary data */
2515 struct anv_state_stream surface_state_stream
;
2516 struct anv_state_stream dynamic_state_stream
;
2518 VkCommandBufferUsageFlags usage_flags
;
2519 VkCommandBufferLevel level
;
2521 struct anv_cmd_state state
;
2524 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2525 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2526 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2527 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2528 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2529 struct anv_cmd_buffer
*secondary
);
2530 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2531 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2532 struct anv_cmd_buffer
*cmd_buffer
,
2533 const VkSemaphore
*in_semaphores
,
2534 uint32_t num_in_semaphores
,
2535 const VkSemaphore
*out_semaphores
,
2536 uint32_t num_out_semaphores
,
2539 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2541 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2542 const void *data
, uint32_t size
, uint32_t alignment
);
2543 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2544 uint32_t *a
, uint32_t *b
,
2545 uint32_t dwords
, uint32_t alignment
);
2548 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2550 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2551 uint32_t entries
, uint32_t *state_offset
);
2553 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2555 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2556 uint32_t size
, uint32_t alignment
);
2559 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2561 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2562 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2563 bool depth_clamp_enable
);
2564 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2566 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2567 struct anv_render_pass
*pass
,
2568 struct anv_framebuffer
*framebuffer
,
2569 const VkClearValue
*clear_values
);
2571 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2574 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2575 gl_shader_stage stage
);
2577 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2579 const struct anv_image_view
*
2580 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2583 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2584 uint32_t num_entries
,
2585 uint32_t *state_offset
,
2586 struct anv_state
*bt_state
);
2588 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2590 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2592 enum anv_fence_type
{
2593 ANV_FENCE_TYPE_NONE
= 0,
2595 ANV_FENCE_TYPE_SYNCOBJ
,
2599 enum anv_bo_fence_state
{
2600 /** Indicates that this is a new (or newly reset fence) */
2601 ANV_BO_FENCE_STATE_RESET
,
2603 /** Indicates that this fence has been submitted to the GPU but is still
2604 * (as far as we know) in use by the GPU.
2606 ANV_BO_FENCE_STATE_SUBMITTED
,
2608 ANV_BO_FENCE_STATE_SIGNALED
,
2611 struct anv_fence_impl
{
2612 enum anv_fence_type type
;
2615 /** Fence implementation for BO fences
2617 * These fences use a BO and a set of CPU-tracked state flags. The BO
2618 * is added to the object list of the last execbuf call in a QueueSubmit
2619 * and is marked EXEC_WRITE. The state flags track when the BO has been
2620 * submitted to the kernel. We need to do this because Vulkan lets you
2621 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2622 * will say it's idle in this case.
2626 enum anv_bo_fence_state state
;
2629 /** DRM syncobj handle for syncobj-based fences */
2633 struct wsi_fence
*fence_wsi
;
2638 /* Permanent fence state. Every fence has some form of permanent state
2639 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2640 * cross-process fences) or it could just be a dummy for use internally.
2642 struct anv_fence_impl permanent
;
2644 /* Temporary fence state. A fence *may* have temporary state. That state
2645 * is added to the fence by an import operation and is reset back to
2646 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2647 * state cannot be signaled because the fence must already be signaled
2648 * before the temporary state can be exported from the fence in the other
2649 * process and imported here.
2651 struct anv_fence_impl temporary
;
2656 struct anv_state state
;
2659 enum anv_semaphore_type
{
2660 ANV_SEMAPHORE_TYPE_NONE
= 0,
2661 ANV_SEMAPHORE_TYPE_DUMMY
,
2662 ANV_SEMAPHORE_TYPE_BO
,
2663 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2664 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2667 struct anv_semaphore_impl
{
2668 enum anv_semaphore_type type
;
2671 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2672 * This BO will be added to the object list on any execbuf2 calls for
2673 * which this semaphore is used as a wait or signal fence. When used as
2674 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2678 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2679 * If the semaphore is in the unsignaled state due to either just being
2680 * created or because it has been used for a wait, fd will be -1.
2684 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2685 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2686 * import so we don't need to bother with a userspace cache.
2692 struct anv_semaphore
{
2693 /* Permanent semaphore state. Every semaphore has some form of permanent
2694 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2695 * (for cross-process semaphores0 or it could just be a dummy for use
2698 struct anv_semaphore_impl permanent
;
2700 /* Temporary semaphore state. A semaphore *may* have temporary state.
2701 * That state is added to the semaphore by an import operation and is reset
2702 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2703 * semaphore with temporary state cannot be signaled because the semaphore
2704 * must already be signaled before the temporary state can be exported from
2705 * the semaphore in the other process and imported here.
2707 struct anv_semaphore_impl temporary
;
2710 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2711 struct anv_semaphore
*semaphore
);
2713 struct anv_shader_module
{
2714 unsigned char sha1
[20];
2719 static inline gl_shader_stage
2720 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2722 assert(__builtin_popcount(vk_stage
) == 1);
2723 return ffs(vk_stage
) - 1;
2726 static inline VkShaderStageFlagBits
2727 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2729 return (1 << mesa_stage
);
2732 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2734 #define anv_foreach_stage(stage, stage_bits) \
2735 for (gl_shader_stage stage, \
2736 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2737 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2738 __tmp &= ~(1 << (stage)))
2740 struct anv_pipeline_bind_map
{
2741 uint32_t surface_count
;
2742 uint32_t sampler_count
;
2744 struct anv_pipeline_binding
* surface_to_descriptor
;
2745 struct anv_pipeline_binding
* sampler_to_descriptor
;
2748 struct anv_shader_bin_key
{
2753 struct anv_shader_bin
{
2756 const struct anv_shader_bin_key
*key
;
2758 struct anv_state kernel
;
2759 uint32_t kernel_size
;
2761 struct anv_state constant_data
;
2762 uint32_t constant_data_size
;
2764 const struct brw_stage_prog_data
*prog_data
;
2765 uint32_t prog_data_size
;
2767 struct brw_compile_stats stats
[3];
2770 struct nir_xfb_info
*xfb_info
;
2772 struct anv_pipeline_bind_map bind_map
;
2775 struct anv_shader_bin
*
2776 anv_shader_bin_create(struct anv_device
*device
,
2777 const void *key
, uint32_t key_size
,
2778 const void *kernel
, uint32_t kernel_size
,
2779 const void *constant_data
, uint32_t constant_data_size
,
2780 const struct brw_stage_prog_data
*prog_data
,
2781 uint32_t prog_data_size
, const void *prog_data_param
,
2782 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2783 const struct nir_xfb_info
*xfb_info
,
2784 const struct anv_pipeline_bind_map
*bind_map
);
2787 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2790 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2792 assert(shader
&& shader
->ref_cnt
>= 1);
2793 p_atomic_inc(&shader
->ref_cnt
);
2797 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2799 assert(shader
&& shader
->ref_cnt
>= 1);
2800 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2801 anv_shader_bin_destroy(device
, shader
);
2804 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2805 #define MAX_PIPELINE_EXECUTABLES 7
2807 struct anv_pipeline_executable
{
2808 gl_shader_stage stage
;
2810 struct brw_compile_stats stats
;
2815 struct anv_pipeline
{
2816 struct anv_device
* device
;
2817 struct anv_batch batch
;
2818 uint32_t batch_data
[512];
2819 struct anv_reloc_list batch_relocs
;
2820 anv_cmd_dirty_mask_t dynamic_state_mask
;
2821 struct anv_dynamic_state dynamic_state
;
2825 VkPipelineCreateFlags flags
;
2826 struct anv_subpass
* subpass
;
2828 bool needs_data_cache
;
2830 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2832 uint32_t num_executables
;
2833 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2836 const struct gen_l3_config
* l3_config
;
2837 uint32_t total_size
;
2840 VkShaderStageFlags active_stages
;
2841 struct anv_state blend_state
;
2844 struct anv_pipeline_vertex_binding
{
2847 uint32_t instance_divisor
;
2852 bool primitive_restart
;
2855 uint32_t cs_right_mask
;
2858 bool depth_test_enable
;
2859 bool writes_stencil
;
2860 bool stencil_test_enable
;
2861 bool depth_clamp_enable
;
2862 bool depth_clip_enable
;
2863 bool sample_shading_enable
;
2868 uint32_t depth_stencil_state
[3];
2874 uint32_t wm_depth_stencil
[3];
2878 uint32_t wm_depth_stencil
[4];
2881 uint32_t interface_descriptor_data
[8];
2885 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2886 gl_shader_stage stage
)
2888 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2891 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2892 static inline const struct brw_##prefix##_prog_data * \
2893 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2895 if (anv_pipeline_has_stage(pipeline, stage)) { \
2896 return (const struct brw_##prefix##_prog_data *) \
2897 pipeline->shaders[stage]->prog_data; \
2903 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2904 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2905 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2906 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2907 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2908 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2910 static inline const struct brw_vue_prog_data
*
2911 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2913 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2914 return &get_gs_prog_data(pipeline
)->base
;
2915 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2916 return &get_tes_prog_data(pipeline
)->base
;
2918 return &get_vs_prog_data(pipeline
)->base
;
2922 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2923 struct anv_pipeline_cache
*cache
,
2924 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2925 const VkAllocationCallbacks
*alloc
);
2928 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2929 struct anv_pipeline_cache
*cache
,
2930 const VkComputePipelineCreateInfo
*info
,
2931 const struct anv_shader_module
*module
,
2932 const char *entrypoint
,
2933 const VkSpecializationInfo
*spec_info
);
2935 struct anv_format_plane
{
2936 enum isl_format isl_format
:16;
2937 struct isl_swizzle swizzle
;
2939 /* Whether this plane contains chroma channels */
2942 /* For downscaling of YUV planes */
2943 uint8_t denominator_scales
[2];
2945 /* How to map sampled ycbcr planes to a single 4 component element. */
2946 struct isl_swizzle ycbcr_swizzle
;
2948 /* What aspect is associated to this plane */
2949 VkImageAspectFlags aspect
;
2954 struct anv_format_plane planes
[3];
2960 static inline uint32_t
2961 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2962 VkImageAspectFlags aspect_mask
)
2964 switch (aspect_mask
) {
2965 case VK_IMAGE_ASPECT_COLOR_BIT
:
2966 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2967 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2969 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2970 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2973 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2975 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2978 /* Purposefully assert with depth/stencil aspects. */
2979 unreachable("invalid image aspect");
2983 static inline VkImageAspectFlags
2984 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2987 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2988 if (util_bitcount(image_aspects
) > 1)
2989 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2990 return VK_IMAGE_ASPECT_COLOR_BIT
;
2992 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2993 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2994 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2995 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2998 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2999 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3001 const struct anv_format
*
3002 anv_get_format(VkFormat format
);
3004 static inline uint32_t
3005 anv_get_format_planes(VkFormat vk_format
)
3007 const struct anv_format
*format
= anv_get_format(vk_format
);
3009 return format
!= NULL
? format
->n_planes
: 0;
3012 struct anv_format_plane
3013 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3014 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3016 static inline enum isl_format
3017 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3018 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3020 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3023 static inline struct isl_swizzle
3024 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3026 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3027 * RGB as RGBA for texturing
3029 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3030 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3032 /* But it doesn't matter what we render to that channel */
3033 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3039 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3042 * Subsurface of an anv_image.
3044 struct anv_surface
{
3045 /** Valid only if isl_surf::size_B > 0. */
3046 struct isl_surf isl
;
3049 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3055 VkImageType type
; /**< VkImageCreateInfo::imageType */
3056 /* The original VkFormat provided by the client. This may not match any
3057 * of the actual surface formats.
3060 const struct anv_format
*format
;
3062 VkImageAspectFlags aspects
;
3065 uint32_t array_size
;
3066 uint32_t samples
; /**< VkImageCreateInfo::samples */
3068 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3069 VkImageUsageFlags stencil_usage
;
3070 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3071 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3073 /** True if this is needs to be bound to an appropriately tiled BO.
3075 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3076 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3077 * we require a dedicated allocation so that we can know to allocate a
3080 bool needs_set_tiling
;
3083 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3084 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3086 uint64_t drm_format_mod
;
3091 /* Whether the image is made of several underlying buffer objects rather a
3092 * single one with different offsets.
3096 /* All the formats that can be used when creating views of this image
3097 * are CCS_E compatible.
3099 bool ccs_e_compatible
;
3101 /* Image was created with external format. */
3102 bool external_format
;
3107 * For each foo, anv_image::planes[x].surface is valid if and only if
3108 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3109 * to figure the number associated with a given aspect.
3111 * The hardware requires that the depth buffer and stencil buffer be
3112 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3113 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3114 * allocate the depth and stencil buffers as separate surfaces in the same
3119 * -----------------------
3121 * ----------------------- |
3122 * | shadow surface0 | |
3123 * ----------------------- | Plane 0
3124 * | aux surface0 | |
3125 * ----------------------- |
3126 * | fast clear colors0 | \|/
3127 * -----------------------
3129 * ----------------------- |
3130 * | shadow surface1 | |
3131 * ----------------------- | Plane 1
3132 * | aux surface1 | |
3133 * ----------------------- |
3134 * | fast clear colors1 | \|/
3135 * -----------------------
3138 * -----------------------
3142 * Offset of the entire plane (whenever the image is disjoint this is
3150 struct anv_surface surface
;
3153 * A surface which shadows the main surface and may have different
3154 * tiling. This is used for sampling using a tiling that isn't supported
3155 * for other operations.
3157 struct anv_surface shadow_surface
;
3160 * For color images, this is the aux usage for this image when not used
3161 * as a color attachment.
3163 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3164 * image has a HiZ buffer.
3166 enum isl_aux_usage aux_usage
;
3168 struct anv_surface aux_surface
;
3171 * Offset of the fast clear state (used to compute the
3172 * fast_clear_state_offset of the following planes).
3174 uint32_t fast_clear_state_offset
;
3177 * BO associated with this plane, set when bound.
3179 struct anv_address address
;
3182 * When destroying the image, also free the bo.
3188 /* The ordering of this enum is important */
3189 enum anv_fast_clear_type
{
3190 /** Image does not have/support any fast-clear blocks */
3191 ANV_FAST_CLEAR_NONE
= 0,
3192 /** Image has/supports fast-clear but only to the default value */
3193 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3194 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3195 ANV_FAST_CLEAR_ANY
= 2,
3198 /* Returns the number of auxiliary buffer levels attached to an image. */
3199 static inline uint8_t
3200 anv_image_aux_levels(const struct anv_image
* const image
,
3201 VkImageAspectFlagBits aspect
)
3203 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3204 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3205 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
3208 /* Returns the number of auxiliary buffer layers attached to an image. */
3209 static inline uint32_t
3210 anv_image_aux_layers(const struct anv_image
* const image
,
3211 VkImageAspectFlagBits aspect
,
3212 const uint8_t miplevel
)
3216 /* The miplevel must exist in the main buffer. */
3217 assert(miplevel
< image
->levels
);
3219 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3220 /* There are no layers with auxiliary data because the miplevel has no
3225 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3226 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
3227 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
3231 static inline struct anv_address
3232 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3233 const struct anv_image
*image
,
3234 VkImageAspectFlagBits aspect
)
3236 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3238 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3239 return anv_address_add(image
->planes
[plane
].address
,
3240 image
->planes
[plane
].fast_clear_state_offset
);
3243 static inline struct anv_address
3244 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3245 const struct anv_image
*image
,
3246 VkImageAspectFlagBits aspect
)
3248 struct anv_address addr
=
3249 anv_image_get_clear_color_addr(device
, image
, aspect
);
3251 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3252 device
->isl_dev
.ss
.clear_color_state_size
:
3253 device
->isl_dev
.ss
.clear_value_size
;
3254 return anv_address_add(addr
, clear_color_state_size
);
3257 static inline struct anv_address
3258 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3259 const struct anv_image
*image
,
3260 VkImageAspectFlagBits aspect
,
3261 uint32_t level
, uint32_t array_layer
)
3263 assert(level
< anv_image_aux_levels(image
, aspect
));
3264 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3265 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3266 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3268 struct anv_address addr
=
3269 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3270 addr
.offset
+= 4; /* Go past the fast clear type */
3272 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3273 for (uint32_t l
= 0; l
< level
; l
++)
3274 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3276 addr
.offset
+= level
* image
->array_size
* 4;
3278 addr
.offset
+= array_layer
* 4;
3283 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3285 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3286 const struct anv_image
*image
)
3288 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3291 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3292 * struct. There's documentation which suggests that this feature actually
3293 * reduces performance on BDW, but it has only been observed to help so
3294 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3295 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3297 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3300 return image
->samples
== 1;
3304 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3305 const struct anv_image
*image
,
3306 VkImageAspectFlagBits aspect
,
3307 enum isl_aux_usage aux_usage
,
3309 uint32_t base_layer
,
3310 uint32_t layer_count
);
3313 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3314 const struct anv_image
*image
,
3315 VkImageAspectFlagBits aspect
,
3316 enum isl_aux_usage aux_usage
,
3317 enum isl_format format
, struct isl_swizzle swizzle
,
3318 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3319 VkRect2D area
, union isl_color_value clear_color
);
3321 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3322 const struct anv_image
*image
,
3323 VkImageAspectFlags aspects
,
3324 enum isl_aux_usage depth_aux_usage
,
3326 uint32_t base_layer
, uint32_t layer_count
,
3328 float depth_value
, uint8_t stencil_value
);
3330 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3331 const struct anv_image
*src_image
,
3332 enum isl_aux_usage src_aux_usage
,
3333 uint32_t src_level
, uint32_t src_base_layer
,
3334 const struct anv_image
*dst_image
,
3335 enum isl_aux_usage dst_aux_usage
,
3336 uint32_t dst_level
, uint32_t dst_base_layer
,
3337 VkImageAspectFlagBits aspect
,
3338 uint32_t src_x
, uint32_t src_y
,
3339 uint32_t dst_x
, uint32_t dst_y
,
3340 uint32_t width
, uint32_t height
,
3341 uint32_t layer_count
,
3342 enum blorp_filter filter
);
3344 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3345 const struct anv_image
*image
,
3346 VkImageAspectFlagBits aspect
, uint32_t level
,
3347 uint32_t base_layer
, uint32_t layer_count
,
3348 enum isl_aux_op hiz_op
);
3350 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3351 const struct anv_image
*image
,
3352 VkImageAspectFlags aspects
,
3354 uint32_t base_layer
, uint32_t layer_count
,
3355 VkRect2D area
, uint8_t stencil_value
);
3357 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3358 const struct anv_image
*image
,
3359 enum isl_format format
,
3360 VkImageAspectFlagBits aspect
,
3361 uint32_t base_layer
, uint32_t layer_count
,
3362 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3365 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3366 const struct anv_image
*image
,
3367 enum isl_format format
,
3368 VkImageAspectFlagBits aspect
, uint32_t level
,
3369 uint32_t base_layer
, uint32_t layer_count
,
3370 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3374 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3375 const struct anv_image
*image
,
3376 VkImageAspectFlagBits aspect
,
3377 uint32_t base_level
, uint32_t level_count
,
3378 uint32_t base_layer
, uint32_t layer_count
);
3381 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3382 const struct anv_image
*image
,
3383 const VkImageAspectFlagBits aspect
,
3384 const VkImageLayout layout
);
3386 enum anv_fast_clear_type
3387 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3388 const struct anv_image
* const image
,
3389 const VkImageAspectFlagBits aspect
,
3390 const VkImageLayout layout
);
3392 /* This is defined as a macro so that it works for both
3393 * VkImageSubresourceRange and VkImageSubresourceLayers
3395 #define anv_get_layerCount(_image, _range) \
3396 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3397 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3399 static inline uint32_t
3400 anv_get_levelCount(const struct anv_image
*image
,
3401 const VkImageSubresourceRange
*range
)
3403 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3404 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3407 static inline VkImageAspectFlags
3408 anv_image_expand_aspects(const struct anv_image
*image
,
3409 VkImageAspectFlags aspects
)
3411 /* If the underlying image has color plane aspects and
3412 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3413 * the underlying image. */
3414 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3415 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3416 return image
->aspects
;
3422 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3423 VkImageAspectFlags aspects2
)
3425 if (aspects1
== aspects2
)
3428 /* Only 1 color aspects are compatibles. */
3429 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3430 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3431 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3437 struct anv_image_view
{
3438 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3440 VkImageAspectFlags aspect_mask
;
3442 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3446 uint32_t image_plane
;
3448 struct isl_view isl
;
3451 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3452 * image layout of SHADER_READ_ONLY_OPTIMAL or
3453 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3455 struct anv_surface_state optimal_sampler_surface_state
;
3458 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3459 * image layout of GENERAL.
3461 struct anv_surface_state general_sampler_surface_state
;
3464 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3465 * states for write-only and readable, using the real format for
3466 * write-only and the lowered format for readable.
3468 struct anv_surface_state storage_surface_state
;
3469 struct anv_surface_state writeonly_storage_surface_state
;
3471 struct brw_image_param storage_image_param
;
3475 enum anv_image_view_state_flags
{
3476 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3477 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3480 void anv_image_fill_surface_state(struct anv_device
*device
,
3481 const struct anv_image
*image
,
3482 VkImageAspectFlagBits aspect
,
3483 const struct isl_view
*view
,
3484 isl_surf_usage_flags_t view_usage
,
3485 enum isl_aux_usage aux_usage
,
3486 const union isl_color_value
*clear_color
,
3487 enum anv_image_view_state_flags flags
,
3488 struct anv_surface_state
*state_inout
,
3489 struct brw_image_param
*image_param_out
);
3491 struct anv_image_create_info
{
3492 const VkImageCreateInfo
*vk_info
;
3494 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3495 isl_tiling_flags_t isl_tiling_flags
;
3497 /** These flags will be added to any derived from VkImageCreateInfo. */
3498 isl_surf_usage_flags_t isl_extra_usage_flags
;
3501 bool external_format
;
3504 VkResult
anv_image_create(VkDevice _device
,
3505 const struct anv_image_create_info
*info
,
3506 const VkAllocationCallbacks
* alloc
,
3509 const struct anv_surface
*
3510 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3511 VkImageAspectFlags aspect_mask
);
3514 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3516 static inline struct VkExtent3D
3517 anv_sanitize_image_extent(const VkImageType imageType
,
3518 const struct VkExtent3D imageExtent
)
3520 switch (imageType
) {
3521 case VK_IMAGE_TYPE_1D
:
3522 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3523 case VK_IMAGE_TYPE_2D
:
3524 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3525 case VK_IMAGE_TYPE_3D
:
3528 unreachable("invalid image type");
3532 static inline struct VkOffset3D
3533 anv_sanitize_image_offset(const VkImageType imageType
,
3534 const struct VkOffset3D imageOffset
)
3536 switch (imageType
) {
3537 case VK_IMAGE_TYPE_1D
:
3538 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3539 case VK_IMAGE_TYPE_2D
:
3540 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3541 case VK_IMAGE_TYPE_3D
:
3544 unreachable("invalid image type");
3548 VkFormatFeatureFlags
3549 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3551 const struct anv_format
*anv_format
,
3552 VkImageTiling vk_tiling
);
3554 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3555 struct anv_state state
,
3556 enum isl_format format
,
3557 struct anv_address address
,
3558 uint32_t range
, uint32_t stride
);
3561 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3562 const struct anv_attachment_state
*att_state
,
3563 const struct anv_image_view
*iview
)
3565 const struct isl_format_layout
*view_fmtl
=
3566 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3568 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3569 if (view_fmtl->channels.c.bits) \
3570 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3572 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3573 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3574 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3575 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3577 #undef COPY_CLEAR_COLOR_CHANNEL
3581 struct anv_ycbcr_conversion
{
3582 const struct anv_format
* format
;
3583 VkSamplerYcbcrModelConversion ycbcr_model
;
3584 VkSamplerYcbcrRange ycbcr_range
;
3585 VkComponentSwizzle mapping
[4];
3586 VkChromaLocation chroma_offsets
[2];
3587 VkFilter chroma_filter
;
3588 bool chroma_reconstruction
;
3591 struct anv_sampler
{
3592 uint32_t state
[3][4];
3594 struct anv_ycbcr_conversion
*conversion
;
3596 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3597 * and with a 32-byte stride for use as bindless samplers.
3599 struct anv_state bindless_state
;
3602 struct anv_framebuffer
{
3607 uint32_t attachment_count
;
3608 struct anv_image_view
* attachments
[0];
3611 struct anv_subpass_attachment
{
3612 VkImageUsageFlagBits usage
;
3613 uint32_t attachment
;
3614 VkImageLayout layout
;
3617 struct anv_subpass
{
3618 uint32_t attachment_count
;
3621 * A pointer to all attachment references used in this subpass.
3622 * Only valid if ::attachment_count > 0.
3624 struct anv_subpass_attachment
* attachments
;
3625 uint32_t input_count
;
3626 struct anv_subpass_attachment
* input_attachments
;
3627 uint32_t color_count
;
3628 struct anv_subpass_attachment
* color_attachments
;
3629 struct anv_subpass_attachment
* resolve_attachments
;
3631 struct anv_subpass_attachment
* depth_stencil_attachment
;
3632 struct anv_subpass_attachment
* ds_resolve_attachment
;
3633 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3634 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3638 /** Subpass has a depth/stencil self-dependency */
3639 bool has_ds_self_dep
;
3641 /** Subpass has at least one color resolve attachment */
3642 bool has_color_resolve
;
3645 static inline unsigned
3646 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3648 return MAX2(1, util_bitcount(subpass
->view_mask
));
3651 struct anv_render_pass_attachment
{
3652 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3653 * its members individually.
3657 VkImageUsageFlags usage
;
3658 VkAttachmentLoadOp load_op
;
3659 VkAttachmentStoreOp store_op
;
3660 VkAttachmentLoadOp stencil_load_op
;
3661 VkImageLayout initial_layout
;
3662 VkImageLayout final_layout
;
3663 VkImageLayout first_subpass_layout
;
3665 /* The subpass id in which the attachment will be used last. */
3666 uint32_t last_subpass_idx
;
3669 struct anv_render_pass
{
3670 uint32_t attachment_count
;
3671 uint32_t subpass_count
;
3672 /* An array of subpass_count+1 flushes, one per subpass boundary */
3673 enum anv_pipe_bits
* subpass_flushes
;
3674 struct anv_render_pass_attachment
* attachments
;
3675 struct anv_subpass subpasses
[0];
3678 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3680 struct anv_query_pool
{
3682 VkQueryPipelineStatisticFlags pipeline_statistics
;
3683 /** Stride between slots, in bytes */
3685 /** Number of slots in this query pool */
3690 int anv_get_instance_entrypoint_index(const char *name
);
3691 int anv_get_device_entrypoint_index(const char *name
);
3694 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3695 const struct anv_instance_extension_table
*instance
);
3698 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3699 const struct anv_instance_extension_table
*instance
,
3700 const struct anv_device_extension_table
*device
);
3702 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3705 void anv_dump_image_to_ppm(struct anv_device
*device
,
3706 struct anv_image
*image
, unsigned miplevel
,
3707 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3708 const char *filename
);
3710 enum anv_dump_action
{
3711 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3714 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3715 void anv_dump_finish(void);
3717 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3719 static inline uint32_t
3720 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3722 /* This function must be called from within a subpass. */
3723 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3725 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3727 /* The id of this subpass shouldn't exceed the number of subpasses in this
3728 * render pass minus 1.
3730 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3734 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3736 static inline struct __anv_type * \
3737 __anv_type ## _from_handle(__VkType _handle) \
3739 return (struct __anv_type *) _handle; \
3742 static inline __VkType \
3743 __anv_type ## _to_handle(struct __anv_type *_obj) \
3745 return (__VkType) _obj; \
3748 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3750 static inline struct __anv_type * \
3751 __anv_type ## _from_handle(__VkType _handle) \
3753 return (struct __anv_type *)(uintptr_t) _handle; \
3756 static inline __VkType \
3757 __anv_type ## _to_handle(struct __anv_type *_obj) \
3759 return (__VkType)(uintptr_t) _obj; \
3762 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3763 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3765 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3766 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3767 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3768 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3769 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3771 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3772 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3773 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3774 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3775 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3776 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3777 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3778 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3779 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3780 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3781 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3782 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3783 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3784 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3785 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3786 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3787 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3788 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3789 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3790 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3791 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3792 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3793 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3795 /* Gen-specific function declarations */
3797 # include "anv_genX.h"
3799 # define genX(x) gen7_##x
3800 # include "anv_genX.h"
3802 # define genX(x) gen75_##x
3803 # include "anv_genX.h"
3805 # define genX(x) gen8_##x
3806 # include "anv_genX.h"
3808 # define genX(x) gen9_##x
3809 # include "anv_genX.h"
3811 # define genX(x) gen10_##x
3812 # include "anv_genX.h"
3814 # define genX(x) gen11_##x
3815 # include "anv_genX.h"
3817 # define genX(x) gen12_##x
3818 # include "anv_genX.h"
3822 #endif /* ANV_PRIVATE_H */