2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
60 #include "util/xmlconfig.h"
62 #include "vk_debug_report.h"
64 /* Pre-declarations needed for WSI entrypoints */
67 typedef struct xcb_connection_t xcb_connection_t
;
68 typedef uint32_t xcb_visualid_t
;
69 typedef uint32_t xcb_window_t
;
72 struct anv_buffer_view
;
73 struct anv_image_view
;
78 #include <vulkan/vulkan.h>
79 #include <vulkan/vulkan_intel.h>
80 #include <vulkan/vk_icd.h>
82 #include "anv_android.h"
83 #include "anv_entrypoints.h"
84 #include "anv_extensions.h"
87 #include "dev/gen_debug.h"
88 #include "common/intel_log.h"
89 #include "wsi_common.h"
91 /* anv Virtual Memory Layout
92 * =========================
94 * When the anv driver is determining the virtual graphics addresses of memory
95 * objects itself using the softpin mechanism, the following memory ranges
98 * Three special considerations to notice:
100 * (1) the dynamic state pool is located within the same 4 GiB as the low
101 * heap. This is to work around a VF cache issue described in a comment in
102 * anv_physical_device_init_heaps.
104 * (2) the binding table pool is located at lower addresses than the surface
105 * state pool, within a 4 GiB range. This allows surface state base addresses
106 * to cover both binding tables (16 bit offsets) and surface states (32 bit
109 * (3) the last 4 GiB of the address space is withheld from the high
110 * heap. Various hardware units will read past the end of an object for
111 * various reasons. This healthy margin prevents reads from wrapping around
114 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
115 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
116 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
117 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
118 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
119 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
120 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
121 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
122 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
123 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
124 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
126 #define LOW_HEAP_SIZE \
127 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
128 #define DYNAMIC_STATE_POOL_SIZE \
129 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
130 #define BINDING_TABLE_POOL_SIZE \
131 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
132 #define SURFACE_STATE_POOL_SIZE \
133 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
134 #define INSTRUCTION_STATE_POOL_SIZE \
135 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
137 /* Allowing different clear colors requires us to perform a depth resolve at
138 * the end of certain render passes. This is because while slow clears store
139 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
140 * See the PRMs for examples describing when additional resolves would be
141 * necessary. To enable fast clears without requiring extra resolves, we set
142 * the clear value to a globally-defined one. We could allow different values
143 * if the user doesn't expect coherent data during or after a render passes
144 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
145 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
146 * 1.0f seems to be the only value used. The only application that doesn't set
147 * this value does so through the usage of an seemingly uninitialized clear
150 #define ANV_HZ_FC_VAL 1.0f
153 #define MAX_XFB_BUFFERS 4
154 #define MAX_XFB_STREAMS 4
157 #define MAX_VIEWPORTS 16
158 #define MAX_SCISSORS 16
159 #define MAX_PUSH_CONSTANTS_SIZE 128
160 #define MAX_DYNAMIC_BUFFERS 16
161 #define MAX_IMAGES 64
162 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
163 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
164 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
166 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
168 * "The surface state model is used when a Binding Table Index (specified
169 * in the message descriptor) of less than 240 is specified. In this model,
170 * the Binding Table Index is used to index into the binding table, and the
171 * binding table entry contains a pointer to the SURFACE_STATE."
173 * Binding table values above 240 are used for various things in the hardware
174 * such as stateless, stateless with incoherent cache, SLM, and bindless.
176 #define MAX_BINDING_TABLE_SIZE 240
178 /* The kernel relocation API has a limitation of a 32-bit delta value
179 * applied to the address before it is written which, in spite of it being
180 * unsigned, is treated as signed . Because of the way that this maps to
181 * the Vulkan API, we cannot handle an offset into a buffer that does not
182 * fit into a signed 32 bits. The only mechanism we have for dealing with
183 * this at the moment is to limit all VkDeviceMemory objects to a maximum
184 * of 2GB each. The Vulkan spec allows us to do this:
186 * "Some platforms may have a limit on the maximum size of a single
187 * allocation. For example, certain systems may fail to create
188 * allocations with a size greater than or equal to 4GB. Such a limit is
189 * implementation-dependent, and if such a failure occurs then the error
190 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
192 * We don't use vk_error here because it's not an error so much as an
193 * indication to the application that the allocation is too large.
195 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
197 #define ANV_SVGS_VB_INDEX MAX_VBS
198 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
200 /* We reserve this MI ALU register for the purpose of handling predication.
201 * Other code which uses the MI ALU should leave it alone.
203 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
205 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
207 static inline uint32_t
208 align_down_npot_u32(uint32_t v
, uint32_t a
)
213 static inline uint32_t
214 align_u32(uint32_t v
, uint32_t a
)
216 assert(a
!= 0 && a
== (a
& -a
));
217 return (v
+ a
- 1) & ~(a
- 1);
220 static inline uint64_t
221 align_u64(uint64_t v
, uint64_t a
)
223 assert(a
!= 0 && a
== (a
& -a
));
224 return (v
+ a
- 1) & ~(a
- 1);
227 static inline int32_t
228 align_i32(int32_t v
, int32_t a
)
230 assert(a
!= 0 && a
== (a
& -a
));
231 return (v
+ a
- 1) & ~(a
- 1);
234 /** Alignment must be a power of 2. */
236 anv_is_aligned(uintmax_t n
, uintmax_t a
)
238 assert(a
== (a
& -a
));
239 return (n
& (a
- 1)) == 0;
242 static inline uint32_t
243 anv_minify(uint32_t n
, uint32_t levels
)
245 if (unlikely(n
== 0))
248 return MAX2(n
>> levels
, 1);
252 anv_clamp_f(float f
, float min
, float max
)
265 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
267 if (*inout_mask
& clear_mask
) {
268 *inout_mask
&= ~clear_mask
;
275 static inline union isl_color_value
276 vk_to_isl_color(VkClearColorValue color
)
278 return (union isl_color_value
) {
288 #define for_each_bit(b, dword) \
289 for (uint32_t __dword = (dword); \
290 (b) = __builtin_ffs(__dword) - 1, __dword; \
291 __dword &= ~(1 << (b)))
293 #define typed_memcpy(dest, src, count) ({ \
294 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
295 memcpy((dest), (src), (count) * sizeof(*(src))); \
298 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
299 * to be added here in order to utilize mapping in debug/error/perf macros.
301 #define REPORT_OBJECT_TYPE(o) \
302 __builtin_choose_expr ( \
303 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
304 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
305 __builtin_choose_expr ( \
306 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
307 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
308 __builtin_choose_expr ( \
309 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
310 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
311 __builtin_choose_expr ( \
312 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
313 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), void*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
395 /* The void expression results in a compile-time error \
396 when assigning the result to something. */ \
397 (void)0)))))))))))))))))))))))))))))))
399 /* Whenever we generate an error, pass it through this function. Useful for
400 * debugging, where we can break on it. Only call at error site, not when
401 * propagating errors. Might be useful to plug in a stack trace here.
404 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
405 VkDebugReportObjectTypeEXT type
, VkResult error
,
406 const char *file
, int line
, const char *format
,
409 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
410 VkDebugReportObjectTypeEXT type
, VkResult error
,
411 const char *file
, int line
, const char *format
, ...);
414 #define vk_error(error) __vk_errorf(NULL, NULL,\
415 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
416 error, __FILE__, __LINE__, NULL)
417 #define vk_errorv(instance, obj, error, format, args)\
418 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
419 __FILE__, __LINE__, format, args)
420 #define vk_errorf(instance, obj, error, format, ...)\
421 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
422 __FILE__, __LINE__, format, ## __VA_ARGS__)
424 #define vk_error(error) error
425 #define vk_errorf(instance, obj, error, format, ...) error
429 * Warn on ignored extension structs.
431 * The Vulkan spec requires us to ignore unsupported or unknown structs in
432 * a pNext chain. In debug mode, emitting warnings for ignored structs may
433 * help us discover structs that we should not have ignored.
436 * From the Vulkan 1.0.38 spec:
438 * Any component of the implementation (the loader, any enabled layers,
439 * and drivers) must skip over, without processing (other than reading the
440 * sType and pNext members) any chained structures with sType values not
441 * defined by extensions supported by that component.
443 #define anv_debug_ignored_stype(sType) \
444 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
446 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
447 VkDebugReportObjectTypeEXT type
, const char *file
,
448 int line
, const char *format
, ...)
449 anv_printflike(6, 7);
450 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
451 void anv_loge_v(const char *format
, va_list va
);
454 * Print a FINISHME message, including its source location.
456 #define anv_finishme(format, ...) \
458 static bool reported = false; \
460 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
467 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
469 #define anv_perf_warn(instance, obj, format, ...) \
471 static bool reported = false; \
472 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
473 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
474 format, ##__VA_ARGS__); \
479 /* A non-fatal assert. Useful for debugging. */
481 #define anv_assert(x) ({ \
482 if (unlikely(!(x))) \
483 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
486 #define anv_assert(x)
489 /* A multi-pointer allocator
491 * When copying data structures from the user (such as a render pass), it's
492 * common to need to allocate data for a bunch of different things. Instead
493 * of doing several allocations and having to handle all of the error checking
494 * that entails, it can be easier to do a single allocation. This struct
495 * helps facilitate that. The intended usage looks like this:
498 * anv_multialloc_add(&ma, &main_ptr, 1);
499 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
500 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
502 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
503 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
505 struct anv_multialloc
{
513 #define ANV_MULTIALLOC_INIT \
514 ((struct anv_multialloc) { 0, })
516 #define ANV_MULTIALLOC(_name) \
517 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
519 __attribute__((always_inline
))
521 _anv_multialloc_add(struct anv_multialloc
*ma
,
522 void **ptr
, size_t size
, size_t align
)
524 size_t offset
= align_u64(ma
->size
, align
);
525 ma
->size
= offset
+ size
;
526 ma
->align
= MAX2(ma
->align
, align
);
528 /* Store the offset in the pointer. */
529 *ptr
= (void *)(uintptr_t)offset
;
531 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
532 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
535 #define anv_multialloc_add_size(_ma, _ptr, _size) \
536 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
538 #define anv_multialloc_add(_ma, _ptr, _count) \
539 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
541 __attribute__((always_inline
))
543 anv_multialloc_alloc(struct anv_multialloc
*ma
,
544 const VkAllocationCallbacks
*alloc
,
545 VkSystemAllocationScope scope
)
547 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
551 /* Fill out each of the pointers with their final value.
553 * for (uint32_t i = 0; i < ma->ptr_count; i++)
554 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
556 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
557 * constant, GCC is incapable of figuring this out and unrolling the loop
558 * so we have to give it a little help.
560 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
561 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
562 if ((_i) < ma->ptr_count) \
563 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
564 _ANV_MULTIALLOC_UPDATE_POINTER(0);
565 _ANV_MULTIALLOC_UPDATE_POINTER(1);
566 _ANV_MULTIALLOC_UPDATE_POINTER(2);
567 _ANV_MULTIALLOC_UPDATE_POINTER(3);
568 _ANV_MULTIALLOC_UPDATE_POINTER(4);
569 _ANV_MULTIALLOC_UPDATE_POINTER(5);
570 _ANV_MULTIALLOC_UPDATE_POINTER(6);
571 _ANV_MULTIALLOC_UPDATE_POINTER(7);
572 #undef _ANV_MULTIALLOC_UPDATE_POINTER
577 __attribute__((always_inline
))
579 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
580 const VkAllocationCallbacks
*parent_alloc
,
581 const VkAllocationCallbacks
*alloc
,
582 VkSystemAllocationScope scope
)
584 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
587 /* Extra ANV-defined BO flags which won't be passed to the kernel */
588 #define ANV_BO_EXTERNAL (1ull << 31)
589 #define ANV_BO_FLAG_MASK (1ull << 31)
594 /* Index into the current validation list. This is used by the
595 * validation list building alrogithm to track which buffers are already
596 * in the validation list so that we can ensure uniqueness.
600 /* Last known offset. This value is provided by the kernel when we
601 * execbuf and is used as the presumed offset for the next bunch of
609 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
614 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
616 bo
->gem_handle
= gem_handle
;
624 /* Represents a lock-free linked list of "free" things. This is used by
625 * both the block pool and the state pools. Unfortunately, in order to
626 * solve the ABA problem, we can't use a single uint32_t head.
628 union anv_free_list
{
632 /* A simple count that is incremented every time the head changes. */
638 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
640 struct anv_block_state
{
650 #define anv_block_pool_foreach_bo(bo, pool) \
651 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
653 #define ANV_MAX_BLOCK_POOL_BOS 20
655 struct anv_block_pool
{
656 struct anv_device
*device
;
660 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
666 /* The address where the start of the pool is pinned. The various bos that
667 * are created as the pool grows will have addresses in the range
668 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
670 uint64_t start_address
;
672 /* The offset from the start of the bo to the "center" of the block
673 * pool. Pointers to allocated blocks are given by
674 * bo.map + center_bo_offset + offsets.
676 uint32_t center_bo_offset
;
678 /* Current memory map of the block pool. This pointer may or may not
679 * point to the actual beginning of the block pool memory. If
680 * anv_block_pool_alloc_back has ever been called, then this pointer
681 * will point to the "center" position of the buffer and all offsets
682 * (negative or positive) given out by the block pool alloc functions
683 * will be valid relative to this pointer.
685 * In particular, map == bo.map + center_offset
687 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
688 * since it will handle the softpin case as well, where this points to NULL.
694 * Array of mmaps and gem handles owned by the block pool, reclaimed when
695 * the block pool is destroyed.
697 struct u_vector mmap_cleanups
;
699 struct anv_block_state state
;
701 struct anv_block_state back_state
;
704 /* Block pools are backed by a fixed-size 1GB memfd */
705 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
707 /* The center of the block pool is also the middle of the memfd. This may
708 * change in the future if we decide differently for some reason.
710 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
712 static inline uint32_t
713 anv_block_pool_size(struct anv_block_pool
*pool
)
715 return pool
->state
.end
+ pool
->back_state
.end
;
725 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
727 struct anv_fixed_size_state_pool
{
728 union anv_free_list free_list
;
729 struct anv_block_state block
;
732 #define ANV_MIN_STATE_SIZE_LOG2 6
733 #define ANV_MAX_STATE_SIZE_LOG2 21
735 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
737 struct anv_free_entry
{
739 struct anv_state state
;
742 struct anv_state_table
{
743 struct anv_device
*device
;
745 struct anv_free_entry
*map
;
747 struct anv_block_state state
;
748 struct u_vector cleanups
;
751 struct anv_state_pool
{
752 struct anv_block_pool block_pool
;
754 struct anv_state_table table
;
756 /* The size of blocks which will be allocated from the block pool */
759 /** Free list for "back" allocations */
760 union anv_free_list back_alloc_free_list
;
762 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
765 struct anv_state_stream_block
;
767 struct anv_state_stream
{
768 struct anv_state_pool
*state_pool
;
770 /* The size of blocks to allocate from the state pool */
773 /* Current block we're allocating from */
774 struct anv_state block
;
776 /* Offset into the current block at which to allocate the next state */
779 /* List of all blocks allocated from this pool */
780 struct anv_state_stream_block
*block_list
;
783 /* The block_pool functions exported for testing only. The block pool should
784 * only be used via a state pool (see below).
786 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
787 struct anv_device
*device
,
788 uint64_t start_address
,
789 uint32_t initial_size
,
791 void anv_block_pool_finish(struct anv_block_pool
*pool
);
792 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
793 uint32_t block_size
, uint32_t *padding
);
794 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
795 uint32_t block_size
);
796 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
798 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
799 struct anv_device
*device
,
800 uint64_t start_address
,
803 void anv_state_pool_finish(struct anv_state_pool
*pool
);
804 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
805 uint32_t state_size
, uint32_t alignment
);
806 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
807 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
808 void anv_state_stream_init(struct anv_state_stream
*stream
,
809 struct anv_state_pool
*state_pool
,
810 uint32_t block_size
);
811 void anv_state_stream_finish(struct anv_state_stream
*stream
);
812 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
813 uint32_t size
, uint32_t alignment
);
815 VkResult
anv_state_table_init(struct anv_state_table
*table
,
816 struct anv_device
*device
,
817 uint32_t initial_entries
);
818 void anv_state_table_finish(struct anv_state_table
*table
);
819 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
821 void anv_free_list_push(union anv_free_list
*list
,
822 struct anv_state_table
*table
,
823 uint32_t idx
, uint32_t count
);
824 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
825 struct anv_state_table
*table
);
828 static inline struct anv_state
*
829 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
831 return &table
->map
[idx
].state
;
834 * Implements a pool of re-usable BOs. The interface is identical to that
835 * of block_pool except that each block is its own BO.
838 struct anv_device
*device
;
845 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
847 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
848 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
850 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
852 struct anv_scratch_bo
{
857 struct anv_scratch_pool
{
858 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
859 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
862 void anv_scratch_pool_init(struct anv_device
*device
,
863 struct anv_scratch_pool
*pool
);
864 void anv_scratch_pool_finish(struct anv_device
*device
,
865 struct anv_scratch_pool
*pool
);
866 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
867 struct anv_scratch_pool
*pool
,
868 gl_shader_stage stage
,
869 unsigned per_thread_scratch
);
871 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
872 struct anv_bo_cache
{
873 struct hash_table
*bo_map
;
874 pthread_mutex_t mutex
;
877 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
878 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
879 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
880 struct anv_bo_cache
*cache
,
881 uint64_t size
, uint64_t bo_flags
,
883 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
884 struct anv_bo_cache
*cache
,
885 void *host_ptr
, uint32_t size
,
886 uint64_t bo_flags
, struct anv_bo
**bo_out
);
887 VkResult
anv_bo_cache_import(struct anv_device
*device
,
888 struct anv_bo_cache
*cache
,
889 int fd
, uint64_t bo_flags
,
891 VkResult
anv_bo_cache_export(struct anv_device
*device
,
892 struct anv_bo_cache
*cache
,
893 struct anv_bo
*bo_in
, int *fd_out
);
894 void anv_bo_cache_release(struct anv_device
*device
,
895 struct anv_bo_cache
*cache
,
898 struct anv_memory_type
{
899 /* Standard bits passed on to the client */
900 VkMemoryPropertyFlags propertyFlags
;
903 /* Driver-internal book-keeping */
904 VkBufferUsageFlags valid_buffer_usage
;
907 struct anv_memory_heap
{
908 /* Standard bits passed on to the client */
910 VkMemoryHeapFlags flags
;
912 /* Driver-internal book-keeping */
915 bool supports_48bit_addresses
;
919 struct anv_physical_device
{
920 VK_LOADER_DATA _loader_data
;
922 struct anv_instance
* instance
;
933 struct gen_device_info info
;
934 /** Amount of "GPU memory" we want to advertise
936 * Clearly, this value is bogus since Intel is a UMA architecture. On
937 * gen7 platforms, we are limited by GTT size unless we want to implement
938 * fine-grained tracking and GTT splitting. On Broadwell and above we are
939 * practically unlimited. However, we will never report more than 3/4 of
940 * the total system ram to try and avoid running out of RAM.
942 bool supports_48bit_addresses
;
943 struct brw_compiler
* compiler
;
944 struct isl_device isl_dev
;
945 int cmd_parser_version
;
947 bool has_exec_capture
;
950 bool has_syncobj_wait
;
951 bool has_context_priority
;
953 bool has_context_isolation
;
954 bool has_mem_available
;
955 bool always_use_bindless
;
957 /** True if we can access buffers using A64 messages */
958 bool has_a64_buffer_access
;
959 /** True if we can use bindless access for images */
960 bool has_bindless_images
;
961 /** True if we can use bindless access for samplers */
962 bool has_bindless_samplers
;
964 struct anv_device_extension_table supported_extensions
;
965 struct anv_physical_device_dispatch_table dispatch
;
968 uint32_t subslice_total
;
972 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
974 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
977 uint8_t driver_build_sha1
[20];
978 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
979 uint8_t driver_uuid
[VK_UUID_SIZE
];
980 uint8_t device_uuid
[VK_UUID_SIZE
];
982 struct disk_cache
* disk_cache
;
984 struct wsi_device wsi_device
;
989 struct anv_app_info
{
990 const char* app_name
;
991 uint32_t app_version
;
992 const char* engine_name
;
993 uint32_t engine_version
;
994 uint32_t api_version
;
997 struct anv_instance
{
998 VK_LOADER_DATA _loader_data
;
1000 VkAllocationCallbacks alloc
;
1002 struct anv_app_info app_info
;
1004 struct anv_instance_extension_table enabled_extensions
;
1005 struct anv_instance_dispatch_table dispatch
;
1006 struct anv_device_dispatch_table device_dispatch
;
1008 int physicalDeviceCount
;
1009 struct anv_physical_device physicalDevice
;
1011 bool pipeline_cache_enabled
;
1013 struct vk_debug_report_instance debug_report_callbacks
;
1015 struct driOptionCache dri_options
;
1016 struct driOptionCache available_dri_options
;
1019 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1020 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1022 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1023 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1027 VK_LOADER_DATA _loader_data
;
1029 struct anv_device
* device
;
1031 VkDeviceQueueCreateFlags flags
;
1034 struct anv_pipeline_cache
{
1035 struct anv_device
* device
;
1036 pthread_mutex_t mutex
;
1038 struct hash_table
* nir_cache
;
1040 struct hash_table
* cache
;
1043 struct nir_xfb_info
;
1044 struct anv_pipeline_bind_map
;
1046 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1047 struct anv_device
*device
,
1048 bool cache_enabled
);
1049 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1051 struct anv_shader_bin
*
1052 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1053 const void *key
, uint32_t key_size
);
1054 struct anv_shader_bin
*
1055 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1056 const void *key_data
, uint32_t key_size
,
1057 const void *kernel_data
, uint32_t kernel_size
,
1058 const void *constant_data
,
1059 uint32_t constant_data_size
,
1060 const struct brw_stage_prog_data
*prog_data
,
1061 uint32_t prog_data_size
,
1062 const struct brw_compile_stats
*stats
,
1064 const struct nir_xfb_info
*xfb_info
,
1065 const struct anv_pipeline_bind_map
*bind_map
);
1067 struct anv_shader_bin
*
1068 anv_device_search_for_kernel(struct anv_device
*device
,
1069 struct anv_pipeline_cache
*cache
,
1070 const void *key_data
, uint32_t key_size
,
1071 bool *user_cache_bit
);
1073 struct anv_shader_bin
*
1074 anv_device_upload_kernel(struct anv_device
*device
,
1075 struct anv_pipeline_cache
*cache
,
1076 const void *key_data
, uint32_t key_size
,
1077 const void *kernel_data
, uint32_t kernel_size
,
1078 const void *constant_data
,
1079 uint32_t constant_data_size
,
1080 const struct brw_stage_prog_data
*prog_data
,
1081 uint32_t prog_data_size
,
1082 const struct brw_compile_stats
*stats
,
1084 const struct nir_xfb_info
*xfb_info
,
1085 const struct anv_pipeline_bind_map
*bind_map
);
1088 struct nir_shader_compiler_options
;
1091 anv_device_search_for_nir(struct anv_device
*device
,
1092 struct anv_pipeline_cache
*cache
,
1093 const struct nir_shader_compiler_options
*nir_options
,
1094 unsigned char sha1_key
[20],
1098 anv_device_upload_nir(struct anv_device
*device
,
1099 struct anv_pipeline_cache
*cache
,
1100 const struct nir_shader
*nir
,
1101 unsigned char sha1_key
[20]);
1104 VK_LOADER_DATA _loader_data
;
1106 VkAllocationCallbacks alloc
;
1108 struct anv_instance
* instance
;
1109 uint32_t chipset_id
;
1111 struct gen_device_info info
;
1112 struct isl_device isl_dev
;
1115 bool can_chain_batches
;
1116 bool robust_buffer_access
;
1117 struct anv_device_extension_table enabled_extensions
;
1118 struct anv_device_dispatch_table dispatch
;
1120 pthread_mutex_t vma_mutex
;
1121 struct util_vma_heap vma_lo
;
1122 struct util_vma_heap vma_hi
;
1123 uint64_t vma_lo_available
;
1124 uint64_t vma_hi_available
;
1126 /** List of all anv_device_memory objects */
1127 struct list_head memory_objects
;
1129 struct anv_bo_pool batch_bo_pool
;
1131 struct anv_bo_cache bo_cache
;
1133 struct anv_state_pool dynamic_state_pool
;
1134 struct anv_state_pool instruction_state_pool
;
1135 struct anv_state_pool binding_table_pool
;
1136 struct anv_state_pool surface_state_pool
;
1138 struct anv_bo workaround_bo
;
1139 struct anv_bo trivial_batch_bo
;
1140 struct anv_bo hiz_clear_bo
;
1142 struct anv_pipeline_cache default_pipeline_cache
;
1143 struct blorp_context blorp
;
1145 struct anv_state border_colors
;
1147 struct anv_state slice_hash
;
1149 struct anv_queue queue
;
1151 struct anv_scratch_pool scratch_pool
;
1153 uint32_t default_mocs
;
1154 uint32_t external_mocs
;
1156 pthread_mutex_t mutex
;
1157 pthread_cond_t queue_submit
;
1160 struct gen_batch_decode_ctx decoder_ctx
;
1162 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1163 * the cmd_buffer's list.
1165 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1168 static inline struct anv_state_pool
*
1169 anv_binding_table_pool(struct anv_device
*device
)
1171 if (device
->instance
->physicalDevice
.use_softpin
)
1172 return &device
->binding_table_pool
;
1174 return &device
->surface_state_pool
;
1177 static inline struct anv_state
1178 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1179 if (device
->instance
->physicalDevice
.use_softpin
)
1180 return anv_state_pool_alloc(&device
->binding_table_pool
,
1181 device
->binding_table_pool
.block_size
, 0);
1183 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1187 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1188 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1191 static inline uint32_t
1192 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1194 if (bo
->flags
& ANV_BO_EXTERNAL
)
1195 return device
->external_mocs
;
1197 return device
->default_mocs
;
1200 void anv_device_init_blorp(struct anv_device
*device
);
1201 void anv_device_finish_blorp(struct anv_device
*device
);
1203 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1204 const char *file
, int line
,
1205 const char *msg
, ...);
1206 #define anv_device_set_lost(dev, ...) \
1207 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1210 anv_device_is_lost(struct anv_device
*device
)
1212 return unlikely(device
->_lost
);
1215 VkResult
anv_device_execbuf(struct anv_device
*device
,
1216 struct drm_i915_gem_execbuffer2
*execbuf
,
1217 struct anv_bo
**execbuf_bos
);
1218 VkResult
anv_device_query_status(struct anv_device
*device
);
1219 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1220 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1223 void* anv_gem_mmap(struct anv_device
*device
,
1224 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1225 void anv_gem_munmap(void *p
, uint64_t size
);
1226 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1227 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1228 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1229 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1230 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1231 int anv_gem_execbuffer(struct anv_device
*device
,
1232 struct drm_i915_gem_execbuffer2
*execbuf
);
1233 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1234 uint32_t stride
, uint32_t tiling
);
1235 int anv_gem_create_context(struct anv_device
*device
);
1236 bool anv_gem_has_context_priority(int fd
);
1237 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1238 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1240 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1242 int anv_gem_get_param(int fd
, uint32_t param
);
1243 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1244 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1245 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1246 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1247 uint32_t *active
, uint32_t *pending
);
1248 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1249 int anv_gem_reg_read(struct anv_device
*device
,
1250 uint32_t offset
, uint64_t *result
);
1251 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1252 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1253 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1254 uint32_t read_domains
, uint32_t write_domain
);
1255 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1256 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1257 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1258 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1259 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1260 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1262 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1263 uint32_t handle
, int fd
);
1264 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1265 bool anv_gem_supports_syncobj_wait(int fd
);
1266 int anv_gem_syncobj_wait(struct anv_device
*device
,
1267 uint32_t *handles
, uint32_t num_handles
,
1268 int64_t abs_timeout_ns
, bool wait_all
);
1270 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1271 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1273 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1275 struct anv_reloc_list
{
1276 uint32_t num_relocs
;
1277 uint32_t array_length
;
1278 struct drm_i915_gem_relocation_entry
* relocs
;
1279 struct anv_bo
** reloc_bos
;
1283 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1284 const VkAllocationCallbacks
*alloc
);
1285 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1286 const VkAllocationCallbacks
*alloc
);
1288 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1289 const VkAllocationCallbacks
*alloc
,
1290 uint32_t offset
, struct anv_bo
*target_bo
,
1293 struct anv_batch_bo
{
1294 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1295 struct list_head link
;
1299 /* Bytes actually consumed in this batch BO */
1302 struct anv_reloc_list relocs
;
1306 const VkAllocationCallbacks
* alloc
;
1312 struct anv_reloc_list
* relocs
;
1314 /* This callback is called (with the associated user data) in the event
1315 * that the batch runs out of space.
1317 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1321 * Current error status of the command buffer. Used to track inconsistent
1322 * or incomplete command buffer states that are the consequence of run-time
1323 * errors such as out of memory scenarios. We want to track this in the
1324 * batch because the command buffer object is not visible to some parts
1330 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1331 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1332 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1333 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1334 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1335 struct anv_batch
*batch
);
1337 static inline VkResult
1338 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1340 assert(error
!= VK_SUCCESS
);
1341 if (batch
->status
== VK_SUCCESS
)
1342 batch
->status
= error
;
1343 return batch
->status
;
1347 anv_batch_has_error(struct anv_batch
*batch
)
1349 return batch
->status
!= VK_SUCCESS
;
1352 struct anv_address
{
1357 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1360 anv_address_is_null(struct anv_address addr
)
1362 return addr
.bo
== NULL
&& addr
.offset
== 0;
1365 static inline uint64_t
1366 anv_address_physical(struct anv_address addr
)
1368 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1369 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1371 return gen_canonical_address(addr
.offset
);
1374 static inline struct anv_address
1375 anv_address_add(struct anv_address addr
, uint64_t offset
)
1377 addr
.offset
+= offset
;
1382 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1384 unsigned reloc_size
= 0;
1385 if (device
->info
.gen
>= 8) {
1386 reloc_size
= sizeof(uint64_t);
1387 *(uint64_t *)p
= gen_canonical_address(v
);
1389 reloc_size
= sizeof(uint32_t);
1393 if (flush
&& !device
->info
.has_llc
)
1394 gen_flush_range(p
, reloc_size
);
1397 static inline uint64_t
1398 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1399 const struct anv_address address
, uint32_t delta
)
1401 if (address
.bo
== NULL
) {
1402 return address
.offset
+ delta
;
1404 assert(batch
->start
<= location
&& location
< batch
->end
);
1406 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1410 #define __gen_address_type struct anv_address
1411 #define __gen_user_data struct anv_batch
1412 #define __gen_combine_address _anv_combine_address
1414 /* Wrapper macros needed to work around preprocessor argument issues. In
1415 * particular, arguments don't get pre-evaluated if they are concatenated.
1416 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1417 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1418 * We can work around this easily enough with these helpers.
1420 #define __anv_cmd_length(cmd) cmd ## _length
1421 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1422 #define __anv_cmd_header(cmd) cmd ## _header
1423 #define __anv_cmd_pack(cmd) cmd ## _pack
1424 #define __anv_reg_num(reg) reg ## _num
1426 #define anv_pack_struct(dst, struc, ...) do { \
1427 struct struc __template = { \
1430 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1431 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1434 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1435 void *__dst = anv_batch_emit_dwords(batch, n); \
1437 struct cmd __template = { \
1438 __anv_cmd_header(cmd), \
1439 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1442 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1447 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1451 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1452 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1455 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1456 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1457 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1460 #define anv_batch_emit(batch, cmd, name) \
1461 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1462 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1463 __builtin_expect(_dst != NULL, 1); \
1464 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1465 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1469 /* MEMORY_OBJECT_CONTROL_STATE:
1470 * .GraphicsDataTypeGFDT = 0,
1471 * .LLCCacheabilityControlLLCCC = 0,
1472 * .L3CacheabilityControlL3CC = 1,
1476 /* MEMORY_OBJECT_CONTROL_STATE:
1477 * .LLCeLLCCacheabilityControlLLCCC = 0,
1478 * .L3CacheabilityControlL3CC = 1,
1480 #define GEN75_MOCS 1
1482 /* MEMORY_OBJECT_CONTROL_STATE:
1483 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1484 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1485 * .AgeforQUADLRU = 0
1487 #define GEN8_MOCS 0x78
1489 /* MEMORY_OBJECT_CONTROL_STATE:
1490 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1491 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1492 * .AgeforQUADLRU = 0
1494 #define GEN8_EXTERNAL_MOCS 0x18
1496 /* Skylake: MOCS is now an index into an array of 62 different caching
1497 * configurations programmed by the kernel.
1500 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1501 #define GEN9_MOCS (2 << 1)
1503 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1504 #define GEN9_EXTERNAL_MOCS (1 << 1)
1506 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1507 #define GEN10_MOCS GEN9_MOCS
1508 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1510 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1511 #define GEN11_MOCS GEN9_MOCS
1512 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1514 /* TigerLake MOCS */
1515 #define GEN12_MOCS GEN9_MOCS
1516 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1517 #define GEN12_EXTERNAL_MOCS (3 << 1)
1519 struct anv_device_memory
{
1520 struct list_head link
;
1523 struct anv_memory_type
* type
;
1524 VkDeviceSize map_size
;
1527 /* If set, we are holding reference to AHardwareBuffer
1528 * which we must release when memory is freed.
1530 struct AHardwareBuffer
* ahw
;
1532 /* If set, this memory comes from a host pointer. */
1537 * Header for Vertex URB Entry (VUE)
1539 struct anv_vue_header
{
1541 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1542 uint32_t ViewportIndex
;
1546 /** Struct representing a sampled image descriptor
1548 * This descriptor layout is used for sampled images, bare sampler, and
1549 * combined image/sampler descriptors.
1551 struct anv_sampled_image_descriptor
{
1552 /** Bindless image handle
1554 * This is expected to already be shifted such that the 20-bit
1555 * SURFACE_STATE table index is in the top 20 bits.
1559 /** Bindless sampler handle
1561 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1562 * to the dynamic state base address.
1567 struct anv_texture_swizzle_descriptor
{
1570 * See also nir_intrinsic_channel_select_intel
1574 /** Unused padding to ensure the struct is a multiple of 64 bits */
1578 /** Struct representing a storage image descriptor */
1579 struct anv_storage_image_descriptor
{
1580 /** Bindless image handles
1582 * These are expected to already be shifted such that the 20-bit
1583 * SURFACE_STATE table index is in the top 20 bits.
1585 uint32_t read_write
;
1586 uint32_t write_only
;
1589 /** Struct representing a address/range descriptor
1591 * The fields of this struct correspond directly to the data layout of
1592 * nir_address_format_64bit_bounded_global addresses. The last field is the
1593 * offset in the NIR address so it must be zero so that when you load the
1594 * descriptor you get a pointer to the start of the range.
1596 struct anv_address_range_descriptor
{
1602 enum anv_descriptor_data
{
1603 /** The descriptor contains a BTI reference to a surface state */
1604 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1605 /** The descriptor contains a BTI reference to a sampler state */
1606 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1607 /** The descriptor contains an actual buffer view */
1608 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1609 /** The descriptor contains auxiliary image layout data */
1610 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1611 /** The descriptor contains auxiliary image layout data */
1612 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1613 /** anv_address_range_descriptor with a buffer address and range */
1614 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1615 /** Bindless surface handle */
1616 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1617 /** Storage image handles */
1618 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1619 /** Storage image handles */
1620 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1623 struct anv_descriptor_set_binding_layout
{
1625 /* The type of the descriptors in this binding */
1626 VkDescriptorType type
;
1629 /* Flags provided when this binding was created */
1630 VkDescriptorBindingFlagsEXT flags
;
1632 /* Bitfield representing the type of data this descriptor contains */
1633 enum anv_descriptor_data data
;
1635 /* Maximum number of YCbCr texture/sampler planes */
1636 uint8_t max_plane_count
;
1638 /* Number of array elements in this binding (or size in bytes for inline
1641 uint16_t array_size
;
1643 /* Index into the flattend descriptor set */
1644 uint16_t descriptor_index
;
1646 /* Index into the dynamic state array for a dynamic buffer */
1647 int16_t dynamic_offset_index
;
1649 /* Index into the descriptor set buffer views */
1650 int16_t buffer_view_index
;
1652 /* Offset into the descriptor buffer where this descriptor lives */
1653 uint32_t descriptor_offset
;
1655 /* Immutable samplers (or NULL if no immutable samplers) */
1656 struct anv_sampler
**immutable_samplers
;
1659 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1661 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1662 VkDescriptorType type
);
1664 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1665 const struct anv_descriptor_set_binding_layout
*binding
,
1668 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1669 const struct anv_descriptor_set_binding_layout
*binding
,
1672 struct anv_descriptor_set_layout
{
1673 /* Descriptor set layouts can be destroyed at almost any time */
1676 /* Number of bindings in this descriptor set */
1677 uint16_t binding_count
;
1679 /* Total size of the descriptor set with room for all array entries */
1682 /* Shader stages affected by this descriptor set */
1683 uint16_t shader_stages
;
1685 /* Number of buffer views in this descriptor set */
1686 uint16_t buffer_view_count
;
1688 /* Number of dynamic offsets used by this descriptor set */
1689 uint16_t dynamic_offset_count
;
1691 /* Size of the descriptor buffer for this descriptor set */
1692 uint32_t descriptor_buffer_size
;
1694 /* Bindings in this descriptor set */
1695 struct anv_descriptor_set_binding_layout binding
[0];
1699 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1701 assert(layout
&& layout
->ref_cnt
>= 1);
1702 p_atomic_inc(&layout
->ref_cnt
);
1706 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1707 struct anv_descriptor_set_layout
*layout
)
1709 assert(layout
&& layout
->ref_cnt
>= 1);
1710 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1711 vk_free(&device
->alloc
, layout
);
1714 struct anv_descriptor
{
1715 VkDescriptorType type
;
1719 VkImageLayout layout
;
1720 struct anv_image_view
*image_view
;
1721 struct anv_sampler
*sampler
;
1725 struct anv_buffer
*buffer
;
1730 struct anv_buffer_view
*buffer_view
;
1734 struct anv_descriptor_set
{
1735 struct anv_descriptor_pool
*pool
;
1736 struct anv_descriptor_set_layout
*layout
;
1739 /* State relative to anv_descriptor_pool::bo */
1740 struct anv_state desc_mem
;
1741 /* Surface state for the descriptor buffer */
1742 struct anv_state desc_surface_state
;
1744 uint32_t buffer_view_count
;
1745 struct anv_buffer_view
*buffer_views
;
1747 /* Link to descriptor pool's desc_sets list . */
1748 struct list_head pool_link
;
1750 struct anv_descriptor descriptors
[0];
1753 struct anv_buffer_view
{
1754 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1755 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1757 struct anv_address address
;
1759 struct anv_state surface_state
;
1760 struct anv_state storage_surface_state
;
1761 struct anv_state writeonly_storage_surface_state
;
1763 struct brw_image_param storage_image_param
;
1766 struct anv_push_descriptor_set
{
1767 struct anv_descriptor_set set
;
1769 /* Put this field right behind anv_descriptor_set so it fills up the
1770 * descriptors[0] field. */
1771 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1773 /** True if the descriptor set buffer has been referenced by a draw or
1776 bool set_used_on_gpu
;
1778 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1781 struct anv_descriptor_pool
{
1787 struct util_vma_heap bo_heap
;
1789 struct anv_state_stream surface_state_stream
;
1790 void *surface_state_free_list
;
1792 struct list_head desc_sets
;
1797 enum anv_descriptor_template_entry_type
{
1798 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1799 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1800 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1803 struct anv_descriptor_template_entry
{
1804 /* The type of descriptor in this entry */
1805 VkDescriptorType type
;
1807 /* Binding in the descriptor set */
1810 /* Offset at which to write into the descriptor set binding */
1811 uint32_t array_element
;
1813 /* Number of elements to write into the descriptor set binding */
1814 uint32_t array_count
;
1816 /* Offset into the user provided data */
1819 /* Stride between elements into the user provided data */
1823 struct anv_descriptor_update_template
{
1824 VkPipelineBindPoint bind_point
;
1826 /* The descriptor set this template corresponds to. This value is only
1827 * valid if the template was created with the templateType
1828 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1832 /* Number of entries in this template */
1833 uint32_t entry_count
;
1835 /* Entries of the template */
1836 struct anv_descriptor_template_entry entries
[0];
1840 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1843 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1844 struct anv_descriptor_set
*set
,
1845 const VkDescriptorImageInfo
* const info
,
1846 VkDescriptorType type
,
1851 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1852 struct anv_descriptor_set
*set
,
1853 VkDescriptorType type
,
1854 struct anv_buffer_view
*buffer_view
,
1859 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1860 struct anv_descriptor_set
*set
,
1861 struct anv_state_stream
*alloc_stream
,
1862 VkDescriptorType type
,
1863 struct anv_buffer
*buffer
,
1866 VkDeviceSize offset
,
1867 VkDeviceSize range
);
1869 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1870 struct anv_descriptor_set
*set
,
1877 anv_descriptor_set_write_template(struct anv_device
*device
,
1878 struct anv_descriptor_set
*set
,
1879 struct anv_state_stream
*alloc_stream
,
1880 const struct anv_descriptor_update_template
*template,
1884 anv_descriptor_set_create(struct anv_device
*device
,
1885 struct anv_descriptor_pool
*pool
,
1886 struct anv_descriptor_set_layout
*layout
,
1887 struct anv_descriptor_set
**out_set
);
1890 anv_descriptor_set_destroy(struct anv_device
*device
,
1891 struct anv_descriptor_pool
*pool
,
1892 struct anv_descriptor_set
*set
);
1894 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1895 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1896 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1897 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1899 struct anv_pipeline_binding
{
1900 /* The descriptor set this surface corresponds to. The special value of
1901 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1902 * to a color attachment and not a regular descriptor.
1906 /* Binding in the descriptor set */
1909 /* Index in the binding */
1912 /* Plane in the binding index */
1915 /* Input attachment index (relative to the subpass) */
1916 uint8_t input_attachment_index
;
1918 /* For a storage image, whether it is write-only */
1922 struct anv_pipeline_layout
{
1924 struct anv_descriptor_set_layout
*layout
;
1925 uint32_t dynamic_offset_start
;
1930 unsigned char sha1
[20];
1934 struct anv_device
* device
;
1937 VkBufferUsageFlags usage
;
1939 /* Set when bound */
1940 struct anv_address address
;
1943 static inline uint64_t
1944 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1946 assert(offset
<= buffer
->size
);
1947 if (range
== VK_WHOLE_SIZE
) {
1948 return buffer
->size
- offset
;
1950 assert(range
+ offset
>= range
);
1951 assert(range
+ offset
<= buffer
->size
);
1956 enum anv_cmd_dirty_bits
{
1957 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1958 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1959 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1960 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1961 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1962 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1963 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1964 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1965 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1966 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1967 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1968 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1969 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1970 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
1972 typedef uint32_t anv_cmd_dirty_mask_t
;
1974 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
1975 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
1976 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
1977 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
1978 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
1979 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
1980 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
1981 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
1982 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
1983 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
1984 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
1986 static inline enum anv_cmd_dirty_bits
1987 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
1990 case VK_DYNAMIC_STATE_VIEWPORT
:
1991 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
1992 case VK_DYNAMIC_STATE_SCISSOR
:
1993 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1994 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1995 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
1996 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1997 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1998 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1999 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2000 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2001 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2002 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2003 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2004 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2005 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2006 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2007 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2008 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2009 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2011 assert(!"Unsupported dynamic state");
2017 enum anv_pipe_bits
{
2018 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2019 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2020 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2021 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2022 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2023 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2024 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2025 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2026 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2027 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2028 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2030 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2031 * a flush has happened but not a CS stall. The next time we do any sort
2032 * of invalidation we need to insert a CS stall at that time. Otherwise,
2033 * we would have to CS stall on every flush which could be bad.
2035 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2037 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2038 * target operations related to transfer commands with VkBuffer as
2039 * destination are ongoing. Some operations like copies on the command
2040 * streamer might need to be aware of this to trigger the appropriate stall
2041 * before they can proceed with the copy.
2043 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2046 #define ANV_PIPE_FLUSH_BITS ( \
2047 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2048 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2049 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
2051 #define ANV_PIPE_STALL_BITS ( \
2052 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2053 ANV_PIPE_DEPTH_STALL_BIT | \
2054 ANV_PIPE_CS_STALL_BIT)
2056 #define ANV_PIPE_INVALIDATE_BITS ( \
2057 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2058 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2059 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2060 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2061 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2062 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2064 static inline enum anv_pipe_bits
2065 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2067 enum anv_pipe_bits pipe_bits
= 0;
2070 for_each_bit(b
, flags
) {
2071 switch ((VkAccessFlagBits
)(1 << b
)) {
2072 case VK_ACCESS_SHADER_WRITE_BIT
:
2073 /* We're transitioning a buffer that was previously used as write
2074 * destination through the data port. To make its content available
2075 * to future operations, flush the data cache.
2077 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2079 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2080 /* We're transitioning a buffer that was previously used as render
2081 * target. To make its content available to future operations, flush
2082 * the render target cache.
2084 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2086 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2087 /* We're transitioning a buffer that was previously used as depth
2088 * buffer. To make its content available to future operations, flush
2091 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2093 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2094 /* We're transitioning a buffer that was previously used as a
2095 * transfer write destination. Generic write operations include color
2096 * & depth operations as well as buffer operations like :
2097 * - vkCmdClearColorImage()
2098 * - vkCmdClearDepthStencilImage()
2099 * - vkCmdBlitImage()
2100 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2102 * Most of these operations are implemented using Blorp which writes
2103 * through the render target, so flush that cache to make it visible
2104 * to future operations. And for depth related operations we also
2105 * need to flush the depth cache.
2107 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2108 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2110 case VK_ACCESS_MEMORY_WRITE_BIT
:
2111 /* We're transitioning a buffer for generic write operations. Flush
2114 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2117 break; /* Nothing to do */
2124 static inline enum anv_pipe_bits
2125 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2127 enum anv_pipe_bits pipe_bits
= 0;
2130 for_each_bit(b
, flags
) {
2131 switch ((VkAccessFlagBits
)(1 << b
)) {
2132 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2133 /* Indirect draw commands take a buffer as input that we're going to
2134 * read from the command streamer to load some of the HW registers
2135 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2136 * command streamer stall so that all the cache flushes have
2137 * completed before the command streamer loads from memory.
2139 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2140 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2141 * through a vertex buffer, so invalidate that cache.
2143 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2144 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2145 * UBO from the buffer, so we need to invalidate constant cache.
2147 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2149 case VK_ACCESS_INDEX_READ_BIT
:
2150 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2151 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2152 * commands, so we invalidate the VF cache to make sure there is no
2153 * stale data when we start rendering.
2155 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2157 case VK_ACCESS_UNIFORM_READ_BIT
:
2158 /* We transitioning a buffer to be used as uniform data. Because
2159 * uniform is accessed through the data port & sampler, we need to
2160 * invalidate the texture cache (sampler) & constant cache (data
2161 * port) to avoid stale data.
2163 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2164 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2166 case VK_ACCESS_SHADER_READ_BIT
:
2167 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2168 case VK_ACCESS_TRANSFER_READ_BIT
:
2169 /* Transitioning a buffer to be read through the sampler, so
2170 * invalidate the texture cache, we don't want any stale data.
2172 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2174 case VK_ACCESS_MEMORY_READ_BIT
:
2175 /* Transitioning a buffer for generic read, invalidate all the
2178 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2180 case VK_ACCESS_MEMORY_WRITE_BIT
:
2181 /* Generic write, make sure all previously written things land in
2184 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2186 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2187 /* Transitioning a buffer for conditional rendering. We'll load the
2188 * content of this buffer into HW registers using the command
2189 * streamer, so we need to stall the command streamer to make sure
2190 * any in-flight flush operations have completed.
2192 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2195 break; /* Nothing to do */
2202 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2203 VK_IMAGE_ASPECT_COLOR_BIT | \
2204 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2205 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2206 VK_IMAGE_ASPECT_PLANE_2_BIT)
2207 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2208 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2209 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2210 VK_IMAGE_ASPECT_PLANE_2_BIT)
2212 struct anv_vertex_binding
{
2213 struct anv_buffer
* buffer
;
2214 VkDeviceSize offset
;
2217 struct anv_xfb_binding
{
2218 struct anv_buffer
* buffer
;
2219 VkDeviceSize offset
;
2223 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2224 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2225 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2227 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2228 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2229 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2231 struct anv_push_constants
{
2232 /* Push constant data provided by the client through vkPushConstants */
2233 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2235 /* Used for vkCmdDispatchBase */
2236 uint32_t base_work_group_id
[3];
2239 struct anv_dynamic_state
{
2242 VkViewport viewports
[MAX_VIEWPORTS
];
2247 VkRect2D scissors
[MAX_SCISSORS
];
2258 float blend_constants
[4];
2268 } stencil_compare_mask
;
2273 } stencil_write_mask
;
2278 } stencil_reference
;
2286 extern const struct anv_dynamic_state default_dynamic_state
;
2288 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2289 const struct anv_dynamic_state
*src
,
2290 uint32_t copy_mask
);
2292 struct anv_surface_state
{
2293 struct anv_state state
;
2294 /** Address of the surface referred to by this state
2296 * This address is relative to the start of the BO.
2298 struct anv_address address
;
2299 /* Address of the aux surface, if any
2301 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2303 * With the exception of gen8, the bottom 12 bits of this address' offset
2304 * include extra aux information.
2306 struct anv_address aux_address
;
2307 /* Address of the clear color, if any
2309 * This address is relative to the start of the BO.
2311 struct anv_address clear_address
;
2315 * Attachment state when recording a renderpass instance.
2317 * The clear value is valid only if there exists a pending clear.
2319 struct anv_attachment_state
{
2320 enum isl_aux_usage aux_usage
;
2321 enum isl_aux_usage input_aux_usage
;
2322 struct anv_surface_state color
;
2323 struct anv_surface_state input
;
2325 VkImageLayout current_layout
;
2326 VkImageAspectFlags pending_clear_aspects
;
2327 VkImageAspectFlags pending_load_aspects
;
2329 VkClearValue clear_value
;
2330 bool clear_color_is_zero_one
;
2331 bool clear_color_is_zero
;
2333 /* When multiview is active, attachments with a renderpass clear
2334 * operation have their respective layers cleared on the first
2335 * subpass that uses them, and only in that subpass. We keep track
2336 * of this using a bitfield to indicate which layers of an attachment
2337 * have not been cleared yet when multiview is active.
2339 uint32_t pending_clear_views
;
2340 struct anv_image_view
* image_view
;
2343 /** State tracking for particular pipeline bind point
2345 * This struct is the base struct for anv_cmd_graphics_state and
2346 * anv_cmd_compute_state. These are used to track state which is bound to a
2347 * particular type of pipeline. Generic state that applies per-stage such as
2348 * binding table offsets and push constants is tracked generically with a
2349 * per-stage array in anv_cmd_state.
2351 struct anv_cmd_pipeline_state
{
2352 struct anv_pipeline
*pipeline
;
2353 struct anv_pipeline_layout
*layout
;
2355 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2356 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2358 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2361 /** State tracking for graphics pipeline
2363 * This has anv_cmd_pipeline_state as a base struct to track things which get
2364 * bound to a graphics pipeline. Along with general pipeline bind point state
2365 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2366 * state which is graphics-specific.
2368 struct anv_cmd_graphics_state
{
2369 struct anv_cmd_pipeline_state base
;
2371 anv_cmd_dirty_mask_t dirty
;
2374 struct anv_dynamic_state dynamic
;
2377 struct anv_buffer
*index_buffer
;
2378 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2379 uint32_t index_offset
;
2383 /** State tracking for compute pipeline
2385 * This has anv_cmd_pipeline_state as a base struct to track things which get
2386 * bound to a compute pipeline. Along with general pipeline bind point state
2387 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2388 * state which is compute-specific.
2390 struct anv_cmd_compute_state
{
2391 struct anv_cmd_pipeline_state base
;
2393 bool pipeline_dirty
;
2395 struct anv_address num_workgroups
;
2398 /** State required while building cmd buffer */
2399 struct anv_cmd_state
{
2400 /* PIPELINE_SELECT.PipelineSelection */
2401 uint32_t current_pipeline
;
2402 const struct gen_l3_config
* current_l3_config
;
2404 struct anv_cmd_graphics_state gfx
;
2405 struct anv_cmd_compute_state compute
;
2407 enum anv_pipe_bits pending_pipe_bits
;
2408 VkShaderStageFlags descriptors_dirty
;
2409 VkShaderStageFlags push_constants_dirty
;
2411 struct anv_framebuffer
* framebuffer
;
2412 struct anv_render_pass
* pass
;
2413 struct anv_subpass
* subpass
;
2414 VkRect2D render_area
;
2415 uint32_t restart_index
;
2416 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2418 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2419 VkShaderStageFlags push_constant_stages
;
2420 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2421 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2422 struct anv_state samplers
[MESA_SHADER_STAGES
];
2425 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2426 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2427 * and before invoking the secondary in ExecuteCommands.
2429 bool pma_fix_enabled
;
2432 * Whether or not we know for certain that HiZ is enabled for the current
2433 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2434 * enabled or not, this will be false.
2438 bool conditional_render_enabled
;
2441 * Last rendering scale argument provided to
2442 * genX(cmd_buffer_emit_hashing_mode)().
2444 unsigned current_hash_scale
;
2447 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2448 * valid only when recording a render pass instance.
2450 struct anv_attachment_state
* attachments
;
2453 * Surface states for color render targets. These are stored in a single
2454 * flat array. For depth-stencil attachments, the surface state is simply
2457 struct anv_state render_pass_states
;
2460 * A null surface state of the right size to match the framebuffer. This
2461 * is one of the states in render_pass_states.
2463 struct anv_state null_surface_state
;
2466 struct anv_cmd_pool
{
2467 VkAllocationCallbacks alloc
;
2468 struct list_head cmd_buffers
;
2471 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2473 enum anv_cmd_buffer_exec_mode
{
2474 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2475 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2476 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2477 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2478 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2481 struct anv_cmd_buffer
{
2482 VK_LOADER_DATA _loader_data
;
2484 struct anv_device
* device
;
2486 struct anv_cmd_pool
* pool
;
2487 struct list_head pool_link
;
2489 struct anv_batch batch
;
2491 /* Fields required for the actual chain of anv_batch_bo's.
2493 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2495 struct list_head batch_bos
;
2496 enum anv_cmd_buffer_exec_mode exec_mode
;
2498 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2499 * referenced by this command buffer
2501 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2503 struct u_vector seen_bbos
;
2505 /* A vector of int32_t's for every block of binding tables.
2507 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2509 struct u_vector bt_block_states
;
2512 struct anv_reloc_list surface_relocs
;
2513 /** Last seen surface state block pool center bo offset */
2514 uint32_t last_ss_pool_center
;
2516 /* Serial for tracking buffer completion */
2519 /* Stream objects for storing temporary data */
2520 struct anv_state_stream surface_state_stream
;
2521 struct anv_state_stream dynamic_state_stream
;
2523 VkCommandBufferUsageFlags usage_flags
;
2524 VkCommandBufferLevel level
;
2526 struct anv_cmd_state state
;
2529 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2530 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2531 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2532 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2533 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2534 struct anv_cmd_buffer
*secondary
);
2535 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2536 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2537 struct anv_cmd_buffer
*cmd_buffer
,
2538 const VkSemaphore
*in_semaphores
,
2539 uint32_t num_in_semaphores
,
2540 const VkSemaphore
*out_semaphores
,
2541 uint32_t num_out_semaphores
,
2544 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2546 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2547 const void *data
, uint32_t size
, uint32_t alignment
);
2548 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2549 uint32_t *a
, uint32_t *b
,
2550 uint32_t dwords
, uint32_t alignment
);
2553 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2555 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2556 uint32_t entries
, uint32_t *state_offset
);
2558 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2560 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2561 uint32_t size
, uint32_t alignment
);
2564 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2566 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2567 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2568 bool depth_clamp_enable
);
2569 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2571 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2572 struct anv_render_pass
*pass
,
2573 struct anv_framebuffer
*framebuffer
,
2574 const VkClearValue
*clear_values
);
2576 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2579 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2580 gl_shader_stage stage
);
2582 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2584 const struct anv_image_view
*
2585 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2588 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2589 uint32_t num_entries
,
2590 uint32_t *state_offset
,
2591 struct anv_state
*bt_state
);
2593 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2595 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2597 enum anv_fence_type
{
2598 ANV_FENCE_TYPE_NONE
= 0,
2600 ANV_FENCE_TYPE_SYNCOBJ
,
2604 enum anv_bo_fence_state
{
2605 /** Indicates that this is a new (or newly reset fence) */
2606 ANV_BO_FENCE_STATE_RESET
,
2608 /** Indicates that this fence has been submitted to the GPU but is still
2609 * (as far as we know) in use by the GPU.
2611 ANV_BO_FENCE_STATE_SUBMITTED
,
2613 ANV_BO_FENCE_STATE_SIGNALED
,
2616 struct anv_fence_impl
{
2617 enum anv_fence_type type
;
2620 /** Fence implementation for BO fences
2622 * These fences use a BO and a set of CPU-tracked state flags. The BO
2623 * is added to the object list of the last execbuf call in a QueueSubmit
2624 * and is marked EXEC_WRITE. The state flags track when the BO has been
2625 * submitted to the kernel. We need to do this because Vulkan lets you
2626 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2627 * will say it's idle in this case.
2631 enum anv_bo_fence_state state
;
2634 /** DRM syncobj handle for syncobj-based fences */
2638 struct wsi_fence
*fence_wsi
;
2643 /* Permanent fence state. Every fence has some form of permanent state
2644 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2645 * cross-process fences) or it could just be a dummy for use internally.
2647 struct anv_fence_impl permanent
;
2649 /* Temporary fence state. A fence *may* have temporary state. That state
2650 * is added to the fence by an import operation and is reset back to
2651 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2652 * state cannot be signaled because the fence must already be signaled
2653 * before the temporary state can be exported from the fence in the other
2654 * process and imported here.
2656 struct anv_fence_impl temporary
;
2661 struct anv_state state
;
2664 enum anv_semaphore_type
{
2665 ANV_SEMAPHORE_TYPE_NONE
= 0,
2666 ANV_SEMAPHORE_TYPE_DUMMY
,
2667 ANV_SEMAPHORE_TYPE_BO
,
2668 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2669 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2672 struct anv_semaphore_impl
{
2673 enum anv_semaphore_type type
;
2676 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2677 * This BO will be added to the object list on any execbuf2 calls for
2678 * which this semaphore is used as a wait or signal fence. When used as
2679 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2683 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2684 * If the semaphore is in the unsignaled state due to either just being
2685 * created or because it has been used for a wait, fd will be -1.
2689 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2690 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2691 * import so we don't need to bother with a userspace cache.
2697 struct anv_semaphore
{
2698 /* Permanent semaphore state. Every semaphore has some form of permanent
2699 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2700 * (for cross-process semaphores0 or it could just be a dummy for use
2703 struct anv_semaphore_impl permanent
;
2705 /* Temporary semaphore state. A semaphore *may* have temporary state.
2706 * That state is added to the semaphore by an import operation and is reset
2707 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2708 * semaphore with temporary state cannot be signaled because the semaphore
2709 * must already be signaled before the temporary state can be exported from
2710 * the semaphore in the other process and imported here.
2712 struct anv_semaphore_impl temporary
;
2715 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2716 struct anv_semaphore
*semaphore
);
2718 struct anv_shader_module
{
2719 unsigned char sha1
[20];
2724 static inline gl_shader_stage
2725 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2727 assert(__builtin_popcount(vk_stage
) == 1);
2728 return ffs(vk_stage
) - 1;
2731 static inline VkShaderStageFlagBits
2732 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2734 return (1 << mesa_stage
);
2737 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2739 #define anv_foreach_stage(stage, stage_bits) \
2740 for (gl_shader_stage stage, \
2741 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2742 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2743 __tmp &= ~(1 << (stage)))
2745 struct anv_pipeline_bind_map
{
2746 uint32_t surface_count
;
2747 uint32_t sampler_count
;
2749 struct anv_pipeline_binding
* surface_to_descriptor
;
2750 struct anv_pipeline_binding
* sampler_to_descriptor
;
2753 struct anv_shader_bin_key
{
2758 struct anv_shader_bin
{
2761 const struct anv_shader_bin_key
*key
;
2763 struct anv_state kernel
;
2764 uint32_t kernel_size
;
2766 struct anv_state constant_data
;
2767 uint32_t constant_data_size
;
2769 const struct brw_stage_prog_data
*prog_data
;
2770 uint32_t prog_data_size
;
2772 struct brw_compile_stats stats
[3];
2775 struct nir_xfb_info
*xfb_info
;
2777 struct anv_pipeline_bind_map bind_map
;
2780 struct anv_shader_bin
*
2781 anv_shader_bin_create(struct anv_device
*device
,
2782 const void *key
, uint32_t key_size
,
2783 const void *kernel
, uint32_t kernel_size
,
2784 const void *constant_data
, uint32_t constant_data_size
,
2785 const struct brw_stage_prog_data
*prog_data
,
2786 uint32_t prog_data_size
, const void *prog_data_param
,
2787 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2788 const struct nir_xfb_info
*xfb_info
,
2789 const struct anv_pipeline_bind_map
*bind_map
);
2792 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2795 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2797 assert(shader
&& shader
->ref_cnt
>= 1);
2798 p_atomic_inc(&shader
->ref_cnt
);
2802 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2804 assert(shader
&& shader
->ref_cnt
>= 1);
2805 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2806 anv_shader_bin_destroy(device
, shader
);
2809 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2810 #define MAX_PIPELINE_EXECUTABLES 7
2812 struct anv_pipeline_executable
{
2813 gl_shader_stage stage
;
2815 struct brw_compile_stats stats
;
2820 struct anv_pipeline
{
2821 struct anv_device
* device
;
2822 struct anv_batch batch
;
2823 uint32_t batch_data
[512];
2824 struct anv_reloc_list batch_relocs
;
2825 anv_cmd_dirty_mask_t dynamic_state_mask
;
2826 struct anv_dynamic_state dynamic_state
;
2830 VkPipelineCreateFlags flags
;
2831 struct anv_subpass
* subpass
;
2833 bool needs_data_cache
;
2835 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2837 uint32_t num_executables
;
2838 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2841 const struct gen_l3_config
* l3_config
;
2842 uint32_t total_size
;
2845 VkShaderStageFlags active_stages
;
2846 struct anv_state blend_state
;
2849 struct anv_pipeline_vertex_binding
{
2852 uint32_t instance_divisor
;
2857 bool primitive_restart
;
2860 uint32_t cs_right_mask
;
2863 bool depth_test_enable
;
2864 bool writes_stencil
;
2865 bool stencil_test_enable
;
2866 bool depth_clamp_enable
;
2867 bool depth_clip_enable
;
2868 bool sample_shading_enable
;
2873 uint32_t depth_stencil_state
[3];
2879 uint32_t wm_depth_stencil
[3];
2883 uint32_t wm_depth_stencil
[4];
2886 uint32_t interface_descriptor_data
[8];
2890 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2891 gl_shader_stage stage
)
2893 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2896 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2897 static inline const struct brw_##prefix##_prog_data * \
2898 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2900 if (anv_pipeline_has_stage(pipeline, stage)) { \
2901 return (const struct brw_##prefix##_prog_data *) \
2902 pipeline->shaders[stage]->prog_data; \
2908 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2909 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2910 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2911 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2912 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2913 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2915 static inline const struct brw_vue_prog_data
*
2916 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2918 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2919 return &get_gs_prog_data(pipeline
)->base
;
2920 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2921 return &get_tes_prog_data(pipeline
)->base
;
2923 return &get_vs_prog_data(pipeline
)->base
;
2927 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2928 struct anv_pipeline_cache
*cache
,
2929 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2930 const VkAllocationCallbacks
*alloc
);
2933 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2934 struct anv_pipeline_cache
*cache
,
2935 const VkComputePipelineCreateInfo
*info
,
2936 const struct anv_shader_module
*module
,
2937 const char *entrypoint
,
2938 const VkSpecializationInfo
*spec_info
);
2940 struct anv_format_plane
{
2941 enum isl_format isl_format
:16;
2942 struct isl_swizzle swizzle
;
2944 /* Whether this plane contains chroma channels */
2947 /* For downscaling of YUV planes */
2948 uint8_t denominator_scales
[2];
2950 /* How to map sampled ycbcr planes to a single 4 component element. */
2951 struct isl_swizzle ycbcr_swizzle
;
2953 /* What aspect is associated to this plane */
2954 VkImageAspectFlags aspect
;
2959 struct anv_format_plane planes
[3];
2965 static inline uint32_t
2966 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2967 VkImageAspectFlags aspect_mask
)
2969 switch (aspect_mask
) {
2970 case VK_IMAGE_ASPECT_COLOR_BIT
:
2971 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2972 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2974 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2975 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2978 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2980 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2983 /* Purposefully assert with depth/stencil aspects. */
2984 unreachable("invalid image aspect");
2988 static inline VkImageAspectFlags
2989 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2992 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2993 if (util_bitcount(image_aspects
) > 1)
2994 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2995 return VK_IMAGE_ASPECT_COLOR_BIT
;
2997 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2998 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2999 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3000 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3003 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3004 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3006 const struct anv_format
*
3007 anv_get_format(VkFormat format
);
3009 static inline uint32_t
3010 anv_get_format_planes(VkFormat vk_format
)
3012 const struct anv_format
*format
= anv_get_format(vk_format
);
3014 return format
!= NULL
? format
->n_planes
: 0;
3017 struct anv_format_plane
3018 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3019 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3021 static inline enum isl_format
3022 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3023 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3025 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3028 static inline struct isl_swizzle
3029 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3031 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3032 * RGB as RGBA for texturing
3034 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3035 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3037 /* But it doesn't matter what we render to that channel */
3038 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3044 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3047 * Subsurface of an anv_image.
3049 struct anv_surface
{
3050 /** Valid only if isl_surf::size_B > 0. */
3051 struct isl_surf isl
;
3054 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3060 VkImageType type
; /**< VkImageCreateInfo::imageType */
3061 /* The original VkFormat provided by the client. This may not match any
3062 * of the actual surface formats.
3065 const struct anv_format
*format
;
3067 VkImageAspectFlags aspects
;
3070 uint32_t array_size
;
3071 uint32_t samples
; /**< VkImageCreateInfo::samples */
3073 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3074 VkImageUsageFlags stencil_usage
;
3075 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3076 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3078 /** True if this is needs to be bound to an appropriately tiled BO.
3080 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3081 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3082 * we require a dedicated allocation so that we can know to allocate a
3085 bool needs_set_tiling
;
3088 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3089 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3091 uint64_t drm_format_mod
;
3096 /* Whether the image is made of several underlying buffer objects rather a
3097 * single one with different offsets.
3101 /* All the formats that can be used when creating views of this image
3102 * are CCS_E compatible.
3104 bool ccs_e_compatible
;
3106 /* Image was created with external format. */
3107 bool external_format
;
3112 * For each foo, anv_image::planes[x].surface is valid if and only if
3113 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3114 * to figure the number associated with a given aspect.
3116 * The hardware requires that the depth buffer and stencil buffer be
3117 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3118 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3119 * allocate the depth and stencil buffers as separate surfaces in the same
3124 * -----------------------
3126 * ----------------------- |
3127 * | shadow surface0 | |
3128 * ----------------------- | Plane 0
3129 * | aux surface0 | |
3130 * ----------------------- |
3131 * | fast clear colors0 | \|/
3132 * -----------------------
3134 * ----------------------- |
3135 * | shadow surface1 | |
3136 * ----------------------- | Plane 1
3137 * | aux surface1 | |
3138 * ----------------------- |
3139 * | fast clear colors1 | \|/
3140 * -----------------------
3143 * -----------------------
3147 * Offset of the entire plane (whenever the image is disjoint this is
3155 struct anv_surface surface
;
3158 * A surface which shadows the main surface and may have different
3159 * tiling. This is used for sampling using a tiling that isn't supported
3160 * for other operations.
3162 struct anv_surface shadow_surface
;
3165 * For color images, this is the aux usage for this image when not used
3166 * as a color attachment.
3168 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3169 * image has a HiZ buffer.
3171 enum isl_aux_usage aux_usage
;
3173 struct anv_surface aux_surface
;
3176 * Offset of the fast clear state (used to compute the
3177 * fast_clear_state_offset of the following planes).
3179 uint32_t fast_clear_state_offset
;
3182 * BO associated with this plane, set when bound.
3184 struct anv_address address
;
3187 * When destroying the image, also free the bo.
3193 /* The ordering of this enum is important */
3194 enum anv_fast_clear_type
{
3195 /** Image does not have/support any fast-clear blocks */
3196 ANV_FAST_CLEAR_NONE
= 0,
3197 /** Image has/supports fast-clear but only to the default value */
3198 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3199 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3200 ANV_FAST_CLEAR_ANY
= 2,
3203 /* Returns the number of auxiliary buffer levels attached to an image. */
3204 static inline uint8_t
3205 anv_image_aux_levels(const struct anv_image
* const image
,
3206 VkImageAspectFlagBits aspect
)
3208 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3209 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3210 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
3213 /* Returns the number of auxiliary buffer layers attached to an image. */
3214 static inline uint32_t
3215 anv_image_aux_layers(const struct anv_image
* const image
,
3216 VkImageAspectFlagBits aspect
,
3217 const uint8_t miplevel
)
3221 /* The miplevel must exist in the main buffer. */
3222 assert(miplevel
< image
->levels
);
3224 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3225 /* There are no layers with auxiliary data because the miplevel has no
3230 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3231 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
3232 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
3236 static inline struct anv_address
3237 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3238 const struct anv_image
*image
,
3239 VkImageAspectFlagBits aspect
)
3241 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3243 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3244 return anv_address_add(image
->planes
[plane
].address
,
3245 image
->planes
[plane
].fast_clear_state_offset
);
3248 static inline struct anv_address
3249 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3250 const struct anv_image
*image
,
3251 VkImageAspectFlagBits aspect
)
3253 struct anv_address addr
=
3254 anv_image_get_clear_color_addr(device
, image
, aspect
);
3256 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3257 device
->isl_dev
.ss
.clear_color_state_size
:
3258 device
->isl_dev
.ss
.clear_value_size
;
3259 return anv_address_add(addr
, clear_color_state_size
);
3262 static inline struct anv_address
3263 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3264 const struct anv_image
*image
,
3265 VkImageAspectFlagBits aspect
,
3266 uint32_t level
, uint32_t array_layer
)
3268 assert(level
< anv_image_aux_levels(image
, aspect
));
3269 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3270 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3271 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3273 struct anv_address addr
=
3274 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3275 addr
.offset
+= 4; /* Go past the fast clear type */
3277 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3278 for (uint32_t l
= 0; l
< level
; l
++)
3279 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3281 addr
.offset
+= level
* image
->array_size
* 4;
3283 addr
.offset
+= array_layer
* 4;
3288 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3290 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3291 const struct anv_image
*image
)
3293 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3296 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3297 * struct. There's documentation which suggests that this feature actually
3298 * reduces performance on BDW, but it has only been observed to help so
3299 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3300 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3302 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3305 return image
->samples
== 1;
3309 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3310 const struct anv_image
*image
,
3311 VkImageAspectFlagBits aspect
,
3312 enum isl_aux_usage aux_usage
,
3314 uint32_t base_layer
,
3315 uint32_t layer_count
);
3318 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3319 const struct anv_image
*image
,
3320 VkImageAspectFlagBits aspect
,
3321 enum isl_aux_usage aux_usage
,
3322 enum isl_format format
, struct isl_swizzle swizzle
,
3323 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3324 VkRect2D area
, union isl_color_value clear_color
);
3326 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3327 const struct anv_image
*image
,
3328 VkImageAspectFlags aspects
,
3329 enum isl_aux_usage depth_aux_usage
,
3331 uint32_t base_layer
, uint32_t layer_count
,
3333 float depth_value
, uint8_t stencil_value
);
3335 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3336 const struct anv_image
*src_image
,
3337 enum isl_aux_usage src_aux_usage
,
3338 uint32_t src_level
, uint32_t src_base_layer
,
3339 const struct anv_image
*dst_image
,
3340 enum isl_aux_usage dst_aux_usage
,
3341 uint32_t dst_level
, uint32_t dst_base_layer
,
3342 VkImageAspectFlagBits aspect
,
3343 uint32_t src_x
, uint32_t src_y
,
3344 uint32_t dst_x
, uint32_t dst_y
,
3345 uint32_t width
, uint32_t height
,
3346 uint32_t layer_count
,
3347 enum blorp_filter filter
);
3349 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3350 const struct anv_image
*image
,
3351 VkImageAspectFlagBits aspect
, uint32_t level
,
3352 uint32_t base_layer
, uint32_t layer_count
,
3353 enum isl_aux_op hiz_op
);
3355 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3356 const struct anv_image
*image
,
3357 VkImageAspectFlags aspects
,
3359 uint32_t base_layer
, uint32_t layer_count
,
3360 VkRect2D area
, uint8_t stencil_value
);
3362 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3363 const struct anv_image
*image
,
3364 enum isl_format format
,
3365 VkImageAspectFlagBits aspect
,
3366 uint32_t base_layer
, uint32_t layer_count
,
3367 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3370 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3371 const struct anv_image
*image
,
3372 enum isl_format format
,
3373 VkImageAspectFlagBits aspect
, uint32_t level
,
3374 uint32_t base_layer
, uint32_t layer_count
,
3375 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3379 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3380 const struct anv_image
*image
,
3381 VkImageAspectFlagBits aspect
,
3382 uint32_t base_level
, uint32_t level_count
,
3383 uint32_t base_layer
, uint32_t layer_count
);
3386 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3387 const struct anv_image
*image
,
3388 const VkImageAspectFlagBits aspect
,
3389 const VkImageLayout layout
);
3391 enum anv_fast_clear_type
3392 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3393 const struct anv_image
* const image
,
3394 const VkImageAspectFlagBits aspect
,
3395 const VkImageLayout layout
);
3397 /* This is defined as a macro so that it works for both
3398 * VkImageSubresourceRange and VkImageSubresourceLayers
3400 #define anv_get_layerCount(_image, _range) \
3401 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3402 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3404 static inline uint32_t
3405 anv_get_levelCount(const struct anv_image
*image
,
3406 const VkImageSubresourceRange
*range
)
3408 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3409 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3412 static inline VkImageAspectFlags
3413 anv_image_expand_aspects(const struct anv_image
*image
,
3414 VkImageAspectFlags aspects
)
3416 /* If the underlying image has color plane aspects and
3417 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3418 * the underlying image. */
3419 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3420 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3421 return image
->aspects
;
3427 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3428 VkImageAspectFlags aspects2
)
3430 if (aspects1
== aspects2
)
3433 /* Only 1 color aspects are compatibles. */
3434 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3435 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3436 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3442 struct anv_image_view
{
3443 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3445 VkImageAspectFlags aspect_mask
;
3447 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3451 uint32_t image_plane
;
3453 struct isl_view isl
;
3456 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3457 * image layout of SHADER_READ_ONLY_OPTIMAL or
3458 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3460 struct anv_surface_state optimal_sampler_surface_state
;
3463 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3464 * image layout of GENERAL.
3466 struct anv_surface_state general_sampler_surface_state
;
3469 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3470 * states for write-only and readable, using the real format for
3471 * write-only and the lowered format for readable.
3473 struct anv_surface_state storage_surface_state
;
3474 struct anv_surface_state writeonly_storage_surface_state
;
3476 struct brw_image_param storage_image_param
;
3480 enum anv_image_view_state_flags
{
3481 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3482 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3485 void anv_image_fill_surface_state(struct anv_device
*device
,
3486 const struct anv_image
*image
,
3487 VkImageAspectFlagBits aspect
,
3488 const struct isl_view
*view
,
3489 isl_surf_usage_flags_t view_usage
,
3490 enum isl_aux_usage aux_usage
,
3491 const union isl_color_value
*clear_color
,
3492 enum anv_image_view_state_flags flags
,
3493 struct anv_surface_state
*state_inout
,
3494 struct brw_image_param
*image_param_out
);
3496 struct anv_image_create_info
{
3497 const VkImageCreateInfo
*vk_info
;
3499 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3500 isl_tiling_flags_t isl_tiling_flags
;
3502 /** These flags will be added to any derived from VkImageCreateInfo. */
3503 isl_surf_usage_flags_t isl_extra_usage_flags
;
3506 bool external_format
;
3509 VkResult
anv_image_create(VkDevice _device
,
3510 const struct anv_image_create_info
*info
,
3511 const VkAllocationCallbacks
* alloc
,
3514 const struct anv_surface
*
3515 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3516 VkImageAspectFlags aspect_mask
);
3519 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3521 static inline struct VkExtent3D
3522 anv_sanitize_image_extent(const VkImageType imageType
,
3523 const struct VkExtent3D imageExtent
)
3525 switch (imageType
) {
3526 case VK_IMAGE_TYPE_1D
:
3527 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3528 case VK_IMAGE_TYPE_2D
:
3529 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3530 case VK_IMAGE_TYPE_3D
:
3533 unreachable("invalid image type");
3537 static inline struct VkOffset3D
3538 anv_sanitize_image_offset(const VkImageType imageType
,
3539 const struct VkOffset3D imageOffset
)
3541 switch (imageType
) {
3542 case VK_IMAGE_TYPE_1D
:
3543 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3544 case VK_IMAGE_TYPE_2D
:
3545 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3546 case VK_IMAGE_TYPE_3D
:
3549 unreachable("invalid image type");
3553 VkFormatFeatureFlags
3554 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3556 const struct anv_format
*anv_format
,
3557 VkImageTiling vk_tiling
);
3559 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3560 struct anv_state state
,
3561 enum isl_format format
,
3562 struct anv_address address
,
3563 uint32_t range
, uint32_t stride
);
3566 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3567 const struct anv_attachment_state
*att_state
,
3568 const struct anv_image_view
*iview
)
3570 const struct isl_format_layout
*view_fmtl
=
3571 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3573 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3574 if (view_fmtl->channels.c.bits) \
3575 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3577 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3578 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3579 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3580 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3582 #undef COPY_CLEAR_COLOR_CHANNEL
3586 struct anv_ycbcr_conversion
{
3587 const struct anv_format
* format
;
3588 VkSamplerYcbcrModelConversion ycbcr_model
;
3589 VkSamplerYcbcrRange ycbcr_range
;
3590 VkComponentSwizzle mapping
[4];
3591 VkChromaLocation chroma_offsets
[2];
3592 VkFilter chroma_filter
;
3593 bool chroma_reconstruction
;
3596 struct anv_sampler
{
3597 uint32_t state
[3][4];
3599 struct anv_ycbcr_conversion
*conversion
;
3601 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3602 * and with a 32-byte stride for use as bindless samplers.
3604 struct anv_state bindless_state
;
3607 struct anv_framebuffer
{
3612 uint32_t attachment_count
;
3613 struct anv_image_view
* attachments
[0];
3616 struct anv_subpass_attachment
{
3617 VkImageUsageFlagBits usage
;
3618 uint32_t attachment
;
3619 VkImageLayout layout
;
3622 struct anv_subpass
{
3623 uint32_t attachment_count
;
3626 * A pointer to all attachment references used in this subpass.
3627 * Only valid if ::attachment_count > 0.
3629 struct anv_subpass_attachment
* attachments
;
3630 uint32_t input_count
;
3631 struct anv_subpass_attachment
* input_attachments
;
3632 uint32_t color_count
;
3633 struct anv_subpass_attachment
* color_attachments
;
3634 struct anv_subpass_attachment
* resolve_attachments
;
3636 struct anv_subpass_attachment
* depth_stencil_attachment
;
3637 struct anv_subpass_attachment
* ds_resolve_attachment
;
3638 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3639 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3643 /** Subpass has a depth/stencil self-dependency */
3644 bool has_ds_self_dep
;
3646 /** Subpass has at least one color resolve attachment */
3647 bool has_color_resolve
;
3650 static inline unsigned
3651 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3653 return MAX2(1, util_bitcount(subpass
->view_mask
));
3656 struct anv_render_pass_attachment
{
3657 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3658 * its members individually.
3662 VkImageUsageFlags usage
;
3663 VkAttachmentLoadOp load_op
;
3664 VkAttachmentStoreOp store_op
;
3665 VkAttachmentLoadOp stencil_load_op
;
3666 VkImageLayout initial_layout
;
3667 VkImageLayout final_layout
;
3668 VkImageLayout first_subpass_layout
;
3670 /* The subpass id in which the attachment will be used last. */
3671 uint32_t last_subpass_idx
;
3674 struct anv_render_pass
{
3675 uint32_t attachment_count
;
3676 uint32_t subpass_count
;
3677 /* An array of subpass_count+1 flushes, one per subpass boundary */
3678 enum anv_pipe_bits
* subpass_flushes
;
3679 struct anv_render_pass_attachment
* attachments
;
3680 struct anv_subpass subpasses
[0];
3683 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3685 struct anv_query_pool
{
3687 VkQueryPipelineStatisticFlags pipeline_statistics
;
3688 /** Stride between slots, in bytes */
3690 /** Number of slots in this query pool */
3695 int anv_get_instance_entrypoint_index(const char *name
);
3696 int anv_get_device_entrypoint_index(const char *name
);
3697 int anv_get_physical_device_entrypoint_index(const char *name
);
3699 const char *anv_get_instance_entry_name(int index
);
3700 const char *anv_get_physical_device_entry_name(int index
);
3701 const char *anv_get_device_entry_name(int index
);
3704 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3705 const struct anv_instance_extension_table
*instance
);
3707 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3708 const struct anv_instance_extension_table
*instance
);
3710 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3711 const struct anv_instance_extension_table
*instance
,
3712 const struct anv_device_extension_table
*device
);
3714 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3717 void anv_dump_image_to_ppm(struct anv_device
*device
,
3718 struct anv_image
*image
, unsigned miplevel
,
3719 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3720 const char *filename
);
3722 enum anv_dump_action
{
3723 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3726 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3727 void anv_dump_finish(void);
3729 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3731 static inline uint32_t
3732 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3734 /* This function must be called from within a subpass. */
3735 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3737 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3739 /* The id of this subpass shouldn't exceed the number of subpasses in this
3740 * render pass minus 1.
3742 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3746 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3748 static inline struct __anv_type * \
3749 __anv_type ## _from_handle(__VkType _handle) \
3751 return (struct __anv_type *) _handle; \
3754 static inline __VkType \
3755 __anv_type ## _to_handle(struct __anv_type *_obj) \
3757 return (__VkType) _obj; \
3760 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3762 static inline struct __anv_type * \
3763 __anv_type ## _from_handle(__VkType _handle) \
3765 return (struct __anv_type *)(uintptr_t) _handle; \
3768 static inline __VkType \
3769 __anv_type ## _to_handle(struct __anv_type *_obj) \
3771 return (__VkType)(uintptr_t) _obj; \
3774 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3775 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3777 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3778 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3779 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3780 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3781 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3783 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3784 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3785 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3786 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3787 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3788 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3789 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3790 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3791 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3792 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3793 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3794 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3795 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3796 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3797 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3798 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3799 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3800 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3801 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3802 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3803 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3804 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3805 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3807 /* Gen-specific function declarations */
3809 # include "anv_genX.h"
3811 # define genX(x) gen7_##x
3812 # include "anv_genX.h"
3814 # define genX(x) gen75_##x
3815 # include "anv_genX.h"
3817 # define genX(x) gen8_##x
3818 # include "anv_genX.h"
3820 # define genX(x) gen9_##x
3821 # include "anv_genX.h"
3823 # define genX(x) gen10_##x
3824 # include "anv_genX.h"
3826 # define genX(x) gen11_##x
3827 # include "anv_genX.h"
3829 # define genX(x) gen12_##x
3830 # include "anv_genX.h"
3834 #endif /* ANV_PRIVATE_H */