2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
60 #include "util/xmlconfig.h"
62 #include "vk_debug_report.h"
64 /* Pre-declarations needed for WSI entrypoints */
67 typedef struct xcb_connection_t xcb_connection_t
;
68 typedef uint32_t xcb_visualid_t
;
69 typedef uint32_t xcb_window_t
;
72 struct anv_buffer_view
;
73 struct anv_image_view
;
77 struct gen_perf_config
;
79 #include <vulkan/vulkan.h>
80 #include <vulkan/vulkan_intel.h>
81 #include <vulkan/vk_icd.h>
83 #include "anv_android.h"
84 #include "anv_entrypoints.h"
85 #include "anv_extensions.h"
88 #include "dev/gen_debug.h"
89 #include "common/intel_log.h"
90 #include "wsi_common.h"
92 /* anv Virtual Memory Layout
93 * =========================
95 * When the anv driver is determining the virtual graphics addresses of memory
96 * objects itself using the softpin mechanism, the following memory ranges
99 * Three special considerations to notice:
101 * (1) the dynamic state pool is located within the same 4 GiB as the low
102 * heap. This is to work around a VF cache issue described in a comment in
103 * anv_physical_device_init_heaps.
105 * (2) the binding table pool is located at lower addresses than the surface
106 * state pool, within a 4 GiB range. This allows surface state base addresses
107 * to cover both binding tables (16 bit offsets) and surface states (32 bit
110 * (3) the last 4 GiB of the address space is withheld from the high
111 * heap. Various hardware units will read past the end of an object for
112 * various reasons. This healthy margin prevents reads from wrapping around
115 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
116 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
117 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
118 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
119 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
120 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
121 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
122 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
123 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
124 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
125 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
127 #define LOW_HEAP_SIZE \
128 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
129 #define DYNAMIC_STATE_POOL_SIZE \
130 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
131 #define BINDING_TABLE_POOL_SIZE \
132 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
133 #define SURFACE_STATE_POOL_SIZE \
134 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
135 #define INSTRUCTION_STATE_POOL_SIZE \
136 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
138 /* Allowing different clear colors requires us to perform a depth resolve at
139 * the end of certain render passes. This is because while slow clears store
140 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
141 * See the PRMs for examples describing when additional resolves would be
142 * necessary. To enable fast clears without requiring extra resolves, we set
143 * the clear value to a globally-defined one. We could allow different values
144 * if the user doesn't expect coherent data during or after a render passes
145 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
146 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
147 * 1.0f seems to be the only value used. The only application that doesn't set
148 * this value does so through the usage of an seemingly uninitialized clear
151 #define ANV_HZ_FC_VAL 1.0f
154 #define MAX_XFB_BUFFERS 4
155 #define MAX_XFB_STREAMS 4
158 #define MAX_VIEWPORTS 16
159 #define MAX_SCISSORS 16
160 #define MAX_PUSH_CONSTANTS_SIZE 128
161 #define MAX_DYNAMIC_BUFFERS 16
162 #define MAX_IMAGES 64
163 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
164 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
165 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
167 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
169 * "The surface state model is used when a Binding Table Index (specified
170 * in the message descriptor) of less than 240 is specified. In this model,
171 * the Binding Table Index is used to index into the binding table, and the
172 * binding table entry contains a pointer to the SURFACE_STATE."
174 * Binding table values above 240 are used for various things in the hardware
175 * such as stateless, stateless with incoherent cache, SLM, and bindless.
177 #define MAX_BINDING_TABLE_SIZE 240
179 /* The kernel relocation API has a limitation of a 32-bit delta value
180 * applied to the address before it is written which, in spite of it being
181 * unsigned, is treated as signed . Because of the way that this maps to
182 * the Vulkan API, we cannot handle an offset into a buffer that does not
183 * fit into a signed 32 bits. The only mechanism we have for dealing with
184 * this at the moment is to limit all VkDeviceMemory objects to a maximum
185 * of 2GB each. The Vulkan spec allows us to do this:
187 * "Some platforms may have a limit on the maximum size of a single
188 * allocation. For example, certain systems may fail to create
189 * allocations with a size greater than or equal to 4GB. Such a limit is
190 * implementation-dependent, and if such a failure occurs then the error
191 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
193 * We don't use vk_error here because it's not an error so much as an
194 * indication to the application that the allocation is too large.
196 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
198 #define ANV_SVGS_VB_INDEX MAX_VBS
199 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
201 /* We reserve this MI ALU register for the purpose of handling predication.
202 * Other code which uses the MI ALU should leave it alone.
204 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
206 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
208 static inline uint32_t
209 align_down_npot_u32(uint32_t v
, uint32_t a
)
214 static inline uint32_t
215 align_u32(uint32_t v
, uint32_t a
)
217 assert(a
!= 0 && a
== (a
& -a
));
218 return (v
+ a
- 1) & ~(a
- 1);
221 static inline uint64_t
222 align_u64(uint64_t v
, uint64_t a
)
224 assert(a
!= 0 && a
== (a
& -a
));
225 return (v
+ a
- 1) & ~(a
- 1);
228 static inline int32_t
229 align_i32(int32_t v
, int32_t a
)
231 assert(a
!= 0 && a
== (a
& -a
));
232 return (v
+ a
- 1) & ~(a
- 1);
235 /** Alignment must be a power of 2. */
237 anv_is_aligned(uintmax_t n
, uintmax_t a
)
239 assert(a
== (a
& -a
));
240 return (n
& (a
- 1)) == 0;
243 static inline uint32_t
244 anv_minify(uint32_t n
, uint32_t levels
)
246 if (unlikely(n
== 0))
249 return MAX2(n
>> levels
, 1);
253 anv_clamp_f(float f
, float min
, float max
)
266 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
268 if (*inout_mask
& clear_mask
) {
269 *inout_mask
&= ~clear_mask
;
276 static inline union isl_color_value
277 vk_to_isl_color(VkClearColorValue color
)
279 return (union isl_color_value
) {
289 #define for_each_bit(b, dword) \
290 for (uint32_t __dword = (dword); \
291 (b) = __builtin_ffs(__dword) - 1, __dword; \
292 __dword &= ~(1 << (b)))
294 #define typed_memcpy(dest, src, count) ({ \
295 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
296 memcpy((dest), (src), (count) * sizeof(*(src))); \
299 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
300 * to be added here in order to utilize mapping in debug/error/perf macros.
302 #define REPORT_OBJECT_TYPE(o) \
303 __builtin_choose_expr ( \
304 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
305 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
306 __builtin_choose_expr ( \
307 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
308 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
309 __builtin_choose_expr ( \
310 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
311 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
312 __builtin_choose_expr ( \
313 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
314 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
315 __builtin_choose_expr ( \
316 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
317 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
318 __builtin_choose_expr ( \
319 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
320 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
321 __builtin_choose_expr ( \
322 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
323 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
324 __builtin_choose_expr ( \
325 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
326 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
327 __builtin_choose_expr ( \
328 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
329 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
330 __builtin_choose_expr ( \
331 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
332 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
333 __builtin_choose_expr ( \
334 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
335 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
336 __builtin_choose_expr ( \
337 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
338 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
339 __builtin_choose_expr ( \
340 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
341 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
342 __builtin_choose_expr ( \
343 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
344 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
345 __builtin_choose_expr ( \
346 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
347 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
348 __builtin_choose_expr ( \
349 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
350 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
351 __builtin_choose_expr ( \
352 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
353 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
354 __builtin_choose_expr ( \
355 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
356 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
372 __builtin_choose_expr ( \
373 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
374 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
375 __builtin_choose_expr ( \
376 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
377 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
378 __builtin_choose_expr ( \
379 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
380 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
381 __builtin_choose_expr ( \
382 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
383 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
384 __builtin_choose_expr ( \
385 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
386 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
387 __builtin_choose_expr ( \
388 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
389 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
390 __builtin_choose_expr ( \
391 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
392 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
393 __builtin_choose_expr ( \
394 __builtin_types_compatible_p (__typeof (o), void*), \
395 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
396 /* The void expression results in a compile-time error \
397 when assigning the result to something. */ \
398 (void)0)))))))))))))))))))))))))))))))
400 /* Whenever we generate an error, pass it through this function. Useful for
401 * debugging, where we can break on it. Only call at error site, not when
402 * propagating errors. Might be useful to plug in a stack trace here.
405 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
406 VkDebugReportObjectTypeEXT type
, VkResult error
,
407 const char *file
, int line
, const char *format
,
410 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
411 VkDebugReportObjectTypeEXT type
, VkResult error
,
412 const char *file
, int line
, const char *format
, ...);
415 #define vk_error(error) __vk_errorf(NULL, NULL,\
416 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
417 error, __FILE__, __LINE__, NULL)
418 #define vk_errorv(instance, obj, error, format, args)\
419 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
420 __FILE__, __LINE__, format, args)
421 #define vk_errorf(instance, obj, error, format, ...)\
422 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
423 __FILE__, __LINE__, format, ## __VA_ARGS__)
425 #define vk_error(error) error
426 #define vk_errorf(instance, obj, error, format, ...) error
430 * Warn on ignored extension structs.
432 * The Vulkan spec requires us to ignore unsupported or unknown structs in
433 * a pNext chain. In debug mode, emitting warnings for ignored structs may
434 * help us discover structs that we should not have ignored.
437 * From the Vulkan 1.0.38 spec:
439 * Any component of the implementation (the loader, any enabled layers,
440 * and drivers) must skip over, without processing (other than reading the
441 * sType and pNext members) any chained structures with sType values not
442 * defined by extensions supported by that component.
444 #define anv_debug_ignored_stype(sType) \
445 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
447 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
448 VkDebugReportObjectTypeEXT type
, const char *file
,
449 int line
, const char *format
, ...)
450 anv_printflike(6, 7);
451 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
452 void anv_loge_v(const char *format
, va_list va
);
455 * Print a FINISHME message, including its source location.
457 #define anv_finishme(format, ...) \
459 static bool reported = false; \
461 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
468 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
470 #define anv_perf_warn(instance, obj, format, ...) \
472 static bool reported = false; \
473 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
474 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
475 format, ##__VA_ARGS__); \
480 /* A non-fatal assert. Useful for debugging. */
482 #define anv_assert(x) ({ \
483 if (unlikely(!(x))) \
484 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
487 #define anv_assert(x)
490 /* A multi-pointer allocator
492 * When copying data structures from the user (such as a render pass), it's
493 * common to need to allocate data for a bunch of different things. Instead
494 * of doing several allocations and having to handle all of the error checking
495 * that entails, it can be easier to do a single allocation. This struct
496 * helps facilitate that. The intended usage looks like this:
499 * anv_multialloc_add(&ma, &main_ptr, 1);
500 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
501 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
503 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
504 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
506 struct anv_multialloc
{
514 #define ANV_MULTIALLOC_INIT \
515 ((struct anv_multialloc) { 0, })
517 #define ANV_MULTIALLOC(_name) \
518 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
520 __attribute__((always_inline
))
522 _anv_multialloc_add(struct anv_multialloc
*ma
,
523 void **ptr
, size_t size
, size_t align
)
525 size_t offset
= align_u64(ma
->size
, align
);
526 ma
->size
= offset
+ size
;
527 ma
->align
= MAX2(ma
->align
, align
);
529 /* Store the offset in the pointer. */
530 *ptr
= (void *)(uintptr_t)offset
;
532 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
533 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
536 #define anv_multialloc_add_size(_ma, _ptr, _size) \
537 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
539 #define anv_multialloc_add(_ma, _ptr, _count) \
540 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
542 __attribute__((always_inline
))
544 anv_multialloc_alloc(struct anv_multialloc
*ma
,
545 const VkAllocationCallbacks
*alloc
,
546 VkSystemAllocationScope scope
)
548 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
552 /* Fill out each of the pointers with their final value.
554 * for (uint32_t i = 0; i < ma->ptr_count; i++)
555 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
557 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
558 * constant, GCC is incapable of figuring this out and unrolling the loop
559 * so we have to give it a little help.
561 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
562 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
563 if ((_i) < ma->ptr_count) \
564 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
565 _ANV_MULTIALLOC_UPDATE_POINTER(0);
566 _ANV_MULTIALLOC_UPDATE_POINTER(1);
567 _ANV_MULTIALLOC_UPDATE_POINTER(2);
568 _ANV_MULTIALLOC_UPDATE_POINTER(3);
569 _ANV_MULTIALLOC_UPDATE_POINTER(4);
570 _ANV_MULTIALLOC_UPDATE_POINTER(5);
571 _ANV_MULTIALLOC_UPDATE_POINTER(6);
572 _ANV_MULTIALLOC_UPDATE_POINTER(7);
573 #undef _ANV_MULTIALLOC_UPDATE_POINTER
578 __attribute__((always_inline
))
580 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
581 const VkAllocationCallbacks
*parent_alloc
,
582 const VkAllocationCallbacks
*alloc
,
583 VkSystemAllocationScope scope
)
585 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
588 /* Extra ANV-defined BO flags which won't be passed to the kernel */
589 #define ANV_BO_EXTERNAL (1ull << 31)
590 #define ANV_BO_FLAG_MASK (1ull << 31)
595 /* Index into the current validation list. This is used by the
596 * validation list building alrogithm to track which buffers are already
597 * in the validation list so that we can ensure uniqueness.
601 /* Last known offset. This value is provided by the kernel when we
602 * execbuf and is used as the presumed offset for the next bunch of
610 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
615 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
617 bo
->gem_handle
= gem_handle
;
625 /* Represents a lock-free linked list of "free" things. This is used by
626 * both the block pool and the state pools. Unfortunately, in order to
627 * solve the ABA problem, we can't use a single uint32_t head.
629 union anv_free_list
{
633 /* A simple count that is incremented every time the head changes. */
636 /* Make sure it's aligned to 64 bits. This will make atomic operations
637 * faster on 32 bit platforms.
639 uint64_t u64
__attribute__ ((aligned (8)));
642 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
644 struct anv_block_state
{
650 /* Make sure it's aligned to 64 bits. This will make atomic operations
651 * faster on 32 bit platforms.
653 uint64_t u64
__attribute__ ((aligned (8)));
657 #define anv_block_pool_foreach_bo(bo, pool) \
658 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
660 #define ANV_MAX_BLOCK_POOL_BOS 20
662 struct anv_block_pool
{
663 struct anv_device
*device
;
667 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
673 /* The address where the start of the pool is pinned. The various bos that
674 * are created as the pool grows will have addresses in the range
675 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
677 uint64_t start_address
;
679 /* The offset from the start of the bo to the "center" of the block
680 * pool. Pointers to allocated blocks are given by
681 * bo.map + center_bo_offset + offsets.
683 uint32_t center_bo_offset
;
685 /* Current memory map of the block pool. This pointer may or may not
686 * point to the actual beginning of the block pool memory. If
687 * anv_block_pool_alloc_back has ever been called, then this pointer
688 * will point to the "center" position of the buffer and all offsets
689 * (negative or positive) given out by the block pool alloc functions
690 * will be valid relative to this pointer.
692 * In particular, map == bo.map + center_offset
694 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
695 * since it will handle the softpin case as well, where this points to NULL.
701 * Array of mmaps and gem handles owned by the block pool, reclaimed when
702 * the block pool is destroyed.
704 struct u_vector mmap_cleanups
;
706 struct anv_block_state state
;
708 struct anv_block_state back_state
;
711 /* Block pools are backed by a fixed-size 1GB memfd */
712 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
714 /* The center of the block pool is also the middle of the memfd. This may
715 * change in the future if we decide differently for some reason.
717 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
719 static inline uint32_t
720 anv_block_pool_size(struct anv_block_pool
*pool
)
722 return pool
->state
.end
+ pool
->back_state
.end
;
732 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
734 struct anv_fixed_size_state_pool
{
735 union anv_free_list free_list
;
736 struct anv_block_state block
;
739 #define ANV_MIN_STATE_SIZE_LOG2 6
740 #define ANV_MAX_STATE_SIZE_LOG2 21
742 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
744 struct anv_free_entry
{
746 struct anv_state state
;
749 struct anv_state_table
{
750 struct anv_device
*device
;
752 struct anv_free_entry
*map
;
754 struct anv_block_state state
;
755 struct u_vector cleanups
;
758 struct anv_state_pool
{
759 struct anv_block_pool block_pool
;
761 struct anv_state_table table
;
763 /* The size of blocks which will be allocated from the block pool */
766 /** Free list for "back" allocations */
767 union anv_free_list back_alloc_free_list
;
769 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
772 struct anv_state_stream_block
;
774 struct anv_state_stream
{
775 struct anv_state_pool
*state_pool
;
777 /* The size of blocks to allocate from the state pool */
780 /* Current block we're allocating from */
781 struct anv_state block
;
783 /* Offset into the current block at which to allocate the next state */
786 /* List of all blocks allocated from this pool */
787 struct anv_state_stream_block
*block_list
;
790 /* The block_pool functions exported for testing only. The block pool should
791 * only be used via a state pool (see below).
793 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
794 struct anv_device
*device
,
795 uint64_t start_address
,
796 uint32_t initial_size
,
798 void anv_block_pool_finish(struct anv_block_pool
*pool
);
799 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
800 uint32_t block_size
, uint32_t *padding
);
801 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
802 uint32_t block_size
);
803 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
805 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
806 struct anv_device
*device
,
807 uint64_t start_address
,
810 void anv_state_pool_finish(struct anv_state_pool
*pool
);
811 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
812 uint32_t state_size
, uint32_t alignment
);
813 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
814 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
815 void anv_state_stream_init(struct anv_state_stream
*stream
,
816 struct anv_state_pool
*state_pool
,
817 uint32_t block_size
);
818 void anv_state_stream_finish(struct anv_state_stream
*stream
);
819 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
820 uint32_t size
, uint32_t alignment
);
822 VkResult
anv_state_table_init(struct anv_state_table
*table
,
823 struct anv_device
*device
,
824 uint32_t initial_entries
);
825 void anv_state_table_finish(struct anv_state_table
*table
);
826 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
828 void anv_free_list_push(union anv_free_list
*list
,
829 struct anv_state_table
*table
,
830 uint32_t idx
, uint32_t count
);
831 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
832 struct anv_state_table
*table
);
835 static inline struct anv_state
*
836 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
838 return &table
->map
[idx
].state
;
841 * Implements a pool of re-usable BOs. The interface is identical to that
842 * of block_pool except that each block is its own BO.
845 struct anv_device
*device
;
852 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
854 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
855 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
857 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
859 struct anv_scratch_bo
{
864 struct anv_scratch_pool
{
865 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
866 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
869 void anv_scratch_pool_init(struct anv_device
*device
,
870 struct anv_scratch_pool
*pool
);
871 void anv_scratch_pool_finish(struct anv_device
*device
,
872 struct anv_scratch_pool
*pool
);
873 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
874 struct anv_scratch_pool
*pool
,
875 gl_shader_stage stage
,
876 unsigned per_thread_scratch
);
878 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
879 struct anv_bo_cache
{
880 struct hash_table
*bo_map
;
881 pthread_mutex_t mutex
;
884 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
885 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
886 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
887 struct anv_bo_cache
*cache
,
888 uint64_t size
, uint64_t bo_flags
,
890 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
891 struct anv_bo_cache
*cache
,
892 void *host_ptr
, uint32_t size
,
893 uint64_t bo_flags
, struct anv_bo
**bo_out
);
894 VkResult
anv_bo_cache_import(struct anv_device
*device
,
895 struct anv_bo_cache
*cache
,
896 int fd
, uint64_t bo_flags
,
898 VkResult
anv_bo_cache_export(struct anv_device
*device
,
899 struct anv_bo_cache
*cache
,
900 struct anv_bo
*bo_in
, int *fd_out
);
901 void anv_bo_cache_release(struct anv_device
*device
,
902 struct anv_bo_cache
*cache
,
905 struct anv_memory_type
{
906 /* Standard bits passed on to the client */
907 VkMemoryPropertyFlags propertyFlags
;
910 /* Driver-internal book-keeping */
911 VkBufferUsageFlags valid_buffer_usage
;
914 struct anv_memory_heap
{
915 /* Standard bits passed on to the client */
917 VkMemoryHeapFlags flags
;
919 /* Driver-internal book-keeping */
922 bool supports_48bit_addresses
;
926 struct anv_physical_device
{
927 VK_LOADER_DATA _loader_data
;
929 struct anv_instance
* instance
;
940 struct gen_device_info info
;
941 /** Amount of "GPU memory" we want to advertise
943 * Clearly, this value is bogus since Intel is a UMA architecture. On
944 * gen7 platforms, we are limited by GTT size unless we want to implement
945 * fine-grained tracking and GTT splitting. On Broadwell and above we are
946 * practically unlimited. However, we will never report more than 3/4 of
947 * the total system ram to try and avoid running out of RAM.
949 bool supports_48bit_addresses
;
950 struct brw_compiler
* compiler
;
951 struct isl_device isl_dev
;
952 struct gen_perf_config
* perf
;
953 int cmd_parser_version
;
955 bool has_exec_capture
;
958 bool has_syncobj_wait
;
959 bool has_context_priority
;
961 bool has_context_isolation
;
962 bool has_mem_available
;
963 bool always_use_bindless
;
965 /** True if we can access buffers using A64 messages */
966 bool has_a64_buffer_access
;
967 /** True if we can use bindless access for images */
968 bool has_bindless_images
;
969 /** True if we can use bindless access for samplers */
970 bool has_bindless_samplers
;
972 struct anv_device_extension_table supported_extensions
;
973 struct anv_physical_device_dispatch_table dispatch
;
976 uint32_t subslice_total
;
980 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
982 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
985 uint8_t driver_build_sha1
[20];
986 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
987 uint8_t driver_uuid
[VK_UUID_SIZE
];
988 uint8_t device_uuid
[VK_UUID_SIZE
];
990 struct disk_cache
* disk_cache
;
992 struct wsi_device wsi_device
;
997 struct anv_app_info
{
998 const char* app_name
;
999 uint32_t app_version
;
1000 const char* engine_name
;
1001 uint32_t engine_version
;
1002 uint32_t api_version
;
1005 struct anv_instance
{
1006 VK_LOADER_DATA _loader_data
;
1008 VkAllocationCallbacks alloc
;
1010 struct anv_app_info app_info
;
1012 struct anv_instance_extension_table enabled_extensions
;
1013 struct anv_instance_dispatch_table dispatch
;
1014 struct anv_device_dispatch_table device_dispatch
;
1016 int physicalDeviceCount
;
1017 struct anv_physical_device physicalDevice
;
1019 bool pipeline_cache_enabled
;
1021 struct vk_debug_report_instance debug_report_callbacks
;
1023 struct driOptionCache dri_options
;
1024 struct driOptionCache available_dri_options
;
1027 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1028 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1030 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1031 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1035 VK_LOADER_DATA _loader_data
;
1037 struct anv_device
* device
;
1039 VkDeviceQueueCreateFlags flags
;
1042 struct anv_pipeline_cache
{
1043 struct anv_device
* device
;
1044 pthread_mutex_t mutex
;
1046 struct hash_table
* nir_cache
;
1048 struct hash_table
* cache
;
1051 struct nir_xfb_info
;
1052 struct anv_pipeline_bind_map
;
1054 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1055 struct anv_device
*device
,
1056 bool cache_enabled
);
1057 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1059 struct anv_shader_bin
*
1060 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1061 const void *key
, uint32_t key_size
);
1062 struct anv_shader_bin
*
1063 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1064 const void *key_data
, uint32_t key_size
,
1065 const void *kernel_data
, uint32_t kernel_size
,
1066 const void *constant_data
,
1067 uint32_t constant_data_size
,
1068 const struct brw_stage_prog_data
*prog_data
,
1069 uint32_t prog_data_size
,
1070 const struct brw_compile_stats
*stats
,
1072 const struct nir_xfb_info
*xfb_info
,
1073 const struct anv_pipeline_bind_map
*bind_map
);
1075 struct anv_shader_bin
*
1076 anv_device_search_for_kernel(struct anv_device
*device
,
1077 struct anv_pipeline_cache
*cache
,
1078 const void *key_data
, uint32_t key_size
,
1079 bool *user_cache_bit
);
1081 struct anv_shader_bin
*
1082 anv_device_upload_kernel(struct anv_device
*device
,
1083 struct anv_pipeline_cache
*cache
,
1084 const void *key_data
, uint32_t key_size
,
1085 const void *kernel_data
, uint32_t kernel_size
,
1086 const void *constant_data
,
1087 uint32_t constant_data_size
,
1088 const struct brw_stage_prog_data
*prog_data
,
1089 uint32_t prog_data_size
,
1090 const struct brw_compile_stats
*stats
,
1092 const struct nir_xfb_info
*xfb_info
,
1093 const struct anv_pipeline_bind_map
*bind_map
);
1096 struct nir_shader_compiler_options
;
1099 anv_device_search_for_nir(struct anv_device
*device
,
1100 struct anv_pipeline_cache
*cache
,
1101 const struct nir_shader_compiler_options
*nir_options
,
1102 unsigned char sha1_key
[20],
1106 anv_device_upload_nir(struct anv_device
*device
,
1107 struct anv_pipeline_cache
*cache
,
1108 const struct nir_shader
*nir
,
1109 unsigned char sha1_key
[20]);
1112 VK_LOADER_DATA _loader_data
;
1114 VkAllocationCallbacks alloc
;
1116 struct anv_instance
* instance
;
1117 uint32_t chipset_id
;
1119 struct gen_device_info info
;
1120 struct isl_device isl_dev
;
1123 bool can_chain_batches
;
1124 bool robust_buffer_access
;
1125 struct anv_device_extension_table enabled_extensions
;
1126 struct anv_device_dispatch_table dispatch
;
1128 pthread_mutex_t vma_mutex
;
1129 struct util_vma_heap vma_lo
;
1130 struct util_vma_heap vma_hi
;
1131 uint64_t vma_lo_available
;
1132 uint64_t vma_hi_available
;
1134 /** List of all anv_device_memory objects */
1135 struct list_head memory_objects
;
1137 struct anv_bo_pool batch_bo_pool
;
1139 struct anv_bo_cache bo_cache
;
1141 struct anv_state_pool dynamic_state_pool
;
1142 struct anv_state_pool instruction_state_pool
;
1143 struct anv_state_pool binding_table_pool
;
1144 struct anv_state_pool surface_state_pool
;
1146 struct anv_bo workaround_bo
;
1147 struct anv_bo trivial_batch_bo
;
1148 struct anv_bo hiz_clear_bo
;
1150 struct anv_pipeline_cache default_pipeline_cache
;
1151 struct blorp_context blorp
;
1153 struct anv_state border_colors
;
1155 struct anv_state slice_hash
;
1157 struct anv_queue queue
;
1159 struct anv_scratch_pool scratch_pool
;
1161 uint32_t default_mocs
;
1162 uint32_t external_mocs
;
1164 pthread_mutex_t mutex
;
1165 pthread_cond_t queue_submit
;
1168 struct gen_batch_decode_ctx decoder_ctx
;
1170 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1171 * the cmd_buffer's list.
1173 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1175 int perf_fd
; /* -1 if no opened */
1176 uint64_t perf_metric
; /* 0 if unset */
1179 static inline struct anv_state_pool
*
1180 anv_binding_table_pool(struct anv_device
*device
)
1182 if (device
->instance
->physicalDevice
.use_softpin
)
1183 return &device
->binding_table_pool
;
1185 return &device
->surface_state_pool
;
1188 static inline struct anv_state
1189 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1190 if (device
->instance
->physicalDevice
.use_softpin
)
1191 return anv_state_pool_alloc(&device
->binding_table_pool
,
1192 device
->binding_table_pool
.block_size
, 0);
1194 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1198 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1199 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1202 static inline uint32_t
1203 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1205 if (bo
->flags
& ANV_BO_EXTERNAL
)
1206 return device
->external_mocs
;
1208 return device
->default_mocs
;
1211 void anv_device_init_blorp(struct anv_device
*device
);
1212 void anv_device_finish_blorp(struct anv_device
*device
);
1214 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1215 const char *file
, int line
,
1216 const char *msg
, ...);
1217 #define anv_device_set_lost(dev, ...) \
1218 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1221 anv_device_is_lost(struct anv_device
*device
)
1223 return unlikely(device
->_lost
);
1226 VkResult
anv_device_execbuf(struct anv_device
*device
,
1227 struct drm_i915_gem_execbuffer2
*execbuf
,
1228 struct anv_bo
**execbuf_bos
);
1229 VkResult
anv_device_query_status(struct anv_device
*device
);
1230 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1231 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1234 void* anv_gem_mmap(struct anv_device
*device
,
1235 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1236 void anv_gem_munmap(void *p
, uint64_t size
);
1237 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1238 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1239 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1240 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1241 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1242 int anv_gem_execbuffer(struct anv_device
*device
,
1243 struct drm_i915_gem_execbuffer2
*execbuf
);
1244 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1245 uint32_t stride
, uint32_t tiling
);
1246 int anv_gem_create_context(struct anv_device
*device
);
1247 bool anv_gem_has_context_priority(int fd
);
1248 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1249 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1251 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1253 int anv_gem_get_param(int fd
, uint32_t param
);
1254 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1255 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1256 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1257 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1258 uint32_t *active
, uint32_t *pending
);
1259 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1260 int anv_gem_reg_read(struct anv_device
*device
,
1261 uint32_t offset
, uint64_t *result
);
1262 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1263 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1264 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1265 uint32_t read_domains
, uint32_t write_domain
);
1266 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1267 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1268 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1269 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1270 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1271 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1273 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1274 uint32_t handle
, int fd
);
1275 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1276 bool anv_gem_supports_syncobj_wait(int fd
);
1277 int anv_gem_syncobj_wait(struct anv_device
*device
,
1278 uint32_t *handles
, uint32_t num_handles
,
1279 int64_t abs_timeout_ns
, bool wait_all
);
1281 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1282 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1284 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1286 struct anv_reloc_list
{
1287 uint32_t num_relocs
;
1288 uint32_t array_length
;
1289 struct drm_i915_gem_relocation_entry
* relocs
;
1290 struct anv_bo
** reloc_bos
;
1294 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1295 const VkAllocationCallbacks
*alloc
);
1296 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1297 const VkAllocationCallbacks
*alloc
);
1299 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1300 const VkAllocationCallbacks
*alloc
,
1301 uint32_t offset
, struct anv_bo
*target_bo
,
1304 struct anv_batch_bo
{
1305 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1306 struct list_head link
;
1310 /* Bytes actually consumed in this batch BO */
1313 struct anv_reloc_list relocs
;
1317 const VkAllocationCallbacks
* alloc
;
1323 struct anv_reloc_list
* relocs
;
1325 /* This callback is called (with the associated user data) in the event
1326 * that the batch runs out of space.
1328 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1332 * Current error status of the command buffer. Used to track inconsistent
1333 * or incomplete command buffer states that are the consequence of run-time
1334 * errors such as out of memory scenarios. We want to track this in the
1335 * batch because the command buffer object is not visible to some parts
1341 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1342 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1343 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1344 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1345 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1346 struct anv_batch
*batch
);
1348 static inline VkResult
1349 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1351 assert(error
!= VK_SUCCESS
);
1352 if (batch
->status
== VK_SUCCESS
)
1353 batch
->status
= error
;
1354 return batch
->status
;
1358 anv_batch_has_error(struct anv_batch
*batch
)
1360 return batch
->status
!= VK_SUCCESS
;
1363 struct anv_address
{
1368 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1371 anv_address_is_null(struct anv_address addr
)
1373 return addr
.bo
== NULL
&& addr
.offset
== 0;
1376 static inline uint64_t
1377 anv_address_physical(struct anv_address addr
)
1379 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1380 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1382 return gen_canonical_address(addr
.offset
);
1385 static inline struct anv_address
1386 anv_address_add(struct anv_address addr
, uint64_t offset
)
1388 addr
.offset
+= offset
;
1393 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1395 unsigned reloc_size
= 0;
1396 if (device
->info
.gen
>= 8) {
1397 reloc_size
= sizeof(uint64_t);
1398 *(uint64_t *)p
= gen_canonical_address(v
);
1400 reloc_size
= sizeof(uint32_t);
1404 if (flush
&& !device
->info
.has_llc
)
1405 gen_flush_range(p
, reloc_size
);
1408 static inline uint64_t
1409 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1410 const struct anv_address address
, uint32_t delta
)
1412 if (address
.bo
== NULL
) {
1413 return address
.offset
+ delta
;
1415 assert(batch
->start
<= location
&& location
< batch
->end
);
1417 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1421 #define __gen_address_type struct anv_address
1422 #define __gen_user_data struct anv_batch
1423 #define __gen_combine_address _anv_combine_address
1425 /* Wrapper macros needed to work around preprocessor argument issues. In
1426 * particular, arguments don't get pre-evaluated if they are concatenated.
1427 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1428 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1429 * We can work around this easily enough with these helpers.
1431 #define __anv_cmd_length(cmd) cmd ## _length
1432 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1433 #define __anv_cmd_header(cmd) cmd ## _header
1434 #define __anv_cmd_pack(cmd) cmd ## _pack
1435 #define __anv_reg_num(reg) reg ## _num
1437 #define anv_pack_struct(dst, struc, ...) do { \
1438 struct struc __template = { \
1441 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1442 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1445 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1446 void *__dst = anv_batch_emit_dwords(batch, n); \
1448 struct cmd __template = { \
1449 __anv_cmd_header(cmd), \
1450 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1453 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1458 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1462 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1463 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1466 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1467 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1468 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1471 #define anv_batch_emit(batch, cmd, name) \
1472 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1473 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1474 __builtin_expect(_dst != NULL, 1); \
1475 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1476 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1480 /* MEMORY_OBJECT_CONTROL_STATE:
1481 * .GraphicsDataTypeGFDT = 0,
1482 * .LLCCacheabilityControlLLCCC = 0,
1483 * .L3CacheabilityControlL3CC = 1,
1487 /* MEMORY_OBJECT_CONTROL_STATE:
1488 * .LLCeLLCCacheabilityControlLLCCC = 0,
1489 * .L3CacheabilityControlL3CC = 1,
1491 #define GEN75_MOCS 1
1493 /* MEMORY_OBJECT_CONTROL_STATE:
1494 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1495 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1496 * .AgeforQUADLRU = 0
1498 #define GEN8_MOCS 0x78
1500 /* MEMORY_OBJECT_CONTROL_STATE:
1501 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1502 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1503 * .AgeforQUADLRU = 0
1505 #define GEN8_EXTERNAL_MOCS 0x18
1507 /* Skylake: MOCS is now an index into an array of 62 different caching
1508 * configurations programmed by the kernel.
1511 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1512 #define GEN9_MOCS (2 << 1)
1514 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1515 #define GEN9_EXTERNAL_MOCS (1 << 1)
1517 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1518 #define GEN10_MOCS GEN9_MOCS
1519 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1521 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1522 #define GEN11_MOCS GEN9_MOCS
1523 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1525 /* TigerLake MOCS */
1526 #define GEN12_MOCS GEN9_MOCS
1527 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1528 #define GEN12_EXTERNAL_MOCS (3 << 1)
1530 struct anv_device_memory
{
1531 struct list_head link
;
1534 struct anv_memory_type
* type
;
1535 VkDeviceSize map_size
;
1538 /* If set, we are holding reference to AHardwareBuffer
1539 * which we must release when memory is freed.
1541 struct AHardwareBuffer
* ahw
;
1543 /* If set, this memory comes from a host pointer. */
1548 * Header for Vertex URB Entry (VUE)
1550 struct anv_vue_header
{
1552 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1553 uint32_t ViewportIndex
;
1557 /** Struct representing a sampled image descriptor
1559 * This descriptor layout is used for sampled images, bare sampler, and
1560 * combined image/sampler descriptors.
1562 struct anv_sampled_image_descriptor
{
1563 /** Bindless image handle
1565 * This is expected to already be shifted such that the 20-bit
1566 * SURFACE_STATE table index is in the top 20 bits.
1570 /** Bindless sampler handle
1572 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1573 * to the dynamic state base address.
1578 struct anv_texture_swizzle_descriptor
{
1581 * See also nir_intrinsic_channel_select_intel
1585 /** Unused padding to ensure the struct is a multiple of 64 bits */
1589 /** Struct representing a storage image descriptor */
1590 struct anv_storage_image_descriptor
{
1591 /** Bindless image handles
1593 * These are expected to already be shifted such that the 20-bit
1594 * SURFACE_STATE table index is in the top 20 bits.
1596 uint32_t read_write
;
1597 uint32_t write_only
;
1600 /** Struct representing a address/range descriptor
1602 * The fields of this struct correspond directly to the data layout of
1603 * nir_address_format_64bit_bounded_global addresses. The last field is the
1604 * offset in the NIR address so it must be zero so that when you load the
1605 * descriptor you get a pointer to the start of the range.
1607 struct anv_address_range_descriptor
{
1613 enum anv_descriptor_data
{
1614 /** The descriptor contains a BTI reference to a surface state */
1615 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1616 /** The descriptor contains a BTI reference to a sampler state */
1617 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1618 /** The descriptor contains an actual buffer view */
1619 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1620 /** The descriptor contains auxiliary image layout data */
1621 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1622 /** The descriptor contains auxiliary image layout data */
1623 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1624 /** anv_address_range_descriptor with a buffer address and range */
1625 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1626 /** Bindless surface handle */
1627 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1628 /** Storage image handles */
1629 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1630 /** Storage image handles */
1631 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1634 struct anv_descriptor_set_binding_layout
{
1636 /* The type of the descriptors in this binding */
1637 VkDescriptorType type
;
1640 /* Flags provided when this binding was created */
1641 VkDescriptorBindingFlagsEXT flags
;
1643 /* Bitfield representing the type of data this descriptor contains */
1644 enum anv_descriptor_data data
;
1646 /* Maximum number of YCbCr texture/sampler planes */
1647 uint8_t max_plane_count
;
1649 /* Number of array elements in this binding (or size in bytes for inline
1652 uint16_t array_size
;
1654 /* Index into the flattend descriptor set */
1655 uint16_t descriptor_index
;
1657 /* Index into the dynamic state array for a dynamic buffer */
1658 int16_t dynamic_offset_index
;
1660 /* Index into the descriptor set buffer views */
1661 int16_t buffer_view_index
;
1663 /* Offset into the descriptor buffer where this descriptor lives */
1664 uint32_t descriptor_offset
;
1666 /* Immutable samplers (or NULL if no immutable samplers) */
1667 struct anv_sampler
**immutable_samplers
;
1670 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1672 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1673 VkDescriptorType type
);
1675 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1676 const struct anv_descriptor_set_binding_layout
*binding
,
1679 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1680 const struct anv_descriptor_set_binding_layout
*binding
,
1683 struct anv_descriptor_set_layout
{
1684 /* Descriptor set layouts can be destroyed at almost any time */
1687 /* Number of bindings in this descriptor set */
1688 uint16_t binding_count
;
1690 /* Total size of the descriptor set with room for all array entries */
1693 /* Shader stages affected by this descriptor set */
1694 uint16_t shader_stages
;
1696 /* Number of buffer views in this descriptor set */
1697 uint16_t buffer_view_count
;
1699 /* Number of dynamic offsets used by this descriptor set */
1700 uint16_t dynamic_offset_count
;
1702 /* Size of the descriptor buffer for this descriptor set */
1703 uint32_t descriptor_buffer_size
;
1705 /* Bindings in this descriptor set */
1706 struct anv_descriptor_set_binding_layout binding
[0];
1710 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1712 assert(layout
&& layout
->ref_cnt
>= 1);
1713 p_atomic_inc(&layout
->ref_cnt
);
1717 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1718 struct anv_descriptor_set_layout
*layout
)
1720 assert(layout
&& layout
->ref_cnt
>= 1);
1721 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1722 vk_free(&device
->alloc
, layout
);
1725 struct anv_descriptor
{
1726 VkDescriptorType type
;
1730 VkImageLayout layout
;
1731 struct anv_image_view
*image_view
;
1732 struct anv_sampler
*sampler
;
1736 struct anv_buffer
*buffer
;
1741 struct anv_buffer_view
*buffer_view
;
1745 struct anv_descriptor_set
{
1746 struct anv_descriptor_pool
*pool
;
1747 struct anv_descriptor_set_layout
*layout
;
1750 /* State relative to anv_descriptor_pool::bo */
1751 struct anv_state desc_mem
;
1752 /* Surface state for the descriptor buffer */
1753 struct anv_state desc_surface_state
;
1755 uint32_t buffer_view_count
;
1756 struct anv_buffer_view
*buffer_views
;
1758 /* Link to descriptor pool's desc_sets list . */
1759 struct list_head pool_link
;
1761 struct anv_descriptor descriptors
[0];
1764 struct anv_buffer_view
{
1765 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1766 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1768 struct anv_address address
;
1770 struct anv_state surface_state
;
1771 struct anv_state storage_surface_state
;
1772 struct anv_state writeonly_storage_surface_state
;
1774 struct brw_image_param storage_image_param
;
1777 struct anv_push_descriptor_set
{
1778 struct anv_descriptor_set set
;
1780 /* Put this field right behind anv_descriptor_set so it fills up the
1781 * descriptors[0] field. */
1782 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1784 /** True if the descriptor set buffer has been referenced by a draw or
1787 bool set_used_on_gpu
;
1789 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1792 struct anv_descriptor_pool
{
1798 struct util_vma_heap bo_heap
;
1800 struct anv_state_stream surface_state_stream
;
1801 void *surface_state_free_list
;
1803 struct list_head desc_sets
;
1808 enum anv_descriptor_template_entry_type
{
1809 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1810 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1811 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1814 struct anv_descriptor_template_entry
{
1815 /* The type of descriptor in this entry */
1816 VkDescriptorType type
;
1818 /* Binding in the descriptor set */
1821 /* Offset at which to write into the descriptor set binding */
1822 uint32_t array_element
;
1824 /* Number of elements to write into the descriptor set binding */
1825 uint32_t array_count
;
1827 /* Offset into the user provided data */
1830 /* Stride between elements into the user provided data */
1834 struct anv_descriptor_update_template
{
1835 VkPipelineBindPoint bind_point
;
1837 /* The descriptor set this template corresponds to. This value is only
1838 * valid if the template was created with the templateType
1839 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1843 /* Number of entries in this template */
1844 uint32_t entry_count
;
1846 /* Entries of the template */
1847 struct anv_descriptor_template_entry entries
[0];
1851 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1854 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1855 struct anv_descriptor_set
*set
,
1856 const VkDescriptorImageInfo
* const info
,
1857 VkDescriptorType type
,
1862 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1863 struct anv_descriptor_set
*set
,
1864 VkDescriptorType type
,
1865 struct anv_buffer_view
*buffer_view
,
1870 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1871 struct anv_descriptor_set
*set
,
1872 struct anv_state_stream
*alloc_stream
,
1873 VkDescriptorType type
,
1874 struct anv_buffer
*buffer
,
1877 VkDeviceSize offset
,
1878 VkDeviceSize range
);
1880 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1881 struct anv_descriptor_set
*set
,
1888 anv_descriptor_set_write_template(struct anv_device
*device
,
1889 struct anv_descriptor_set
*set
,
1890 struct anv_state_stream
*alloc_stream
,
1891 const struct anv_descriptor_update_template
*template,
1895 anv_descriptor_set_create(struct anv_device
*device
,
1896 struct anv_descriptor_pool
*pool
,
1897 struct anv_descriptor_set_layout
*layout
,
1898 struct anv_descriptor_set
**out_set
);
1901 anv_descriptor_set_destroy(struct anv_device
*device
,
1902 struct anv_descriptor_pool
*pool
,
1903 struct anv_descriptor_set
*set
);
1905 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1906 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1907 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1908 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1910 struct anv_pipeline_binding
{
1911 /* The descriptor set this surface corresponds to. The special value of
1912 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1913 * to a color attachment and not a regular descriptor.
1917 /* Binding in the descriptor set */
1920 /* Index in the binding */
1923 /* Plane in the binding index */
1926 /* Input attachment index (relative to the subpass) */
1927 uint8_t input_attachment_index
;
1929 /* For a storage image, whether it is write-only */
1933 struct anv_pipeline_layout
{
1935 struct anv_descriptor_set_layout
*layout
;
1936 uint32_t dynamic_offset_start
;
1941 unsigned char sha1
[20];
1945 struct anv_device
* device
;
1948 VkBufferUsageFlags usage
;
1950 /* Set when bound */
1951 struct anv_address address
;
1954 static inline uint64_t
1955 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1957 assert(offset
<= buffer
->size
);
1958 if (range
== VK_WHOLE_SIZE
) {
1959 return buffer
->size
- offset
;
1961 assert(range
+ offset
>= range
);
1962 assert(range
+ offset
<= buffer
->size
);
1967 enum anv_cmd_dirty_bits
{
1968 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1969 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1970 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1971 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1972 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1973 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1974 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1975 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1976 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1977 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1978 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1979 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1980 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1981 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
1983 typedef uint32_t anv_cmd_dirty_mask_t
;
1985 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
1986 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
1987 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
1988 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
1989 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
1990 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
1991 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
1992 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
1993 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
1994 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
1995 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
1997 static inline enum anv_cmd_dirty_bits
1998 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2001 case VK_DYNAMIC_STATE_VIEWPORT
:
2002 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2003 case VK_DYNAMIC_STATE_SCISSOR
:
2004 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2005 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2006 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2007 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2008 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2009 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2010 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2011 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2012 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2013 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2014 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2015 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2016 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2017 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2018 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2019 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2020 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2022 assert(!"Unsupported dynamic state");
2028 enum anv_pipe_bits
{
2029 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2030 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2031 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2032 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2033 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2034 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2035 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2036 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2037 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2038 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2039 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2041 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2042 * a flush has happened but not a CS stall. The next time we do any sort
2043 * of invalidation we need to insert a CS stall at that time. Otherwise,
2044 * we would have to CS stall on every flush which could be bad.
2046 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2048 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2049 * target operations related to transfer commands with VkBuffer as
2050 * destination are ongoing. Some operations like copies on the command
2051 * streamer might need to be aware of this to trigger the appropriate stall
2052 * before they can proceed with the copy.
2054 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2057 #define ANV_PIPE_FLUSH_BITS ( \
2058 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2059 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2060 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
2062 #define ANV_PIPE_STALL_BITS ( \
2063 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2064 ANV_PIPE_DEPTH_STALL_BIT | \
2065 ANV_PIPE_CS_STALL_BIT)
2067 #define ANV_PIPE_INVALIDATE_BITS ( \
2068 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2069 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2070 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2071 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2072 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2073 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2075 static inline enum anv_pipe_bits
2076 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2078 enum anv_pipe_bits pipe_bits
= 0;
2081 for_each_bit(b
, flags
) {
2082 switch ((VkAccessFlagBits
)(1 << b
)) {
2083 case VK_ACCESS_SHADER_WRITE_BIT
:
2084 /* We're transitioning a buffer that was previously used as write
2085 * destination through the data port. To make its content available
2086 * to future operations, flush the data cache.
2088 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2090 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2091 /* We're transitioning a buffer that was previously used as render
2092 * target. To make its content available to future operations, flush
2093 * the render target cache.
2095 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2097 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2098 /* We're transitioning a buffer that was previously used as depth
2099 * buffer. To make its content available to future operations, flush
2102 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2104 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2105 /* We're transitioning a buffer that was previously used as a
2106 * transfer write destination. Generic write operations include color
2107 * & depth operations as well as buffer operations like :
2108 * - vkCmdClearColorImage()
2109 * - vkCmdClearDepthStencilImage()
2110 * - vkCmdBlitImage()
2111 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2113 * Most of these operations are implemented using Blorp which writes
2114 * through the render target, so flush that cache to make it visible
2115 * to future operations. And for depth related operations we also
2116 * need to flush the depth cache.
2118 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2119 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2121 case VK_ACCESS_MEMORY_WRITE_BIT
:
2122 /* We're transitioning a buffer for generic write operations. Flush
2125 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2128 break; /* Nothing to do */
2135 static inline enum anv_pipe_bits
2136 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2138 enum anv_pipe_bits pipe_bits
= 0;
2141 for_each_bit(b
, flags
) {
2142 switch ((VkAccessFlagBits
)(1 << b
)) {
2143 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2144 /* Indirect draw commands take a buffer as input that we're going to
2145 * read from the command streamer to load some of the HW registers
2146 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2147 * command streamer stall so that all the cache flushes have
2148 * completed before the command streamer loads from memory.
2150 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2151 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2152 * through a vertex buffer, so invalidate that cache.
2154 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2155 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2156 * UBO from the buffer, so we need to invalidate constant cache.
2158 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2160 case VK_ACCESS_INDEX_READ_BIT
:
2161 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2162 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2163 * commands, so we invalidate the VF cache to make sure there is no
2164 * stale data when we start rendering.
2166 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2168 case VK_ACCESS_UNIFORM_READ_BIT
:
2169 /* We transitioning a buffer to be used as uniform data. Because
2170 * uniform is accessed through the data port & sampler, we need to
2171 * invalidate the texture cache (sampler) & constant cache (data
2172 * port) to avoid stale data.
2174 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2175 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2177 case VK_ACCESS_SHADER_READ_BIT
:
2178 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2179 case VK_ACCESS_TRANSFER_READ_BIT
:
2180 /* Transitioning a buffer to be read through the sampler, so
2181 * invalidate the texture cache, we don't want any stale data.
2183 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2185 case VK_ACCESS_MEMORY_READ_BIT
:
2186 /* Transitioning a buffer for generic read, invalidate all the
2189 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2191 case VK_ACCESS_MEMORY_WRITE_BIT
:
2192 /* Generic write, make sure all previously written things land in
2195 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2197 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2198 /* Transitioning a buffer for conditional rendering. We'll load the
2199 * content of this buffer into HW registers using the command
2200 * streamer, so we need to stall the command streamer to make sure
2201 * any in-flight flush operations have completed.
2203 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2206 break; /* Nothing to do */
2213 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2214 VK_IMAGE_ASPECT_COLOR_BIT | \
2215 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2216 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2217 VK_IMAGE_ASPECT_PLANE_2_BIT)
2218 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2219 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2220 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2221 VK_IMAGE_ASPECT_PLANE_2_BIT)
2223 struct anv_vertex_binding
{
2224 struct anv_buffer
* buffer
;
2225 VkDeviceSize offset
;
2228 struct anv_xfb_binding
{
2229 struct anv_buffer
* buffer
;
2230 VkDeviceSize offset
;
2234 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2235 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2236 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2238 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2239 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2240 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2242 struct anv_push_constants
{
2243 /* Push constant data provided by the client through vkPushConstants */
2244 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2246 /* Used for vkCmdDispatchBase */
2247 uint32_t base_work_group_id
[3];
2250 struct anv_dynamic_state
{
2253 VkViewport viewports
[MAX_VIEWPORTS
];
2258 VkRect2D scissors
[MAX_SCISSORS
];
2269 float blend_constants
[4];
2279 } stencil_compare_mask
;
2284 } stencil_write_mask
;
2289 } stencil_reference
;
2297 extern const struct anv_dynamic_state default_dynamic_state
;
2299 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2300 const struct anv_dynamic_state
*src
,
2301 uint32_t copy_mask
);
2303 struct anv_surface_state
{
2304 struct anv_state state
;
2305 /** Address of the surface referred to by this state
2307 * This address is relative to the start of the BO.
2309 struct anv_address address
;
2310 /* Address of the aux surface, if any
2312 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2314 * With the exception of gen8, the bottom 12 bits of this address' offset
2315 * include extra aux information.
2317 struct anv_address aux_address
;
2318 /* Address of the clear color, if any
2320 * This address is relative to the start of the BO.
2322 struct anv_address clear_address
;
2326 * Attachment state when recording a renderpass instance.
2328 * The clear value is valid only if there exists a pending clear.
2330 struct anv_attachment_state
{
2331 enum isl_aux_usage aux_usage
;
2332 enum isl_aux_usage input_aux_usage
;
2333 struct anv_surface_state color
;
2334 struct anv_surface_state input
;
2336 VkImageLayout current_layout
;
2337 VkImageAspectFlags pending_clear_aspects
;
2338 VkImageAspectFlags pending_load_aspects
;
2340 VkClearValue clear_value
;
2341 bool clear_color_is_zero_one
;
2342 bool clear_color_is_zero
;
2344 /* When multiview is active, attachments with a renderpass clear
2345 * operation have their respective layers cleared on the first
2346 * subpass that uses them, and only in that subpass. We keep track
2347 * of this using a bitfield to indicate which layers of an attachment
2348 * have not been cleared yet when multiview is active.
2350 uint32_t pending_clear_views
;
2351 struct anv_image_view
* image_view
;
2354 /** State tracking for particular pipeline bind point
2356 * This struct is the base struct for anv_cmd_graphics_state and
2357 * anv_cmd_compute_state. These are used to track state which is bound to a
2358 * particular type of pipeline. Generic state that applies per-stage such as
2359 * binding table offsets and push constants is tracked generically with a
2360 * per-stage array in anv_cmd_state.
2362 struct anv_cmd_pipeline_state
{
2363 struct anv_pipeline
*pipeline
;
2364 struct anv_pipeline_layout
*layout
;
2366 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2367 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2369 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2372 /** State tracking for graphics pipeline
2374 * This has anv_cmd_pipeline_state as a base struct to track things which get
2375 * bound to a graphics pipeline. Along with general pipeline bind point state
2376 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2377 * state which is graphics-specific.
2379 struct anv_cmd_graphics_state
{
2380 struct anv_cmd_pipeline_state base
;
2382 anv_cmd_dirty_mask_t dirty
;
2385 struct anv_dynamic_state dynamic
;
2388 struct anv_buffer
*index_buffer
;
2389 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2390 uint32_t index_offset
;
2394 /** State tracking for compute pipeline
2396 * This has anv_cmd_pipeline_state as a base struct to track things which get
2397 * bound to a compute pipeline. Along with general pipeline bind point state
2398 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2399 * state which is compute-specific.
2401 struct anv_cmd_compute_state
{
2402 struct anv_cmd_pipeline_state base
;
2404 bool pipeline_dirty
;
2406 struct anv_address num_workgroups
;
2409 /** State required while building cmd buffer */
2410 struct anv_cmd_state
{
2411 /* PIPELINE_SELECT.PipelineSelection */
2412 uint32_t current_pipeline
;
2413 const struct gen_l3_config
* current_l3_config
;
2415 struct anv_cmd_graphics_state gfx
;
2416 struct anv_cmd_compute_state compute
;
2418 enum anv_pipe_bits pending_pipe_bits
;
2419 VkShaderStageFlags descriptors_dirty
;
2420 VkShaderStageFlags push_constants_dirty
;
2422 struct anv_framebuffer
* framebuffer
;
2423 struct anv_render_pass
* pass
;
2424 struct anv_subpass
* subpass
;
2425 VkRect2D render_area
;
2426 uint32_t restart_index
;
2427 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2429 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2430 VkShaderStageFlags push_constant_stages
;
2431 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2432 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2433 struct anv_state samplers
[MESA_SHADER_STAGES
];
2436 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2437 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2438 * and before invoking the secondary in ExecuteCommands.
2440 bool pma_fix_enabled
;
2443 * Whether or not we know for certain that HiZ is enabled for the current
2444 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2445 * enabled or not, this will be false.
2449 bool conditional_render_enabled
;
2452 * Last rendering scale argument provided to
2453 * genX(cmd_buffer_emit_hashing_mode)().
2455 unsigned current_hash_scale
;
2458 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2459 * valid only when recording a render pass instance.
2461 struct anv_attachment_state
* attachments
;
2464 * Surface states for color render targets. These are stored in a single
2465 * flat array. For depth-stencil attachments, the surface state is simply
2468 struct anv_state render_pass_states
;
2471 * A null surface state of the right size to match the framebuffer. This
2472 * is one of the states in render_pass_states.
2474 struct anv_state null_surface_state
;
2477 struct anv_cmd_pool
{
2478 VkAllocationCallbacks alloc
;
2479 struct list_head cmd_buffers
;
2482 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2484 enum anv_cmd_buffer_exec_mode
{
2485 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2486 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2487 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2488 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2489 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2492 struct anv_cmd_buffer
{
2493 VK_LOADER_DATA _loader_data
;
2495 struct anv_device
* device
;
2497 struct anv_cmd_pool
* pool
;
2498 struct list_head pool_link
;
2500 struct anv_batch batch
;
2502 /* Fields required for the actual chain of anv_batch_bo's.
2504 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2506 struct list_head batch_bos
;
2507 enum anv_cmd_buffer_exec_mode exec_mode
;
2509 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2510 * referenced by this command buffer
2512 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2514 struct u_vector seen_bbos
;
2516 /* A vector of int32_t's for every block of binding tables.
2518 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2520 struct u_vector bt_block_states
;
2523 struct anv_reloc_list surface_relocs
;
2524 /** Last seen surface state block pool center bo offset */
2525 uint32_t last_ss_pool_center
;
2527 /* Serial for tracking buffer completion */
2530 /* Stream objects for storing temporary data */
2531 struct anv_state_stream surface_state_stream
;
2532 struct anv_state_stream dynamic_state_stream
;
2534 VkCommandBufferUsageFlags usage_flags
;
2535 VkCommandBufferLevel level
;
2537 struct anv_cmd_state state
;
2539 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2540 uint64_t intel_perf_marker
;
2543 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2544 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2545 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2546 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2547 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2548 struct anv_cmd_buffer
*secondary
);
2549 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2550 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2551 struct anv_cmd_buffer
*cmd_buffer
,
2552 const VkSemaphore
*in_semaphores
,
2553 uint32_t num_in_semaphores
,
2554 const VkSemaphore
*out_semaphores
,
2555 uint32_t num_out_semaphores
,
2558 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2560 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2561 const void *data
, uint32_t size
, uint32_t alignment
);
2562 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2563 uint32_t *a
, uint32_t *b
,
2564 uint32_t dwords
, uint32_t alignment
);
2567 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2569 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2570 uint32_t entries
, uint32_t *state_offset
);
2572 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2574 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2575 uint32_t size
, uint32_t alignment
);
2578 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2580 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2581 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2582 bool depth_clamp_enable
);
2583 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2585 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2586 struct anv_render_pass
*pass
,
2587 struct anv_framebuffer
*framebuffer
,
2588 const VkClearValue
*clear_values
);
2590 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2593 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2594 gl_shader_stage stage
);
2596 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2598 const struct anv_image_view
*
2599 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2602 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2603 uint32_t num_entries
,
2604 uint32_t *state_offset
,
2605 struct anv_state
*bt_state
);
2607 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2609 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2611 enum anv_fence_type
{
2612 ANV_FENCE_TYPE_NONE
= 0,
2614 ANV_FENCE_TYPE_SYNCOBJ
,
2618 enum anv_bo_fence_state
{
2619 /** Indicates that this is a new (or newly reset fence) */
2620 ANV_BO_FENCE_STATE_RESET
,
2622 /** Indicates that this fence has been submitted to the GPU but is still
2623 * (as far as we know) in use by the GPU.
2625 ANV_BO_FENCE_STATE_SUBMITTED
,
2627 ANV_BO_FENCE_STATE_SIGNALED
,
2630 struct anv_fence_impl
{
2631 enum anv_fence_type type
;
2634 /** Fence implementation for BO fences
2636 * These fences use a BO and a set of CPU-tracked state flags. The BO
2637 * is added to the object list of the last execbuf call in a QueueSubmit
2638 * and is marked EXEC_WRITE. The state flags track when the BO has been
2639 * submitted to the kernel. We need to do this because Vulkan lets you
2640 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2641 * will say it's idle in this case.
2645 enum anv_bo_fence_state state
;
2648 /** DRM syncobj handle for syncobj-based fences */
2652 struct wsi_fence
*fence_wsi
;
2657 /* Permanent fence state. Every fence has some form of permanent state
2658 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2659 * cross-process fences) or it could just be a dummy for use internally.
2661 struct anv_fence_impl permanent
;
2663 /* Temporary fence state. A fence *may* have temporary state. That state
2664 * is added to the fence by an import operation and is reset back to
2665 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2666 * state cannot be signaled because the fence must already be signaled
2667 * before the temporary state can be exported from the fence in the other
2668 * process and imported here.
2670 struct anv_fence_impl temporary
;
2675 struct anv_state state
;
2678 enum anv_semaphore_type
{
2679 ANV_SEMAPHORE_TYPE_NONE
= 0,
2680 ANV_SEMAPHORE_TYPE_DUMMY
,
2681 ANV_SEMAPHORE_TYPE_BO
,
2682 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2683 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2686 struct anv_semaphore_impl
{
2687 enum anv_semaphore_type type
;
2690 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2691 * This BO will be added to the object list on any execbuf2 calls for
2692 * which this semaphore is used as a wait or signal fence. When used as
2693 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2697 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2698 * If the semaphore is in the unsignaled state due to either just being
2699 * created or because it has been used for a wait, fd will be -1.
2703 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2704 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2705 * import so we don't need to bother with a userspace cache.
2711 struct anv_semaphore
{
2712 /* Permanent semaphore state. Every semaphore has some form of permanent
2713 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2714 * (for cross-process semaphores0 or it could just be a dummy for use
2717 struct anv_semaphore_impl permanent
;
2719 /* Temporary semaphore state. A semaphore *may* have temporary state.
2720 * That state is added to the semaphore by an import operation and is reset
2721 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2722 * semaphore with temporary state cannot be signaled because the semaphore
2723 * must already be signaled before the temporary state can be exported from
2724 * the semaphore in the other process and imported here.
2726 struct anv_semaphore_impl temporary
;
2729 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2730 struct anv_semaphore
*semaphore
);
2732 struct anv_shader_module
{
2733 unsigned char sha1
[20];
2738 static inline gl_shader_stage
2739 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2741 assert(__builtin_popcount(vk_stage
) == 1);
2742 return ffs(vk_stage
) - 1;
2745 static inline VkShaderStageFlagBits
2746 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2748 return (1 << mesa_stage
);
2751 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2753 #define anv_foreach_stage(stage, stage_bits) \
2754 for (gl_shader_stage stage, \
2755 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2756 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2757 __tmp &= ~(1 << (stage)))
2759 struct anv_pipeline_bind_map
{
2760 uint32_t surface_count
;
2761 uint32_t sampler_count
;
2763 struct anv_pipeline_binding
* surface_to_descriptor
;
2764 struct anv_pipeline_binding
* sampler_to_descriptor
;
2767 struct anv_shader_bin_key
{
2772 struct anv_shader_bin
{
2775 const struct anv_shader_bin_key
*key
;
2777 struct anv_state kernel
;
2778 uint32_t kernel_size
;
2780 struct anv_state constant_data
;
2781 uint32_t constant_data_size
;
2783 const struct brw_stage_prog_data
*prog_data
;
2784 uint32_t prog_data_size
;
2786 struct brw_compile_stats stats
[3];
2789 struct nir_xfb_info
*xfb_info
;
2791 struct anv_pipeline_bind_map bind_map
;
2794 struct anv_shader_bin
*
2795 anv_shader_bin_create(struct anv_device
*device
,
2796 const void *key
, uint32_t key_size
,
2797 const void *kernel
, uint32_t kernel_size
,
2798 const void *constant_data
, uint32_t constant_data_size
,
2799 const struct brw_stage_prog_data
*prog_data
,
2800 uint32_t prog_data_size
, const void *prog_data_param
,
2801 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2802 const struct nir_xfb_info
*xfb_info
,
2803 const struct anv_pipeline_bind_map
*bind_map
);
2806 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2809 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2811 assert(shader
&& shader
->ref_cnt
>= 1);
2812 p_atomic_inc(&shader
->ref_cnt
);
2816 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2818 assert(shader
&& shader
->ref_cnt
>= 1);
2819 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2820 anv_shader_bin_destroy(device
, shader
);
2823 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2824 #define MAX_PIPELINE_EXECUTABLES 7
2826 struct anv_pipeline_executable
{
2827 gl_shader_stage stage
;
2829 struct brw_compile_stats stats
;
2835 struct anv_pipeline
{
2836 struct anv_device
* device
;
2837 struct anv_batch batch
;
2838 uint32_t batch_data
[512];
2839 struct anv_reloc_list batch_relocs
;
2840 anv_cmd_dirty_mask_t dynamic_state_mask
;
2841 struct anv_dynamic_state dynamic_state
;
2845 VkPipelineCreateFlags flags
;
2846 struct anv_subpass
* subpass
;
2848 bool needs_data_cache
;
2850 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2852 uint32_t num_executables
;
2853 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2856 const struct gen_l3_config
* l3_config
;
2857 uint32_t total_size
;
2860 VkShaderStageFlags active_stages
;
2861 struct anv_state blend_state
;
2864 struct anv_pipeline_vertex_binding
{
2867 uint32_t instance_divisor
;
2872 bool primitive_restart
;
2875 uint32_t cs_right_mask
;
2878 bool depth_test_enable
;
2879 bool writes_stencil
;
2880 bool stencil_test_enable
;
2881 bool depth_clamp_enable
;
2882 bool depth_clip_enable
;
2883 bool sample_shading_enable
;
2888 uint32_t depth_stencil_state
[3];
2894 uint32_t wm_depth_stencil
[3];
2898 uint32_t wm_depth_stencil
[4];
2901 uint32_t interface_descriptor_data
[8];
2905 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2906 gl_shader_stage stage
)
2908 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2911 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2912 static inline const struct brw_##prefix##_prog_data * \
2913 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2915 if (anv_pipeline_has_stage(pipeline, stage)) { \
2916 return (const struct brw_##prefix##_prog_data *) \
2917 pipeline->shaders[stage]->prog_data; \
2923 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2924 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2925 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2926 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2927 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2928 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2930 static inline const struct brw_vue_prog_data
*
2931 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2933 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2934 return &get_gs_prog_data(pipeline
)->base
;
2935 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2936 return &get_tes_prog_data(pipeline
)->base
;
2938 return &get_vs_prog_data(pipeline
)->base
;
2942 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2943 struct anv_pipeline_cache
*cache
,
2944 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2945 const VkAllocationCallbacks
*alloc
);
2948 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2949 struct anv_pipeline_cache
*cache
,
2950 const VkComputePipelineCreateInfo
*info
,
2951 const struct anv_shader_module
*module
,
2952 const char *entrypoint
,
2953 const VkSpecializationInfo
*spec_info
);
2955 struct anv_format_plane
{
2956 enum isl_format isl_format
:16;
2957 struct isl_swizzle swizzle
;
2959 /* Whether this plane contains chroma channels */
2962 /* For downscaling of YUV planes */
2963 uint8_t denominator_scales
[2];
2965 /* How to map sampled ycbcr planes to a single 4 component element. */
2966 struct isl_swizzle ycbcr_swizzle
;
2968 /* What aspect is associated to this plane */
2969 VkImageAspectFlags aspect
;
2974 struct anv_format_plane planes
[3];
2980 static inline uint32_t
2981 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2982 VkImageAspectFlags aspect_mask
)
2984 switch (aspect_mask
) {
2985 case VK_IMAGE_ASPECT_COLOR_BIT
:
2986 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2987 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2989 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2990 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2993 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2995 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2998 /* Purposefully assert with depth/stencil aspects. */
2999 unreachable("invalid image aspect");
3003 static inline VkImageAspectFlags
3004 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3007 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3008 if (util_bitcount(image_aspects
) > 1)
3009 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3010 return VK_IMAGE_ASPECT_COLOR_BIT
;
3012 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3013 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3014 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3015 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3018 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3019 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3021 const struct anv_format
*
3022 anv_get_format(VkFormat format
);
3024 static inline uint32_t
3025 anv_get_format_planes(VkFormat vk_format
)
3027 const struct anv_format
*format
= anv_get_format(vk_format
);
3029 return format
!= NULL
? format
->n_planes
: 0;
3032 struct anv_format_plane
3033 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3034 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3036 static inline enum isl_format
3037 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3038 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3040 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3043 static inline struct isl_swizzle
3044 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3046 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3047 * RGB as RGBA for texturing
3049 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3050 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3052 /* But it doesn't matter what we render to that channel */
3053 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3059 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3062 * Subsurface of an anv_image.
3064 struct anv_surface
{
3065 /** Valid only if isl_surf::size_B > 0. */
3066 struct isl_surf isl
;
3069 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3075 VkImageType type
; /**< VkImageCreateInfo::imageType */
3076 /* The original VkFormat provided by the client. This may not match any
3077 * of the actual surface formats.
3080 const struct anv_format
*format
;
3082 VkImageAspectFlags aspects
;
3085 uint32_t array_size
;
3086 uint32_t samples
; /**< VkImageCreateInfo::samples */
3088 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3089 VkImageUsageFlags stencil_usage
;
3090 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3091 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3093 /** True if this is needs to be bound to an appropriately tiled BO.
3095 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3096 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3097 * we require a dedicated allocation so that we can know to allocate a
3100 bool needs_set_tiling
;
3103 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3104 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3106 uint64_t drm_format_mod
;
3111 /* Whether the image is made of several underlying buffer objects rather a
3112 * single one with different offsets.
3116 /* All the formats that can be used when creating views of this image
3117 * are CCS_E compatible.
3119 bool ccs_e_compatible
;
3121 /* Image was created with external format. */
3122 bool external_format
;
3127 * For each foo, anv_image::planes[x].surface is valid if and only if
3128 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3129 * to figure the number associated with a given aspect.
3131 * The hardware requires that the depth buffer and stencil buffer be
3132 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3133 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3134 * allocate the depth and stencil buffers as separate surfaces in the same
3139 * -----------------------
3141 * ----------------------- |
3142 * | shadow surface0 | |
3143 * ----------------------- | Plane 0
3144 * | aux surface0 | |
3145 * ----------------------- |
3146 * | fast clear colors0 | \|/
3147 * -----------------------
3149 * ----------------------- |
3150 * | shadow surface1 | |
3151 * ----------------------- | Plane 1
3152 * | aux surface1 | |
3153 * ----------------------- |
3154 * | fast clear colors1 | \|/
3155 * -----------------------
3158 * -----------------------
3162 * Offset of the entire plane (whenever the image is disjoint this is
3170 struct anv_surface surface
;
3173 * A surface which shadows the main surface and may have different
3174 * tiling. This is used for sampling using a tiling that isn't supported
3175 * for other operations.
3177 struct anv_surface shadow_surface
;
3180 * For color images, this is the aux usage for this image when not used
3181 * as a color attachment.
3183 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3184 * image has a HiZ buffer.
3186 enum isl_aux_usage aux_usage
;
3188 struct anv_surface aux_surface
;
3191 * Offset of the fast clear state (used to compute the
3192 * fast_clear_state_offset of the following planes).
3194 uint32_t fast_clear_state_offset
;
3197 * BO associated with this plane, set when bound.
3199 struct anv_address address
;
3202 * When destroying the image, also free the bo.
3208 /* The ordering of this enum is important */
3209 enum anv_fast_clear_type
{
3210 /** Image does not have/support any fast-clear blocks */
3211 ANV_FAST_CLEAR_NONE
= 0,
3212 /** Image has/supports fast-clear but only to the default value */
3213 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3214 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3215 ANV_FAST_CLEAR_ANY
= 2,
3218 /* Returns the number of auxiliary buffer levels attached to an image. */
3219 static inline uint8_t
3220 anv_image_aux_levels(const struct anv_image
* const image
,
3221 VkImageAspectFlagBits aspect
)
3223 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3224 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3225 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
3228 /* Returns the number of auxiliary buffer layers attached to an image. */
3229 static inline uint32_t
3230 anv_image_aux_layers(const struct anv_image
* const image
,
3231 VkImageAspectFlagBits aspect
,
3232 const uint8_t miplevel
)
3236 /* The miplevel must exist in the main buffer. */
3237 assert(miplevel
< image
->levels
);
3239 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3240 /* There are no layers with auxiliary data because the miplevel has no
3245 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3246 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
3247 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
3251 static inline struct anv_address
3252 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3253 const struct anv_image
*image
,
3254 VkImageAspectFlagBits aspect
)
3256 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3258 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3259 return anv_address_add(image
->planes
[plane
].address
,
3260 image
->planes
[plane
].fast_clear_state_offset
);
3263 static inline struct anv_address
3264 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3265 const struct anv_image
*image
,
3266 VkImageAspectFlagBits aspect
)
3268 struct anv_address addr
=
3269 anv_image_get_clear_color_addr(device
, image
, aspect
);
3271 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3272 device
->isl_dev
.ss
.clear_color_state_size
:
3273 device
->isl_dev
.ss
.clear_value_size
;
3274 return anv_address_add(addr
, clear_color_state_size
);
3277 static inline struct anv_address
3278 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3279 const struct anv_image
*image
,
3280 VkImageAspectFlagBits aspect
,
3281 uint32_t level
, uint32_t array_layer
)
3283 assert(level
< anv_image_aux_levels(image
, aspect
));
3284 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3285 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3286 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3288 struct anv_address addr
=
3289 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3290 addr
.offset
+= 4; /* Go past the fast clear type */
3292 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3293 for (uint32_t l
= 0; l
< level
; l
++)
3294 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3296 addr
.offset
+= level
* image
->array_size
* 4;
3298 addr
.offset
+= array_layer
* 4;
3303 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3305 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3306 const struct anv_image
*image
)
3308 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3311 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3312 * struct. There's documentation which suggests that this feature actually
3313 * reduces performance on BDW, but it has only been observed to help so
3314 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3315 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3317 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3320 return image
->samples
== 1;
3324 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3325 const struct anv_image
*image
,
3326 VkImageAspectFlagBits aspect
,
3327 enum isl_aux_usage aux_usage
,
3329 uint32_t base_layer
,
3330 uint32_t layer_count
);
3333 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3334 const struct anv_image
*image
,
3335 VkImageAspectFlagBits aspect
,
3336 enum isl_aux_usage aux_usage
,
3337 enum isl_format format
, struct isl_swizzle swizzle
,
3338 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3339 VkRect2D area
, union isl_color_value clear_color
);
3341 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3342 const struct anv_image
*image
,
3343 VkImageAspectFlags aspects
,
3344 enum isl_aux_usage depth_aux_usage
,
3346 uint32_t base_layer
, uint32_t layer_count
,
3348 float depth_value
, uint8_t stencil_value
);
3350 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3351 const struct anv_image
*src_image
,
3352 enum isl_aux_usage src_aux_usage
,
3353 uint32_t src_level
, uint32_t src_base_layer
,
3354 const struct anv_image
*dst_image
,
3355 enum isl_aux_usage dst_aux_usage
,
3356 uint32_t dst_level
, uint32_t dst_base_layer
,
3357 VkImageAspectFlagBits aspect
,
3358 uint32_t src_x
, uint32_t src_y
,
3359 uint32_t dst_x
, uint32_t dst_y
,
3360 uint32_t width
, uint32_t height
,
3361 uint32_t layer_count
,
3362 enum blorp_filter filter
);
3364 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3365 const struct anv_image
*image
,
3366 VkImageAspectFlagBits aspect
, uint32_t level
,
3367 uint32_t base_layer
, uint32_t layer_count
,
3368 enum isl_aux_op hiz_op
);
3370 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3371 const struct anv_image
*image
,
3372 VkImageAspectFlags aspects
,
3374 uint32_t base_layer
, uint32_t layer_count
,
3375 VkRect2D area
, uint8_t stencil_value
);
3377 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3378 const struct anv_image
*image
,
3379 enum isl_format format
,
3380 VkImageAspectFlagBits aspect
,
3381 uint32_t base_layer
, uint32_t layer_count
,
3382 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3385 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3386 const struct anv_image
*image
,
3387 enum isl_format format
,
3388 VkImageAspectFlagBits aspect
, uint32_t level
,
3389 uint32_t base_layer
, uint32_t layer_count
,
3390 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3394 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3395 const struct anv_image
*image
,
3396 VkImageAspectFlagBits aspect
,
3397 uint32_t base_level
, uint32_t level_count
,
3398 uint32_t base_layer
, uint32_t layer_count
);
3401 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3402 const struct anv_image
*image
,
3403 const VkImageAspectFlagBits aspect
,
3404 const VkImageLayout layout
);
3406 enum anv_fast_clear_type
3407 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3408 const struct anv_image
* const image
,
3409 const VkImageAspectFlagBits aspect
,
3410 const VkImageLayout layout
);
3412 /* This is defined as a macro so that it works for both
3413 * VkImageSubresourceRange and VkImageSubresourceLayers
3415 #define anv_get_layerCount(_image, _range) \
3416 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3417 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3419 static inline uint32_t
3420 anv_get_levelCount(const struct anv_image
*image
,
3421 const VkImageSubresourceRange
*range
)
3423 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3424 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3427 static inline VkImageAspectFlags
3428 anv_image_expand_aspects(const struct anv_image
*image
,
3429 VkImageAspectFlags aspects
)
3431 /* If the underlying image has color plane aspects and
3432 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3433 * the underlying image. */
3434 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3435 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3436 return image
->aspects
;
3442 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3443 VkImageAspectFlags aspects2
)
3445 if (aspects1
== aspects2
)
3448 /* Only 1 color aspects are compatibles. */
3449 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3450 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3451 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3457 struct anv_image_view
{
3458 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3460 VkImageAspectFlags aspect_mask
;
3462 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3466 uint32_t image_plane
;
3468 struct isl_view isl
;
3471 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3472 * image layout of SHADER_READ_ONLY_OPTIMAL or
3473 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3475 struct anv_surface_state optimal_sampler_surface_state
;
3478 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3479 * image layout of GENERAL.
3481 struct anv_surface_state general_sampler_surface_state
;
3484 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3485 * states for write-only and readable, using the real format for
3486 * write-only and the lowered format for readable.
3488 struct anv_surface_state storage_surface_state
;
3489 struct anv_surface_state writeonly_storage_surface_state
;
3491 struct brw_image_param storage_image_param
;
3495 enum anv_image_view_state_flags
{
3496 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3497 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3500 void anv_image_fill_surface_state(struct anv_device
*device
,
3501 const struct anv_image
*image
,
3502 VkImageAspectFlagBits aspect
,
3503 const struct isl_view
*view
,
3504 isl_surf_usage_flags_t view_usage
,
3505 enum isl_aux_usage aux_usage
,
3506 const union isl_color_value
*clear_color
,
3507 enum anv_image_view_state_flags flags
,
3508 struct anv_surface_state
*state_inout
,
3509 struct brw_image_param
*image_param_out
);
3511 struct anv_image_create_info
{
3512 const VkImageCreateInfo
*vk_info
;
3514 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3515 isl_tiling_flags_t isl_tiling_flags
;
3517 /** These flags will be added to any derived from VkImageCreateInfo. */
3518 isl_surf_usage_flags_t isl_extra_usage_flags
;
3521 bool external_format
;
3524 VkResult
anv_image_create(VkDevice _device
,
3525 const struct anv_image_create_info
*info
,
3526 const VkAllocationCallbacks
* alloc
,
3529 const struct anv_surface
*
3530 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3531 VkImageAspectFlags aspect_mask
);
3534 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3536 static inline struct VkExtent3D
3537 anv_sanitize_image_extent(const VkImageType imageType
,
3538 const struct VkExtent3D imageExtent
)
3540 switch (imageType
) {
3541 case VK_IMAGE_TYPE_1D
:
3542 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3543 case VK_IMAGE_TYPE_2D
:
3544 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3545 case VK_IMAGE_TYPE_3D
:
3548 unreachable("invalid image type");
3552 static inline struct VkOffset3D
3553 anv_sanitize_image_offset(const VkImageType imageType
,
3554 const struct VkOffset3D imageOffset
)
3556 switch (imageType
) {
3557 case VK_IMAGE_TYPE_1D
:
3558 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3559 case VK_IMAGE_TYPE_2D
:
3560 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3561 case VK_IMAGE_TYPE_3D
:
3564 unreachable("invalid image type");
3568 VkFormatFeatureFlags
3569 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3571 const struct anv_format
*anv_format
,
3572 VkImageTiling vk_tiling
);
3574 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3575 struct anv_state state
,
3576 enum isl_format format
,
3577 struct anv_address address
,
3578 uint32_t range
, uint32_t stride
);
3581 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3582 const struct anv_attachment_state
*att_state
,
3583 const struct anv_image_view
*iview
)
3585 const struct isl_format_layout
*view_fmtl
=
3586 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3588 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3589 if (view_fmtl->channels.c.bits) \
3590 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3592 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3593 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3594 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3595 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3597 #undef COPY_CLEAR_COLOR_CHANNEL
3601 struct anv_ycbcr_conversion
{
3602 const struct anv_format
* format
;
3603 VkSamplerYcbcrModelConversion ycbcr_model
;
3604 VkSamplerYcbcrRange ycbcr_range
;
3605 VkComponentSwizzle mapping
[4];
3606 VkChromaLocation chroma_offsets
[2];
3607 VkFilter chroma_filter
;
3608 bool chroma_reconstruction
;
3611 struct anv_sampler
{
3612 uint32_t state
[3][4];
3614 struct anv_ycbcr_conversion
*conversion
;
3616 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3617 * and with a 32-byte stride for use as bindless samplers.
3619 struct anv_state bindless_state
;
3622 struct anv_framebuffer
{
3627 uint32_t attachment_count
;
3628 struct anv_image_view
* attachments
[0];
3631 struct anv_subpass_attachment
{
3632 VkImageUsageFlagBits usage
;
3633 uint32_t attachment
;
3634 VkImageLayout layout
;
3637 struct anv_subpass
{
3638 uint32_t attachment_count
;
3641 * A pointer to all attachment references used in this subpass.
3642 * Only valid if ::attachment_count > 0.
3644 struct anv_subpass_attachment
* attachments
;
3645 uint32_t input_count
;
3646 struct anv_subpass_attachment
* input_attachments
;
3647 uint32_t color_count
;
3648 struct anv_subpass_attachment
* color_attachments
;
3649 struct anv_subpass_attachment
* resolve_attachments
;
3651 struct anv_subpass_attachment
* depth_stencil_attachment
;
3652 struct anv_subpass_attachment
* ds_resolve_attachment
;
3653 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3654 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3658 /** Subpass has a depth/stencil self-dependency */
3659 bool has_ds_self_dep
;
3661 /** Subpass has at least one color resolve attachment */
3662 bool has_color_resolve
;
3665 static inline unsigned
3666 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3668 return MAX2(1, util_bitcount(subpass
->view_mask
));
3671 struct anv_render_pass_attachment
{
3672 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3673 * its members individually.
3677 VkImageUsageFlags usage
;
3678 VkAttachmentLoadOp load_op
;
3679 VkAttachmentStoreOp store_op
;
3680 VkAttachmentLoadOp stencil_load_op
;
3681 VkImageLayout initial_layout
;
3682 VkImageLayout final_layout
;
3683 VkImageLayout first_subpass_layout
;
3685 /* The subpass id in which the attachment will be used last. */
3686 uint32_t last_subpass_idx
;
3689 struct anv_render_pass
{
3690 uint32_t attachment_count
;
3691 uint32_t subpass_count
;
3692 /* An array of subpass_count+1 flushes, one per subpass boundary */
3693 enum anv_pipe_bits
* subpass_flushes
;
3694 struct anv_render_pass_attachment
* attachments
;
3695 struct anv_subpass subpasses
[0];
3698 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3700 struct anv_query_pool
{
3702 VkQueryPipelineStatisticFlags pipeline_statistics
;
3703 /** Stride between slots, in bytes */
3705 /** Number of slots in this query pool */
3710 int anv_get_instance_entrypoint_index(const char *name
);
3711 int anv_get_device_entrypoint_index(const char *name
);
3712 int anv_get_physical_device_entrypoint_index(const char *name
);
3714 const char *anv_get_instance_entry_name(int index
);
3715 const char *anv_get_physical_device_entry_name(int index
);
3716 const char *anv_get_device_entry_name(int index
);
3719 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3720 const struct anv_instance_extension_table
*instance
);
3722 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3723 const struct anv_instance_extension_table
*instance
);
3725 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3726 const struct anv_instance_extension_table
*instance
,
3727 const struct anv_device_extension_table
*device
);
3729 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3732 void anv_dump_image_to_ppm(struct anv_device
*device
,
3733 struct anv_image
*image
, unsigned miplevel
,
3734 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3735 const char *filename
);
3737 enum anv_dump_action
{
3738 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3741 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3742 void anv_dump_finish(void);
3744 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3746 static inline uint32_t
3747 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3749 /* This function must be called from within a subpass. */
3750 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3752 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3754 /* The id of this subpass shouldn't exceed the number of subpasses in this
3755 * render pass minus 1.
3757 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3761 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
3762 void anv_device_perf_init(struct anv_device
*device
);
3764 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3766 static inline struct __anv_type * \
3767 __anv_type ## _from_handle(__VkType _handle) \
3769 return (struct __anv_type *) _handle; \
3772 static inline __VkType \
3773 __anv_type ## _to_handle(struct __anv_type *_obj) \
3775 return (__VkType) _obj; \
3778 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3780 static inline struct __anv_type * \
3781 __anv_type ## _from_handle(__VkType _handle) \
3783 return (struct __anv_type *)(uintptr_t) _handle; \
3786 static inline __VkType \
3787 __anv_type ## _to_handle(struct __anv_type *_obj) \
3789 return (__VkType)(uintptr_t) _obj; \
3792 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3793 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3795 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3796 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3797 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3798 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3799 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3801 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3802 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3803 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3804 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3805 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3806 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3807 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3808 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3809 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3810 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3811 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3812 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3813 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3814 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3815 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3816 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3817 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3818 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3819 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3820 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3821 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3822 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3823 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3825 /* Gen-specific function declarations */
3827 # include "anv_genX.h"
3829 # define genX(x) gen7_##x
3830 # include "anv_genX.h"
3832 # define genX(x) gen75_##x
3833 # include "anv_genX.h"
3835 # define genX(x) gen8_##x
3836 # include "anv_genX.h"
3838 # define genX(x) gen9_##x
3839 # include "anv_genX.h"
3841 # define genX(x) gen10_##x
3842 # include "anv_genX.h"
3844 # define genX(x) gen11_##x
3845 # include "anv_genX.h"
3847 # define genX(x) gen12_##x
3848 # include "anv_genX.h"
3852 #endif /* ANV_PRIVATE_H */