anv: Add a new anv_surface_state struct
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53
54 /* Pre-declarations needed for WSI entrypoints */
55 struct wl_surface;
56 struct wl_display;
57 typedef struct xcb_connection_t xcb_connection_t;
58 typedef uint32_t xcb_visualid_t;
59 typedef uint32_t xcb_window_t;
60
61 struct anv_buffer;
62 struct anv_buffer_view;
63 struct anv_image_view;
64 struct anv_instance;
65 struct anv_debug_report_callback;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "anv_entrypoints.h"
74 #include "isl/isl.h"
75
76 #include "common/gen_debug.h"
77 #include "wsi_common.h"
78
79 /* Allowing different clear colors requires us to perform a depth resolve at
80 * the end of certain render passes. This is because while slow clears store
81 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
82 * See the PRMs for examples describing when additional resolves would be
83 * necessary. To enable fast clears without requiring extra resolves, we set
84 * the clear value to a globally-defined one. We could allow different values
85 * if the user doesn't expect coherent data during or after a render passes
86 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
87 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
88 * 1.0f seems to be the only value used. The only application that doesn't set
89 * this value does so through the usage of an seemingly uninitialized clear
90 * value.
91 */
92 #define ANV_HZ_FC_VAL 1.0f
93
94 #define MAX_VBS 28
95 #define MAX_SETS 8
96 #define MAX_RTS 8
97 #define MAX_VIEWPORTS 16
98 #define MAX_SCISSORS 16
99 #define MAX_PUSH_CONSTANTS_SIZE 128
100 #define MAX_DYNAMIC_BUFFERS 16
101 #define MAX_IMAGES 8
102 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
103
104 #define ANV_SVGS_VB_INDEX MAX_VBS
105 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
106
107 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
108
109 static inline uint32_t
110 align_down_npot_u32(uint32_t v, uint32_t a)
111 {
112 return v - (v % a);
113 }
114
115 static inline uint32_t
116 align_u32(uint32_t v, uint32_t a)
117 {
118 assert(a != 0 && a == (a & -a));
119 return (v + a - 1) & ~(a - 1);
120 }
121
122 static inline uint64_t
123 align_u64(uint64_t v, uint64_t a)
124 {
125 assert(a != 0 && a == (a & -a));
126 return (v + a - 1) & ~(a - 1);
127 }
128
129 static inline int32_t
130 align_i32(int32_t v, int32_t a)
131 {
132 assert(a != 0 && a == (a & -a));
133 return (v + a - 1) & ~(a - 1);
134 }
135
136 /** Alignment must be a power of 2. */
137 static inline bool
138 anv_is_aligned(uintmax_t n, uintmax_t a)
139 {
140 assert(a == (a & -a));
141 return (n & (a - 1)) == 0;
142 }
143
144 static inline uint32_t
145 anv_minify(uint32_t n, uint32_t levels)
146 {
147 if (unlikely(n == 0))
148 return 0;
149 else
150 return MAX2(n >> levels, 1);
151 }
152
153 static inline float
154 anv_clamp_f(float f, float min, float max)
155 {
156 assert(min < max);
157
158 if (f > max)
159 return max;
160 else if (f < min)
161 return min;
162 else
163 return f;
164 }
165
166 static inline bool
167 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
168 {
169 if (*inout_mask & clear_mask) {
170 *inout_mask &= ~clear_mask;
171 return true;
172 } else {
173 return false;
174 }
175 }
176
177 static inline union isl_color_value
178 vk_to_isl_color(VkClearColorValue color)
179 {
180 return (union isl_color_value) {
181 .u32 = {
182 color.uint32[0],
183 color.uint32[1],
184 color.uint32[2],
185 color.uint32[3],
186 },
187 };
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
201 * to be added here in order to utilize mapping in debug/error/perf macros.
202 */
203 #define REPORT_OBJECT_TYPE(o) \
204 __builtin_choose_expr ( \
205 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
206 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
207 __builtin_choose_expr ( \
208 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
209 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
210 __builtin_choose_expr ( \
211 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
212 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
213 __builtin_choose_expr ( \
214 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
215 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
216 __builtin_choose_expr ( \
217 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
218 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
219 __builtin_choose_expr ( \
220 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
221 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
222 __builtin_choose_expr ( \
223 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
224 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
225 __builtin_choose_expr ( \
226 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
227 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
228 __builtin_choose_expr ( \
229 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
230 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
231 __builtin_choose_expr ( \
232 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
233 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
234 __builtin_choose_expr ( \
235 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
236 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
237 __builtin_choose_expr ( \
238 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
239 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
240 __builtin_choose_expr ( \
241 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
242 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
243 __builtin_choose_expr ( \
244 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
245 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
246 __builtin_choose_expr ( \
247 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
248 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
249 __builtin_choose_expr ( \
250 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
251 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
252 __builtin_choose_expr ( \
253 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
254 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
255 __builtin_choose_expr ( \
256 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
257 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
258 __builtin_choose_expr ( \
259 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
260 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
261 __builtin_choose_expr ( \
262 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
263 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
264 __builtin_choose_expr ( \
265 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
266 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
267 __builtin_choose_expr ( \
268 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
269 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
270 __builtin_choose_expr ( \
271 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
272 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
273 __builtin_choose_expr ( \
274 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
275 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
276 __builtin_choose_expr ( \
277 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
278 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct anv_debug_callback*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), void*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
297 /* The void expression results in a compile-time error \
298 when assigning the result to something. */ \
299 (void)0)))))))))))))))))))))))))))))))
300
301 /* Whenever we generate an error, pass it through this function. Useful for
302 * debugging, where we can break on it. Only call at error site, not when
303 * propagating errors. Might be useful to plug in a stack trace here.
304 */
305
306 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
307 VkDebugReportObjectTypeEXT type, VkResult error,
308 const char *file, int line, const char *format, ...);
309
310 #ifdef DEBUG
311 #define vk_error(error) __vk_errorf(NULL, NULL,\
312 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
313 error, __FILE__, __LINE__, NULL);
314 #define vk_errorf(instance, obj, error, format, ...)\
315 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
316 __FILE__, __LINE__, format, ## __VA_ARGS__);
317 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
318 #else
319 #define vk_error(error) error
320 #define vk_errorf(instance, obj, error, format, ...) error
321 #define anv_debug(format, ...)
322 #endif
323
324 /**
325 * Warn on ignored extension structs.
326 *
327 * The Vulkan spec requires us to ignore unsupported or unknown structs in
328 * a pNext chain. In debug mode, emitting warnings for ignored structs may
329 * help us discover structs that we should not have ignored.
330 *
331 *
332 * From the Vulkan 1.0.38 spec:
333 *
334 * Any component of the implementation (the loader, any enabled layers,
335 * and drivers) must skip over, without processing (other than reading the
336 * sType and pNext members) any chained structures with sType values not
337 * defined by extensions supported by that component.
338 */
339 #define anv_debug_ignored_stype(sType) \
340 anv_debug("%s: ignored VkStructureType %u\n", __func__, (sType))
341
342 void __anv_finishme(const char *file, int line, const char *format, ...)
343 anv_printflike(3, 4);
344 void __anv_perf_warn(struct anv_instance *instance, const void *object,
345 VkDebugReportObjectTypeEXT type, const char *file,
346 int line, const char *format, ...)
347 anv_printflike(6, 7);
348 void anv_loge(const char *format, ...) anv_printflike(1, 2);
349 void anv_loge_v(const char *format, va_list va);
350
351 void anv_debug_report(struct anv_instance *instance,
352 VkDebugReportFlagsEXT flags,
353 VkDebugReportObjectTypeEXT object_type,
354 uint64_t handle,
355 size_t location,
356 int32_t messageCode,
357 const char* pLayerPrefix,
358 const char *pMessage);
359
360 /**
361 * Print a FINISHME message, including its source location.
362 */
363 #define anv_finishme(format, ...) \
364 do { \
365 static bool reported = false; \
366 if (!reported) { \
367 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
368 reported = true; \
369 } \
370 } while (0)
371
372 /**
373 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
374 */
375 #define anv_perf_warn(instance, obj, format, ...) \
376 do { \
377 static bool reported = false; \
378 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
379 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
380 format, ##__VA_ARGS__); \
381 reported = true; \
382 } \
383 } while (0)
384
385 /* A non-fatal assert. Useful for debugging. */
386 #ifdef DEBUG
387 #define anv_assert(x) ({ \
388 if (unlikely(!(x))) \
389 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
390 })
391 #else
392 #define anv_assert(x)
393 #endif
394
395 /* A multi-pointer allocator
396 *
397 * When copying data structures from the user (such as a render pass), it's
398 * common to need to allocate data for a bunch of different things. Instead
399 * of doing several allocations and having to handle all of the error checking
400 * that entails, it can be easier to do a single allocation. This struct
401 * helps facilitate that. The intended usage looks like this:
402 *
403 * ANV_MULTIALLOC(ma)
404 * anv_multialloc_add(&ma, &main_ptr, 1);
405 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
406 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
407 *
408 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
409 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
410 */
411 struct anv_multialloc {
412 size_t size;
413 size_t align;
414
415 uint32_t ptr_count;
416 void **ptrs[8];
417 };
418
419 #define ANV_MULTIALLOC_INIT \
420 ((struct anv_multialloc) { 0, })
421
422 #define ANV_MULTIALLOC(_name) \
423 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
424
425 __attribute__((always_inline))
426 static inline void
427 _anv_multialloc_add(struct anv_multialloc *ma,
428 void **ptr, size_t size, size_t align)
429 {
430 size_t offset = align_u64(ma->size, align);
431 ma->size = offset + size;
432 ma->align = MAX2(ma->align, align);
433
434 /* Store the offset in the pointer. */
435 *ptr = (void *)(uintptr_t)offset;
436
437 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
438 ma->ptrs[ma->ptr_count++] = ptr;
439 }
440
441 #define anv_multialloc_add(_ma, _ptr, _count) \
442 _anv_multialloc_add((_ma), (void **)(_ptr), \
443 (_count) * sizeof(**(_ptr)), __alignof__(**(_ptr)))
444
445 __attribute__((always_inline))
446 static inline void *
447 anv_multialloc_alloc(struct anv_multialloc *ma,
448 const VkAllocationCallbacks *alloc,
449 VkSystemAllocationScope scope)
450 {
451 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
452 if (!ptr)
453 return NULL;
454
455 /* Fill out each of the pointers with their final value.
456 *
457 * for (uint32_t i = 0; i < ma->ptr_count; i++)
458 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
459 *
460 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
461 * constant, GCC is incapable of figuring this out and unrolling the loop
462 * so we have to give it a little help.
463 */
464 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
465 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
466 if ((_i) < ma->ptr_count) \
467 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
468 _ANV_MULTIALLOC_UPDATE_POINTER(0);
469 _ANV_MULTIALLOC_UPDATE_POINTER(1);
470 _ANV_MULTIALLOC_UPDATE_POINTER(2);
471 _ANV_MULTIALLOC_UPDATE_POINTER(3);
472 _ANV_MULTIALLOC_UPDATE_POINTER(4);
473 _ANV_MULTIALLOC_UPDATE_POINTER(5);
474 _ANV_MULTIALLOC_UPDATE_POINTER(6);
475 _ANV_MULTIALLOC_UPDATE_POINTER(7);
476 #undef _ANV_MULTIALLOC_UPDATE_POINTER
477
478 return ptr;
479 }
480
481 __attribute__((always_inline))
482 static inline void *
483 anv_multialloc_alloc2(struct anv_multialloc *ma,
484 const VkAllocationCallbacks *parent_alloc,
485 const VkAllocationCallbacks *alloc,
486 VkSystemAllocationScope scope)
487 {
488 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
489 }
490
491 struct anv_bo {
492 uint32_t gem_handle;
493
494 /* Index into the current validation list. This is used by the
495 * validation list building alrogithm to track which buffers are already
496 * in the validation list so that we can ensure uniqueness.
497 */
498 uint32_t index;
499
500 /* Last known offset. This value is provided by the kernel when we
501 * execbuf and is used as the presumed offset for the next bunch of
502 * relocations.
503 */
504 uint64_t offset;
505
506 uint64_t size;
507 void *map;
508
509 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
510 uint32_t flags;
511 };
512
513 static inline void
514 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
515 {
516 bo->gem_handle = gem_handle;
517 bo->index = 0;
518 bo->offset = -1;
519 bo->size = size;
520 bo->map = NULL;
521 bo->flags = 0;
522 }
523
524 /* Represents a lock-free linked list of "free" things. This is used by
525 * both the block pool and the state pools. Unfortunately, in order to
526 * solve the ABA problem, we can't use a single uint32_t head.
527 */
528 union anv_free_list {
529 struct {
530 int32_t offset;
531
532 /* A simple count that is incremented every time the head changes. */
533 uint32_t count;
534 };
535 uint64_t u64;
536 };
537
538 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
539
540 struct anv_block_state {
541 union {
542 struct {
543 uint32_t next;
544 uint32_t end;
545 };
546 uint64_t u64;
547 };
548 };
549
550 struct anv_block_pool {
551 struct anv_device *device;
552
553 struct anv_bo bo;
554
555 /* The offset from the start of the bo to the "center" of the block
556 * pool. Pointers to allocated blocks are given by
557 * bo.map + center_bo_offset + offsets.
558 */
559 uint32_t center_bo_offset;
560
561 /* Current memory map of the block pool. This pointer may or may not
562 * point to the actual beginning of the block pool memory. If
563 * anv_block_pool_alloc_back has ever been called, then this pointer
564 * will point to the "center" position of the buffer and all offsets
565 * (negative or positive) given out by the block pool alloc functions
566 * will be valid relative to this pointer.
567 *
568 * In particular, map == bo.map + center_offset
569 */
570 void *map;
571 int fd;
572
573 /**
574 * Array of mmaps and gem handles owned by the block pool, reclaimed when
575 * the block pool is destroyed.
576 */
577 struct u_vector mmap_cleanups;
578
579 struct anv_block_state state;
580
581 struct anv_block_state back_state;
582 };
583
584 /* Block pools are backed by a fixed-size 1GB memfd */
585 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
586
587 /* The center of the block pool is also the middle of the memfd. This may
588 * change in the future if we decide differently for some reason.
589 */
590 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
591
592 static inline uint32_t
593 anv_block_pool_size(struct anv_block_pool *pool)
594 {
595 return pool->state.end + pool->back_state.end;
596 }
597
598 struct anv_state {
599 int32_t offset;
600 uint32_t alloc_size;
601 void *map;
602 };
603
604 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
605
606 struct anv_fixed_size_state_pool {
607 union anv_free_list free_list;
608 struct anv_block_state block;
609 };
610
611 #define ANV_MIN_STATE_SIZE_LOG2 6
612 #define ANV_MAX_STATE_SIZE_LOG2 20
613
614 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
615
616 struct anv_state_pool {
617 struct anv_block_pool block_pool;
618
619 /* The size of blocks which will be allocated from the block pool */
620 uint32_t block_size;
621
622 /** Free list for "back" allocations */
623 union anv_free_list back_alloc_free_list;
624
625 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
626 };
627
628 struct anv_state_stream_block;
629
630 struct anv_state_stream {
631 struct anv_state_pool *state_pool;
632
633 /* The size of blocks to allocate from the state pool */
634 uint32_t block_size;
635
636 /* Current block we're allocating from */
637 struct anv_state block;
638
639 /* Offset into the current block at which to allocate the next state */
640 uint32_t next;
641
642 /* List of all blocks allocated from this pool */
643 struct anv_state_stream_block *block_list;
644 };
645
646 /* The block_pool functions exported for testing only. The block pool should
647 * only be used via a state pool (see below).
648 */
649 VkResult anv_block_pool_init(struct anv_block_pool *pool,
650 struct anv_device *device,
651 uint32_t initial_size);
652 void anv_block_pool_finish(struct anv_block_pool *pool);
653 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
654 uint32_t block_size);
655 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
656 uint32_t block_size);
657
658 VkResult anv_state_pool_init(struct anv_state_pool *pool,
659 struct anv_device *device,
660 uint32_t block_size);
661 void anv_state_pool_finish(struct anv_state_pool *pool);
662 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
663 uint32_t state_size, uint32_t alignment);
664 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
665 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
666 void anv_state_stream_init(struct anv_state_stream *stream,
667 struct anv_state_pool *state_pool,
668 uint32_t block_size);
669 void anv_state_stream_finish(struct anv_state_stream *stream);
670 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
671 uint32_t size, uint32_t alignment);
672
673 /**
674 * Implements a pool of re-usable BOs. The interface is identical to that
675 * of block_pool except that each block is its own BO.
676 */
677 struct anv_bo_pool {
678 struct anv_device *device;
679
680 void *free_list[16];
681 };
682
683 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
684 void anv_bo_pool_finish(struct anv_bo_pool *pool);
685 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
686 uint32_t size);
687 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
688
689 struct anv_scratch_bo {
690 bool exists;
691 struct anv_bo bo;
692 };
693
694 struct anv_scratch_pool {
695 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
696 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
697 };
698
699 void anv_scratch_pool_init(struct anv_device *device,
700 struct anv_scratch_pool *pool);
701 void anv_scratch_pool_finish(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
704 struct anv_scratch_pool *pool,
705 gl_shader_stage stage,
706 unsigned per_thread_scratch);
707
708 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
709 struct anv_bo_cache {
710 struct hash_table *bo_map;
711 pthread_mutex_t mutex;
712 };
713
714 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
715 void anv_bo_cache_finish(struct anv_bo_cache *cache);
716 VkResult anv_bo_cache_alloc(struct anv_device *device,
717 struct anv_bo_cache *cache,
718 uint64_t size, struct anv_bo **bo);
719 VkResult anv_bo_cache_import(struct anv_device *device,
720 struct anv_bo_cache *cache,
721 int fd, uint64_t size, struct anv_bo **bo);
722 VkResult anv_bo_cache_export(struct anv_device *device,
723 struct anv_bo_cache *cache,
724 struct anv_bo *bo_in, int *fd_out);
725 void anv_bo_cache_release(struct anv_device *device,
726 struct anv_bo_cache *cache,
727 struct anv_bo *bo);
728
729 struct anv_memory_type {
730 /* Standard bits passed on to the client */
731 VkMemoryPropertyFlags propertyFlags;
732 uint32_t heapIndex;
733
734 /* Driver-internal book-keeping */
735 VkBufferUsageFlags valid_buffer_usage;
736 };
737
738 struct anv_memory_heap {
739 /* Standard bits passed on to the client */
740 VkDeviceSize size;
741 VkMemoryHeapFlags flags;
742
743 /* Driver-internal book-keeping */
744 bool supports_48bit_addresses;
745 };
746
747 struct anv_physical_device {
748 VK_LOADER_DATA _loader_data;
749
750 struct anv_instance * instance;
751 uint32_t chipset_id;
752 char path[20];
753 const char * name;
754 struct gen_device_info info;
755 /** Amount of "GPU memory" we want to advertise
756 *
757 * Clearly, this value is bogus since Intel is a UMA architecture. On
758 * gen7 platforms, we are limited by GTT size unless we want to implement
759 * fine-grained tracking and GTT splitting. On Broadwell and above we are
760 * practically unlimited. However, we will never report more than 3/4 of
761 * the total system ram to try and avoid running out of RAM.
762 */
763 bool supports_48bit_addresses;
764 struct brw_compiler * compiler;
765 struct isl_device isl_dev;
766 int cmd_parser_version;
767 bool has_exec_async;
768 bool has_exec_fence;
769 bool has_syncobj;
770 bool has_syncobj_wait;
771
772 uint32_t eu_total;
773 uint32_t subslice_total;
774
775 struct {
776 uint32_t type_count;
777 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
778 uint32_t heap_count;
779 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
780 } memory;
781
782 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
783 uint8_t driver_uuid[VK_UUID_SIZE];
784 uint8_t device_uuid[VK_UUID_SIZE];
785
786 struct wsi_device wsi_device;
787 int local_fd;
788 };
789
790 struct anv_debug_report_callback {
791 /* Link in the 'callbacks' list in anv_instance struct. */
792 struct list_head link;
793 VkDebugReportFlagsEXT flags;
794 PFN_vkDebugReportCallbackEXT callback;
795 void * data;
796 };
797
798 struct anv_instance {
799 VK_LOADER_DATA _loader_data;
800
801 VkAllocationCallbacks alloc;
802
803 uint32_t apiVersion;
804 int physicalDeviceCount;
805 struct anv_physical_device physicalDevice;
806
807 /* VK_EXT_debug_report debug callbacks */
808 pthread_mutex_t callbacks_mutex;
809 struct list_head callbacks;
810 struct anv_debug_report_callback destroy_debug_cb;
811 };
812
813 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
814 void anv_finish_wsi(struct anv_physical_device *physical_device);
815
816 bool anv_instance_extension_supported(const char *name);
817 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
818 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
819 const char *name);
820
821 struct anv_queue {
822 VK_LOADER_DATA _loader_data;
823
824 struct anv_device * device;
825
826 struct anv_state_pool * pool;
827 };
828
829 struct anv_pipeline_cache {
830 struct anv_device * device;
831 pthread_mutex_t mutex;
832
833 struct hash_table * cache;
834 };
835
836 struct anv_pipeline_bind_map;
837
838 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
839 struct anv_device *device,
840 bool cache_enabled);
841 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
842
843 struct anv_shader_bin *
844 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
845 const void *key, uint32_t key_size);
846 struct anv_shader_bin *
847 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
848 const void *key_data, uint32_t key_size,
849 const void *kernel_data, uint32_t kernel_size,
850 const struct brw_stage_prog_data *prog_data,
851 uint32_t prog_data_size,
852 const struct anv_pipeline_bind_map *bind_map);
853
854 struct anv_device {
855 VK_LOADER_DATA _loader_data;
856
857 VkAllocationCallbacks alloc;
858
859 struct anv_instance * instance;
860 uint32_t chipset_id;
861 struct gen_device_info info;
862 struct isl_device isl_dev;
863 int context_id;
864 int fd;
865 bool can_chain_batches;
866 bool robust_buffer_access;
867
868 struct anv_bo_pool batch_bo_pool;
869
870 struct anv_bo_cache bo_cache;
871
872 struct anv_state_pool dynamic_state_pool;
873 struct anv_state_pool instruction_state_pool;
874 struct anv_state_pool surface_state_pool;
875
876 struct anv_bo workaround_bo;
877 struct anv_bo trivial_batch_bo;
878
879 struct anv_pipeline_cache blorp_shader_cache;
880 struct blorp_context blorp;
881
882 struct anv_state border_colors;
883
884 struct anv_queue queue;
885
886 struct anv_scratch_pool scratch_pool;
887
888 uint32_t default_mocs;
889
890 pthread_mutex_t mutex;
891 pthread_cond_t queue_submit;
892 bool lost;
893 };
894
895 static void inline
896 anv_state_flush(struct anv_device *device, struct anv_state state)
897 {
898 if (device->info.has_llc)
899 return;
900
901 gen_flush_range(state.map, state.alloc_size);
902 }
903
904 void anv_device_init_blorp(struct anv_device *device);
905 void anv_device_finish_blorp(struct anv_device *device);
906
907 VkResult anv_device_execbuf(struct anv_device *device,
908 struct drm_i915_gem_execbuffer2 *execbuf,
909 struct anv_bo **execbuf_bos);
910 VkResult anv_device_query_status(struct anv_device *device);
911 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
912 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
913 int64_t timeout);
914
915 void* anv_gem_mmap(struct anv_device *device,
916 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
917 void anv_gem_munmap(void *p, uint64_t size);
918 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
919 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
920 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
921 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
922 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
923 int anv_gem_execbuffer(struct anv_device *device,
924 struct drm_i915_gem_execbuffer2 *execbuf);
925 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
926 uint32_t stride, uint32_t tiling);
927 int anv_gem_create_context(struct anv_device *device);
928 int anv_gem_destroy_context(struct anv_device *device, int context);
929 int anv_gem_get_context_param(int fd, int context, uint32_t param,
930 uint64_t *value);
931 int anv_gem_get_param(int fd, uint32_t param);
932 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
933 int anv_gem_get_aperture(int fd, uint64_t *size);
934 bool anv_gem_supports_48b_addresses(int fd);
935 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
936 uint32_t *active, uint32_t *pending);
937 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
938 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
939 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
940 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
941 uint32_t read_domains, uint32_t write_domain);
942 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
943 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
944 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
945 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
946 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
947 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
948 uint32_t handle);
949 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
950 uint32_t handle, int fd);
951 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
952 bool anv_gem_supports_syncobj_wait(int fd);
953 int anv_gem_syncobj_wait(struct anv_device *device,
954 uint32_t *handles, uint32_t num_handles,
955 int64_t abs_timeout_ns, bool wait_all);
956
957 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
958
959 struct anv_reloc_list {
960 uint32_t num_relocs;
961 uint32_t array_length;
962 struct drm_i915_gem_relocation_entry * relocs;
963 struct anv_bo ** reloc_bos;
964 };
965
966 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
967 const VkAllocationCallbacks *alloc);
968 void anv_reloc_list_finish(struct anv_reloc_list *list,
969 const VkAllocationCallbacks *alloc);
970
971 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
972 const VkAllocationCallbacks *alloc,
973 uint32_t offset, struct anv_bo *target_bo,
974 uint32_t delta);
975
976 struct anv_batch_bo {
977 /* Link in the anv_cmd_buffer.owned_batch_bos list */
978 struct list_head link;
979
980 struct anv_bo bo;
981
982 /* Bytes actually consumed in this batch BO */
983 uint32_t length;
984
985 struct anv_reloc_list relocs;
986 };
987
988 struct anv_batch {
989 const VkAllocationCallbacks * alloc;
990
991 void * start;
992 void * end;
993 void * next;
994
995 struct anv_reloc_list * relocs;
996
997 /* This callback is called (with the associated user data) in the event
998 * that the batch runs out of space.
999 */
1000 VkResult (*extend_cb)(struct anv_batch *, void *);
1001 void * user_data;
1002
1003 /**
1004 * Current error status of the command buffer. Used to track inconsistent
1005 * or incomplete command buffer states that are the consequence of run-time
1006 * errors such as out of memory scenarios. We want to track this in the
1007 * batch because the command buffer object is not visible to some parts
1008 * of the driver.
1009 */
1010 VkResult status;
1011 };
1012
1013 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1014 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1015 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1016 void *location, struct anv_bo *bo, uint32_t offset);
1017 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1018 struct anv_batch *batch);
1019
1020 static inline VkResult
1021 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1022 {
1023 assert(error != VK_SUCCESS);
1024 if (batch->status == VK_SUCCESS)
1025 batch->status = error;
1026 return batch->status;
1027 }
1028
1029 static inline bool
1030 anv_batch_has_error(struct anv_batch *batch)
1031 {
1032 return batch->status != VK_SUCCESS;
1033 }
1034
1035 struct anv_address {
1036 struct anv_bo *bo;
1037 uint32_t offset;
1038 };
1039
1040 static inline uint64_t
1041 _anv_combine_address(struct anv_batch *batch, void *location,
1042 const struct anv_address address, uint32_t delta)
1043 {
1044 if (address.bo == NULL) {
1045 return address.offset + delta;
1046 } else {
1047 assert(batch->start <= location && location < batch->end);
1048
1049 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1050 }
1051 }
1052
1053 #define __gen_address_type struct anv_address
1054 #define __gen_user_data struct anv_batch
1055 #define __gen_combine_address _anv_combine_address
1056
1057 /* Wrapper macros needed to work around preprocessor argument issues. In
1058 * particular, arguments don't get pre-evaluated if they are concatenated.
1059 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1060 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1061 * We can work around this easily enough with these helpers.
1062 */
1063 #define __anv_cmd_length(cmd) cmd ## _length
1064 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1065 #define __anv_cmd_header(cmd) cmd ## _header
1066 #define __anv_cmd_pack(cmd) cmd ## _pack
1067 #define __anv_reg_num(reg) reg ## _num
1068
1069 #define anv_pack_struct(dst, struc, ...) do { \
1070 struct struc __template = { \
1071 __VA_ARGS__ \
1072 }; \
1073 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1074 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1075 } while (0)
1076
1077 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1078 void *__dst = anv_batch_emit_dwords(batch, n); \
1079 if (__dst) { \
1080 struct cmd __template = { \
1081 __anv_cmd_header(cmd), \
1082 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1083 __VA_ARGS__ \
1084 }; \
1085 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1086 } \
1087 __dst; \
1088 })
1089
1090 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1091 do { \
1092 uint32_t *dw; \
1093 \
1094 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1095 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1096 if (!dw) \
1097 break; \
1098 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1099 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1100 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1101 } while (0)
1102
1103 #define anv_batch_emit(batch, cmd, name) \
1104 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1105 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1106 __builtin_expect(_dst != NULL, 1); \
1107 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1108 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1109 _dst = NULL; \
1110 }))
1111
1112 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1113 .GraphicsDataTypeGFDT = 0, \
1114 .LLCCacheabilityControlLLCCC = 0, \
1115 .L3CacheabilityControlL3CC = 1, \
1116 }
1117
1118 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1119 .LLCeLLCCacheabilityControlLLCCC = 0, \
1120 .L3CacheabilityControlL3CC = 1, \
1121 }
1122
1123 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1124 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1125 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1126 .AgeforQUADLRU = 0 \
1127 }
1128
1129 /* Skylake: MOCS is now an index into an array of 62 different caching
1130 * configurations programmed by the kernel.
1131 */
1132
1133 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1134 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1135 .IndextoMOCSTables = 2 \
1136 }
1137
1138 #define GEN9_MOCS_PTE { \
1139 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1140 .IndextoMOCSTables = 1 \
1141 }
1142
1143 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1144 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1145 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1146 .IndextoMOCSTables = 2 \
1147 }
1148
1149 #define GEN10_MOCS_PTE { \
1150 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1151 .IndextoMOCSTables = 1 \
1152 }
1153
1154 struct anv_device_memory {
1155 struct anv_bo * bo;
1156 struct anv_memory_type * type;
1157 VkDeviceSize map_size;
1158 void * map;
1159 };
1160
1161 /**
1162 * Header for Vertex URB Entry (VUE)
1163 */
1164 struct anv_vue_header {
1165 uint32_t Reserved;
1166 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1167 uint32_t ViewportIndex;
1168 float PointWidth;
1169 };
1170
1171 struct anv_descriptor_set_binding_layout {
1172 #ifndef NDEBUG
1173 /* The type of the descriptors in this binding */
1174 VkDescriptorType type;
1175 #endif
1176
1177 /* Number of array elements in this binding */
1178 uint16_t array_size;
1179
1180 /* Index into the flattend descriptor set */
1181 uint16_t descriptor_index;
1182
1183 /* Index into the dynamic state array for a dynamic buffer */
1184 int16_t dynamic_offset_index;
1185
1186 /* Index into the descriptor set buffer views */
1187 int16_t buffer_index;
1188
1189 struct {
1190 /* Index into the binding table for the associated surface */
1191 int16_t surface_index;
1192
1193 /* Index into the sampler table for the associated sampler */
1194 int16_t sampler_index;
1195
1196 /* Index into the image table for the associated image */
1197 int16_t image_index;
1198 } stage[MESA_SHADER_STAGES];
1199
1200 /* Immutable samplers (or NULL if no immutable samplers) */
1201 struct anv_sampler **immutable_samplers;
1202 };
1203
1204 struct anv_descriptor_set_layout {
1205 /* Number of bindings in this descriptor set */
1206 uint16_t binding_count;
1207
1208 /* Total size of the descriptor set with room for all array entries */
1209 uint16_t size;
1210
1211 /* Shader stages affected by this descriptor set */
1212 uint16_t shader_stages;
1213
1214 /* Number of buffers in this descriptor set */
1215 uint16_t buffer_count;
1216
1217 /* Number of dynamic offsets used by this descriptor set */
1218 uint16_t dynamic_offset_count;
1219
1220 /* Bindings in this descriptor set */
1221 struct anv_descriptor_set_binding_layout binding[0];
1222 };
1223
1224 struct anv_descriptor {
1225 VkDescriptorType type;
1226
1227 union {
1228 struct {
1229 VkImageLayout layout;
1230 struct anv_image_view *image_view;
1231 struct anv_sampler *sampler;
1232 };
1233
1234 struct {
1235 struct anv_buffer *buffer;
1236 uint64_t offset;
1237 uint64_t range;
1238 };
1239
1240 struct anv_buffer_view *buffer_view;
1241 };
1242 };
1243
1244 struct anv_descriptor_set {
1245 const struct anv_descriptor_set_layout *layout;
1246 uint32_t size;
1247 uint32_t buffer_count;
1248 struct anv_buffer_view *buffer_views;
1249 struct anv_descriptor descriptors[0];
1250 };
1251
1252 struct anv_buffer_view {
1253 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1254 struct anv_bo *bo;
1255 uint32_t offset; /**< Offset into bo. */
1256 uint64_t range; /**< VkBufferViewCreateInfo::range */
1257
1258 struct anv_state surface_state;
1259 struct anv_state storage_surface_state;
1260 struct anv_state writeonly_storage_surface_state;
1261
1262 struct brw_image_param storage_image_param;
1263 };
1264
1265 struct anv_push_descriptor_set {
1266 struct anv_descriptor_set set;
1267
1268 /* Put this field right behind anv_descriptor_set so it fills up the
1269 * descriptors[0] field. */
1270 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1271
1272 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1273 };
1274
1275 struct anv_descriptor_pool {
1276 uint32_t size;
1277 uint32_t next;
1278 uint32_t free_list;
1279
1280 struct anv_state_stream surface_state_stream;
1281 void *surface_state_free_list;
1282
1283 char data[0];
1284 };
1285
1286 enum anv_descriptor_template_entry_type {
1287 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1288 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1289 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1290 };
1291
1292 struct anv_descriptor_template_entry {
1293 /* The type of descriptor in this entry */
1294 VkDescriptorType type;
1295
1296 /* Binding in the descriptor set */
1297 uint32_t binding;
1298
1299 /* Offset at which to write into the descriptor set binding */
1300 uint32_t array_element;
1301
1302 /* Number of elements to write into the descriptor set binding */
1303 uint32_t array_count;
1304
1305 /* Offset into the user provided data */
1306 size_t offset;
1307
1308 /* Stride between elements into the user provided data */
1309 size_t stride;
1310 };
1311
1312 struct anv_descriptor_update_template {
1313 /* The descriptor set this template corresponds to. This value is only
1314 * valid if the template was created with the templateType
1315 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1316 */
1317 uint8_t set;
1318
1319 /* Number of entries in this template */
1320 uint32_t entry_count;
1321
1322 /* Entries of the template */
1323 struct anv_descriptor_template_entry entries[0];
1324 };
1325
1326 size_t
1327 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1328
1329 void
1330 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1331 const struct gen_device_info * const devinfo,
1332 const VkDescriptorImageInfo * const info,
1333 VkDescriptorType type,
1334 uint32_t binding,
1335 uint32_t element);
1336
1337 void
1338 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1339 VkDescriptorType type,
1340 struct anv_buffer_view *buffer_view,
1341 uint32_t binding,
1342 uint32_t element);
1343
1344 void
1345 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1346 struct anv_device *device,
1347 struct anv_state_stream *alloc_stream,
1348 VkDescriptorType type,
1349 struct anv_buffer *buffer,
1350 uint32_t binding,
1351 uint32_t element,
1352 VkDeviceSize offset,
1353 VkDeviceSize range);
1354
1355 void
1356 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1357 struct anv_device *device,
1358 struct anv_state_stream *alloc_stream,
1359 const struct anv_descriptor_update_template *template,
1360 const void *data);
1361
1362 VkResult
1363 anv_descriptor_set_create(struct anv_device *device,
1364 struct anv_descriptor_pool *pool,
1365 const struct anv_descriptor_set_layout *layout,
1366 struct anv_descriptor_set **out_set);
1367
1368 void
1369 anv_descriptor_set_destroy(struct anv_device *device,
1370 struct anv_descriptor_pool *pool,
1371 struct anv_descriptor_set *set);
1372
1373 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1374
1375 struct anv_pipeline_binding {
1376 /* The descriptor set this surface corresponds to. The special value of
1377 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1378 * to a color attachment and not a regular descriptor.
1379 */
1380 uint8_t set;
1381
1382 /* Binding in the descriptor set */
1383 uint32_t binding;
1384
1385 /* Index in the binding */
1386 uint32_t index;
1387
1388 /* Input attachment index (relative to the subpass) */
1389 uint8_t input_attachment_index;
1390
1391 /* For a storage image, whether it is write-only */
1392 bool write_only;
1393 };
1394
1395 struct anv_pipeline_layout {
1396 struct {
1397 struct anv_descriptor_set_layout *layout;
1398 uint32_t dynamic_offset_start;
1399 } set[MAX_SETS];
1400
1401 uint32_t num_sets;
1402
1403 struct {
1404 bool has_dynamic_offsets;
1405 } stage[MESA_SHADER_STAGES];
1406
1407 unsigned char sha1[20];
1408 };
1409
1410 struct anv_buffer {
1411 struct anv_device * device;
1412 VkDeviceSize size;
1413
1414 VkBufferUsageFlags usage;
1415
1416 /* Set when bound */
1417 struct anv_bo * bo;
1418 VkDeviceSize offset;
1419 };
1420
1421 static inline uint64_t
1422 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1423 {
1424 assert(offset <= buffer->size);
1425 if (range == VK_WHOLE_SIZE) {
1426 return buffer->size - offset;
1427 } else {
1428 assert(range <= buffer->size);
1429 return range;
1430 }
1431 }
1432
1433 enum anv_cmd_dirty_bits {
1434 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1435 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1436 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1437 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1438 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1439 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1440 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1441 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1442 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1443 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1444 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1445 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1446 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1447 };
1448 typedef uint32_t anv_cmd_dirty_mask_t;
1449
1450 enum anv_pipe_bits {
1451 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1452 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1453 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1454 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1455 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1456 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1457 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1458 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1459 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1460 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1461 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1462
1463 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1464 * a flush has happened but not a CS stall. The next time we do any sort
1465 * of invalidation we need to insert a CS stall at that time. Otherwise,
1466 * we would have to CS stall on every flush which could be bad.
1467 */
1468 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1469 };
1470
1471 #define ANV_PIPE_FLUSH_BITS ( \
1472 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1473 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1474 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1475
1476 #define ANV_PIPE_STALL_BITS ( \
1477 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1478 ANV_PIPE_DEPTH_STALL_BIT | \
1479 ANV_PIPE_CS_STALL_BIT)
1480
1481 #define ANV_PIPE_INVALIDATE_BITS ( \
1482 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1483 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1484 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1485 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1486 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1487 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1488
1489 static inline enum anv_pipe_bits
1490 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1491 {
1492 enum anv_pipe_bits pipe_bits = 0;
1493
1494 unsigned b;
1495 for_each_bit(b, flags) {
1496 switch ((VkAccessFlagBits)(1 << b)) {
1497 case VK_ACCESS_SHADER_WRITE_BIT:
1498 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1499 break;
1500 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1501 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1502 break;
1503 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1504 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1505 break;
1506 case VK_ACCESS_TRANSFER_WRITE_BIT:
1507 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1508 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1509 break;
1510 default:
1511 break; /* Nothing to do */
1512 }
1513 }
1514
1515 return pipe_bits;
1516 }
1517
1518 static inline enum anv_pipe_bits
1519 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1520 {
1521 enum anv_pipe_bits pipe_bits = 0;
1522
1523 unsigned b;
1524 for_each_bit(b, flags) {
1525 switch ((VkAccessFlagBits)(1 << b)) {
1526 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1527 case VK_ACCESS_INDEX_READ_BIT:
1528 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1529 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1530 break;
1531 case VK_ACCESS_UNIFORM_READ_BIT:
1532 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1533 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1534 break;
1535 case VK_ACCESS_SHADER_READ_BIT:
1536 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1537 case VK_ACCESS_TRANSFER_READ_BIT:
1538 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1539 break;
1540 default:
1541 break; /* Nothing to do */
1542 }
1543 }
1544
1545 return pipe_bits;
1546 }
1547
1548 struct anv_vertex_binding {
1549 struct anv_buffer * buffer;
1550 VkDeviceSize offset;
1551 };
1552
1553 struct anv_push_constants {
1554 /* Current allocated size of this push constants data structure.
1555 * Because a decent chunk of it may not be used (images on SKL, for
1556 * instance), we won't actually allocate the entire structure up-front.
1557 */
1558 uint32_t size;
1559
1560 /* Push constant data provided by the client through vkPushConstants */
1561 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1562
1563 /* Our hardware only provides zero-based vertex and instance id so, in
1564 * order to satisfy the vulkan requirements, we may have to push one or
1565 * both of these into the shader.
1566 */
1567 uint32_t base_vertex;
1568 uint32_t base_instance;
1569
1570 /* Image data for image_load_store on pre-SKL */
1571 struct brw_image_param images[MAX_IMAGES];
1572 };
1573
1574 struct anv_dynamic_state {
1575 struct {
1576 uint32_t count;
1577 VkViewport viewports[MAX_VIEWPORTS];
1578 } viewport;
1579
1580 struct {
1581 uint32_t count;
1582 VkRect2D scissors[MAX_SCISSORS];
1583 } scissor;
1584
1585 float line_width;
1586
1587 struct {
1588 float bias;
1589 float clamp;
1590 float slope;
1591 } depth_bias;
1592
1593 float blend_constants[4];
1594
1595 struct {
1596 float min;
1597 float max;
1598 } depth_bounds;
1599
1600 struct {
1601 uint32_t front;
1602 uint32_t back;
1603 } stencil_compare_mask;
1604
1605 struct {
1606 uint32_t front;
1607 uint32_t back;
1608 } stencil_write_mask;
1609
1610 struct {
1611 uint32_t front;
1612 uint32_t back;
1613 } stencil_reference;
1614 };
1615
1616 extern const struct anv_dynamic_state default_dynamic_state;
1617
1618 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1619 const struct anv_dynamic_state *src,
1620 uint32_t copy_mask);
1621
1622 struct anv_surface_state {
1623 struct anv_state state;
1624 /** Address of the surface referred to by this state
1625 *
1626 * This address is relative to the start of the BO.
1627 */
1628 uint64_t address;
1629 /* Address of the aux surface, if any
1630 *
1631 * This field is 0 if and only if no aux surface exists.
1632 *
1633 * This address is relative to the start of the BO. On gen7, the bottom 12
1634 * bits of this address include extra aux information.
1635 */
1636 uint64_t aux_address;
1637 };
1638
1639 /**
1640 * Attachment state when recording a renderpass instance.
1641 *
1642 * The clear value is valid only if there exists a pending clear.
1643 */
1644 struct anv_attachment_state {
1645 enum isl_aux_usage aux_usage;
1646 enum isl_aux_usage input_aux_usage;
1647 struct anv_surface_state color;
1648 struct anv_surface_state input;
1649
1650 VkImageLayout current_layout;
1651 VkImageAspectFlags pending_clear_aspects;
1652 bool fast_clear;
1653 VkClearValue clear_value;
1654 bool clear_color_is_zero_one;
1655 bool clear_color_is_zero;
1656 };
1657
1658 /** State required while building cmd buffer */
1659 struct anv_cmd_state {
1660 /* PIPELINE_SELECT.PipelineSelection */
1661 uint32_t current_pipeline;
1662 const struct gen_l3_config * current_l3_config;
1663 uint32_t vb_dirty;
1664 anv_cmd_dirty_mask_t dirty;
1665 anv_cmd_dirty_mask_t compute_dirty;
1666 enum anv_pipe_bits pending_pipe_bits;
1667 uint32_t num_workgroups_offset;
1668 struct anv_bo *num_workgroups_bo;
1669 VkShaderStageFlags descriptors_dirty;
1670 VkShaderStageFlags push_constants_dirty;
1671 uint32_t scratch_size;
1672 struct anv_pipeline * pipeline;
1673 struct anv_pipeline * compute_pipeline;
1674 struct anv_framebuffer * framebuffer;
1675 struct anv_render_pass * pass;
1676 struct anv_subpass * subpass;
1677 VkRect2D render_area;
1678 uint32_t restart_index;
1679 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1680 struct anv_descriptor_set * descriptors[MAX_SETS];
1681 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1682 VkShaderStageFlags push_constant_stages;
1683 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1684 struct anv_state binding_tables[MESA_SHADER_STAGES];
1685 struct anv_state samplers[MESA_SHADER_STAGES];
1686 struct anv_dynamic_state dynamic;
1687 bool need_query_wa;
1688
1689 struct anv_push_descriptor_set push_descriptor;
1690
1691 /**
1692 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1693 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1694 * and before invoking the secondary in ExecuteCommands.
1695 */
1696 bool pma_fix_enabled;
1697
1698 /**
1699 * Whether or not we know for certain that HiZ is enabled for the current
1700 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1701 * enabled or not, this will be false.
1702 */
1703 bool hiz_enabled;
1704
1705 /**
1706 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1707 * valid only when recording a render pass instance.
1708 */
1709 struct anv_attachment_state * attachments;
1710
1711 /**
1712 * Surface states for color render targets. These are stored in a single
1713 * flat array. For depth-stencil attachments, the surface state is simply
1714 * left blank.
1715 */
1716 struct anv_state render_pass_states;
1717
1718 /**
1719 * A null surface state of the right size to match the framebuffer. This
1720 * is one of the states in render_pass_states.
1721 */
1722 struct anv_state null_surface_state;
1723
1724 struct {
1725 struct anv_buffer * index_buffer;
1726 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1727 uint32_t index_offset;
1728 } gen7;
1729 };
1730
1731 struct anv_cmd_pool {
1732 VkAllocationCallbacks alloc;
1733 struct list_head cmd_buffers;
1734 };
1735
1736 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1737
1738 enum anv_cmd_buffer_exec_mode {
1739 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1740 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1741 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1742 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1743 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1744 };
1745
1746 struct anv_cmd_buffer {
1747 VK_LOADER_DATA _loader_data;
1748
1749 struct anv_device * device;
1750
1751 struct anv_cmd_pool * pool;
1752 struct list_head pool_link;
1753
1754 struct anv_batch batch;
1755
1756 /* Fields required for the actual chain of anv_batch_bo's.
1757 *
1758 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1759 */
1760 struct list_head batch_bos;
1761 enum anv_cmd_buffer_exec_mode exec_mode;
1762
1763 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1764 * referenced by this command buffer
1765 *
1766 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1767 */
1768 struct u_vector seen_bbos;
1769
1770 /* A vector of int32_t's for every block of binding tables.
1771 *
1772 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1773 */
1774 struct u_vector bt_block_states;
1775 uint32_t bt_next;
1776
1777 struct anv_reloc_list surface_relocs;
1778 /** Last seen surface state block pool center bo offset */
1779 uint32_t last_ss_pool_center;
1780
1781 /* Serial for tracking buffer completion */
1782 uint32_t serial;
1783
1784 /* Stream objects for storing temporary data */
1785 struct anv_state_stream surface_state_stream;
1786 struct anv_state_stream dynamic_state_stream;
1787
1788 VkCommandBufferUsageFlags usage_flags;
1789 VkCommandBufferLevel level;
1790
1791 struct anv_cmd_state state;
1792 };
1793
1794 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1795 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1796 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1797 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1798 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1799 struct anv_cmd_buffer *secondary);
1800 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1801 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1802 struct anv_cmd_buffer *cmd_buffer,
1803 const VkSemaphore *in_semaphores,
1804 uint32_t num_in_semaphores,
1805 const VkSemaphore *out_semaphores,
1806 uint32_t num_out_semaphores,
1807 VkFence fence);
1808
1809 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1810
1811 VkResult
1812 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1813 gl_shader_stage stage, uint32_t size);
1814 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1815 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1816 (offsetof(struct anv_push_constants, field) + \
1817 sizeof(cmd_buffer->state.push_constants[0]->field)))
1818
1819 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1820 const void *data, uint32_t size, uint32_t alignment);
1821 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1822 uint32_t *a, uint32_t *b,
1823 uint32_t dwords, uint32_t alignment);
1824
1825 struct anv_address
1826 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1827 struct anv_state
1828 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1829 uint32_t entries, uint32_t *state_offset);
1830 struct anv_state
1831 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1832 struct anv_state
1833 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1834 uint32_t size, uint32_t alignment);
1835
1836 VkResult
1837 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1838
1839 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1840 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1841 bool depth_clamp_enable);
1842 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1843
1844 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1845 struct anv_render_pass *pass,
1846 struct anv_framebuffer *framebuffer,
1847 const VkClearValue *clear_values);
1848
1849 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1850
1851 struct anv_state
1852 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1853 gl_shader_stage stage);
1854 struct anv_state
1855 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1856
1857 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1858 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1859
1860 const struct anv_image_view *
1861 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1862
1863 VkResult
1864 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1865 uint32_t num_entries,
1866 uint32_t *state_offset,
1867 struct anv_state *bt_state);
1868
1869 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1870
1871 enum anv_fence_type {
1872 ANV_FENCE_TYPE_NONE = 0,
1873 ANV_FENCE_TYPE_BO,
1874 ANV_FENCE_TYPE_SYNCOBJ,
1875 };
1876
1877 enum anv_bo_fence_state {
1878 /** Indicates that this is a new (or newly reset fence) */
1879 ANV_BO_FENCE_STATE_RESET,
1880
1881 /** Indicates that this fence has been submitted to the GPU but is still
1882 * (as far as we know) in use by the GPU.
1883 */
1884 ANV_BO_FENCE_STATE_SUBMITTED,
1885
1886 ANV_BO_FENCE_STATE_SIGNALED,
1887 };
1888
1889 struct anv_fence_impl {
1890 enum anv_fence_type type;
1891
1892 union {
1893 /** Fence implementation for BO fences
1894 *
1895 * These fences use a BO and a set of CPU-tracked state flags. The BO
1896 * is added to the object list of the last execbuf call in a QueueSubmit
1897 * and is marked EXEC_WRITE. The state flags track when the BO has been
1898 * submitted to the kernel. We need to do this because Vulkan lets you
1899 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1900 * will say it's idle in this case.
1901 */
1902 struct {
1903 struct anv_bo bo;
1904 enum anv_bo_fence_state state;
1905 } bo;
1906
1907 /** DRM syncobj handle for syncobj-based fences */
1908 uint32_t syncobj;
1909 };
1910 };
1911
1912 struct anv_fence {
1913 /* Permanent fence state. Every fence has some form of permanent state
1914 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1915 * cross-process fences0 or it could just be a dummy for use internally.
1916 */
1917 struct anv_fence_impl permanent;
1918
1919 /* Temporary fence state. A fence *may* have temporary state. That state
1920 * is added to the fence by an import operation and is reset back to
1921 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1922 * state cannot be signaled because the fence must already be signaled
1923 * before the temporary state can be exported from the fence in the other
1924 * process and imported here.
1925 */
1926 struct anv_fence_impl temporary;
1927 };
1928
1929 struct anv_event {
1930 uint64_t semaphore;
1931 struct anv_state state;
1932 };
1933
1934 enum anv_semaphore_type {
1935 ANV_SEMAPHORE_TYPE_NONE = 0,
1936 ANV_SEMAPHORE_TYPE_DUMMY,
1937 ANV_SEMAPHORE_TYPE_BO,
1938 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1939 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1940 };
1941
1942 struct anv_semaphore_impl {
1943 enum anv_semaphore_type type;
1944
1945 union {
1946 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1947 * This BO will be added to the object list on any execbuf2 calls for
1948 * which this semaphore is used as a wait or signal fence. When used as
1949 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1950 */
1951 struct anv_bo *bo;
1952
1953 /* The sync file descriptor when type == AKV_SEMAPHORE_TYPE_SYNC_FILE.
1954 * If the semaphore is in the unsignaled state due to either just being
1955 * created or because it has been used for a wait, fd will be -1.
1956 */
1957 int fd;
1958
1959 /* Sync object handle when type == AKV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1960 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1961 * import so we don't need to bother with a userspace cache.
1962 */
1963 uint32_t syncobj;
1964 };
1965 };
1966
1967 struct anv_semaphore {
1968 /* Permanent semaphore state. Every semaphore has some form of permanent
1969 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1970 * (for cross-process semaphores0 or it could just be a dummy for use
1971 * internally.
1972 */
1973 struct anv_semaphore_impl permanent;
1974
1975 /* Temporary semaphore state. A semaphore *may* have temporary state.
1976 * That state is added to the semaphore by an import operation and is reset
1977 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1978 * semaphore with temporary state cannot be signaled because the semaphore
1979 * must already be signaled before the temporary state can be exported from
1980 * the semaphore in the other process and imported here.
1981 */
1982 struct anv_semaphore_impl temporary;
1983 };
1984
1985 void anv_semaphore_reset_temporary(struct anv_device *device,
1986 struct anv_semaphore *semaphore);
1987
1988 struct anv_shader_module {
1989 unsigned char sha1[20];
1990 uint32_t size;
1991 char data[0];
1992 };
1993
1994 static inline gl_shader_stage
1995 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1996 {
1997 assert(__builtin_popcount(vk_stage) == 1);
1998 return ffs(vk_stage) - 1;
1999 }
2000
2001 static inline VkShaderStageFlagBits
2002 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2003 {
2004 return (1 << mesa_stage);
2005 }
2006
2007 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2008
2009 #define anv_foreach_stage(stage, stage_bits) \
2010 for (gl_shader_stage stage, \
2011 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2012 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2013 __tmp &= ~(1 << (stage)))
2014
2015 struct anv_pipeline_bind_map {
2016 uint32_t surface_count;
2017 uint32_t sampler_count;
2018 uint32_t image_count;
2019
2020 struct anv_pipeline_binding * surface_to_descriptor;
2021 struct anv_pipeline_binding * sampler_to_descriptor;
2022 };
2023
2024 struct anv_shader_bin_key {
2025 uint32_t size;
2026 uint8_t data[0];
2027 };
2028
2029 struct anv_shader_bin {
2030 uint32_t ref_cnt;
2031
2032 const struct anv_shader_bin_key *key;
2033
2034 struct anv_state kernel;
2035 uint32_t kernel_size;
2036
2037 const struct brw_stage_prog_data *prog_data;
2038 uint32_t prog_data_size;
2039
2040 struct anv_pipeline_bind_map bind_map;
2041
2042 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
2043 };
2044
2045 struct anv_shader_bin *
2046 anv_shader_bin_create(struct anv_device *device,
2047 const void *key, uint32_t key_size,
2048 const void *kernel, uint32_t kernel_size,
2049 const struct brw_stage_prog_data *prog_data,
2050 uint32_t prog_data_size, const void *prog_data_param,
2051 const struct anv_pipeline_bind_map *bind_map);
2052
2053 void
2054 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2055
2056 static inline void
2057 anv_shader_bin_ref(struct anv_shader_bin *shader)
2058 {
2059 assert(shader && shader->ref_cnt >= 1);
2060 p_atomic_inc(&shader->ref_cnt);
2061 }
2062
2063 static inline void
2064 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2065 {
2066 assert(shader && shader->ref_cnt >= 1);
2067 if (p_atomic_dec_zero(&shader->ref_cnt))
2068 anv_shader_bin_destroy(device, shader);
2069 }
2070
2071 struct anv_pipeline {
2072 struct anv_device * device;
2073 struct anv_batch batch;
2074 uint32_t batch_data[512];
2075 struct anv_reloc_list batch_relocs;
2076 uint32_t dynamic_state_mask;
2077 struct anv_dynamic_state dynamic_state;
2078
2079 struct anv_subpass * subpass;
2080 struct anv_pipeline_layout * layout;
2081
2082 bool needs_data_cache;
2083
2084 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2085
2086 struct {
2087 const struct gen_l3_config * l3_config;
2088 uint32_t total_size;
2089 } urb;
2090
2091 VkShaderStageFlags active_stages;
2092 struct anv_state blend_state;
2093
2094 uint32_t vb_used;
2095 uint32_t binding_stride[MAX_VBS];
2096 bool instancing_enable[MAX_VBS];
2097 bool primitive_restart;
2098 uint32_t topology;
2099
2100 uint32_t cs_right_mask;
2101
2102 bool writes_depth;
2103 bool depth_test_enable;
2104 bool writes_stencil;
2105 bool stencil_test_enable;
2106 bool depth_clamp_enable;
2107 bool sample_shading_enable;
2108 bool kill_pixel;
2109
2110 struct {
2111 uint32_t sf[7];
2112 uint32_t depth_stencil_state[3];
2113 } gen7;
2114
2115 struct {
2116 uint32_t sf[4];
2117 uint32_t raster[5];
2118 uint32_t wm_depth_stencil[3];
2119 } gen8;
2120
2121 struct {
2122 uint32_t wm_depth_stencil[4];
2123 } gen9;
2124
2125 uint32_t interface_descriptor_data[8];
2126 };
2127
2128 static inline bool
2129 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2130 gl_shader_stage stage)
2131 {
2132 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2133 }
2134
2135 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2136 static inline const struct brw_##prefix##_prog_data * \
2137 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2138 { \
2139 if (anv_pipeline_has_stage(pipeline, stage)) { \
2140 return (const struct brw_##prefix##_prog_data *) \
2141 pipeline->shaders[stage]->prog_data; \
2142 } else { \
2143 return NULL; \
2144 } \
2145 }
2146
2147 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2148 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2149 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2150 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2151 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2152 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2153
2154 static inline const struct brw_vue_prog_data *
2155 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2156 {
2157 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2158 return &get_gs_prog_data(pipeline)->base;
2159 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2160 return &get_tes_prog_data(pipeline)->base;
2161 else
2162 return &get_vs_prog_data(pipeline)->base;
2163 }
2164
2165 VkResult
2166 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2167 struct anv_pipeline_cache *cache,
2168 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2169 const VkAllocationCallbacks *alloc);
2170
2171 VkResult
2172 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2173 struct anv_pipeline_cache *cache,
2174 const VkComputePipelineCreateInfo *info,
2175 struct anv_shader_module *module,
2176 const char *entrypoint,
2177 const VkSpecializationInfo *spec_info);
2178
2179 struct anv_format {
2180 enum isl_format isl_format:16;
2181 struct isl_swizzle swizzle;
2182 };
2183
2184 struct anv_format
2185 anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
2186 VkImageAspectFlags aspect, VkImageTiling tiling);
2187
2188 static inline enum isl_format
2189 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2190 VkImageAspectFlags aspect, VkImageTiling tiling)
2191 {
2192 return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
2193 }
2194
2195 static inline struct isl_swizzle
2196 anv_swizzle_for_render(struct isl_swizzle swizzle)
2197 {
2198 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2199 * RGB as RGBA for texturing
2200 */
2201 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2202 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2203
2204 /* But it doesn't matter what we render to that channel */
2205 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2206
2207 return swizzle;
2208 }
2209
2210 void
2211 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2212
2213 /**
2214 * Subsurface of an anv_image.
2215 */
2216 struct anv_surface {
2217 /** Valid only if isl_surf::size > 0. */
2218 struct isl_surf isl;
2219
2220 /**
2221 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2222 */
2223 uint32_t offset;
2224 };
2225
2226 struct anv_image {
2227 VkImageType type;
2228 /* The original VkFormat provided by the client. This may not match any
2229 * of the actual surface formats.
2230 */
2231 VkFormat vk_format;
2232 VkImageAspectFlags aspects;
2233 VkExtent3D extent;
2234 uint32_t levels;
2235 uint32_t array_size;
2236 uint32_t samples; /**< VkImageCreateInfo::samples */
2237 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2238 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2239
2240 VkDeviceSize size;
2241 uint32_t alignment;
2242
2243 /* Set when bound */
2244 struct anv_bo *bo;
2245 VkDeviceSize offset;
2246
2247 /**
2248 * Image subsurfaces
2249 *
2250 * For each foo, anv_image::foo_surface is valid if and only if
2251 * anv_image::aspects has a foo aspect.
2252 *
2253 * The hardware requires that the depth buffer and stencil buffer be
2254 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2255 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2256 * allocate the depth and stencil buffers as separate surfaces in the same
2257 * bo.
2258 */
2259 union {
2260 struct anv_surface color_surface;
2261
2262 struct {
2263 struct anv_surface depth_surface;
2264 struct anv_surface stencil_surface;
2265 };
2266 };
2267
2268 /**
2269 * For color images, this is the aux usage for this image when not used as a
2270 * color attachment.
2271 *
2272 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
2273 * has a HiZ buffer.
2274 */
2275 enum isl_aux_usage aux_usage;
2276
2277 struct anv_surface aux_surface;
2278 };
2279
2280 /* Returns the number of auxiliary buffer levels attached to an image. */
2281 static inline uint8_t
2282 anv_image_aux_levels(const struct anv_image * const image)
2283 {
2284 assert(image);
2285 return image->aux_surface.isl.size > 0 ? image->aux_surface.isl.levels : 0;
2286 }
2287
2288 /* Returns the number of auxiliary buffer layers attached to an image. */
2289 static inline uint32_t
2290 anv_image_aux_layers(const struct anv_image * const image,
2291 const uint8_t miplevel)
2292 {
2293 assert(image);
2294
2295 /* The miplevel must exist in the main buffer. */
2296 assert(miplevel < image->levels);
2297
2298 if (miplevel >= anv_image_aux_levels(image)) {
2299 /* There are no layers with auxiliary data because the miplevel has no
2300 * auxiliary data.
2301 */
2302 return 0;
2303 } else {
2304 return MAX2(image->aux_surface.isl.logical_level0_px.array_len,
2305 image->aux_surface.isl.logical_level0_px.depth >> miplevel);
2306 }
2307 }
2308
2309 static inline unsigned
2310 anv_fast_clear_state_entry_size(const struct anv_device *device)
2311 {
2312 assert(device);
2313 /* Entry contents:
2314 * +--------------------------------------------+
2315 * | clear value dword(s) | needs resolve dword |
2316 * +--------------------------------------------+
2317 */
2318
2319 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2320 * GPU memcpy operations.
2321 */
2322 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2323 return device->isl_dev.ss.clear_value_size + 4;
2324 }
2325
2326 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2327 static inline bool
2328 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2329 const VkImageAspectFlags aspect_mask,
2330 const uint32_t samples)
2331 {
2332 /* Validate the inputs. */
2333 assert(devinfo && aspect_mask && samples);
2334 return devinfo->gen >= 8 && (aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2335 samples == 1;
2336 }
2337
2338 void
2339 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2340 const struct anv_image *image,
2341 enum blorp_hiz_op op);
2342 void
2343 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2344 const struct anv_state surface_state,
2345 const struct anv_image * const image,
2346 const uint8_t level, const uint32_t layer_count,
2347 const enum blorp_fast_clear_op op);
2348
2349 void
2350 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2351 const struct anv_image *image,
2352 const uint32_t base_level, const uint32_t level_count,
2353 const uint32_t base_layer, uint32_t layer_count);
2354
2355 enum isl_aux_usage
2356 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2357 const struct anv_image *image,
2358 const VkImageAspectFlags aspects,
2359 const VkImageLayout layout);
2360
2361 /* This is defined as a macro so that it works for both
2362 * VkImageSubresourceRange and VkImageSubresourceLayers
2363 */
2364 #define anv_get_layerCount(_image, _range) \
2365 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2366 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2367
2368 static inline uint32_t
2369 anv_get_levelCount(const struct anv_image *image,
2370 const VkImageSubresourceRange *range)
2371 {
2372 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2373 image->levels - range->baseMipLevel : range->levelCount;
2374 }
2375
2376
2377 struct anv_image_view {
2378 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2379
2380 struct isl_view isl;
2381
2382 VkImageAspectFlags aspect_mask;
2383 VkFormat vk_format;
2384 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2385
2386 /**
2387 * RENDER_SURFACE_STATE when using image as a sampler surface with an image
2388 * layout of SHADER_READ_ONLY_OPTIMAL or DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2389 */
2390 struct anv_surface_state optimal_sampler_surface_state;
2391
2392 /**
2393 * RENDER_SURFACE_STATE when using image as a sampler surface with an image
2394 * layout of GENERAL.
2395 */
2396 struct anv_surface_state general_sampler_surface_state;
2397
2398 /**
2399 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
2400 * for write-only and readable, using the real format for write-only and the
2401 * lowered format for readable.
2402 */
2403 struct anv_surface_state storage_surface_state;
2404 struct anv_surface_state writeonly_storage_surface_state;
2405
2406 struct brw_image_param storage_image_param;
2407 };
2408
2409 enum anv_image_view_state_flags {
2410 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2411 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2412 };
2413
2414 void anv_image_fill_surface_state(struct anv_device *device,
2415 const struct anv_image *image,
2416 VkImageAspectFlagBits aspect,
2417 const struct isl_view *view,
2418 isl_surf_usage_flags_t view_usage,
2419 enum isl_aux_usage aux_usage,
2420 const union isl_color_value *clear_color,
2421 enum anv_image_view_state_flags flags,
2422 struct anv_surface_state *state_inout,
2423 struct brw_image_param *image_param_out);
2424
2425 struct anv_image_create_info {
2426 const VkImageCreateInfo *vk_info;
2427
2428 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2429 isl_tiling_flags_t isl_tiling_flags;
2430
2431 uint32_t stride;
2432 };
2433
2434 VkResult anv_image_create(VkDevice _device,
2435 const struct anv_image_create_info *info,
2436 const VkAllocationCallbacks* alloc,
2437 VkImage *pImage);
2438
2439 const struct anv_surface *
2440 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2441 VkImageAspectFlags aspect_mask);
2442
2443 enum isl_format
2444 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2445
2446 static inline struct VkExtent3D
2447 anv_sanitize_image_extent(const VkImageType imageType,
2448 const struct VkExtent3D imageExtent)
2449 {
2450 switch (imageType) {
2451 case VK_IMAGE_TYPE_1D:
2452 return (VkExtent3D) { imageExtent.width, 1, 1 };
2453 case VK_IMAGE_TYPE_2D:
2454 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2455 case VK_IMAGE_TYPE_3D:
2456 return imageExtent;
2457 default:
2458 unreachable("invalid image type");
2459 }
2460 }
2461
2462 static inline struct VkOffset3D
2463 anv_sanitize_image_offset(const VkImageType imageType,
2464 const struct VkOffset3D imageOffset)
2465 {
2466 switch (imageType) {
2467 case VK_IMAGE_TYPE_1D:
2468 return (VkOffset3D) { imageOffset.x, 0, 0 };
2469 case VK_IMAGE_TYPE_2D:
2470 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2471 case VK_IMAGE_TYPE_3D:
2472 return imageOffset;
2473 default:
2474 unreachable("invalid image type");
2475 }
2476 }
2477
2478
2479 void anv_fill_buffer_surface_state(struct anv_device *device,
2480 struct anv_state state,
2481 enum isl_format format,
2482 uint32_t offset, uint32_t range,
2483 uint32_t stride);
2484
2485 struct anv_sampler {
2486 uint32_t state[4];
2487 };
2488
2489 struct anv_framebuffer {
2490 uint32_t width;
2491 uint32_t height;
2492 uint32_t layers;
2493
2494 uint32_t attachment_count;
2495 struct anv_image_view * attachments[0];
2496 };
2497
2498 struct anv_subpass {
2499 uint32_t attachment_count;
2500
2501 /**
2502 * A pointer to all attachment references used in this subpass.
2503 * Only valid if ::attachment_count > 0.
2504 */
2505 VkAttachmentReference * attachments;
2506 uint32_t input_count;
2507 VkAttachmentReference * input_attachments;
2508 uint32_t color_count;
2509 VkAttachmentReference * color_attachments;
2510 VkAttachmentReference * resolve_attachments;
2511
2512 VkAttachmentReference depth_stencil_attachment;
2513
2514 uint32_t view_mask;
2515
2516 /** Subpass has a depth/stencil self-dependency */
2517 bool has_ds_self_dep;
2518
2519 /** Subpass has at least one resolve attachment */
2520 bool has_resolve;
2521 };
2522
2523 static inline unsigned
2524 anv_subpass_view_count(const struct anv_subpass *subpass)
2525 {
2526 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2527 }
2528
2529 struct anv_render_pass_attachment {
2530 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2531 * its members individually.
2532 */
2533 VkFormat format;
2534 uint32_t samples;
2535 VkImageUsageFlags usage;
2536 VkAttachmentLoadOp load_op;
2537 VkAttachmentStoreOp store_op;
2538 VkAttachmentLoadOp stencil_load_op;
2539 VkImageLayout initial_layout;
2540 VkImageLayout final_layout;
2541 VkImageLayout first_subpass_layout;
2542
2543 /* The subpass id in which the attachment will be used last. */
2544 uint32_t last_subpass_idx;
2545 };
2546
2547 struct anv_render_pass {
2548 uint32_t attachment_count;
2549 uint32_t subpass_count;
2550 /* An array of subpass_count+1 flushes, one per subpass boundary */
2551 enum anv_pipe_bits * subpass_flushes;
2552 struct anv_render_pass_attachment * attachments;
2553 struct anv_subpass subpasses[0];
2554 };
2555
2556 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2557
2558 struct anv_query_pool {
2559 VkQueryType type;
2560 VkQueryPipelineStatisticFlags pipeline_statistics;
2561 /** Stride between slots, in bytes */
2562 uint32_t stride;
2563 /** Number of slots in this query pool */
2564 uint32_t slots;
2565 struct anv_bo bo;
2566 };
2567
2568 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2569 const char *name);
2570
2571 void anv_dump_image_to_ppm(struct anv_device *device,
2572 struct anv_image *image, unsigned miplevel,
2573 unsigned array_layer, VkImageAspectFlagBits aspect,
2574 const char *filename);
2575
2576 enum anv_dump_action {
2577 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2578 };
2579
2580 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2581 void anv_dump_finish(void);
2582
2583 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2584 struct anv_framebuffer *fb);
2585
2586 static inline uint32_t
2587 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2588 {
2589 /* This function must be called from within a subpass. */
2590 assert(cmd_state->pass && cmd_state->subpass);
2591
2592 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2593
2594 /* The id of this subpass shouldn't exceed the number of subpasses in this
2595 * render pass minus 1.
2596 */
2597 assert(subpass_id < cmd_state->pass->subpass_count);
2598 return subpass_id;
2599 }
2600
2601 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2602 \
2603 static inline struct __anv_type * \
2604 __anv_type ## _from_handle(__VkType _handle) \
2605 { \
2606 return (struct __anv_type *) _handle; \
2607 } \
2608 \
2609 static inline __VkType \
2610 __anv_type ## _to_handle(struct __anv_type *_obj) \
2611 { \
2612 return (__VkType) _obj; \
2613 }
2614
2615 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2616 \
2617 static inline struct __anv_type * \
2618 __anv_type ## _from_handle(__VkType _handle) \
2619 { \
2620 return (struct __anv_type *)(uintptr_t) _handle; \
2621 } \
2622 \
2623 static inline __VkType \
2624 __anv_type ## _to_handle(struct __anv_type *_obj) \
2625 { \
2626 return (__VkType)(uintptr_t) _obj; \
2627 }
2628
2629 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2630 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2631
2632 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2633 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2634 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2635 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2636 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2637
2638 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2639 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2640 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2641 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2642 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2643 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2644 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2645 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2646 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2647 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2648 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2649 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2650 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2651 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2652 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2653 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2654 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2655 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2656 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2657 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2658 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2659 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_debug_report_callback, VkDebugReportCallbackEXT)
2660
2661 /* Gen-specific function declarations */
2662 #ifdef genX
2663 # include "anv_genX.h"
2664 #else
2665 # define genX(x) gen7_##x
2666 # include "anv_genX.h"
2667 # undef genX
2668 # define genX(x) gen75_##x
2669 # include "anv_genX.h"
2670 # undef genX
2671 # define genX(x) gen8_##x
2672 # include "anv_genX.h"
2673 # undef genX
2674 # define genX(x) gen9_##x
2675 # include "anv_genX.h"
2676 # undef genX
2677 # define genX(x) gen10_##x
2678 # include "anv_genX.h"
2679 # undef genX
2680 #endif
2681
2682 #endif /* ANV_PRIVATE_H */