2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
60 #include "util/xmlconfig.h"
62 #include "vk_debug_report.h"
64 /* Pre-declarations needed for WSI entrypoints */
67 typedef struct xcb_connection_t xcb_connection_t
;
68 typedef uint32_t xcb_visualid_t
;
69 typedef uint32_t xcb_window_t
;
72 struct anv_buffer_view
;
73 struct anv_image_view
;
76 struct gen_aux_map_context
;
78 struct gen_perf_config
;
80 #include <vulkan/vulkan.h>
81 #include <vulkan/vulkan_intel.h>
82 #include <vulkan/vk_icd.h>
84 #include "anv_android.h"
85 #include "anv_entrypoints.h"
86 #include "anv_extensions.h"
89 #include "dev/gen_debug.h"
90 #include "common/intel_log.h"
91 #include "wsi_common.h"
93 /* anv Virtual Memory Layout
94 * =========================
96 * When the anv driver is determining the virtual graphics addresses of memory
97 * objects itself using the softpin mechanism, the following memory ranges
100 * Three special considerations to notice:
102 * (1) the dynamic state pool is located within the same 4 GiB as the low
103 * heap. This is to work around a VF cache issue described in a comment in
104 * anv_physical_device_init_heaps.
106 * (2) the binding table pool is located at lower addresses than the surface
107 * state pool, within a 4 GiB range. This allows surface state base addresses
108 * to cover both binding tables (16 bit offsets) and surface states (32 bit
111 * (3) the last 4 GiB of the address space is withheld from the high
112 * heap. Various hardware units will read past the end of an object for
113 * various reasons. This healthy margin prevents reads from wrapping around
116 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
117 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
118 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
119 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
120 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
121 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
122 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
123 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
124 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
125 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
126 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
128 #define LOW_HEAP_SIZE \
129 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
130 #define DYNAMIC_STATE_POOL_SIZE \
131 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
132 #define BINDING_TABLE_POOL_SIZE \
133 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
134 #define SURFACE_STATE_POOL_SIZE \
135 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
136 #define INSTRUCTION_STATE_POOL_SIZE \
137 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
139 /* Allowing different clear colors requires us to perform a depth resolve at
140 * the end of certain render passes. This is because while slow clears store
141 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
142 * See the PRMs for examples describing when additional resolves would be
143 * necessary. To enable fast clears without requiring extra resolves, we set
144 * the clear value to a globally-defined one. We could allow different values
145 * if the user doesn't expect coherent data during or after a render passes
146 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
147 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
148 * 1.0f seems to be the only value used. The only application that doesn't set
149 * this value does so through the usage of an seemingly uninitialized clear
152 #define ANV_HZ_FC_VAL 1.0f
155 #define MAX_XFB_BUFFERS 4
156 #define MAX_XFB_STREAMS 4
159 #define MAX_VIEWPORTS 16
160 #define MAX_SCISSORS 16
161 #define MAX_PUSH_CONSTANTS_SIZE 128
162 #define MAX_DYNAMIC_BUFFERS 16
163 #define MAX_IMAGES 64
164 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
165 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
166 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
168 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
170 * "The surface state model is used when a Binding Table Index (specified
171 * in the message descriptor) of less than 240 is specified. In this model,
172 * the Binding Table Index is used to index into the binding table, and the
173 * binding table entry contains a pointer to the SURFACE_STATE."
175 * Binding table values above 240 are used for various things in the hardware
176 * such as stateless, stateless with incoherent cache, SLM, and bindless.
178 #define MAX_BINDING_TABLE_SIZE 240
180 /* The kernel relocation API has a limitation of a 32-bit delta value
181 * applied to the address before it is written which, in spite of it being
182 * unsigned, is treated as signed . Because of the way that this maps to
183 * the Vulkan API, we cannot handle an offset into a buffer that does not
184 * fit into a signed 32 bits. The only mechanism we have for dealing with
185 * this at the moment is to limit all VkDeviceMemory objects to a maximum
186 * of 2GB each. The Vulkan spec allows us to do this:
188 * "Some platforms may have a limit on the maximum size of a single
189 * allocation. For example, certain systems may fail to create
190 * allocations with a size greater than or equal to 4GB. Such a limit is
191 * implementation-dependent, and if such a failure occurs then the error
192 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
194 * We don't use vk_error here because it's not an error so much as an
195 * indication to the application that the allocation is too large.
197 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
199 #define ANV_SVGS_VB_INDEX MAX_VBS
200 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
202 /* We reserve this MI ALU register for the purpose of handling predication.
203 * Other code which uses the MI ALU should leave it alone.
205 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
207 /* For gen12 we set the streamout buffers using 4 separate commands
208 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
209 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
210 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
211 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
212 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
213 * 3DSTATE_SO_BUFFER_INDEX_0.
215 #define SO_BUFFER_INDEX_0_CMD 0x60
216 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
218 static inline uint32_t
219 align_down_npot_u32(uint32_t v
, uint32_t a
)
224 static inline uint32_t
225 align_u32(uint32_t v
, uint32_t a
)
227 assert(a
!= 0 && a
== (a
& -a
));
228 return (v
+ a
- 1) & ~(a
- 1);
231 static inline uint64_t
232 align_u64(uint64_t v
, uint64_t a
)
234 assert(a
!= 0 && a
== (a
& -a
));
235 return (v
+ a
- 1) & ~(a
- 1);
238 static inline int32_t
239 align_i32(int32_t v
, int32_t a
)
241 assert(a
!= 0 && a
== (a
& -a
));
242 return (v
+ a
- 1) & ~(a
- 1);
245 /** Alignment must be a power of 2. */
247 anv_is_aligned(uintmax_t n
, uintmax_t a
)
249 assert(a
== (a
& -a
));
250 return (n
& (a
- 1)) == 0;
253 static inline uint32_t
254 anv_minify(uint32_t n
, uint32_t levels
)
256 if (unlikely(n
== 0))
259 return MAX2(n
>> levels
, 1);
263 anv_clamp_f(float f
, float min
, float max
)
276 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
278 if (*inout_mask
& clear_mask
) {
279 *inout_mask
&= ~clear_mask
;
286 static inline union isl_color_value
287 vk_to_isl_color(VkClearColorValue color
)
289 return (union isl_color_value
) {
299 #define for_each_bit(b, dword) \
300 for (uint32_t __dword = (dword); \
301 (b) = __builtin_ffs(__dword) - 1, __dword; \
302 __dword &= ~(1 << (b)))
304 #define typed_memcpy(dest, src, count) ({ \
305 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
306 memcpy((dest), (src), (count) * sizeof(*(src))); \
309 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
310 * to be added here in order to utilize mapping in debug/error/perf macros.
312 #define REPORT_OBJECT_TYPE(o) \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
376 __builtin_choose_expr ( \
377 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
378 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
379 __builtin_choose_expr ( \
380 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
381 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
382 __builtin_choose_expr ( \
383 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
384 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
385 __builtin_choose_expr ( \
386 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
387 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
388 __builtin_choose_expr ( \
389 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
390 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
391 __builtin_choose_expr ( \
392 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
393 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
394 __builtin_choose_expr ( \
395 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
396 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
397 __builtin_choose_expr ( \
398 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
399 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
400 __builtin_choose_expr ( \
401 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
402 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
403 __builtin_choose_expr ( \
404 __builtin_types_compatible_p (__typeof (o), void*), \
405 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
406 /* The void expression results in a compile-time error \
407 when assigning the result to something. */ \
408 (void)0)))))))))))))))))))))))))))))))
410 /* Whenever we generate an error, pass it through this function. Useful for
411 * debugging, where we can break on it. Only call at error site, not when
412 * propagating errors. Might be useful to plug in a stack trace here.
415 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
416 VkDebugReportObjectTypeEXT type
, VkResult error
,
417 const char *file
, int line
, const char *format
,
420 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
421 VkDebugReportObjectTypeEXT type
, VkResult error
,
422 const char *file
, int line
, const char *format
, ...)
423 anv_printflike(7, 8);
426 #define vk_error(error) __vk_errorf(NULL, NULL,\
427 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
428 error, __FILE__, __LINE__, NULL)
429 #define vk_errorv(instance, obj, error, format, args)\
430 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
431 __FILE__, __LINE__, format, args)
432 #define vk_errorf(instance, obj, error, format, ...)\
433 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
434 __FILE__, __LINE__, format, ## __VA_ARGS__)
436 #define vk_error(error) error
437 #define vk_errorf(instance, obj, error, format, ...) error
441 * Warn on ignored extension structs.
443 * The Vulkan spec requires us to ignore unsupported or unknown structs in
444 * a pNext chain. In debug mode, emitting warnings for ignored structs may
445 * help us discover structs that we should not have ignored.
448 * From the Vulkan 1.0.38 spec:
450 * Any component of the implementation (the loader, any enabled layers,
451 * and drivers) must skip over, without processing (other than reading the
452 * sType and pNext members) any chained structures with sType values not
453 * defined by extensions supported by that component.
455 #define anv_debug_ignored_stype(sType) \
456 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
458 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
459 VkDebugReportObjectTypeEXT type
, const char *file
,
460 int line
, const char *format
, ...)
461 anv_printflike(6, 7);
462 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
463 void anv_loge_v(const char *format
, va_list va
);
466 * Print a FINISHME message, including its source location.
468 #define anv_finishme(format, ...) \
470 static bool reported = false; \
472 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
479 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
481 #define anv_perf_warn(instance, obj, format, ...) \
483 static bool reported = false; \
484 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
485 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
486 format, ##__VA_ARGS__); \
491 /* A non-fatal assert. Useful for debugging. */
493 #define anv_assert(x) ({ \
494 if (unlikely(!(x))) \
495 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
498 #define anv_assert(x)
501 /* A multi-pointer allocator
503 * When copying data structures from the user (such as a render pass), it's
504 * common to need to allocate data for a bunch of different things. Instead
505 * of doing several allocations and having to handle all of the error checking
506 * that entails, it can be easier to do a single allocation. This struct
507 * helps facilitate that. The intended usage looks like this:
510 * anv_multialloc_add(&ma, &main_ptr, 1);
511 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
512 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
514 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
515 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
517 struct anv_multialloc
{
525 #define ANV_MULTIALLOC_INIT \
526 ((struct anv_multialloc) { 0, })
528 #define ANV_MULTIALLOC(_name) \
529 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
531 __attribute__((always_inline
))
533 _anv_multialloc_add(struct anv_multialloc
*ma
,
534 void **ptr
, size_t size
, size_t align
)
536 size_t offset
= align_u64(ma
->size
, align
);
537 ma
->size
= offset
+ size
;
538 ma
->align
= MAX2(ma
->align
, align
);
540 /* Store the offset in the pointer. */
541 *ptr
= (void *)(uintptr_t)offset
;
543 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
544 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
547 #define anv_multialloc_add_size(_ma, _ptr, _size) \
548 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
550 #define anv_multialloc_add(_ma, _ptr, _count) \
551 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
553 __attribute__((always_inline
))
555 anv_multialloc_alloc(struct anv_multialloc
*ma
,
556 const VkAllocationCallbacks
*alloc
,
557 VkSystemAllocationScope scope
)
559 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
563 /* Fill out each of the pointers with their final value.
565 * for (uint32_t i = 0; i < ma->ptr_count; i++)
566 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
568 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
569 * constant, GCC is incapable of figuring this out and unrolling the loop
570 * so we have to give it a little help.
572 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
573 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
574 if ((_i) < ma->ptr_count) \
575 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
576 _ANV_MULTIALLOC_UPDATE_POINTER(0);
577 _ANV_MULTIALLOC_UPDATE_POINTER(1);
578 _ANV_MULTIALLOC_UPDATE_POINTER(2);
579 _ANV_MULTIALLOC_UPDATE_POINTER(3);
580 _ANV_MULTIALLOC_UPDATE_POINTER(4);
581 _ANV_MULTIALLOC_UPDATE_POINTER(5);
582 _ANV_MULTIALLOC_UPDATE_POINTER(6);
583 _ANV_MULTIALLOC_UPDATE_POINTER(7);
584 #undef _ANV_MULTIALLOC_UPDATE_POINTER
589 __attribute__((always_inline
))
591 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
592 const VkAllocationCallbacks
*parent_alloc
,
593 const VkAllocationCallbacks
*alloc
,
594 VkSystemAllocationScope scope
)
596 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
599 /* Extra ANV-defined BO flags which won't be passed to the kernel */
600 #define ANV_BO_EXTERNAL (1ull << 31)
601 #define ANV_BO_FLAG_MASK (1ull << 31)
606 /* Index into the current validation list. This is used by the
607 * validation list building alrogithm to track which buffers are already
608 * in the validation list so that we can ensure uniqueness.
612 /* Last known offset. This value is provided by the kernel when we
613 * execbuf and is used as the presumed offset for the next bunch of
621 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
626 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
628 bo
->gem_handle
= gem_handle
;
636 /* Represents a lock-free linked list of "free" things. This is used by
637 * both the block pool and the state pools. Unfortunately, in order to
638 * solve the ABA problem, we can't use a single uint32_t head.
640 union anv_free_list
{
644 /* A simple count that is incremented every time the head changes. */
647 /* Make sure it's aligned to 64 bits. This will make atomic operations
648 * faster on 32 bit platforms.
650 uint64_t u64
__attribute__ ((aligned (8)));
653 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
655 struct anv_block_state
{
661 /* Make sure it's aligned to 64 bits. This will make atomic operations
662 * faster on 32 bit platforms.
664 uint64_t u64
__attribute__ ((aligned (8)));
668 #define anv_block_pool_foreach_bo(bo, pool) \
669 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
671 #define ANV_MAX_BLOCK_POOL_BOS 20
673 struct anv_block_pool
{
674 struct anv_device
*device
;
678 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
684 /* The address where the start of the pool is pinned. The various bos that
685 * are created as the pool grows will have addresses in the range
686 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
688 uint64_t start_address
;
690 /* The offset from the start of the bo to the "center" of the block
691 * pool. Pointers to allocated blocks are given by
692 * bo.map + center_bo_offset + offsets.
694 uint32_t center_bo_offset
;
696 /* Current memory map of the block pool. This pointer may or may not
697 * point to the actual beginning of the block pool memory. If
698 * anv_block_pool_alloc_back has ever been called, then this pointer
699 * will point to the "center" position of the buffer and all offsets
700 * (negative or positive) given out by the block pool alloc functions
701 * will be valid relative to this pointer.
703 * In particular, map == bo.map + center_offset
705 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
706 * since it will handle the softpin case as well, where this points to NULL.
712 * Array of mmaps and gem handles owned by the block pool, reclaimed when
713 * the block pool is destroyed.
715 struct u_vector mmap_cleanups
;
717 struct anv_block_state state
;
719 struct anv_block_state back_state
;
722 /* Block pools are backed by a fixed-size 1GB memfd */
723 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
725 /* The center of the block pool is also the middle of the memfd. This may
726 * change in the future if we decide differently for some reason.
728 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
730 static inline uint32_t
731 anv_block_pool_size(struct anv_block_pool
*pool
)
733 return pool
->state
.end
+ pool
->back_state
.end
;
743 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
745 struct anv_fixed_size_state_pool
{
746 union anv_free_list free_list
;
747 struct anv_block_state block
;
750 #define ANV_MIN_STATE_SIZE_LOG2 6
751 #define ANV_MAX_STATE_SIZE_LOG2 21
753 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
755 struct anv_free_entry
{
757 struct anv_state state
;
760 struct anv_state_table
{
761 struct anv_device
*device
;
763 struct anv_free_entry
*map
;
765 struct anv_block_state state
;
766 struct u_vector cleanups
;
769 struct anv_state_pool
{
770 struct anv_block_pool block_pool
;
772 struct anv_state_table table
;
774 /* The size of blocks which will be allocated from the block pool */
777 /** Free list for "back" allocations */
778 union anv_free_list back_alloc_free_list
;
780 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
783 struct anv_state_stream_block
;
785 struct anv_state_stream
{
786 struct anv_state_pool
*state_pool
;
788 /* The size of blocks to allocate from the state pool */
791 /* Current block we're allocating from */
792 struct anv_state block
;
794 /* Offset into the current block at which to allocate the next state */
797 /* List of all blocks allocated from this pool */
798 struct anv_state_stream_block
*block_list
;
801 /* The block_pool functions exported for testing only. The block pool should
802 * only be used via a state pool (see below).
804 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
805 struct anv_device
*device
,
806 uint64_t start_address
,
807 uint32_t initial_size
,
809 void anv_block_pool_finish(struct anv_block_pool
*pool
);
810 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
811 uint32_t block_size
, uint32_t *padding
);
812 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
813 uint32_t block_size
);
814 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
816 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
817 struct anv_device
*device
,
818 uint64_t start_address
,
821 void anv_state_pool_finish(struct anv_state_pool
*pool
);
822 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
823 uint32_t state_size
, uint32_t alignment
);
824 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
825 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
826 void anv_state_stream_init(struct anv_state_stream
*stream
,
827 struct anv_state_pool
*state_pool
,
828 uint32_t block_size
);
829 void anv_state_stream_finish(struct anv_state_stream
*stream
);
830 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
831 uint32_t size
, uint32_t alignment
);
833 VkResult
anv_state_table_init(struct anv_state_table
*table
,
834 struct anv_device
*device
,
835 uint32_t initial_entries
);
836 void anv_state_table_finish(struct anv_state_table
*table
);
837 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
839 void anv_free_list_push(union anv_free_list
*list
,
840 struct anv_state_table
*table
,
841 uint32_t idx
, uint32_t count
);
842 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
843 struct anv_state_table
*table
);
846 static inline struct anv_state
*
847 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
849 return &table
->map
[idx
].state
;
852 * Implements a pool of re-usable BOs. The interface is identical to that
853 * of block_pool except that each block is its own BO.
856 struct anv_device
*device
;
863 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
865 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
866 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
868 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
870 struct anv_scratch_bo
{
875 struct anv_scratch_pool
{
876 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
877 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
880 void anv_scratch_pool_init(struct anv_device
*device
,
881 struct anv_scratch_pool
*pool
);
882 void anv_scratch_pool_finish(struct anv_device
*device
,
883 struct anv_scratch_pool
*pool
);
884 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
885 struct anv_scratch_pool
*pool
,
886 gl_shader_stage stage
,
887 unsigned per_thread_scratch
);
889 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
890 struct anv_bo_cache
{
891 struct hash_table
*bo_map
;
892 pthread_mutex_t mutex
;
895 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
896 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
897 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
898 struct anv_bo_cache
*cache
,
899 uint64_t size
, uint64_t bo_flags
,
901 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
902 struct anv_bo_cache
*cache
,
903 void *host_ptr
, uint32_t size
,
904 uint64_t bo_flags
, struct anv_bo
**bo_out
);
905 VkResult
anv_bo_cache_import(struct anv_device
*device
,
906 struct anv_bo_cache
*cache
,
907 int fd
, uint64_t bo_flags
,
909 VkResult
anv_bo_cache_export(struct anv_device
*device
,
910 struct anv_bo_cache
*cache
,
911 struct anv_bo
*bo_in
, int *fd_out
);
912 void anv_bo_cache_release(struct anv_device
*device
,
913 struct anv_bo_cache
*cache
,
916 struct anv_memory_type
{
917 /* Standard bits passed on to the client */
918 VkMemoryPropertyFlags propertyFlags
;
921 /* Driver-internal book-keeping */
922 VkBufferUsageFlags valid_buffer_usage
;
925 struct anv_memory_heap
{
926 /* Standard bits passed on to the client */
928 VkMemoryHeapFlags flags
;
930 /* Driver-internal book-keeping */
933 bool supports_48bit_addresses
;
937 struct anv_physical_device
{
938 VK_LOADER_DATA _loader_data
;
940 struct anv_instance
* instance
;
951 struct gen_device_info info
;
952 /** Amount of "GPU memory" we want to advertise
954 * Clearly, this value is bogus since Intel is a UMA architecture. On
955 * gen7 platforms, we are limited by GTT size unless we want to implement
956 * fine-grained tracking and GTT splitting. On Broadwell and above we are
957 * practically unlimited. However, we will never report more than 3/4 of
958 * the total system ram to try and avoid running out of RAM.
960 bool supports_48bit_addresses
;
961 struct brw_compiler
* compiler
;
962 struct isl_device isl_dev
;
963 struct gen_perf_config
* perf
;
964 int cmd_parser_version
;
966 bool has_exec_capture
;
969 bool has_syncobj_wait
;
970 bool has_context_priority
;
972 bool has_context_isolation
;
973 bool has_mem_available
;
974 bool always_use_bindless
;
976 /** True if we can access buffers using A64 messages */
977 bool has_a64_buffer_access
;
978 /** True if we can use bindless access for images */
979 bool has_bindless_images
;
980 /** True if we can use bindless access for samplers */
981 bool has_bindless_samplers
;
983 struct anv_device_extension_table supported_extensions
;
984 struct anv_physical_device_dispatch_table dispatch
;
987 uint32_t subslice_total
;
991 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
993 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
996 uint8_t driver_build_sha1
[20];
997 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
998 uint8_t driver_uuid
[VK_UUID_SIZE
];
999 uint8_t device_uuid
[VK_UUID_SIZE
];
1001 struct disk_cache
* disk_cache
;
1003 struct wsi_device wsi_device
;
1008 struct anv_app_info
{
1009 const char* app_name
;
1010 uint32_t app_version
;
1011 const char* engine_name
;
1012 uint32_t engine_version
;
1013 uint32_t api_version
;
1016 struct anv_instance
{
1017 VK_LOADER_DATA _loader_data
;
1019 VkAllocationCallbacks alloc
;
1021 struct anv_app_info app_info
;
1023 struct anv_instance_extension_table enabled_extensions
;
1024 struct anv_instance_dispatch_table dispatch
;
1025 struct anv_device_dispatch_table device_dispatch
;
1027 int physicalDeviceCount
;
1028 struct anv_physical_device physicalDevice
;
1030 bool pipeline_cache_enabled
;
1032 struct vk_debug_report_instance debug_report_callbacks
;
1034 struct driOptionCache dri_options
;
1035 struct driOptionCache available_dri_options
;
1038 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1039 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1041 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1042 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1046 VK_LOADER_DATA _loader_data
;
1048 struct anv_device
* device
;
1050 VkDeviceQueueCreateFlags flags
;
1053 struct anv_pipeline_cache
{
1054 struct anv_device
* device
;
1055 pthread_mutex_t mutex
;
1057 struct hash_table
* nir_cache
;
1059 struct hash_table
* cache
;
1062 struct nir_xfb_info
;
1063 struct anv_pipeline_bind_map
;
1065 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1066 struct anv_device
*device
,
1067 bool cache_enabled
);
1068 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1070 struct anv_shader_bin
*
1071 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1072 const void *key
, uint32_t key_size
);
1073 struct anv_shader_bin
*
1074 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1075 const void *key_data
, uint32_t key_size
,
1076 const void *kernel_data
, uint32_t kernel_size
,
1077 const void *constant_data
,
1078 uint32_t constant_data_size
,
1079 const struct brw_stage_prog_data
*prog_data
,
1080 uint32_t prog_data_size
,
1081 const struct brw_compile_stats
*stats
,
1083 const struct nir_xfb_info
*xfb_info
,
1084 const struct anv_pipeline_bind_map
*bind_map
);
1086 struct anv_shader_bin
*
1087 anv_device_search_for_kernel(struct anv_device
*device
,
1088 struct anv_pipeline_cache
*cache
,
1089 const void *key_data
, uint32_t key_size
,
1090 bool *user_cache_bit
);
1092 struct anv_shader_bin
*
1093 anv_device_upload_kernel(struct anv_device
*device
,
1094 struct anv_pipeline_cache
*cache
,
1095 const void *key_data
, uint32_t key_size
,
1096 const void *kernel_data
, uint32_t kernel_size
,
1097 const void *constant_data
,
1098 uint32_t constant_data_size
,
1099 const struct brw_stage_prog_data
*prog_data
,
1100 uint32_t prog_data_size
,
1101 const struct brw_compile_stats
*stats
,
1103 const struct nir_xfb_info
*xfb_info
,
1104 const struct anv_pipeline_bind_map
*bind_map
);
1107 struct nir_shader_compiler_options
;
1110 anv_device_search_for_nir(struct anv_device
*device
,
1111 struct anv_pipeline_cache
*cache
,
1112 const struct nir_shader_compiler_options
*nir_options
,
1113 unsigned char sha1_key
[20],
1117 anv_device_upload_nir(struct anv_device
*device
,
1118 struct anv_pipeline_cache
*cache
,
1119 const struct nir_shader
*nir
,
1120 unsigned char sha1_key
[20]);
1123 VK_LOADER_DATA _loader_data
;
1125 VkAllocationCallbacks alloc
;
1127 struct anv_instance
* instance
;
1128 uint32_t chipset_id
;
1130 struct gen_device_info info
;
1131 struct isl_device isl_dev
;
1134 bool can_chain_batches
;
1135 bool robust_buffer_access
;
1136 struct anv_device_extension_table enabled_extensions
;
1137 struct anv_device_dispatch_table dispatch
;
1139 pthread_mutex_t vma_mutex
;
1140 struct util_vma_heap vma_lo
;
1141 struct util_vma_heap vma_hi
;
1142 uint64_t vma_lo_available
;
1143 uint64_t vma_hi_available
;
1145 /** List of all anv_device_memory objects */
1146 struct list_head memory_objects
;
1148 struct anv_bo_pool batch_bo_pool
;
1150 struct anv_bo_cache bo_cache
;
1152 struct anv_state_pool dynamic_state_pool
;
1153 struct anv_state_pool instruction_state_pool
;
1154 struct anv_state_pool binding_table_pool
;
1155 struct anv_state_pool surface_state_pool
;
1157 struct anv_bo workaround_bo
;
1158 struct anv_bo trivial_batch_bo
;
1159 struct anv_bo hiz_clear_bo
;
1161 struct anv_pipeline_cache default_pipeline_cache
;
1162 struct blorp_context blorp
;
1164 struct anv_state border_colors
;
1166 struct anv_state slice_hash
;
1168 struct anv_queue queue
;
1170 struct anv_scratch_pool scratch_pool
;
1172 uint32_t default_mocs
;
1173 uint32_t external_mocs
;
1175 pthread_mutex_t mutex
;
1176 pthread_cond_t queue_submit
;
1179 struct gen_batch_decode_ctx decoder_ctx
;
1181 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1182 * the cmd_buffer's list.
1184 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1186 int perf_fd
; /* -1 if no opened */
1187 uint64_t perf_metric
; /* 0 if unset */
1189 struct gen_aux_map_context
*aux_map_ctx
;
1192 static inline struct anv_state_pool
*
1193 anv_binding_table_pool(struct anv_device
*device
)
1195 if (device
->instance
->physicalDevice
.use_softpin
)
1196 return &device
->binding_table_pool
;
1198 return &device
->surface_state_pool
;
1201 static inline struct anv_state
1202 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1203 if (device
->instance
->physicalDevice
.use_softpin
)
1204 return anv_state_pool_alloc(&device
->binding_table_pool
,
1205 device
->binding_table_pool
.block_size
, 0);
1207 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1211 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1212 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1215 static inline uint32_t
1216 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1218 if (bo
->flags
& ANV_BO_EXTERNAL
)
1219 return device
->external_mocs
;
1221 return device
->default_mocs
;
1224 void anv_device_init_blorp(struct anv_device
*device
);
1225 void anv_device_finish_blorp(struct anv_device
*device
);
1227 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1228 const char *file
, int line
,
1229 const char *msg
, ...)
1230 anv_printflike(4, 5);
1231 #define anv_device_set_lost(dev, ...) \
1232 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1235 anv_device_is_lost(struct anv_device
*device
)
1237 return unlikely(device
->_lost
);
1240 VkResult
anv_device_execbuf(struct anv_device
*device
,
1241 struct drm_i915_gem_execbuffer2
*execbuf
,
1242 struct anv_bo
**execbuf_bos
);
1243 VkResult
anv_device_query_status(struct anv_device
*device
);
1244 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1245 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1248 void* anv_gem_mmap(struct anv_device
*device
,
1249 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1250 void anv_gem_munmap(void *p
, uint64_t size
);
1251 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1252 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1253 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1254 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1255 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1256 int anv_gem_execbuffer(struct anv_device
*device
,
1257 struct drm_i915_gem_execbuffer2
*execbuf
);
1258 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1259 uint32_t stride
, uint32_t tiling
);
1260 int anv_gem_create_context(struct anv_device
*device
);
1261 bool anv_gem_has_context_priority(int fd
);
1262 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1263 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1265 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1267 int anv_gem_get_param(int fd
, uint32_t param
);
1268 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1269 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1270 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1271 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1272 uint32_t *active
, uint32_t *pending
);
1273 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1274 int anv_gem_reg_read(struct anv_device
*device
,
1275 uint32_t offset
, uint64_t *result
);
1276 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1277 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1278 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1279 uint32_t read_domains
, uint32_t write_domain
);
1280 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1281 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1282 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1283 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1284 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1285 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1287 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1288 uint32_t handle
, int fd
);
1289 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1290 bool anv_gem_supports_syncobj_wait(int fd
);
1291 int anv_gem_syncobj_wait(struct anv_device
*device
,
1292 uint32_t *handles
, uint32_t num_handles
,
1293 int64_t abs_timeout_ns
, bool wait_all
);
1295 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1296 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1298 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1300 struct anv_reloc_list
{
1301 uint32_t num_relocs
;
1302 uint32_t array_length
;
1303 struct drm_i915_gem_relocation_entry
* relocs
;
1304 struct anv_bo
** reloc_bos
;
1308 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1309 const VkAllocationCallbacks
*alloc
);
1310 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1311 const VkAllocationCallbacks
*alloc
);
1313 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1314 const VkAllocationCallbacks
*alloc
,
1315 uint32_t offset
, struct anv_bo
*target_bo
,
1318 struct anv_batch_bo
{
1319 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1320 struct list_head link
;
1324 /* Bytes actually consumed in this batch BO */
1327 struct anv_reloc_list relocs
;
1331 const VkAllocationCallbacks
* alloc
;
1337 struct anv_reloc_list
* relocs
;
1339 /* This callback is called (with the associated user data) in the event
1340 * that the batch runs out of space.
1342 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1346 * Current error status of the command buffer. Used to track inconsistent
1347 * or incomplete command buffer states that are the consequence of run-time
1348 * errors such as out of memory scenarios. We want to track this in the
1349 * batch because the command buffer object is not visible to some parts
1355 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1356 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1357 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1358 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1359 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1360 struct anv_batch
*batch
);
1362 static inline VkResult
1363 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1365 assert(error
!= VK_SUCCESS
);
1366 if (batch
->status
== VK_SUCCESS
)
1367 batch
->status
= error
;
1368 return batch
->status
;
1372 anv_batch_has_error(struct anv_batch
*batch
)
1374 return batch
->status
!= VK_SUCCESS
;
1377 struct anv_address
{
1382 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1385 anv_address_is_null(struct anv_address addr
)
1387 return addr
.bo
== NULL
&& addr
.offset
== 0;
1390 static inline uint64_t
1391 anv_address_physical(struct anv_address addr
)
1393 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1394 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1396 return gen_canonical_address(addr
.offset
);
1399 static inline struct anv_address
1400 anv_address_add(struct anv_address addr
, uint64_t offset
)
1402 addr
.offset
+= offset
;
1407 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1409 unsigned reloc_size
= 0;
1410 if (device
->info
.gen
>= 8) {
1411 reloc_size
= sizeof(uint64_t);
1412 *(uint64_t *)p
= gen_canonical_address(v
);
1414 reloc_size
= sizeof(uint32_t);
1418 if (flush
&& !device
->info
.has_llc
)
1419 gen_flush_range(p
, reloc_size
);
1422 static inline uint64_t
1423 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1424 const struct anv_address address
, uint32_t delta
)
1426 if (address
.bo
== NULL
) {
1427 return address
.offset
+ delta
;
1429 assert(batch
->start
<= location
&& location
< batch
->end
);
1431 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1435 #define __gen_address_type struct anv_address
1436 #define __gen_user_data struct anv_batch
1437 #define __gen_combine_address _anv_combine_address
1439 /* Wrapper macros needed to work around preprocessor argument issues. In
1440 * particular, arguments don't get pre-evaluated if they are concatenated.
1441 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1442 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1443 * We can work around this easily enough with these helpers.
1445 #define __anv_cmd_length(cmd) cmd ## _length
1446 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1447 #define __anv_cmd_header(cmd) cmd ## _header
1448 #define __anv_cmd_pack(cmd) cmd ## _pack
1449 #define __anv_reg_num(reg) reg ## _num
1451 #define anv_pack_struct(dst, struc, ...) do { \
1452 struct struc __template = { \
1455 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1456 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1459 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1460 void *__dst = anv_batch_emit_dwords(batch, n); \
1462 struct cmd __template = { \
1463 __anv_cmd_header(cmd), \
1464 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1467 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1472 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1476 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1477 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1480 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1481 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1482 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1485 #define anv_batch_emit(batch, cmd, name) \
1486 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1487 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1488 __builtin_expect(_dst != NULL, 1); \
1489 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1490 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1494 /* MEMORY_OBJECT_CONTROL_STATE:
1495 * .GraphicsDataTypeGFDT = 0,
1496 * .LLCCacheabilityControlLLCCC = 0,
1497 * .L3CacheabilityControlL3CC = 1,
1501 /* MEMORY_OBJECT_CONTROL_STATE:
1502 * .LLCeLLCCacheabilityControlLLCCC = 0,
1503 * .L3CacheabilityControlL3CC = 1,
1505 #define GEN75_MOCS 1
1507 /* MEMORY_OBJECT_CONTROL_STATE:
1508 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1509 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1510 * .AgeforQUADLRU = 0
1512 #define GEN8_MOCS 0x78
1514 /* MEMORY_OBJECT_CONTROL_STATE:
1515 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1516 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1517 * .AgeforQUADLRU = 0
1519 #define GEN8_EXTERNAL_MOCS 0x18
1521 /* Skylake: MOCS is now an index into an array of 62 different caching
1522 * configurations programmed by the kernel.
1525 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1526 #define GEN9_MOCS (2 << 1)
1528 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1529 #define GEN9_EXTERNAL_MOCS (1 << 1)
1531 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1532 #define GEN10_MOCS GEN9_MOCS
1533 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1535 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1536 #define GEN11_MOCS GEN9_MOCS
1537 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1539 /* TigerLake MOCS */
1540 #define GEN12_MOCS GEN9_MOCS
1541 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1542 #define GEN12_EXTERNAL_MOCS (3 << 1)
1544 struct anv_device_memory
{
1545 struct list_head link
;
1548 struct anv_memory_type
* type
;
1549 VkDeviceSize map_size
;
1552 /* If set, we are holding reference to AHardwareBuffer
1553 * which we must release when memory is freed.
1555 struct AHardwareBuffer
* ahw
;
1557 /* If set, this memory comes from a host pointer. */
1562 * Header for Vertex URB Entry (VUE)
1564 struct anv_vue_header
{
1566 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1567 uint32_t ViewportIndex
;
1571 /** Struct representing a sampled image descriptor
1573 * This descriptor layout is used for sampled images, bare sampler, and
1574 * combined image/sampler descriptors.
1576 struct anv_sampled_image_descriptor
{
1577 /** Bindless image handle
1579 * This is expected to already be shifted such that the 20-bit
1580 * SURFACE_STATE table index is in the top 20 bits.
1584 /** Bindless sampler handle
1586 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1587 * to the dynamic state base address.
1592 struct anv_texture_swizzle_descriptor
{
1595 * See also nir_intrinsic_channel_select_intel
1599 /** Unused padding to ensure the struct is a multiple of 64 bits */
1603 /** Struct representing a storage image descriptor */
1604 struct anv_storage_image_descriptor
{
1605 /** Bindless image handles
1607 * These are expected to already be shifted such that the 20-bit
1608 * SURFACE_STATE table index is in the top 20 bits.
1610 uint32_t read_write
;
1611 uint32_t write_only
;
1614 /** Struct representing a address/range descriptor
1616 * The fields of this struct correspond directly to the data layout of
1617 * nir_address_format_64bit_bounded_global addresses. The last field is the
1618 * offset in the NIR address so it must be zero so that when you load the
1619 * descriptor you get a pointer to the start of the range.
1621 struct anv_address_range_descriptor
{
1627 enum anv_descriptor_data
{
1628 /** The descriptor contains a BTI reference to a surface state */
1629 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1630 /** The descriptor contains a BTI reference to a sampler state */
1631 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1632 /** The descriptor contains an actual buffer view */
1633 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1634 /** The descriptor contains auxiliary image layout data */
1635 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1636 /** The descriptor contains auxiliary image layout data */
1637 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1638 /** anv_address_range_descriptor with a buffer address and range */
1639 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1640 /** Bindless surface handle */
1641 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1642 /** Storage image handles */
1643 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1644 /** Storage image handles */
1645 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1648 struct anv_descriptor_set_binding_layout
{
1650 /* The type of the descriptors in this binding */
1651 VkDescriptorType type
;
1654 /* Flags provided when this binding was created */
1655 VkDescriptorBindingFlagsEXT flags
;
1657 /* Bitfield representing the type of data this descriptor contains */
1658 enum anv_descriptor_data data
;
1660 /* Maximum number of YCbCr texture/sampler planes */
1661 uint8_t max_plane_count
;
1663 /* Number of array elements in this binding (or size in bytes for inline
1666 uint16_t array_size
;
1668 /* Index into the flattend descriptor set */
1669 uint16_t descriptor_index
;
1671 /* Index into the dynamic state array for a dynamic buffer */
1672 int16_t dynamic_offset_index
;
1674 /* Index into the descriptor set buffer views */
1675 int16_t buffer_view_index
;
1677 /* Offset into the descriptor buffer where this descriptor lives */
1678 uint32_t descriptor_offset
;
1680 /* Immutable samplers (or NULL if no immutable samplers) */
1681 struct anv_sampler
**immutable_samplers
;
1684 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1686 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1687 VkDescriptorType type
);
1689 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1690 const struct anv_descriptor_set_binding_layout
*binding
,
1693 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1694 const struct anv_descriptor_set_binding_layout
*binding
,
1697 struct anv_descriptor_set_layout
{
1698 /* Descriptor set layouts can be destroyed at almost any time */
1701 /* Number of bindings in this descriptor set */
1702 uint16_t binding_count
;
1704 /* Total size of the descriptor set with room for all array entries */
1707 /* Shader stages affected by this descriptor set */
1708 uint16_t shader_stages
;
1710 /* Number of buffer views in this descriptor set */
1711 uint16_t buffer_view_count
;
1713 /* Number of dynamic offsets used by this descriptor set */
1714 uint16_t dynamic_offset_count
;
1716 /* Size of the descriptor buffer for this descriptor set */
1717 uint32_t descriptor_buffer_size
;
1719 /* Bindings in this descriptor set */
1720 struct anv_descriptor_set_binding_layout binding
[0];
1724 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1726 assert(layout
&& layout
->ref_cnt
>= 1);
1727 p_atomic_inc(&layout
->ref_cnt
);
1731 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1732 struct anv_descriptor_set_layout
*layout
)
1734 assert(layout
&& layout
->ref_cnt
>= 1);
1735 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1736 vk_free(&device
->alloc
, layout
);
1739 struct anv_descriptor
{
1740 VkDescriptorType type
;
1744 VkImageLayout layout
;
1745 struct anv_image_view
*image_view
;
1746 struct anv_sampler
*sampler
;
1750 struct anv_buffer
*buffer
;
1755 struct anv_buffer_view
*buffer_view
;
1759 struct anv_descriptor_set
{
1760 struct anv_descriptor_pool
*pool
;
1761 struct anv_descriptor_set_layout
*layout
;
1764 /* State relative to anv_descriptor_pool::bo */
1765 struct anv_state desc_mem
;
1766 /* Surface state for the descriptor buffer */
1767 struct anv_state desc_surface_state
;
1769 uint32_t buffer_view_count
;
1770 struct anv_buffer_view
*buffer_views
;
1772 /* Link to descriptor pool's desc_sets list . */
1773 struct list_head pool_link
;
1775 struct anv_descriptor descriptors
[0];
1778 struct anv_buffer_view
{
1779 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1780 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1782 struct anv_address address
;
1784 struct anv_state surface_state
;
1785 struct anv_state storage_surface_state
;
1786 struct anv_state writeonly_storage_surface_state
;
1788 struct brw_image_param storage_image_param
;
1791 struct anv_push_descriptor_set
{
1792 struct anv_descriptor_set set
;
1794 /* Put this field right behind anv_descriptor_set so it fills up the
1795 * descriptors[0] field. */
1796 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1798 /** True if the descriptor set buffer has been referenced by a draw or
1801 bool set_used_on_gpu
;
1803 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1806 struct anv_descriptor_pool
{
1812 struct util_vma_heap bo_heap
;
1814 struct anv_state_stream surface_state_stream
;
1815 void *surface_state_free_list
;
1817 struct list_head desc_sets
;
1822 enum anv_descriptor_template_entry_type
{
1823 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1824 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1825 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1828 struct anv_descriptor_template_entry
{
1829 /* The type of descriptor in this entry */
1830 VkDescriptorType type
;
1832 /* Binding in the descriptor set */
1835 /* Offset at which to write into the descriptor set binding */
1836 uint32_t array_element
;
1838 /* Number of elements to write into the descriptor set binding */
1839 uint32_t array_count
;
1841 /* Offset into the user provided data */
1844 /* Stride between elements into the user provided data */
1848 struct anv_descriptor_update_template
{
1849 VkPipelineBindPoint bind_point
;
1851 /* The descriptor set this template corresponds to. This value is only
1852 * valid if the template was created with the templateType
1853 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1857 /* Number of entries in this template */
1858 uint32_t entry_count
;
1860 /* Entries of the template */
1861 struct anv_descriptor_template_entry entries
[0];
1865 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1868 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1869 struct anv_descriptor_set
*set
,
1870 const VkDescriptorImageInfo
* const info
,
1871 VkDescriptorType type
,
1876 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1877 struct anv_descriptor_set
*set
,
1878 VkDescriptorType type
,
1879 struct anv_buffer_view
*buffer_view
,
1884 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1885 struct anv_descriptor_set
*set
,
1886 struct anv_state_stream
*alloc_stream
,
1887 VkDescriptorType type
,
1888 struct anv_buffer
*buffer
,
1891 VkDeviceSize offset
,
1892 VkDeviceSize range
);
1894 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1895 struct anv_descriptor_set
*set
,
1902 anv_descriptor_set_write_template(struct anv_device
*device
,
1903 struct anv_descriptor_set
*set
,
1904 struct anv_state_stream
*alloc_stream
,
1905 const struct anv_descriptor_update_template
*template,
1909 anv_descriptor_set_create(struct anv_device
*device
,
1910 struct anv_descriptor_pool
*pool
,
1911 struct anv_descriptor_set_layout
*layout
,
1912 struct anv_descriptor_set
**out_set
);
1915 anv_descriptor_set_destroy(struct anv_device
*device
,
1916 struct anv_descriptor_pool
*pool
,
1917 struct anv_descriptor_set
*set
);
1919 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1920 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1921 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1922 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1924 struct anv_pipeline_binding
{
1925 /* The descriptor set this surface corresponds to. The special value of
1926 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1927 * to a color attachment and not a regular descriptor.
1931 /* Binding in the descriptor set */
1934 /* Index in the binding */
1937 /* Plane in the binding index */
1940 /* Input attachment index (relative to the subpass) */
1941 uint8_t input_attachment_index
;
1943 /* For a storage image, whether it is write-only */
1947 struct anv_pipeline_layout
{
1949 struct anv_descriptor_set_layout
*layout
;
1950 uint32_t dynamic_offset_start
;
1955 unsigned char sha1
[20];
1959 struct anv_device
* device
;
1962 VkBufferUsageFlags usage
;
1964 /* Set when bound */
1965 struct anv_address address
;
1968 static inline uint64_t
1969 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1971 assert(offset
<= buffer
->size
);
1972 if (range
== VK_WHOLE_SIZE
) {
1973 return buffer
->size
- offset
;
1975 assert(range
+ offset
>= range
);
1976 assert(range
+ offset
<= buffer
->size
);
1981 enum anv_cmd_dirty_bits
{
1982 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1983 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1984 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1985 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1986 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1987 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1988 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1989 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1990 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1991 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1992 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1993 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1994 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1995 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
1997 typedef uint32_t anv_cmd_dirty_mask_t
;
1999 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2000 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2001 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2002 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2003 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2004 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2005 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2006 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2007 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2008 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2009 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2011 static inline enum anv_cmd_dirty_bits
2012 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2015 case VK_DYNAMIC_STATE_VIEWPORT
:
2016 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2017 case VK_DYNAMIC_STATE_SCISSOR
:
2018 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2019 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2020 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2021 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2022 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2023 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2024 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2025 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2026 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2027 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2028 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2029 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2030 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2031 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2032 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2033 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2034 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2036 assert(!"Unsupported dynamic state");
2042 enum anv_pipe_bits
{
2043 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2044 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2045 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2046 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2047 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2048 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2049 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2050 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2051 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2052 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2053 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2055 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2056 * a flush has happened but not a CS stall. The next time we do any sort
2057 * of invalidation we need to insert a CS stall at that time. Otherwise,
2058 * we would have to CS stall on every flush which could be bad.
2060 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2062 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2063 * target operations related to transfer commands with VkBuffer as
2064 * destination are ongoing. Some operations like copies on the command
2065 * streamer might need to be aware of this to trigger the appropriate stall
2066 * before they can proceed with the copy.
2068 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2071 #define ANV_PIPE_FLUSH_BITS ( \
2072 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2073 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2074 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
2076 #define ANV_PIPE_STALL_BITS ( \
2077 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2078 ANV_PIPE_DEPTH_STALL_BIT | \
2079 ANV_PIPE_CS_STALL_BIT)
2081 #define ANV_PIPE_INVALIDATE_BITS ( \
2082 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2083 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2084 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2085 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2086 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2087 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2089 static inline enum anv_pipe_bits
2090 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2092 enum anv_pipe_bits pipe_bits
= 0;
2095 for_each_bit(b
, flags
) {
2096 switch ((VkAccessFlagBits
)(1 << b
)) {
2097 case VK_ACCESS_SHADER_WRITE_BIT
:
2098 /* We're transitioning a buffer that was previously used as write
2099 * destination through the data port. To make its content available
2100 * to future operations, flush the data cache.
2102 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2104 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2105 /* We're transitioning a buffer that was previously used as render
2106 * target. To make its content available to future operations, flush
2107 * the render target cache.
2109 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2111 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2112 /* We're transitioning a buffer that was previously used as depth
2113 * buffer. To make its content available to future operations, flush
2116 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2118 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2119 /* We're transitioning a buffer that was previously used as a
2120 * transfer write destination. Generic write operations include color
2121 * & depth operations as well as buffer operations like :
2122 * - vkCmdClearColorImage()
2123 * - vkCmdClearDepthStencilImage()
2124 * - vkCmdBlitImage()
2125 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2127 * Most of these operations are implemented using Blorp which writes
2128 * through the render target, so flush that cache to make it visible
2129 * to future operations. And for depth related operations we also
2130 * need to flush the depth cache.
2132 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2133 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2135 case VK_ACCESS_MEMORY_WRITE_BIT
:
2136 /* We're transitioning a buffer for generic write operations. Flush
2139 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2142 break; /* Nothing to do */
2149 static inline enum anv_pipe_bits
2150 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2152 enum anv_pipe_bits pipe_bits
= 0;
2155 for_each_bit(b
, flags
) {
2156 switch ((VkAccessFlagBits
)(1 << b
)) {
2157 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2158 /* Indirect draw commands take a buffer as input that we're going to
2159 * read from the command streamer to load some of the HW registers
2160 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2161 * command streamer stall so that all the cache flushes have
2162 * completed before the command streamer loads from memory.
2164 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2165 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2166 * through a vertex buffer, so invalidate that cache.
2168 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2169 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2170 * UBO from the buffer, so we need to invalidate constant cache.
2172 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2174 case VK_ACCESS_INDEX_READ_BIT
:
2175 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2176 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2177 * commands, so we invalidate the VF cache to make sure there is no
2178 * stale data when we start rendering.
2180 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2182 case VK_ACCESS_UNIFORM_READ_BIT
:
2183 /* We transitioning a buffer to be used as uniform data. Because
2184 * uniform is accessed through the data port & sampler, we need to
2185 * invalidate the texture cache (sampler) & constant cache (data
2186 * port) to avoid stale data.
2188 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2189 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2191 case VK_ACCESS_SHADER_READ_BIT
:
2192 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2193 case VK_ACCESS_TRANSFER_READ_BIT
:
2194 /* Transitioning a buffer to be read through the sampler, so
2195 * invalidate the texture cache, we don't want any stale data.
2197 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2199 case VK_ACCESS_MEMORY_READ_BIT
:
2200 /* Transitioning a buffer for generic read, invalidate all the
2203 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2205 case VK_ACCESS_MEMORY_WRITE_BIT
:
2206 /* Generic write, make sure all previously written things land in
2209 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2211 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2212 /* Transitioning a buffer for conditional rendering. We'll load the
2213 * content of this buffer into HW registers using the command
2214 * streamer, so we need to stall the command streamer to make sure
2215 * any in-flight flush operations have completed.
2217 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2220 break; /* Nothing to do */
2227 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2228 VK_IMAGE_ASPECT_COLOR_BIT | \
2229 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2230 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2231 VK_IMAGE_ASPECT_PLANE_2_BIT)
2232 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2233 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2234 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2235 VK_IMAGE_ASPECT_PLANE_2_BIT)
2237 struct anv_vertex_binding
{
2238 struct anv_buffer
* buffer
;
2239 VkDeviceSize offset
;
2242 struct anv_xfb_binding
{
2243 struct anv_buffer
* buffer
;
2244 VkDeviceSize offset
;
2248 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2249 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2250 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2252 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2253 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2254 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2256 struct anv_push_constants
{
2257 /* Push constant data provided by the client through vkPushConstants */
2258 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2260 /* Used for vkCmdDispatchBase */
2261 uint32_t base_work_group_id
[3];
2264 struct anv_dynamic_state
{
2267 VkViewport viewports
[MAX_VIEWPORTS
];
2272 VkRect2D scissors
[MAX_SCISSORS
];
2283 float blend_constants
[4];
2293 } stencil_compare_mask
;
2298 } stencil_write_mask
;
2303 } stencil_reference
;
2311 extern const struct anv_dynamic_state default_dynamic_state
;
2313 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2314 const struct anv_dynamic_state
*src
,
2315 uint32_t copy_mask
);
2317 struct anv_surface_state
{
2318 struct anv_state state
;
2319 /** Address of the surface referred to by this state
2321 * This address is relative to the start of the BO.
2323 struct anv_address address
;
2324 /* Address of the aux surface, if any
2326 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2328 * With the exception of gen8, the bottom 12 bits of this address' offset
2329 * include extra aux information.
2331 struct anv_address aux_address
;
2332 /* Address of the clear color, if any
2334 * This address is relative to the start of the BO.
2336 struct anv_address clear_address
;
2340 * Attachment state when recording a renderpass instance.
2342 * The clear value is valid only if there exists a pending clear.
2344 struct anv_attachment_state
{
2345 enum isl_aux_usage aux_usage
;
2346 enum isl_aux_usage input_aux_usage
;
2347 struct anv_surface_state color
;
2348 struct anv_surface_state input
;
2350 VkImageLayout current_layout
;
2351 VkImageAspectFlags pending_clear_aspects
;
2352 VkImageAspectFlags pending_load_aspects
;
2354 VkClearValue clear_value
;
2355 bool clear_color_is_zero_one
;
2356 bool clear_color_is_zero
;
2358 /* When multiview is active, attachments with a renderpass clear
2359 * operation have their respective layers cleared on the first
2360 * subpass that uses them, and only in that subpass. We keep track
2361 * of this using a bitfield to indicate which layers of an attachment
2362 * have not been cleared yet when multiview is active.
2364 uint32_t pending_clear_views
;
2365 struct anv_image_view
* image_view
;
2368 /** State tracking for particular pipeline bind point
2370 * This struct is the base struct for anv_cmd_graphics_state and
2371 * anv_cmd_compute_state. These are used to track state which is bound to a
2372 * particular type of pipeline. Generic state that applies per-stage such as
2373 * binding table offsets and push constants is tracked generically with a
2374 * per-stage array in anv_cmd_state.
2376 struct anv_cmd_pipeline_state
{
2377 struct anv_pipeline
*pipeline
;
2378 struct anv_pipeline_layout
*layout
;
2380 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2381 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2383 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2386 /** State tracking for graphics pipeline
2388 * This has anv_cmd_pipeline_state as a base struct to track things which get
2389 * bound to a graphics pipeline. Along with general pipeline bind point state
2390 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2391 * state which is graphics-specific.
2393 struct anv_cmd_graphics_state
{
2394 struct anv_cmd_pipeline_state base
;
2396 anv_cmd_dirty_mask_t dirty
;
2399 struct anv_dynamic_state dynamic
;
2402 struct anv_buffer
*index_buffer
;
2403 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2404 uint32_t index_offset
;
2408 /** State tracking for compute pipeline
2410 * This has anv_cmd_pipeline_state as a base struct to track things which get
2411 * bound to a compute pipeline. Along with general pipeline bind point state
2412 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2413 * state which is compute-specific.
2415 struct anv_cmd_compute_state
{
2416 struct anv_cmd_pipeline_state base
;
2418 bool pipeline_dirty
;
2420 struct anv_address num_workgroups
;
2423 /** State required while building cmd buffer */
2424 struct anv_cmd_state
{
2425 /* PIPELINE_SELECT.PipelineSelection */
2426 uint32_t current_pipeline
;
2427 const struct gen_l3_config
* current_l3_config
;
2428 uint32_t last_aux_map_state
;
2430 struct anv_cmd_graphics_state gfx
;
2431 struct anv_cmd_compute_state compute
;
2433 enum anv_pipe_bits pending_pipe_bits
;
2434 VkShaderStageFlags descriptors_dirty
;
2435 VkShaderStageFlags push_constants_dirty
;
2437 struct anv_framebuffer
* framebuffer
;
2438 struct anv_render_pass
* pass
;
2439 struct anv_subpass
* subpass
;
2440 VkRect2D render_area
;
2441 uint32_t restart_index
;
2442 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2444 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2445 VkShaderStageFlags push_constant_stages
;
2446 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2447 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2448 struct anv_state samplers
[MESA_SHADER_STAGES
];
2451 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2452 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2453 * and before invoking the secondary in ExecuteCommands.
2455 bool pma_fix_enabled
;
2458 * Whether or not we know for certain that HiZ is enabled for the current
2459 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2460 * enabled or not, this will be false.
2464 bool conditional_render_enabled
;
2467 * Last rendering scale argument provided to
2468 * genX(cmd_buffer_emit_hashing_mode)().
2470 unsigned current_hash_scale
;
2473 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2474 * valid only when recording a render pass instance.
2476 struct anv_attachment_state
* attachments
;
2479 * Surface states for color render targets. These are stored in a single
2480 * flat array. For depth-stencil attachments, the surface state is simply
2483 struct anv_state render_pass_states
;
2486 * A null surface state of the right size to match the framebuffer. This
2487 * is one of the states in render_pass_states.
2489 struct anv_state null_surface_state
;
2492 struct anv_cmd_pool
{
2493 VkAllocationCallbacks alloc
;
2494 struct list_head cmd_buffers
;
2497 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2499 enum anv_cmd_buffer_exec_mode
{
2500 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2501 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2502 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2503 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2504 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2507 struct anv_cmd_buffer
{
2508 VK_LOADER_DATA _loader_data
;
2510 struct anv_device
* device
;
2512 struct anv_cmd_pool
* pool
;
2513 struct list_head pool_link
;
2515 struct anv_batch batch
;
2517 /* Fields required for the actual chain of anv_batch_bo's.
2519 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2521 struct list_head batch_bos
;
2522 enum anv_cmd_buffer_exec_mode exec_mode
;
2524 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2525 * referenced by this command buffer
2527 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2529 struct u_vector seen_bbos
;
2531 /* A vector of int32_t's for every block of binding tables.
2533 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2535 struct u_vector bt_block_states
;
2538 struct anv_reloc_list surface_relocs
;
2539 /** Last seen surface state block pool center bo offset */
2540 uint32_t last_ss_pool_center
;
2542 /* Serial for tracking buffer completion */
2545 /* Stream objects for storing temporary data */
2546 struct anv_state_stream surface_state_stream
;
2547 struct anv_state_stream dynamic_state_stream
;
2549 VkCommandBufferUsageFlags usage_flags
;
2550 VkCommandBufferLevel level
;
2552 struct anv_cmd_state state
;
2554 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2555 uint64_t intel_perf_marker
;
2558 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2559 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2560 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2561 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2562 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2563 struct anv_cmd_buffer
*secondary
);
2564 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2565 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2566 struct anv_cmd_buffer
*cmd_buffer
,
2567 const VkSemaphore
*in_semaphores
,
2568 uint32_t num_in_semaphores
,
2569 const VkSemaphore
*out_semaphores
,
2570 uint32_t num_out_semaphores
,
2573 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2575 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2576 const void *data
, uint32_t size
, uint32_t alignment
);
2577 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2578 uint32_t *a
, uint32_t *b
,
2579 uint32_t dwords
, uint32_t alignment
);
2582 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2584 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2585 uint32_t entries
, uint32_t *state_offset
);
2587 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2589 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2590 uint32_t size
, uint32_t alignment
);
2593 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2595 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2596 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2597 bool depth_clamp_enable
);
2598 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2600 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2601 struct anv_render_pass
*pass
,
2602 struct anv_framebuffer
*framebuffer
,
2603 const VkClearValue
*clear_values
);
2605 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2608 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2609 gl_shader_stage stage
);
2611 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2613 const struct anv_image_view
*
2614 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2617 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2618 uint32_t num_entries
,
2619 uint32_t *state_offset
,
2620 struct anv_state
*bt_state
);
2622 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2624 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2626 enum anv_fence_type
{
2627 ANV_FENCE_TYPE_NONE
= 0,
2629 ANV_FENCE_TYPE_SYNCOBJ
,
2633 enum anv_bo_fence_state
{
2634 /** Indicates that this is a new (or newly reset fence) */
2635 ANV_BO_FENCE_STATE_RESET
,
2637 /** Indicates that this fence has been submitted to the GPU but is still
2638 * (as far as we know) in use by the GPU.
2640 ANV_BO_FENCE_STATE_SUBMITTED
,
2642 ANV_BO_FENCE_STATE_SIGNALED
,
2645 struct anv_fence_impl
{
2646 enum anv_fence_type type
;
2649 /** Fence implementation for BO fences
2651 * These fences use a BO and a set of CPU-tracked state flags. The BO
2652 * is added to the object list of the last execbuf call in a QueueSubmit
2653 * and is marked EXEC_WRITE. The state flags track when the BO has been
2654 * submitted to the kernel. We need to do this because Vulkan lets you
2655 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2656 * will say it's idle in this case.
2660 enum anv_bo_fence_state state
;
2663 /** DRM syncobj handle for syncobj-based fences */
2667 struct wsi_fence
*fence_wsi
;
2672 /* Permanent fence state. Every fence has some form of permanent state
2673 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2674 * cross-process fences) or it could just be a dummy for use internally.
2676 struct anv_fence_impl permanent
;
2678 /* Temporary fence state. A fence *may* have temporary state. That state
2679 * is added to the fence by an import operation and is reset back to
2680 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2681 * state cannot be signaled because the fence must already be signaled
2682 * before the temporary state can be exported from the fence in the other
2683 * process and imported here.
2685 struct anv_fence_impl temporary
;
2690 struct anv_state state
;
2693 enum anv_semaphore_type
{
2694 ANV_SEMAPHORE_TYPE_NONE
= 0,
2695 ANV_SEMAPHORE_TYPE_DUMMY
,
2696 ANV_SEMAPHORE_TYPE_BO
,
2697 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2698 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2701 struct anv_semaphore_impl
{
2702 enum anv_semaphore_type type
;
2705 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2706 * This BO will be added to the object list on any execbuf2 calls for
2707 * which this semaphore is used as a wait or signal fence. When used as
2708 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2712 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2713 * If the semaphore is in the unsignaled state due to either just being
2714 * created or because it has been used for a wait, fd will be -1.
2718 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2719 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2720 * import so we don't need to bother with a userspace cache.
2726 struct anv_semaphore
{
2727 /* Permanent semaphore state. Every semaphore has some form of permanent
2728 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2729 * (for cross-process semaphores0 or it could just be a dummy for use
2732 struct anv_semaphore_impl permanent
;
2734 /* Temporary semaphore state. A semaphore *may* have temporary state.
2735 * That state is added to the semaphore by an import operation and is reset
2736 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2737 * semaphore with temporary state cannot be signaled because the semaphore
2738 * must already be signaled before the temporary state can be exported from
2739 * the semaphore in the other process and imported here.
2741 struct anv_semaphore_impl temporary
;
2744 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2745 struct anv_semaphore
*semaphore
);
2747 struct anv_shader_module
{
2748 unsigned char sha1
[20];
2753 static inline gl_shader_stage
2754 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2756 assert(__builtin_popcount(vk_stage
) == 1);
2757 return ffs(vk_stage
) - 1;
2760 static inline VkShaderStageFlagBits
2761 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2763 return (1 << mesa_stage
);
2766 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2768 #define anv_foreach_stage(stage, stage_bits) \
2769 for (gl_shader_stage stage, \
2770 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2771 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2772 __tmp &= ~(1 << (stage)))
2774 struct anv_pipeline_bind_map
{
2775 uint32_t surface_count
;
2776 uint32_t sampler_count
;
2778 struct anv_pipeline_binding
* surface_to_descriptor
;
2779 struct anv_pipeline_binding
* sampler_to_descriptor
;
2782 struct anv_shader_bin_key
{
2787 struct anv_shader_bin
{
2790 const struct anv_shader_bin_key
*key
;
2792 struct anv_state kernel
;
2793 uint32_t kernel_size
;
2795 struct anv_state constant_data
;
2796 uint32_t constant_data_size
;
2798 const struct brw_stage_prog_data
*prog_data
;
2799 uint32_t prog_data_size
;
2801 struct brw_compile_stats stats
[3];
2804 struct nir_xfb_info
*xfb_info
;
2806 struct anv_pipeline_bind_map bind_map
;
2809 struct anv_shader_bin
*
2810 anv_shader_bin_create(struct anv_device
*device
,
2811 const void *key
, uint32_t key_size
,
2812 const void *kernel
, uint32_t kernel_size
,
2813 const void *constant_data
, uint32_t constant_data_size
,
2814 const struct brw_stage_prog_data
*prog_data
,
2815 uint32_t prog_data_size
, const void *prog_data_param
,
2816 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2817 const struct nir_xfb_info
*xfb_info
,
2818 const struct anv_pipeline_bind_map
*bind_map
);
2821 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2824 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2826 assert(shader
&& shader
->ref_cnt
>= 1);
2827 p_atomic_inc(&shader
->ref_cnt
);
2831 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2833 assert(shader
&& shader
->ref_cnt
>= 1);
2834 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2835 anv_shader_bin_destroy(device
, shader
);
2838 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2839 #define MAX_PIPELINE_EXECUTABLES 7
2841 struct anv_pipeline_executable
{
2842 gl_shader_stage stage
;
2844 struct brw_compile_stats stats
;
2850 struct anv_pipeline
{
2851 struct anv_device
* device
;
2852 struct anv_batch batch
;
2853 uint32_t batch_data
[512];
2854 struct anv_reloc_list batch_relocs
;
2855 anv_cmd_dirty_mask_t dynamic_state_mask
;
2856 struct anv_dynamic_state dynamic_state
;
2860 VkPipelineCreateFlags flags
;
2861 struct anv_subpass
* subpass
;
2863 bool needs_data_cache
;
2865 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2867 uint32_t num_executables
;
2868 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2871 const struct gen_l3_config
* l3_config
;
2872 uint32_t total_size
;
2875 VkShaderStageFlags active_stages
;
2876 struct anv_state blend_state
;
2879 struct anv_pipeline_vertex_binding
{
2882 uint32_t instance_divisor
;
2887 bool primitive_restart
;
2890 uint32_t cs_right_mask
;
2893 bool depth_test_enable
;
2894 bool writes_stencil
;
2895 bool stencil_test_enable
;
2896 bool depth_clamp_enable
;
2897 bool depth_clip_enable
;
2898 bool sample_shading_enable
;
2900 bool depth_bounds_test_enable
;
2904 uint32_t depth_stencil_state
[3];
2910 uint32_t wm_depth_stencil
[3];
2914 uint32_t wm_depth_stencil
[4];
2917 uint32_t interface_descriptor_data
[8];
2921 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2922 gl_shader_stage stage
)
2924 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2927 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2928 static inline const struct brw_##prefix##_prog_data * \
2929 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2931 if (anv_pipeline_has_stage(pipeline, stage)) { \
2932 return (const struct brw_##prefix##_prog_data *) \
2933 pipeline->shaders[stage]->prog_data; \
2939 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2940 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2941 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2942 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2943 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2944 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2946 static inline const struct brw_vue_prog_data
*
2947 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2949 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2950 return &get_gs_prog_data(pipeline
)->base
;
2951 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2952 return &get_tes_prog_data(pipeline
)->base
;
2954 return &get_vs_prog_data(pipeline
)->base
;
2958 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2959 struct anv_pipeline_cache
*cache
,
2960 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2961 const VkAllocationCallbacks
*alloc
);
2964 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2965 struct anv_pipeline_cache
*cache
,
2966 const VkComputePipelineCreateInfo
*info
,
2967 const struct anv_shader_module
*module
,
2968 const char *entrypoint
,
2969 const VkSpecializationInfo
*spec_info
);
2971 struct anv_format_plane
{
2972 enum isl_format isl_format
:16;
2973 struct isl_swizzle swizzle
;
2975 /* Whether this plane contains chroma channels */
2978 /* For downscaling of YUV planes */
2979 uint8_t denominator_scales
[2];
2981 /* How to map sampled ycbcr planes to a single 4 component element. */
2982 struct isl_swizzle ycbcr_swizzle
;
2984 /* What aspect is associated to this plane */
2985 VkImageAspectFlags aspect
;
2990 struct anv_format_plane planes
[3];
2996 static inline uint32_t
2997 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2998 VkImageAspectFlags aspect_mask
)
3000 switch (aspect_mask
) {
3001 case VK_IMAGE_ASPECT_COLOR_BIT
:
3002 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3003 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3005 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3006 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3009 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3011 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3014 /* Purposefully assert with depth/stencil aspects. */
3015 unreachable("invalid image aspect");
3019 static inline VkImageAspectFlags
3020 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3023 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3024 if (util_bitcount(image_aspects
) > 1)
3025 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3026 return VK_IMAGE_ASPECT_COLOR_BIT
;
3028 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3029 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3030 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3031 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3034 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3035 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3037 const struct anv_format
*
3038 anv_get_format(VkFormat format
);
3040 static inline uint32_t
3041 anv_get_format_planes(VkFormat vk_format
)
3043 const struct anv_format
*format
= anv_get_format(vk_format
);
3045 return format
!= NULL
? format
->n_planes
: 0;
3048 struct anv_format_plane
3049 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3050 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3052 static inline enum isl_format
3053 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3054 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3056 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3059 static inline struct isl_swizzle
3060 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3062 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3063 * RGB as RGBA for texturing
3065 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3066 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3068 /* But it doesn't matter what we render to that channel */
3069 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3075 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3078 * Subsurface of an anv_image.
3080 struct anv_surface
{
3081 /** Valid only if isl_surf::size_B > 0. */
3082 struct isl_surf isl
;
3085 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3091 VkImageType type
; /**< VkImageCreateInfo::imageType */
3092 /* The original VkFormat provided by the client. This may not match any
3093 * of the actual surface formats.
3096 const struct anv_format
*format
;
3098 VkImageAspectFlags aspects
;
3101 uint32_t array_size
;
3102 uint32_t samples
; /**< VkImageCreateInfo::samples */
3104 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3105 VkImageUsageFlags stencil_usage
;
3106 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3107 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3109 /** True if this is needs to be bound to an appropriately tiled BO.
3111 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3112 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3113 * we require a dedicated allocation so that we can know to allocate a
3116 bool needs_set_tiling
;
3119 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3120 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3122 uint64_t drm_format_mod
;
3127 /* Whether the image is made of several underlying buffer objects rather a
3128 * single one with different offsets.
3132 /* All the formats that can be used when creating views of this image
3133 * are CCS_E compatible.
3135 bool ccs_e_compatible
;
3137 /* Image was created with external format. */
3138 bool external_format
;
3143 * For each foo, anv_image::planes[x].surface is valid if and only if
3144 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3145 * to figure the number associated with a given aspect.
3147 * The hardware requires that the depth buffer and stencil buffer be
3148 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3149 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3150 * allocate the depth and stencil buffers as separate surfaces in the same
3155 * -----------------------
3157 * ----------------------- |
3158 * | shadow surface0 | |
3159 * ----------------------- | Plane 0
3160 * | aux surface0 | |
3161 * ----------------------- |
3162 * | fast clear colors0 | \|/
3163 * -----------------------
3165 * ----------------------- |
3166 * | shadow surface1 | |
3167 * ----------------------- | Plane 1
3168 * | aux surface1 | |
3169 * ----------------------- |
3170 * | fast clear colors1 | \|/
3171 * -----------------------
3174 * -----------------------
3178 * Offset of the entire plane (whenever the image is disjoint this is
3186 struct anv_surface surface
;
3189 * A surface which shadows the main surface and may have different
3190 * tiling. This is used for sampling using a tiling that isn't supported
3191 * for other operations.
3193 struct anv_surface shadow_surface
;
3196 * For color images, this is the aux usage for this image when not used
3197 * as a color attachment.
3199 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3200 * image has a HiZ buffer.
3202 enum isl_aux_usage aux_usage
;
3204 struct anv_surface aux_surface
;
3207 * Offset of the fast clear state (used to compute the
3208 * fast_clear_state_offset of the following planes).
3210 uint32_t fast_clear_state_offset
;
3213 * BO associated with this plane, set when bound.
3215 struct anv_address address
;
3218 * Address of the main surface used to fill the aux map table. This is
3219 * used at destruction of the image since the Vulkan spec does not
3220 * guarantee that the address.bo field we still be valid at destruction.
3222 uint64_t aux_map_surface_address
;
3225 * When destroying the image, also free the bo.
3231 /* The ordering of this enum is important */
3232 enum anv_fast_clear_type
{
3233 /** Image does not have/support any fast-clear blocks */
3234 ANV_FAST_CLEAR_NONE
= 0,
3235 /** Image has/supports fast-clear but only to the default value */
3236 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3237 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3238 ANV_FAST_CLEAR_ANY
= 2,
3241 /* Returns the number of auxiliary buffer levels attached to an image. */
3242 static inline uint8_t
3243 anv_image_aux_levels(const struct anv_image
* const image
,
3244 VkImageAspectFlagBits aspect
)
3246 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3248 /* The Gen12 CCS aux surface is represented with only one level. */
3249 const uint8_t aux_logical_levels
=
3250 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3251 image
->planes
[plane
].surface
.isl
.levels
:
3252 image
->planes
[plane
].aux_surface
.isl
.levels
;
3254 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3255 aux_logical_levels
: 0;
3258 /* Returns the number of auxiliary buffer layers attached to an image. */
3259 static inline uint32_t
3260 anv_image_aux_layers(const struct anv_image
* const image
,
3261 VkImageAspectFlagBits aspect
,
3262 const uint8_t miplevel
)
3266 /* The miplevel must exist in the main buffer. */
3267 assert(miplevel
< image
->levels
);
3269 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3270 /* There are no layers with auxiliary data because the miplevel has no
3275 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3277 /* The Gen12 CCS aux surface is represented with only one layer. */
3278 const struct isl_extent4d
*aux_logical_level0_px
=
3279 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3280 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3281 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3283 return MAX2(aux_logical_level0_px
->array_len
,
3284 aux_logical_level0_px
->depth
>> miplevel
);
3288 static inline struct anv_address
3289 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3290 const struct anv_image
*image
,
3291 VkImageAspectFlagBits aspect
)
3293 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3295 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3296 return anv_address_add(image
->planes
[plane
].address
,
3297 image
->planes
[plane
].fast_clear_state_offset
);
3300 static inline struct anv_address
3301 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3302 const struct anv_image
*image
,
3303 VkImageAspectFlagBits aspect
)
3305 struct anv_address addr
=
3306 anv_image_get_clear_color_addr(device
, image
, aspect
);
3308 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3309 device
->isl_dev
.ss
.clear_color_state_size
:
3310 device
->isl_dev
.ss
.clear_value_size
;
3311 return anv_address_add(addr
, clear_color_state_size
);
3314 static inline struct anv_address
3315 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3316 const struct anv_image
*image
,
3317 VkImageAspectFlagBits aspect
,
3318 uint32_t level
, uint32_t array_layer
)
3320 assert(level
< anv_image_aux_levels(image
, aspect
));
3321 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3322 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3323 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3325 struct anv_address addr
=
3326 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3327 addr
.offset
+= 4; /* Go past the fast clear type */
3329 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3330 for (uint32_t l
= 0; l
< level
; l
++)
3331 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3333 addr
.offset
+= level
* image
->array_size
* 4;
3335 addr
.offset
+= array_layer
* 4;
3337 assert(addr
.offset
<
3338 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3342 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3344 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3345 const struct anv_image
*image
)
3347 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3350 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3351 * struct. There's documentation which suggests that this feature actually
3352 * reduces performance on BDW, but it has only been observed to help so
3353 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3354 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3356 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3359 return image
->samples
== 1;
3363 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3364 const struct anv_image
*image
,
3367 return device
->info
.has_aux_map
&&
3368 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3372 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3373 const struct anv_image
*image
,
3374 VkImageAspectFlagBits aspect
,
3375 enum isl_aux_usage aux_usage
,
3377 uint32_t base_layer
,
3378 uint32_t layer_count
);
3381 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3382 const struct anv_image
*image
,
3383 VkImageAspectFlagBits aspect
,
3384 enum isl_aux_usage aux_usage
,
3385 enum isl_format format
, struct isl_swizzle swizzle
,
3386 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3387 VkRect2D area
, union isl_color_value clear_color
);
3389 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3390 const struct anv_image
*image
,
3391 VkImageAspectFlags aspects
,
3392 enum isl_aux_usage depth_aux_usage
,
3394 uint32_t base_layer
, uint32_t layer_count
,
3396 float depth_value
, uint8_t stencil_value
);
3398 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3399 const struct anv_image
*src_image
,
3400 enum isl_aux_usage src_aux_usage
,
3401 uint32_t src_level
, uint32_t src_base_layer
,
3402 const struct anv_image
*dst_image
,
3403 enum isl_aux_usage dst_aux_usage
,
3404 uint32_t dst_level
, uint32_t dst_base_layer
,
3405 VkImageAspectFlagBits aspect
,
3406 uint32_t src_x
, uint32_t src_y
,
3407 uint32_t dst_x
, uint32_t dst_y
,
3408 uint32_t width
, uint32_t height
,
3409 uint32_t layer_count
,
3410 enum blorp_filter filter
);
3412 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3413 const struct anv_image
*image
,
3414 VkImageAspectFlagBits aspect
, uint32_t level
,
3415 uint32_t base_layer
, uint32_t layer_count
,
3416 enum isl_aux_op hiz_op
);
3418 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3419 const struct anv_image
*image
,
3420 VkImageAspectFlags aspects
,
3422 uint32_t base_layer
, uint32_t layer_count
,
3423 VkRect2D area
, uint8_t stencil_value
);
3425 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3426 const struct anv_image
*image
,
3427 enum isl_format format
,
3428 VkImageAspectFlagBits aspect
,
3429 uint32_t base_layer
, uint32_t layer_count
,
3430 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3433 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3434 const struct anv_image
*image
,
3435 enum isl_format format
,
3436 VkImageAspectFlagBits aspect
, uint32_t level
,
3437 uint32_t base_layer
, uint32_t layer_count
,
3438 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3442 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3443 const struct anv_image
*image
,
3444 VkImageAspectFlagBits aspect
,
3445 uint32_t base_level
, uint32_t level_count
,
3446 uint32_t base_layer
, uint32_t layer_count
);
3449 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3450 const struct anv_image
*image
,
3451 const VkImageAspectFlagBits aspect
,
3452 const VkImageLayout layout
);
3454 enum anv_fast_clear_type
3455 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3456 const struct anv_image
* const image
,
3457 const VkImageAspectFlagBits aspect
,
3458 const VkImageLayout layout
);
3460 /* This is defined as a macro so that it works for both
3461 * VkImageSubresourceRange and VkImageSubresourceLayers
3463 #define anv_get_layerCount(_image, _range) \
3464 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3465 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3467 static inline uint32_t
3468 anv_get_levelCount(const struct anv_image
*image
,
3469 const VkImageSubresourceRange
*range
)
3471 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3472 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3475 static inline VkImageAspectFlags
3476 anv_image_expand_aspects(const struct anv_image
*image
,
3477 VkImageAspectFlags aspects
)
3479 /* If the underlying image has color plane aspects and
3480 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3481 * the underlying image. */
3482 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3483 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3484 return image
->aspects
;
3490 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3491 VkImageAspectFlags aspects2
)
3493 if (aspects1
== aspects2
)
3496 /* Only 1 color aspects are compatibles. */
3497 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3498 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3499 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3505 struct anv_image_view
{
3506 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3508 VkImageAspectFlags aspect_mask
;
3510 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3514 uint32_t image_plane
;
3516 struct isl_view isl
;
3519 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3520 * image layout of SHADER_READ_ONLY_OPTIMAL or
3521 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3523 struct anv_surface_state optimal_sampler_surface_state
;
3526 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3527 * image layout of GENERAL.
3529 struct anv_surface_state general_sampler_surface_state
;
3532 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3533 * states for write-only and readable, using the real format for
3534 * write-only and the lowered format for readable.
3536 struct anv_surface_state storage_surface_state
;
3537 struct anv_surface_state writeonly_storage_surface_state
;
3539 struct brw_image_param storage_image_param
;
3543 enum anv_image_view_state_flags
{
3544 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3545 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3548 void anv_image_fill_surface_state(struct anv_device
*device
,
3549 const struct anv_image
*image
,
3550 VkImageAspectFlagBits aspect
,
3551 const struct isl_view
*view
,
3552 isl_surf_usage_flags_t view_usage
,
3553 enum isl_aux_usage aux_usage
,
3554 const union isl_color_value
*clear_color
,
3555 enum anv_image_view_state_flags flags
,
3556 struct anv_surface_state
*state_inout
,
3557 struct brw_image_param
*image_param_out
);
3559 struct anv_image_create_info
{
3560 const VkImageCreateInfo
*vk_info
;
3562 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3563 isl_tiling_flags_t isl_tiling_flags
;
3565 /** These flags will be added to any derived from VkImageCreateInfo. */
3566 isl_surf_usage_flags_t isl_extra_usage_flags
;
3569 bool external_format
;
3572 VkResult
anv_image_create(VkDevice _device
,
3573 const struct anv_image_create_info
*info
,
3574 const VkAllocationCallbacks
* alloc
,
3577 const struct anv_surface
*
3578 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3579 VkImageAspectFlags aspect_mask
);
3582 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3584 static inline struct VkExtent3D
3585 anv_sanitize_image_extent(const VkImageType imageType
,
3586 const struct VkExtent3D imageExtent
)
3588 switch (imageType
) {
3589 case VK_IMAGE_TYPE_1D
:
3590 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3591 case VK_IMAGE_TYPE_2D
:
3592 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3593 case VK_IMAGE_TYPE_3D
:
3596 unreachable("invalid image type");
3600 static inline struct VkOffset3D
3601 anv_sanitize_image_offset(const VkImageType imageType
,
3602 const struct VkOffset3D imageOffset
)
3604 switch (imageType
) {
3605 case VK_IMAGE_TYPE_1D
:
3606 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3607 case VK_IMAGE_TYPE_2D
:
3608 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3609 case VK_IMAGE_TYPE_3D
:
3612 unreachable("invalid image type");
3616 VkFormatFeatureFlags
3617 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3619 const struct anv_format
*anv_format
,
3620 VkImageTiling vk_tiling
);
3622 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3623 struct anv_state state
,
3624 enum isl_format format
,
3625 struct anv_address address
,
3626 uint32_t range
, uint32_t stride
);
3629 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3630 const struct anv_attachment_state
*att_state
,
3631 const struct anv_image_view
*iview
)
3633 const struct isl_format_layout
*view_fmtl
=
3634 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3636 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3637 if (view_fmtl->channels.c.bits) \
3638 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3640 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3641 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3642 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3643 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3645 #undef COPY_CLEAR_COLOR_CHANNEL
3649 struct anv_ycbcr_conversion
{
3650 const struct anv_format
* format
;
3651 VkSamplerYcbcrModelConversion ycbcr_model
;
3652 VkSamplerYcbcrRange ycbcr_range
;
3653 VkComponentSwizzle mapping
[4];
3654 VkChromaLocation chroma_offsets
[2];
3655 VkFilter chroma_filter
;
3656 bool chroma_reconstruction
;
3659 struct anv_sampler
{
3660 uint32_t state
[3][4];
3662 struct anv_ycbcr_conversion
*conversion
;
3664 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3665 * and with a 32-byte stride for use as bindless samplers.
3667 struct anv_state bindless_state
;
3670 struct anv_framebuffer
{
3675 uint32_t attachment_count
;
3676 struct anv_image_view
* attachments
[0];
3679 struct anv_subpass_attachment
{
3680 VkImageUsageFlagBits usage
;
3681 uint32_t attachment
;
3682 VkImageLayout layout
;
3685 struct anv_subpass
{
3686 uint32_t attachment_count
;
3689 * A pointer to all attachment references used in this subpass.
3690 * Only valid if ::attachment_count > 0.
3692 struct anv_subpass_attachment
* attachments
;
3693 uint32_t input_count
;
3694 struct anv_subpass_attachment
* input_attachments
;
3695 uint32_t color_count
;
3696 struct anv_subpass_attachment
* color_attachments
;
3697 struct anv_subpass_attachment
* resolve_attachments
;
3699 struct anv_subpass_attachment
* depth_stencil_attachment
;
3700 struct anv_subpass_attachment
* ds_resolve_attachment
;
3701 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3702 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3706 /** Subpass has a depth/stencil self-dependency */
3707 bool has_ds_self_dep
;
3709 /** Subpass has at least one color resolve attachment */
3710 bool has_color_resolve
;
3713 static inline unsigned
3714 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3716 return MAX2(1, util_bitcount(subpass
->view_mask
));
3719 struct anv_render_pass_attachment
{
3720 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3721 * its members individually.
3725 VkImageUsageFlags usage
;
3726 VkAttachmentLoadOp load_op
;
3727 VkAttachmentStoreOp store_op
;
3728 VkAttachmentLoadOp stencil_load_op
;
3729 VkImageLayout initial_layout
;
3730 VkImageLayout final_layout
;
3731 VkImageLayout first_subpass_layout
;
3733 /* The subpass id in which the attachment will be used last. */
3734 uint32_t last_subpass_idx
;
3737 struct anv_render_pass
{
3738 uint32_t attachment_count
;
3739 uint32_t subpass_count
;
3740 /* An array of subpass_count+1 flushes, one per subpass boundary */
3741 enum anv_pipe_bits
* subpass_flushes
;
3742 struct anv_render_pass_attachment
* attachments
;
3743 struct anv_subpass subpasses
[0];
3746 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3748 struct anv_query_pool
{
3750 VkQueryPipelineStatisticFlags pipeline_statistics
;
3751 /** Stride between slots, in bytes */
3753 /** Number of slots in this query pool */
3758 int anv_get_instance_entrypoint_index(const char *name
);
3759 int anv_get_device_entrypoint_index(const char *name
);
3760 int anv_get_physical_device_entrypoint_index(const char *name
);
3762 const char *anv_get_instance_entry_name(int index
);
3763 const char *anv_get_physical_device_entry_name(int index
);
3764 const char *anv_get_device_entry_name(int index
);
3767 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3768 const struct anv_instance_extension_table
*instance
);
3770 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3771 const struct anv_instance_extension_table
*instance
);
3773 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3774 const struct anv_instance_extension_table
*instance
,
3775 const struct anv_device_extension_table
*device
);
3777 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3780 void anv_dump_image_to_ppm(struct anv_device
*device
,
3781 struct anv_image
*image
, unsigned miplevel
,
3782 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3783 const char *filename
);
3785 enum anv_dump_action
{
3786 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3789 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3790 void anv_dump_finish(void);
3792 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3794 static inline uint32_t
3795 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3797 /* This function must be called from within a subpass. */
3798 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3800 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3802 /* The id of this subpass shouldn't exceed the number of subpasses in this
3803 * render pass minus 1.
3805 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3809 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
3810 void anv_device_perf_init(struct anv_device
*device
);
3812 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3814 static inline struct __anv_type * \
3815 __anv_type ## _from_handle(__VkType _handle) \
3817 return (struct __anv_type *) _handle; \
3820 static inline __VkType \
3821 __anv_type ## _to_handle(struct __anv_type *_obj) \
3823 return (__VkType) _obj; \
3826 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3828 static inline struct __anv_type * \
3829 __anv_type ## _from_handle(__VkType _handle) \
3831 return (struct __anv_type *)(uintptr_t) _handle; \
3834 static inline __VkType \
3835 __anv_type ## _to_handle(struct __anv_type *_obj) \
3837 return (__VkType)(uintptr_t) _obj; \
3840 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3841 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3843 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3844 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3845 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3846 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3847 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3849 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3850 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3851 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3852 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3853 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3854 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3855 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3856 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3857 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3858 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3859 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3860 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3861 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3862 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3863 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3864 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3865 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3866 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3867 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3868 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3869 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3870 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3871 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3873 /* Gen-specific function declarations */
3875 # include "anv_genX.h"
3877 # define genX(x) gen7_##x
3878 # include "anv_genX.h"
3880 # define genX(x) gen75_##x
3881 # include "anv_genX.h"
3883 # define genX(x) gen8_##x
3884 # include "anv_genX.h"
3886 # define genX(x) gen9_##x
3887 # include "anv_genX.h"
3889 # define genX(x) gen10_##x
3890 # include "anv_genX.h"
3892 # define genX(x) gen11_##x
3893 # include "anv_genX.h"
3895 # define genX(x) gen12_##x
3896 # include "anv_genX.h"
3900 #endif /* ANV_PRIVATE_H */