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anv/cmd_buffer: Add a mark_image_written helper
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 /* Pre-declarations needed for WSI entrypoints */
56 struct wl_surface;
57 struct wl_display;
58 typedef struct xcb_connection_t xcb_connection_t;
59 typedef uint32_t xcb_visualid_t;
60 typedef uint32_t xcb_window_t;
61
62 struct anv_buffer;
63 struct anv_buffer_view;
64 struct anv_image_view;
65 struct anv_instance;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "anv_extensions.h"
76 #include "isl/isl.h"
77
78 #include "common/gen_debug.h"
79 #include "common/intel_log.h"
80 #include "wsi_common.h"
81
82 /* Allowing different clear colors requires us to perform a depth resolve at
83 * the end of certain render passes. This is because while slow clears store
84 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
85 * See the PRMs for examples describing when additional resolves would be
86 * necessary. To enable fast clears without requiring extra resolves, we set
87 * the clear value to a globally-defined one. We could allow different values
88 * if the user doesn't expect coherent data during or after a render passes
89 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
90 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
91 * 1.0f seems to be the only value used. The only application that doesn't set
92 * this value does so through the usage of an seemingly uninitialized clear
93 * value.
94 */
95 #define ANV_HZ_FC_VAL 1.0f
96
97 #define MAX_VBS 28
98 #define MAX_SETS 8
99 #define MAX_RTS 8
100 #define MAX_VIEWPORTS 16
101 #define MAX_SCISSORS 16
102 #define MAX_PUSH_CONSTANTS_SIZE 128
103 #define MAX_DYNAMIC_BUFFERS 16
104 #define MAX_IMAGES 8
105 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
106
107 #define ANV_SVGS_VB_INDEX MAX_VBS
108 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
109
110 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111
112 static inline uint32_t
113 align_down_npot_u32(uint32_t v, uint32_t a)
114 {
115 return v - (v % a);
116 }
117
118 static inline uint32_t
119 align_u32(uint32_t v, uint32_t a)
120 {
121 assert(a != 0 && a == (a & -a));
122 return (v + a - 1) & ~(a - 1);
123 }
124
125 static inline uint64_t
126 align_u64(uint64_t v, uint64_t a)
127 {
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
130 }
131
132 static inline int32_t
133 align_i32(int32_t v, int32_t a)
134 {
135 assert(a != 0 && a == (a & -a));
136 return (v + a - 1) & ~(a - 1);
137 }
138
139 /** Alignment must be a power of 2. */
140 static inline bool
141 anv_is_aligned(uintmax_t n, uintmax_t a)
142 {
143 assert(a == (a & -a));
144 return (n & (a - 1)) == 0;
145 }
146
147 static inline uint32_t
148 anv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155
156 static inline float
157 anv_clamp_f(float f, float min, float max)
158 {
159 assert(min < max);
160
161 if (f > max)
162 return max;
163 else if (f < min)
164 return min;
165 else
166 return f;
167 }
168
169 static inline bool
170 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
171 {
172 if (*inout_mask & clear_mask) {
173 *inout_mask &= ~clear_mask;
174 return true;
175 } else {
176 return false;
177 }
178 }
179
180 static inline union isl_color_value
181 vk_to_isl_color(VkClearColorValue color)
182 {
183 return (union isl_color_value) {
184 .u32 = {
185 color.uint32[0],
186 color.uint32[1],
187 color.uint32[2],
188 color.uint32[3],
189 },
190 };
191 }
192
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
197
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 })
202
203 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
204 * to be added here in order to utilize mapping in debug/error/perf macros.
205 */
206 #define REPORT_OBJECT_TYPE(o) \
207 __builtin_choose_expr ( \
208 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
209 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
210 __builtin_choose_expr ( \
211 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
212 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
213 __builtin_choose_expr ( \
214 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
215 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
216 __builtin_choose_expr ( \
217 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
218 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
219 __builtin_choose_expr ( \
220 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
221 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
222 __builtin_choose_expr ( \
223 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
224 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
225 __builtin_choose_expr ( \
226 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
227 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
228 __builtin_choose_expr ( \
229 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
230 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
231 __builtin_choose_expr ( \
232 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
233 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
234 __builtin_choose_expr ( \
235 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
236 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
237 __builtin_choose_expr ( \
238 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
239 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
240 __builtin_choose_expr ( \
241 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
242 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
243 __builtin_choose_expr ( \
244 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
245 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
246 __builtin_choose_expr ( \
247 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
248 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
249 __builtin_choose_expr ( \
250 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
251 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
252 __builtin_choose_expr ( \
253 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
254 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
255 __builtin_choose_expr ( \
256 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
257 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
258 __builtin_choose_expr ( \
259 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
260 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
261 __builtin_choose_expr ( \
262 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
263 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
264 __builtin_choose_expr ( \
265 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
266 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
267 __builtin_choose_expr ( \
268 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
269 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
270 __builtin_choose_expr ( \
271 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
272 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
273 __builtin_choose_expr ( \
274 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
275 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
276 __builtin_choose_expr ( \
277 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
278 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), void*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
300 /* The void expression results in a compile-time error \
301 when assigning the result to something. */ \
302 (void)0)))))))))))))))))))))))))))))))
303
304 /* Whenever we generate an error, pass it through this function. Useful for
305 * debugging, where we can break on it. Only call at error site, not when
306 * propagating errors. Might be useful to plug in a stack trace here.
307 */
308
309 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
310 VkDebugReportObjectTypeEXT type, VkResult error,
311 const char *file, int line, const char *format, ...);
312
313 #ifdef DEBUG
314 #define vk_error(error) __vk_errorf(NULL, NULL,\
315 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
316 error, __FILE__, __LINE__, NULL)
317 #define vk_errorf(instance, obj, error, format, ...)\
318 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
319 __FILE__, __LINE__, format, ## __VA_ARGS__)
320 #else
321 #define vk_error(error) error
322 #define vk_errorf(instance, obj, error, format, ...) error
323 #endif
324
325 /**
326 * Warn on ignored extension structs.
327 *
328 * The Vulkan spec requires us to ignore unsupported or unknown structs in
329 * a pNext chain. In debug mode, emitting warnings for ignored structs may
330 * help us discover structs that we should not have ignored.
331 *
332 *
333 * From the Vulkan 1.0.38 spec:
334 *
335 * Any component of the implementation (the loader, any enabled layers,
336 * and drivers) must skip over, without processing (other than reading the
337 * sType and pNext members) any chained structures with sType values not
338 * defined by extensions supported by that component.
339 */
340 #define anv_debug_ignored_stype(sType) \
341 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
342
343 void __anv_perf_warn(struct anv_instance *instance, const void *object,
344 VkDebugReportObjectTypeEXT type, const char *file,
345 int line, const char *format, ...)
346 anv_printflike(6, 7);
347 void anv_loge(const char *format, ...) anv_printflike(1, 2);
348 void anv_loge_v(const char *format, va_list va);
349
350 /**
351 * Print a FINISHME message, including its source location.
352 */
353 #define anv_finishme(format, ...) \
354 do { \
355 static bool reported = false; \
356 if (!reported) { \
357 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
358 ##__VA_ARGS__); \
359 reported = true; \
360 } \
361 } while (0)
362
363 /**
364 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
365 */
366 #define anv_perf_warn(instance, obj, format, ...) \
367 do { \
368 static bool reported = false; \
369 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
370 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
371 format, ##__VA_ARGS__); \
372 reported = true; \
373 } \
374 } while (0)
375
376 /* A non-fatal assert. Useful for debugging. */
377 #ifdef DEBUG
378 #define anv_assert(x) ({ \
379 if (unlikely(!(x))) \
380 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
381 })
382 #else
383 #define anv_assert(x)
384 #endif
385
386 /* A multi-pointer allocator
387 *
388 * When copying data structures from the user (such as a render pass), it's
389 * common to need to allocate data for a bunch of different things. Instead
390 * of doing several allocations and having to handle all of the error checking
391 * that entails, it can be easier to do a single allocation. This struct
392 * helps facilitate that. The intended usage looks like this:
393 *
394 * ANV_MULTIALLOC(ma)
395 * anv_multialloc_add(&ma, &main_ptr, 1);
396 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
397 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
398 *
399 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
400 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
401 */
402 struct anv_multialloc {
403 size_t size;
404 size_t align;
405
406 uint32_t ptr_count;
407 void **ptrs[8];
408 };
409
410 #define ANV_MULTIALLOC_INIT \
411 ((struct anv_multialloc) { 0, })
412
413 #define ANV_MULTIALLOC(_name) \
414 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
415
416 __attribute__((always_inline))
417 static inline void
418 _anv_multialloc_add(struct anv_multialloc *ma,
419 void **ptr, size_t size, size_t align)
420 {
421 size_t offset = align_u64(ma->size, align);
422 ma->size = offset + size;
423 ma->align = MAX2(ma->align, align);
424
425 /* Store the offset in the pointer. */
426 *ptr = (void *)(uintptr_t)offset;
427
428 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
429 ma->ptrs[ma->ptr_count++] = ptr;
430 }
431
432 #define anv_multialloc_add_size(_ma, _ptr, _size) \
433 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
434
435 #define anv_multialloc_add(_ma, _ptr, _count) \
436 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
437
438 __attribute__((always_inline))
439 static inline void *
440 anv_multialloc_alloc(struct anv_multialloc *ma,
441 const VkAllocationCallbacks *alloc,
442 VkSystemAllocationScope scope)
443 {
444 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
445 if (!ptr)
446 return NULL;
447
448 /* Fill out each of the pointers with their final value.
449 *
450 * for (uint32_t i = 0; i < ma->ptr_count; i++)
451 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
452 *
453 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
454 * constant, GCC is incapable of figuring this out and unrolling the loop
455 * so we have to give it a little help.
456 */
457 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
458 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
459 if ((_i) < ma->ptr_count) \
460 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
461 _ANV_MULTIALLOC_UPDATE_POINTER(0);
462 _ANV_MULTIALLOC_UPDATE_POINTER(1);
463 _ANV_MULTIALLOC_UPDATE_POINTER(2);
464 _ANV_MULTIALLOC_UPDATE_POINTER(3);
465 _ANV_MULTIALLOC_UPDATE_POINTER(4);
466 _ANV_MULTIALLOC_UPDATE_POINTER(5);
467 _ANV_MULTIALLOC_UPDATE_POINTER(6);
468 _ANV_MULTIALLOC_UPDATE_POINTER(7);
469 #undef _ANV_MULTIALLOC_UPDATE_POINTER
470
471 return ptr;
472 }
473
474 __attribute__((always_inline))
475 static inline void *
476 anv_multialloc_alloc2(struct anv_multialloc *ma,
477 const VkAllocationCallbacks *parent_alloc,
478 const VkAllocationCallbacks *alloc,
479 VkSystemAllocationScope scope)
480 {
481 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
482 }
483
484 struct anv_bo {
485 uint32_t gem_handle;
486
487 /* Index into the current validation list. This is used by the
488 * validation list building alrogithm to track which buffers are already
489 * in the validation list so that we can ensure uniqueness.
490 */
491 uint32_t index;
492
493 /* Last known offset. This value is provided by the kernel when we
494 * execbuf and is used as the presumed offset for the next bunch of
495 * relocations.
496 */
497 uint64_t offset;
498
499 uint64_t size;
500 void *map;
501
502 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
503 uint32_t flags;
504 };
505
506 static inline void
507 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
508 {
509 bo->gem_handle = gem_handle;
510 bo->index = 0;
511 bo->offset = -1;
512 bo->size = size;
513 bo->map = NULL;
514 bo->flags = 0;
515 }
516
517 /* Represents a lock-free linked list of "free" things. This is used by
518 * both the block pool and the state pools. Unfortunately, in order to
519 * solve the ABA problem, we can't use a single uint32_t head.
520 */
521 union anv_free_list {
522 struct {
523 int32_t offset;
524
525 /* A simple count that is incremented every time the head changes. */
526 uint32_t count;
527 };
528 uint64_t u64;
529 };
530
531 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
532
533 struct anv_block_state {
534 union {
535 struct {
536 uint32_t next;
537 uint32_t end;
538 };
539 uint64_t u64;
540 };
541 };
542
543 struct anv_block_pool {
544 struct anv_device *device;
545
546 uint64_t bo_flags;
547
548 struct anv_bo bo;
549
550 /* The offset from the start of the bo to the "center" of the block
551 * pool. Pointers to allocated blocks are given by
552 * bo.map + center_bo_offset + offsets.
553 */
554 uint32_t center_bo_offset;
555
556 /* Current memory map of the block pool. This pointer may or may not
557 * point to the actual beginning of the block pool memory. If
558 * anv_block_pool_alloc_back has ever been called, then this pointer
559 * will point to the "center" position of the buffer and all offsets
560 * (negative or positive) given out by the block pool alloc functions
561 * will be valid relative to this pointer.
562 *
563 * In particular, map == bo.map + center_offset
564 */
565 void *map;
566 int fd;
567
568 /**
569 * Array of mmaps and gem handles owned by the block pool, reclaimed when
570 * the block pool is destroyed.
571 */
572 struct u_vector mmap_cleanups;
573
574 struct anv_block_state state;
575
576 struct anv_block_state back_state;
577 };
578
579 /* Block pools are backed by a fixed-size 1GB memfd */
580 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
581
582 /* The center of the block pool is also the middle of the memfd. This may
583 * change in the future if we decide differently for some reason.
584 */
585 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
586
587 static inline uint32_t
588 anv_block_pool_size(struct anv_block_pool *pool)
589 {
590 return pool->state.end + pool->back_state.end;
591 }
592
593 struct anv_state {
594 int32_t offset;
595 uint32_t alloc_size;
596 void *map;
597 };
598
599 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
600
601 struct anv_fixed_size_state_pool {
602 union anv_free_list free_list;
603 struct anv_block_state block;
604 };
605
606 #define ANV_MIN_STATE_SIZE_LOG2 6
607 #define ANV_MAX_STATE_SIZE_LOG2 20
608
609 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
610
611 struct anv_state_pool {
612 struct anv_block_pool block_pool;
613
614 /* The size of blocks which will be allocated from the block pool */
615 uint32_t block_size;
616
617 /** Free list for "back" allocations */
618 union anv_free_list back_alloc_free_list;
619
620 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
621 };
622
623 struct anv_state_stream_block;
624
625 struct anv_state_stream {
626 struct anv_state_pool *state_pool;
627
628 /* The size of blocks to allocate from the state pool */
629 uint32_t block_size;
630
631 /* Current block we're allocating from */
632 struct anv_state block;
633
634 /* Offset into the current block at which to allocate the next state */
635 uint32_t next;
636
637 /* List of all blocks allocated from this pool */
638 struct anv_state_stream_block *block_list;
639 };
640
641 /* The block_pool functions exported for testing only. The block pool should
642 * only be used via a state pool (see below).
643 */
644 VkResult anv_block_pool_init(struct anv_block_pool *pool,
645 struct anv_device *device,
646 uint32_t initial_size,
647 uint64_t bo_flags);
648 void anv_block_pool_finish(struct anv_block_pool *pool);
649 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
650 uint32_t block_size);
651 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
652 uint32_t block_size);
653
654 VkResult anv_state_pool_init(struct anv_state_pool *pool,
655 struct anv_device *device,
656 uint32_t block_size,
657 uint64_t bo_flags);
658 void anv_state_pool_finish(struct anv_state_pool *pool);
659 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
660 uint32_t state_size, uint32_t alignment);
661 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
662 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
663 void anv_state_stream_init(struct anv_state_stream *stream,
664 struct anv_state_pool *state_pool,
665 uint32_t block_size);
666 void anv_state_stream_finish(struct anv_state_stream *stream);
667 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
668 uint32_t size, uint32_t alignment);
669
670 /**
671 * Implements a pool of re-usable BOs. The interface is identical to that
672 * of block_pool except that each block is its own BO.
673 */
674 struct anv_bo_pool {
675 struct anv_device *device;
676
677 uint64_t bo_flags;
678
679 void *free_list[16];
680 };
681
682 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
683 uint64_t bo_flags);
684 void anv_bo_pool_finish(struct anv_bo_pool *pool);
685 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
686 uint32_t size);
687 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
688
689 struct anv_scratch_bo {
690 bool exists;
691 struct anv_bo bo;
692 };
693
694 struct anv_scratch_pool {
695 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
696 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
697 };
698
699 void anv_scratch_pool_init(struct anv_device *device,
700 struct anv_scratch_pool *pool);
701 void anv_scratch_pool_finish(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
704 struct anv_scratch_pool *pool,
705 gl_shader_stage stage,
706 unsigned per_thread_scratch);
707
708 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
709 struct anv_bo_cache {
710 struct hash_table *bo_map;
711 pthread_mutex_t mutex;
712 };
713
714 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
715 void anv_bo_cache_finish(struct anv_bo_cache *cache);
716 VkResult anv_bo_cache_alloc(struct anv_device *device,
717 struct anv_bo_cache *cache,
718 uint64_t size, struct anv_bo **bo);
719 VkResult anv_bo_cache_import(struct anv_device *device,
720 struct anv_bo_cache *cache,
721 int fd, struct anv_bo **bo);
722 VkResult anv_bo_cache_export(struct anv_device *device,
723 struct anv_bo_cache *cache,
724 struct anv_bo *bo_in, int *fd_out);
725 void anv_bo_cache_release(struct anv_device *device,
726 struct anv_bo_cache *cache,
727 struct anv_bo *bo);
728
729 struct anv_memory_type {
730 /* Standard bits passed on to the client */
731 VkMemoryPropertyFlags propertyFlags;
732 uint32_t heapIndex;
733
734 /* Driver-internal book-keeping */
735 VkBufferUsageFlags valid_buffer_usage;
736 };
737
738 struct anv_memory_heap {
739 /* Standard bits passed on to the client */
740 VkDeviceSize size;
741 VkMemoryHeapFlags flags;
742
743 /* Driver-internal book-keeping */
744 bool supports_48bit_addresses;
745 };
746
747 struct anv_physical_device {
748 VK_LOADER_DATA _loader_data;
749
750 struct anv_instance * instance;
751 uint32_t chipset_id;
752 char path[20];
753 const char * name;
754 struct gen_device_info info;
755 /** Amount of "GPU memory" we want to advertise
756 *
757 * Clearly, this value is bogus since Intel is a UMA architecture. On
758 * gen7 platforms, we are limited by GTT size unless we want to implement
759 * fine-grained tracking and GTT splitting. On Broadwell and above we are
760 * practically unlimited. However, we will never report more than 3/4 of
761 * the total system ram to try and avoid running out of RAM.
762 */
763 bool supports_48bit_addresses;
764 struct brw_compiler * compiler;
765 struct isl_device isl_dev;
766 int cmd_parser_version;
767 bool has_exec_async;
768 bool has_exec_capture;
769 bool has_exec_fence;
770 bool has_syncobj;
771 bool has_syncobj_wait;
772
773 struct anv_device_extension_table supported_extensions;
774
775 uint32_t eu_total;
776 uint32_t subslice_total;
777
778 struct {
779 uint32_t type_count;
780 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
781 uint32_t heap_count;
782 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
783 } memory;
784
785 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
786 uint8_t driver_uuid[VK_UUID_SIZE];
787 uint8_t device_uuid[VK_UUID_SIZE];
788
789 struct wsi_device wsi_device;
790 int local_fd;
791 };
792
793 struct anv_instance {
794 VK_LOADER_DATA _loader_data;
795
796 VkAllocationCallbacks alloc;
797
798 uint32_t apiVersion;
799 struct anv_instance_extension_table enabled_extensions;
800 struct anv_dispatch_table dispatch;
801
802 int physicalDeviceCount;
803 struct anv_physical_device physicalDevice;
804
805 struct vk_debug_report_instance debug_report_callbacks;
806 };
807
808 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
809 void anv_finish_wsi(struct anv_physical_device *physical_device);
810
811 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
812 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
813 const char *name);
814
815 struct anv_queue {
816 VK_LOADER_DATA _loader_data;
817
818 struct anv_device * device;
819
820 struct anv_state_pool * pool;
821 };
822
823 struct anv_pipeline_cache {
824 struct anv_device * device;
825 pthread_mutex_t mutex;
826
827 struct hash_table * cache;
828 };
829
830 struct anv_pipeline_bind_map;
831
832 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
833 struct anv_device *device,
834 bool cache_enabled);
835 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
836
837 struct anv_shader_bin *
838 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
839 const void *key, uint32_t key_size);
840 struct anv_shader_bin *
841 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
842 const void *key_data, uint32_t key_size,
843 const void *kernel_data, uint32_t kernel_size,
844 const struct brw_stage_prog_data *prog_data,
845 uint32_t prog_data_size,
846 const struct anv_pipeline_bind_map *bind_map);
847
848 struct anv_device {
849 VK_LOADER_DATA _loader_data;
850
851 VkAllocationCallbacks alloc;
852
853 struct anv_instance * instance;
854 uint32_t chipset_id;
855 struct gen_device_info info;
856 struct isl_device isl_dev;
857 int context_id;
858 int fd;
859 bool can_chain_batches;
860 bool robust_buffer_access;
861 struct anv_device_extension_table enabled_extensions;
862 struct anv_dispatch_table dispatch;
863
864 struct anv_bo_pool batch_bo_pool;
865
866 struct anv_bo_cache bo_cache;
867
868 struct anv_state_pool dynamic_state_pool;
869 struct anv_state_pool instruction_state_pool;
870 struct anv_state_pool surface_state_pool;
871
872 struct anv_bo workaround_bo;
873 struct anv_bo trivial_batch_bo;
874
875 struct anv_pipeline_cache blorp_shader_cache;
876 struct blorp_context blorp;
877
878 struct anv_state border_colors;
879
880 struct anv_queue queue;
881
882 struct anv_scratch_pool scratch_pool;
883
884 uint32_t default_mocs;
885
886 pthread_mutex_t mutex;
887 pthread_cond_t queue_submit;
888 bool lost;
889 };
890
891 static void inline
892 anv_state_flush(struct anv_device *device, struct anv_state state)
893 {
894 if (device->info.has_llc)
895 return;
896
897 gen_flush_range(state.map, state.alloc_size);
898 }
899
900 void anv_device_init_blorp(struct anv_device *device);
901 void anv_device_finish_blorp(struct anv_device *device);
902
903 VkResult anv_device_execbuf(struct anv_device *device,
904 struct drm_i915_gem_execbuffer2 *execbuf,
905 struct anv_bo **execbuf_bos);
906 VkResult anv_device_query_status(struct anv_device *device);
907 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
908 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
909 int64_t timeout);
910
911 void* anv_gem_mmap(struct anv_device *device,
912 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
913 void anv_gem_munmap(void *p, uint64_t size);
914 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
915 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
916 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
917 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
918 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
919 int anv_gem_execbuffer(struct anv_device *device,
920 struct drm_i915_gem_execbuffer2 *execbuf);
921 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
922 uint32_t stride, uint32_t tiling);
923 int anv_gem_create_context(struct anv_device *device);
924 int anv_gem_destroy_context(struct anv_device *device, int context);
925 int anv_gem_get_context_param(int fd, int context, uint32_t param,
926 uint64_t *value);
927 int anv_gem_get_param(int fd, uint32_t param);
928 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
929 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
930 int anv_gem_get_aperture(int fd, uint64_t *size);
931 bool anv_gem_supports_48b_addresses(int fd);
932 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
933 uint32_t *active, uint32_t *pending);
934 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
935 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
936 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
937 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
938 uint32_t read_domains, uint32_t write_domain);
939 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
940 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
941 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
942 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
943 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
944 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
945 uint32_t handle);
946 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
947 uint32_t handle, int fd);
948 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
949 bool anv_gem_supports_syncobj_wait(int fd);
950 int anv_gem_syncobj_wait(struct anv_device *device,
951 uint32_t *handles, uint32_t num_handles,
952 int64_t abs_timeout_ns, bool wait_all);
953
954 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
955
956 struct anv_reloc_list {
957 uint32_t num_relocs;
958 uint32_t array_length;
959 struct drm_i915_gem_relocation_entry * relocs;
960 struct anv_bo ** reloc_bos;
961 };
962
963 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
964 const VkAllocationCallbacks *alloc);
965 void anv_reloc_list_finish(struct anv_reloc_list *list,
966 const VkAllocationCallbacks *alloc);
967
968 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
969 const VkAllocationCallbacks *alloc,
970 uint32_t offset, struct anv_bo *target_bo,
971 uint32_t delta);
972
973 struct anv_batch_bo {
974 /* Link in the anv_cmd_buffer.owned_batch_bos list */
975 struct list_head link;
976
977 struct anv_bo bo;
978
979 /* Bytes actually consumed in this batch BO */
980 uint32_t length;
981
982 struct anv_reloc_list relocs;
983 };
984
985 struct anv_batch {
986 const VkAllocationCallbacks * alloc;
987
988 void * start;
989 void * end;
990 void * next;
991
992 struct anv_reloc_list * relocs;
993
994 /* This callback is called (with the associated user data) in the event
995 * that the batch runs out of space.
996 */
997 VkResult (*extend_cb)(struct anv_batch *, void *);
998 void * user_data;
999
1000 /**
1001 * Current error status of the command buffer. Used to track inconsistent
1002 * or incomplete command buffer states that are the consequence of run-time
1003 * errors such as out of memory scenarios. We want to track this in the
1004 * batch because the command buffer object is not visible to some parts
1005 * of the driver.
1006 */
1007 VkResult status;
1008 };
1009
1010 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1011 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1012 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1013 void *location, struct anv_bo *bo, uint32_t offset);
1014 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1015 struct anv_batch *batch);
1016
1017 static inline VkResult
1018 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1019 {
1020 assert(error != VK_SUCCESS);
1021 if (batch->status == VK_SUCCESS)
1022 batch->status = error;
1023 return batch->status;
1024 }
1025
1026 static inline bool
1027 anv_batch_has_error(struct anv_batch *batch)
1028 {
1029 return batch->status != VK_SUCCESS;
1030 }
1031
1032 struct anv_address {
1033 struct anv_bo *bo;
1034 uint32_t offset;
1035 };
1036
1037 static inline uint64_t
1038 _anv_combine_address(struct anv_batch *batch, void *location,
1039 const struct anv_address address, uint32_t delta)
1040 {
1041 if (address.bo == NULL) {
1042 return address.offset + delta;
1043 } else {
1044 assert(batch->start <= location && location < batch->end);
1045
1046 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1047 }
1048 }
1049
1050 #define __gen_address_type struct anv_address
1051 #define __gen_user_data struct anv_batch
1052 #define __gen_combine_address _anv_combine_address
1053
1054 /* Wrapper macros needed to work around preprocessor argument issues. In
1055 * particular, arguments don't get pre-evaluated if they are concatenated.
1056 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1057 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1058 * We can work around this easily enough with these helpers.
1059 */
1060 #define __anv_cmd_length(cmd) cmd ## _length
1061 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1062 #define __anv_cmd_header(cmd) cmd ## _header
1063 #define __anv_cmd_pack(cmd) cmd ## _pack
1064 #define __anv_reg_num(reg) reg ## _num
1065
1066 #define anv_pack_struct(dst, struc, ...) do { \
1067 struct struc __template = { \
1068 __VA_ARGS__ \
1069 }; \
1070 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1071 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1072 } while (0)
1073
1074 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1075 void *__dst = anv_batch_emit_dwords(batch, n); \
1076 if (__dst) { \
1077 struct cmd __template = { \
1078 __anv_cmd_header(cmd), \
1079 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1080 __VA_ARGS__ \
1081 }; \
1082 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1083 } \
1084 __dst; \
1085 })
1086
1087 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1088 do { \
1089 uint32_t *dw; \
1090 \
1091 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1092 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1093 if (!dw) \
1094 break; \
1095 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1096 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1097 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1098 } while (0)
1099
1100 #define anv_batch_emit(batch, cmd, name) \
1101 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1102 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1103 __builtin_expect(_dst != NULL, 1); \
1104 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1105 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1106 _dst = NULL; \
1107 }))
1108
1109 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1110 .GraphicsDataTypeGFDT = 0, \
1111 .LLCCacheabilityControlLLCCC = 0, \
1112 .L3CacheabilityControlL3CC = 1, \
1113 }
1114
1115 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1116 .LLCeLLCCacheabilityControlLLCCC = 0, \
1117 .L3CacheabilityControlL3CC = 1, \
1118 }
1119
1120 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1121 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1122 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1123 .AgeforQUADLRU = 0 \
1124 }
1125
1126 /* Skylake: MOCS is now an index into an array of 62 different caching
1127 * configurations programmed by the kernel.
1128 */
1129
1130 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1131 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1132 .IndextoMOCSTables = 2 \
1133 }
1134
1135 #define GEN9_MOCS_PTE { \
1136 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1137 .IndextoMOCSTables = 1 \
1138 }
1139
1140 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1141 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1142 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1143 .IndextoMOCSTables = 2 \
1144 }
1145
1146 #define GEN10_MOCS_PTE { \
1147 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1148 .IndextoMOCSTables = 1 \
1149 }
1150
1151 struct anv_device_memory {
1152 struct anv_bo * bo;
1153 struct anv_memory_type * type;
1154 VkDeviceSize map_size;
1155 void * map;
1156 };
1157
1158 /**
1159 * Header for Vertex URB Entry (VUE)
1160 */
1161 struct anv_vue_header {
1162 uint32_t Reserved;
1163 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1164 uint32_t ViewportIndex;
1165 float PointWidth;
1166 };
1167
1168 struct anv_descriptor_set_binding_layout {
1169 #ifndef NDEBUG
1170 /* The type of the descriptors in this binding */
1171 VkDescriptorType type;
1172 #endif
1173
1174 /* Number of array elements in this binding */
1175 uint16_t array_size;
1176
1177 /* Index into the flattend descriptor set */
1178 uint16_t descriptor_index;
1179
1180 /* Index into the dynamic state array for a dynamic buffer */
1181 int16_t dynamic_offset_index;
1182
1183 /* Index into the descriptor set buffer views */
1184 int16_t buffer_index;
1185
1186 struct {
1187 /* Index into the binding table for the associated surface */
1188 int16_t surface_index;
1189
1190 /* Index into the sampler table for the associated sampler */
1191 int16_t sampler_index;
1192
1193 /* Index into the image table for the associated image */
1194 int16_t image_index;
1195 } stage[MESA_SHADER_STAGES];
1196
1197 /* Immutable samplers (or NULL if no immutable samplers) */
1198 struct anv_sampler **immutable_samplers;
1199 };
1200
1201 struct anv_descriptor_set_layout {
1202 /* Descriptor set layouts can be destroyed at almost any time */
1203 uint32_t ref_cnt;
1204
1205 /* Number of bindings in this descriptor set */
1206 uint16_t binding_count;
1207
1208 /* Total size of the descriptor set with room for all array entries */
1209 uint16_t size;
1210
1211 /* Shader stages affected by this descriptor set */
1212 uint16_t shader_stages;
1213
1214 /* Number of buffers in this descriptor set */
1215 uint16_t buffer_count;
1216
1217 /* Number of dynamic offsets used by this descriptor set */
1218 uint16_t dynamic_offset_count;
1219
1220 /* Bindings in this descriptor set */
1221 struct anv_descriptor_set_binding_layout binding[0];
1222 };
1223
1224 static inline void
1225 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1226 {
1227 assert(layout && layout->ref_cnt >= 1);
1228 p_atomic_inc(&layout->ref_cnt);
1229 }
1230
1231 static inline void
1232 anv_descriptor_set_layout_unref(struct anv_device *device,
1233 struct anv_descriptor_set_layout *layout)
1234 {
1235 assert(layout && layout->ref_cnt >= 1);
1236 if (p_atomic_dec_zero(&layout->ref_cnt))
1237 vk_free(&device->alloc, layout);
1238 }
1239
1240 struct anv_descriptor {
1241 VkDescriptorType type;
1242
1243 union {
1244 struct {
1245 VkImageLayout layout;
1246 struct anv_image_view *image_view;
1247 struct anv_sampler *sampler;
1248 };
1249
1250 struct {
1251 struct anv_buffer *buffer;
1252 uint64_t offset;
1253 uint64_t range;
1254 };
1255
1256 struct anv_buffer_view *buffer_view;
1257 };
1258 };
1259
1260 struct anv_descriptor_set {
1261 struct anv_descriptor_set_layout *layout;
1262 uint32_t size;
1263 uint32_t buffer_count;
1264 struct anv_buffer_view *buffer_views;
1265 struct anv_descriptor descriptors[0];
1266 };
1267
1268 struct anv_buffer_view {
1269 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1270 struct anv_bo *bo;
1271 uint32_t offset; /**< Offset into bo. */
1272 uint64_t range; /**< VkBufferViewCreateInfo::range */
1273
1274 struct anv_state surface_state;
1275 struct anv_state storage_surface_state;
1276 struct anv_state writeonly_storage_surface_state;
1277
1278 struct brw_image_param storage_image_param;
1279 };
1280
1281 struct anv_push_descriptor_set {
1282 struct anv_descriptor_set set;
1283
1284 /* Put this field right behind anv_descriptor_set so it fills up the
1285 * descriptors[0] field. */
1286 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1287 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1288 };
1289
1290 struct anv_descriptor_pool {
1291 uint32_t size;
1292 uint32_t next;
1293 uint32_t free_list;
1294
1295 struct anv_state_stream surface_state_stream;
1296 void *surface_state_free_list;
1297
1298 char data[0];
1299 };
1300
1301 enum anv_descriptor_template_entry_type {
1302 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1303 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1304 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1305 };
1306
1307 struct anv_descriptor_template_entry {
1308 /* The type of descriptor in this entry */
1309 VkDescriptorType type;
1310
1311 /* Binding in the descriptor set */
1312 uint32_t binding;
1313
1314 /* Offset at which to write into the descriptor set binding */
1315 uint32_t array_element;
1316
1317 /* Number of elements to write into the descriptor set binding */
1318 uint32_t array_count;
1319
1320 /* Offset into the user provided data */
1321 size_t offset;
1322
1323 /* Stride between elements into the user provided data */
1324 size_t stride;
1325 };
1326
1327 struct anv_descriptor_update_template {
1328 VkPipelineBindPoint bind_point;
1329
1330 /* The descriptor set this template corresponds to. This value is only
1331 * valid if the template was created with the templateType
1332 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1333 */
1334 uint8_t set;
1335
1336 /* Number of entries in this template */
1337 uint32_t entry_count;
1338
1339 /* Entries of the template */
1340 struct anv_descriptor_template_entry entries[0];
1341 };
1342
1343 size_t
1344 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1345
1346 size_t
1347 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1348
1349 void
1350 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1351 const struct gen_device_info * const devinfo,
1352 const VkDescriptorImageInfo * const info,
1353 VkDescriptorType type,
1354 uint32_t binding,
1355 uint32_t element);
1356
1357 void
1358 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1359 VkDescriptorType type,
1360 struct anv_buffer_view *buffer_view,
1361 uint32_t binding,
1362 uint32_t element);
1363
1364 void
1365 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1366 struct anv_device *device,
1367 struct anv_state_stream *alloc_stream,
1368 VkDescriptorType type,
1369 struct anv_buffer *buffer,
1370 uint32_t binding,
1371 uint32_t element,
1372 VkDeviceSize offset,
1373 VkDeviceSize range);
1374
1375 void
1376 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1377 struct anv_device *device,
1378 struct anv_state_stream *alloc_stream,
1379 const struct anv_descriptor_update_template *template,
1380 const void *data);
1381
1382 VkResult
1383 anv_descriptor_set_create(struct anv_device *device,
1384 struct anv_descriptor_pool *pool,
1385 struct anv_descriptor_set_layout *layout,
1386 struct anv_descriptor_set **out_set);
1387
1388 void
1389 anv_descriptor_set_destroy(struct anv_device *device,
1390 struct anv_descriptor_pool *pool,
1391 struct anv_descriptor_set *set);
1392
1393 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1394
1395 struct anv_pipeline_binding {
1396 /* The descriptor set this surface corresponds to. The special value of
1397 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1398 * to a color attachment and not a regular descriptor.
1399 */
1400 uint8_t set;
1401
1402 /* Binding in the descriptor set */
1403 uint32_t binding;
1404
1405 /* Index in the binding */
1406 uint32_t index;
1407
1408 /* Plane in the binding index */
1409 uint8_t plane;
1410
1411 /* Input attachment index (relative to the subpass) */
1412 uint8_t input_attachment_index;
1413
1414 /* For a storage image, whether it is write-only */
1415 bool write_only;
1416 };
1417
1418 struct anv_pipeline_layout {
1419 struct {
1420 struct anv_descriptor_set_layout *layout;
1421 uint32_t dynamic_offset_start;
1422 } set[MAX_SETS];
1423
1424 uint32_t num_sets;
1425
1426 struct {
1427 bool has_dynamic_offsets;
1428 } stage[MESA_SHADER_STAGES];
1429
1430 unsigned char sha1[20];
1431 };
1432
1433 struct anv_buffer {
1434 struct anv_device * device;
1435 VkDeviceSize size;
1436
1437 VkBufferUsageFlags usage;
1438
1439 /* Set when bound */
1440 struct anv_bo * bo;
1441 VkDeviceSize offset;
1442 };
1443
1444 static inline uint64_t
1445 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1446 {
1447 assert(offset <= buffer->size);
1448 if (range == VK_WHOLE_SIZE) {
1449 return buffer->size - offset;
1450 } else {
1451 assert(range <= buffer->size);
1452 return range;
1453 }
1454 }
1455
1456 enum anv_cmd_dirty_bits {
1457 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1458 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1459 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1460 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1461 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1462 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1463 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1464 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1465 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1466 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1467 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1468 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1469 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1470 };
1471 typedef uint32_t anv_cmd_dirty_mask_t;
1472
1473 enum anv_pipe_bits {
1474 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1475 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1476 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1477 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1478 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1479 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1480 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1481 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1482 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1483 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1484 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1485
1486 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1487 * a flush has happened but not a CS stall. The next time we do any sort
1488 * of invalidation we need to insert a CS stall at that time. Otherwise,
1489 * we would have to CS stall on every flush which could be bad.
1490 */
1491 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1492 };
1493
1494 #define ANV_PIPE_FLUSH_BITS ( \
1495 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1496 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1497 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1498
1499 #define ANV_PIPE_STALL_BITS ( \
1500 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1501 ANV_PIPE_DEPTH_STALL_BIT | \
1502 ANV_PIPE_CS_STALL_BIT)
1503
1504 #define ANV_PIPE_INVALIDATE_BITS ( \
1505 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1506 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1507 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1508 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1509 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1510 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1511
1512 static inline enum anv_pipe_bits
1513 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1514 {
1515 enum anv_pipe_bits pipe_bits = 0;
1516
1517 unsigned b;
1518 for_each_bit(b, flags) {
1519 switch ((VkAccessFlagBits)(1 << b)) {
1520 case VK_ACCESS_SHADER_WRITE_BIT:
1521 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1522 break;
1523 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1524 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1525 break;
1526 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1527 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1528 break;
1529 case VK_ACCESS_TRANSFER_WRITE_BIT:
1530 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1531 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1532 break;
1533 default:
1534 break; /* Nothing to do */
1535 }
1536 }
1537
1538 return pipe_bits;
1539 }
1540
1541 static inline enum anv_pipe_bits
1542 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1543 {
1544 enum anv_pipe_bits pipe_bits = 0;
1545
1546 unsigned b;
1547 for_each_bit(b, flags) {
1548 switch ((VkAccessFlagBits)(1 << b)) {
1549 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1550 case VK_ACCESS_INDEX_READ_BIT:
1551 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1552 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1553 break;
1554 case VK_ACCESS_UNIFORM_READ_BIT:
1555 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1556 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1557 break;
1558 case VK_ACCESS_SHADER_READ_BIT:
1559 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1560 case VK_ACCESS_TRANSFER_READ_BIT:
1561 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1562 break;
1563 default:
1564 break; /* Nothing to do */
1565 }
1566 }
1567
1568 return pipe_bits;
1569 }
1570
1571 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1572 VK_IMAGE_ASPECT_COLOR_BIT | \
1573 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1574 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1575 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1576 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1577 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1578 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1579 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1580
1581 struct anv_vertex_binding {
1582 struct anv_buffer * buffer;
1583 VkDeviceSize offset;
1584 };
1585
1586 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1587 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1588
1589 struct anv_push_constants {
1590 /* Current allocated size of this push constants data structure.
1591 * Because a decent chunk of it may not be used (images on SKL, for
1592 * instance), we won't actually allocate the entire structure up-front.
1593 */
1594 uint32_t size;
1595
1596 /* Push constant data provided by the client through vkPushConstants */
1597 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1598
1599 /* Image data for image_load_store on pre-SKL */
1600 struct brw_image_param images[MAX_IMAGES];
1601 };
1602
1603 struct anv_dynamic_state {
1604 struct {
1605 uint32_t count;
1606 VkViewport viewports[MAX_VIEWPORTS];
1607 } viewport;
1608
1609 struct {
1610 uint32_t count;
1611 VkRect2D scissors[MAX_SCISSORS];
1612 } scissor;
1613
1614 float line_width;
1615
1616 struct {
1617 float bias;
1618 float clamp;
1619 float slope;
1620 } depth_bias;
1621
1622 float blend_constants[4];
1623
1624 struct {
1625 float min;
1626 float max;
1627 } depth_bounds;
1628
1629 struct {
1630 uint32_t front;
1631 uint32_t back;
1632 } stencil_compare_mask;
1633
1634 struct {
1635 uint32_t front;
1636 uint32_t back;
1637 } stencil_write_mask;
1638
1639 struct {
1640 uint32_t front;
1641 uint32_t back;
1642 } stencil_reference;
1643 };
1644
1645 extern const struct anv_dynamic_state default_dynamic_state;
1646
1647 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1648 const struct anv_dynamic_state *src,
1649 uint32_t copy_mask);
1650
1651 struct anv_surface_state {
1652 struct anv_state state;
1653 /** Address of the surface referred to by this state
1654 *
1655 * This address is relative to the start of the BO.
1656 */
1657 uint64_t address;
1658 /* Address of the aux surface, if any
1659 *
1660 * This field is 0 if and only if no aux surface exists.
1661 *
1662 * This address is relative to the start of the BO. On gen7, the bottom 12
1663 * bits of this address include extra aux information.
1664 */
1665 uint64_t aux_address;
1666 };
1667
1668 /**
1669 * Attachment state when recording a renderpass instance.
1670 *
1671 * The clear value is valid only if there exists a pending clear.
1672 */
1673 struct anv_attachment_state {
1674 enum isl_aux_usage aux_usage;
1675 enum isl_aux_usage input_aux_usage;
1676 struct anv_surface_state color;
1677 struct anv_surface_state input;
1678
1679 VkImageLayout current_layout;
1680 VkImageAspectFlags pending_clear_aspects;
1681 bool fast_clear;
1682 VkClearValue clear_value;
1683 bool clear_color_is_zero_one;
1684 bool clear_color_is_zero;
1685 };
1686
1687 /** State tracking for particular pipeline bind point
1688 *
1689 * This struct is the base struct for anv_cmd_graphics_state and
1690 * anv_cmd_compute_state. These are used to track state which is bound to a
1691 * particular type of pipeline. Generic state that applies per-stage such as
1692 * binding table offsets and push constants is tracked generically with a
1693 * per-stage array in anv_cmd_state.
1694 */
1695 struct anv_cmd_pipeline_state {
1696 struct anv_pipeline *pipeline;
1697 struct anv_pipeline_layout *layout;
1698
1699 struct anv_descriptor_set *descriptors[MAX_SETS];
1700 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1701
1702 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
1703 };
1704
1705 /** State tracking for graphics pipeline
1706 *
1707 * This has anv_cmd_pipeline_state as a base struct to track things which get
1708 * bound to a graphics pipeline. Along with general pipeline bind point state
1709 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1710 * state which is graphics-specific.
1711 */
1712 struct anv_cmd_graphics_state {
1713 struct anv_cmd_pipeline_state base;
1714
1715 anv_cmd_dirty_mask_t dirty;
1716 uint32_t vb_dirty;
1717
1718 struct anv_dynamic_state dynamic;
1719
1720 struct {
1721 struct anv_buffer *index_buffer;
1722 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1723 uint32_t index_offset;
1724 } gen7;
1725 };
1726
1727 /** State tracking for compute pipeline
1728 *
1729 * This has anv_cmd_pipeline_state as a base struct to track things which get
1730 * bound to a compute pipeline. Along with general pipeline bind point state
1731 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1732 * state which is compute-specific.
1733 */
1734 struct anv_cmd_compute_state {
1735 struct anv_cmd_pipeline_state base;
1736
1737 bool pipeline_dirty;
1738
1739 struct anv_address num_workgroups;
1740 };
1741
1742 /** State required while building cmd buffer */
1743 struct anv_cmd_state {
1744 /* PIPELINE_SELECT.PipelineSelection */
1745 uint32_t current_pipeline;
1746 const struct gen_l3_config * current_l3_config;
1747
1748 struct anv_cmd_graphics_state gfx;
1749 struct anv_cmd_compute_state compute;
1750
1751 enum anv_pipe_bits pending_pipe_bits;
1752 VkShaderStageFlags descriptors_dirty;
1753 VkShaderStageFlags push_constants_dirty;
1754
1755 struct anv_framebuffer * framebuffer;
1756 struct anv_render_pass * pass;
1757 struct anv_subpass * subpass;
1758 VkRect2D render_area;
1759 uint32_t restart_index;
1760 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1761 VkShaderStageFlags push_constant_stages;
1762 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1763 struct anv_state binding_tables[MESA_SHADER_STAGES];
1764 struct anv_state samplers[MESA_SHADER_STAGES];
1765
1766 /**
1767 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1768 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1769 * and before invoking the secondary in ExecuteCommands.
1770 */
1771 bool pma_fix_enabled;
1772
1773 /**
1774 * Whether or not we know for certain that HiZ is enabled for the current
1775 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1776 * enabled or not, this will be false.
1777 */
1778 bool hiz_enabled;
1779
1780 /**
1781 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1782 * valid only when recording a render pass instance.
1783 */
1784 struct anv_attachment_state * attachments;
1785
1786 /**
1787 * Surface states for color render targets. These are stored in a single
1788 * flat array. For depth-stencil attachments, the surface state is simply
1789 * left blank.
1790 */
1791 struct anv_state render_pass_states;
1792
1793 /**
1794 * A null surface state of the right size to match the framebuffer. This
1795 * is one of the states in render_pass_states.
1796 */
1797 struct anv_state null_surface_state;
1798 };
1799
1800 struct anv_cmd_pool {
1801 VkAllocationCallbacks alloc;
1802 struct list_head cmd_buffers;
1803 };
1804
1805 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1806
1807 enum anv_cmd_buffer_exec_mode {
1808 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1809 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1810 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1811 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1812 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1813 };
1814
1815 struct anv_cmd_buffer {
1816 VK_LOADER_DATA _loader_data;
1817
1818 struct anv_device * device;
1819
1820 struct anv_cmd_pool * pool;
1821 struct list_head pool_link;
1822
1823 struct anv_batch batch;
1824
1825 /* Fields required for the actual chain of anv_batch_bo's.
1826 *
1827 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1828 */
1829 struct list_head batch_bos;
1830 enum anv_cmd_buffer_exec_mode exec_mode;
1831
1832 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1833 * referenced by this command buffer
1834 *
1835 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1836 */
1837 struct u_vector seen_bbos;
1838
1839 /* A vector of int32_t's for every block of binding tables.
1840 *
1841 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1842 */
1843 struct u_vector bt_block_states;
1844 uint32_t bt_next;
1845
1846 struct anv_reloc_list surface_relocs;
1847 /** Last seen surface state block pool center bo offset */
1848 uint32_t last_ss_pool_center;
1849
1850 /* Serial for tracking buffer completion */
1851 uint32_t serial;
1852
1853 /* Stream objects for storing temporary data */
1854 struct anv_state_stream surface_state_stream;
1855 struct anv_state_stream dynamic_state_stream;
1856
1857 VkCommandBufferUsageFlags usage_flags;
1858 VkCommandBufferLevel level;
1859
1860 struct anv_cmd_state state;
1861 };
1862
1863 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1864 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1865 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1866 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1867 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1868 struct anv_cmd_buffer *secondary);
1869 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1870 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1871 struct anv_cmd_buffer *cmd_buffer,
1872 const VkSemaphore *in_semaphores,
1873 uint32_t num_in_semaphores,
1874 const VkSemaphore *out_semaphores,
1875 uint32_t num_out_semaphores,
1876 VkFence fence);
1877
1878 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1879
1880 VkResult
1881 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1882 gl_shader_stage stage, uint32_t size);
1883 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1884 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1885 (offsetof(struct anv_push_constants, field) + \
1886 sizeof(cmd_buffer->state.push_constants[0]->field)))
1887
1888 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1889 const void *data, uint32_t size, uint32_t alignment);
1890 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1891 uint32_t *a, uint32_t *b,
1892 uint32_t dwords, uint32_t alignment);
1893
1894 struct anv_address
1895 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1896 struct anv_state
1897 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1898 uint32_t entries, uint32_t *state_offset);
1899 struct anv_state
1900 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1901 struct anv_state
1902 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1903 uint32_t size, uint32_t alignment);
1904
1905 VkResult
1906 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1907
1908 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1909 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1910 bool depth_clamp_enable);
1911 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1912
1913 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1914 struct anv_render_pass *pass,
1915 struct anv_framebuffer *framebuffer,
1916 const VkClearValue *clear_values);
1917
1918 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1919
1920 struct anv_state
1921 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1922 gl_shader_stage stage);
1923 struct anv_state
1924 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1925
1926 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1927 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1928
1929 const struct anv_image_view *
1930 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1931
1932 VkResult
1933 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1934 uint32_t num_entries,
1935 uint32_t *state_offset,
1936 struct anv_state *bt_state);
1937
1938 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1939
1940 enum anv_fence_type {
1941 ANV_FENCE_TYPE_NONE = 0,
1942 ANV_FENCE_TYPE_BO,
1943 ANV_FENCE_TYPE_SYNCOBJ,
1944 };
1945
1946 enum anv_bo_fence_state {
1947 /** Indicates that this is a new (or newly reset fence) */
1948 ANV_BO_FENCE_STATE_RESET,
1949
1950 /** Indicates that this fence has been submitted to the GPU but is still
1951 * (as far as we know) in use by the GPU.
1952 */
1953 ANV_BO_FENCE_STATE_SUBMITTED,
1954
1955 ANV_BO_FENCE_STATE_SIGNALED,
1956 };
1957
1958 struct anv_fence_impl {
1959 enum anv_fence_type type;
1960
1961 union {
1962 /** Fence implementation for BO fences
1963 *
1964 * These fences use a BO and a set of CPU-tracked state flags. The BO
1965 * is added to the object list of the last execbuf call in a QueueSubmit
1966 * and is marked EXEC_WRITE. The state flags track when the BO has been
1967 * submitted to the kernel. We need to do this because Vulkan lets you
1968 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1969 * will say it's idle in this case.
1970 */
1971 struct {
1972 struct anv_bo bo;
1973 enum anv_bo_fence_state state;
1974 } bo;
1975
1976 /** DRM syncobj handle for syncobj-based fences */
1977 uint32_t syncobj;
1978 };
1979 };
1980
1981 struct anv_fence {
1982 /* Permanent fence state. Every fence has some form of permanent state
1983 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1984 * cross-process fences) or it could just be a dummy for use internally.
1985 */
1986 struct anv_fence_impl permanent;
1987
1988 /* Temporary fence state. A fence *may* have temporary state. That state
1989 * is added to the fence by an import operation and is reset back to
1990 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1991 * state cannot be signaled because the fence must already be signaled
1992 * before the temporary state can be exported from the fence in the other
1993 * process and imported here.
1994 */
1995 struct anv_fence_impl temporary;
1996 };
1997
1998 struct anv_event {
1999 uint64_t semaphore;
2000 struct anv_state state;
2001 };
2002
2003 enum anv_semaphore_type {
2004 ANV_SEMAPHORE_TYPE_NONE = 0,
2005 ANV_SEMAPHORE_TYPE_DUMMY,
2006 ANV_SEMAPHORE_TYPE_BO,
2007 ANV_SEMAPHORE_TYPE_SYNC_FILE,
2008 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
2009 };
2010
2011 struct anv_semaphore_impl {
2012 enum anv_semaphore_type type;
2013
2014 union {
2015 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2016 * This BO will be added to the object list on any execbuf2 calls for
2017 * which this semaphore is used as a wait or signal fence. When used as
2018 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2019 */
2020 struct anv_bo *bo;
2021
2022 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2023 * If the semaphore is in the unsignaled state due to either just being
2024 * created or because it has been used for a wait, fd will be -1.
2025 */
2026 int fd;
2027
2028 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2029 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2030 * import so we don't need to bother with a userspace cache.
2031 */
2032 uint32_t syncobj;
2033 };
2034 };
2035
2036 struct anv_semaphore {
2037 /* Permanent semaphore state. Every semaphore has some form of permanent
2038 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2039 * (for cross-process semaphores0 or it could just be a dummy for use
2040 * internally.
2041 */
2042 struct anv_semaphore_impl permanent;
2043
2044 /* Temporary semaphore state. A semaphore *may* have temporary state.
2045 * That state is added to the semaphore by an import operation and is reset
2046 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2047 * semaphore with temporary state cannot be signaled because the semaphore
2048 * must already be signaled before the temporary state can be exported from
2049 * the semaphore in the other process and imported here.
2050 */
2051 struct anv_semaphore_impl temporary;
2052 };
2053
2054 void anv_semaphore_reset_temporary(struct anv_device *device,
2055 struct anv_semaphore *semaphore);
2056
2057 struct anv_shader_module {
2058 unsigned char sha1[20];
2059 uint32_t size;
2060 char data[0];
2061 };
2062
2063 static inline gl_shader_stage
2064 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2065 {
2066 assert(__builtin_popcount(vk_stage) == 1);
2067 return ffs(vk_stage) - 1;
2068 }
2069
2070 static inline VkShaderStageFlagBits
2071 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2072 {
2073 return (1 << mesa_stage);
2074 }
2075
2076 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2077
2078 #define anv_foreach_stage(stage, stage_bits) \
2079 for (gl_shader_stage stage, \
2080 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2081 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2082 __tmp &= ~(1 << (stage)))
2083
2084 struct anv_pipeline_bind_map {
2085 uint32_t surface_count;
2086 uint32_t sampler_count;
2087 uint32_t image_count;
2088
2089 struct anv_pipeline_binding * surface_to_descriptor;
2090 struct anv_pipeline_binding * sampler_to_descriptor;
2091 };
2092
2093 struct anv_shader_bin_key {
2094 uint32_t size;
2095 uint8_t data[0];
2096 };
2097
2098 struct anv_shader_bin {
2099 uint32_t ref_cnt;
2100
2101 const struct anv_shader_bin_key *key;
2102
2103 struct anv_state kernel;
2104 uint32_t kernel_size;
2105
2106 const struct brw_stage_prog_data *prog_data;
2107 uint32_t prog_data_size;
2108
2109 struct anv_pipeline_bind_map bind_map;
2110 };
2111
2112 struct anv_shader_bin *
2113 anv_shader_bin_create(struct anv_device *device,
2114 const void *key, uint32_t key_size,
2115 const void *kernel, uint32_t kernel_size,
2116 const struct brw_stage_prog_data *prog_data,
2117 uint32_t prog_data_size, const void *prog_data_param,
2118 const struct anv_pipeline_bind_map *bind_map);
2119
2120 void
2121 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2122
2123 static inline void
2124 anv_shader_bin_ref(struct anv_shader_bin *shader)
2125 {
2126 assert(shader && shader->ref_cnt >= 1);
2127 p_atomic_inc(&shader->ref_cnt);
2128 }
2129
2130 static inline void
2131 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2132 {
2133 assert(shader && shader->ref_cnt >= 1);
2134 if (p_atomic_dec_zero(&shader->ref_cnt))
2135 anv_shader_bin_destroy(device, shader);
2136 }
2137
2138 struct anv_pipeline {
2139 struct anv_device * device;
2140 struct anv_batch batch;
2141 uint32_t batch_data[512];
2142 struct anv_reloc_list batch_relocs;
2143 uint32_t dynamic_state_mask;
2144 struct anv_dynamic_state dynamic_state;
2145
2146 struct anv_subpass * subpass;
2147
2148 bool needs_data_cache;
2149
2150 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2151
2152 struct {
2153 const struct gen_l3_config * l3_config;
2154 uint32_t total_size;
2155 } urb;
2156
2157 VkShaderStageFlags active_stages;
2158 struct anv_state blend_state;
2159
2160 uint32_t vb_used;
2161 uint32_t binding_stride[MAX_VBS];
2162 bool instancing_enable[MAX_VBS];
2163 bool primitive_restart;
2164 uint32_t topology;
2165
2166 uint32_t cs_right_mask;
2167
2168 bool writes_depth;
2169 bool depth_test_enable;
2170 bool writes_stencil;
2171 bool stencil_test_enable;
2172 bool depth_clamp_enable;
2173 bool sample_shading_enable;
2174 bool kill_pixel;
2175
2176 struct {
2177 uint32_t sf[7];
2178 uint32_t depth_stencil_state[3];
2179 } gen7;
2180
2181 struct {
2182 uint32_t sf[4];
2183 uint32_t raster[5];
2184 uint32_t wm_depth_stencil[3];
2185 } gen8;
2186
2187 struct {
2188 uint32_t wm_depth_stencil[4];
2189 } gen9;
2190
2191 uint32_t interface_descriptor_data[8];
2192 };
2193
2194 static inline bool
2195 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2196 gl_shader_stage stage)
2197 {
2198 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2199 }
2200
2201 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2202 static inline const struct brw_##prefix##_prog_data * \
2203 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2204 { \
2205 if (anv_pipeline_has_stage(pipeline, stage)) { \
2206 return (const struct brw_##prefix##_prog_data *) \
2207 pipeline->shaders[stage]->prog_data; \
2208 } else { \
2209 return NULL; \
2210 } \
2211 }
2212
2213 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2214 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2215 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2216 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2217 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2218 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2219
2220 static inline const struct brw_vue_prog_data *
2221 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2222 {
2223 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2224 return &get_gs_prog_data(pipeline)->base;
2225 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2226 return &get_tes_prog_data(pipeline)->base;
2227 else
2228 return &get_vs_prog_data(pipeline)->base;
2229 }
2230
2231 VkResult
2232 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2233 struct anv_pipeline_cache *cache,
2234 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2235 const VkAllocationCallbacks *alloc);
2236
2237 VkResult
2238 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2239 struct anv_pipeline_cache *cache,
2240 const VkComputePipelineCreateInfo *info,
2241 struct anv_shader_module *module,
2242 const char *entrypoint,
2243 const VkSpecializationInfo *spec_info);
2244
2245 struct anv_format_plane {
2246 enum isl_format isl_format:16;
2247 struct isl_swizzle swizzle;
2248
2249 /* Whether this plane contains chroma channels */
2250 bool has_chroma;
2251
2252 /* For downscaling of YUV planes */
2253 uint8_t denominator_scales[2];
2254
2255 /* How to map sampled ycbcr planes to a single 4 component element. */
2256 struct isl_swizzle ycbcr_swizzle;
2257 };
2258
2259
2260 struct anv_format {
2261 struct anv_format_plane planes[3];
2262 uint8_t n_planes;
2263 bool can_ycbcr;
2264 };
2265
2266 static inline uint32_t
2267 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2268 VkImageAspectFlags aspect_mask)
2269 {
2270 switch (aspect_mask) {
2271 case VK_IMAGE_ASPECT_COLOR_BIT:
2272 case VK_IMAGE_ASPECT_DEPTH_BIT:
2273 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2274 return 0;
2275 case VK_IMAGE_ASPECT_STENCIL_BIT:
2276 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2277 return 0;
2278 /* Fall-through */
2279 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2280 return 1;
2281 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2282 return 2;
2283 default:
2284 /* Purposefully assert with depth/stencil aspects. */
2285 unreachable("invalid image aspect");
2286 }
2287 }
2288
2289 static inline uint32_t
2290 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2291 {
2292 uint32_t planes = 0;
2293
2294 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2295 VK_IMAGE_ASPECT_DEPTH_BIT |
2296 VK_IMAGE_ASPECT_STENCIL_BIT |
2297 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2298 planes++;
2299 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2300 planes++;
2301 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2302 planes++;
2303
2304 return planes;
2305 }
2306
2307 static inline VkImageAspectFlags
2308 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2309 uint32_t plane)
2310 {
2311 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2312 if (_mesa_bitcount(image_aspects) > 1)
2313 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2314 return VK_IMAGE_ASPECT_COLOR_BIT;
2315 }
2316 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2317 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2318 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2319 return VK_IMAGE_ASPECT_STENCIL_BIT;
2320 }
2321
2322 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2323 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2324
2325 const struct anv_format *
2326 anv_get_format(VkFormat format);
2327
2328 static inline uint32_t
2329 anv_get_format_planes(VkFormat vk_format)
2330 {
2331 const struct anv_format *format = anv_get_format(vk_format);
2332
2333 return format != NULL ? format->n_planes : 0;
2334 }
2335
2336 struct anv_format_plane
2337 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2338 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2339
2340 static inline enum isl_format
2341 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2342 VkImageAspectFlags aspect, VkImageTiling tiling)
2343 {
2344 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2345 }
2346
2347 static inline struct isl_swizzle
2348 anv_swizzle_for_render(struct isl_swizzle swizzle)
2349 {
2350 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2351 * RGB as RGBA for texturing
2352 */
2353 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2354 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2355
2356 /* But it doesn't matter what we render to that channel */
2357 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2358
2359 return swizzle;
2360 }
2361
2362 void
2363 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2364
2365 /**
2366 * Subsurface of an anv_image.
2367 */
2368 struct anv_surface {
2369 /** Valid only if isl_surf::size > 0. */
2370 struct isl_surf isl;
2371
2372 /**
2373 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2374 */
2375 uint32_t offset;
2376 };
2377
2378 struct anv_image {
2379 VkImageType type;
2380 /* The original VkFormat provided by the client. This may not match any
2381 * of the actual surface formats.
2382 */
2383 VkFormat vk_format;
2384 const struct anv_format *format;
2385
2386 VkImageAspectFlags aspects;
2387 VkExtent3D extent;
2388 uint32_t levels;
2389 uint32_t array_size;
2390 uint32_t samples; /**< VkImageCreateInfo::samples */
2391 uint32_t n_planes;
2392 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2393 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2394
2395 /**
2396 * DRM format modifier for this image or DRM_FORMAT_MOD_INVALID.
2397 */
2398 uint64_t drm_format_mod;
2399
2400 VkDeviceSize size;
2401 uint32_t alignment;
2402
2403 /* Whether the image is made of several underlying buffer objects rather a
2404 * single one with different offsets.
2405 */
2406 bool disjoint;
2407
2408 /**
2409 * Image subsurfaces
2410 *
2411 * For each foo, anv_image::planes[x].surface is valid if and only if
2412 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2413 * to figure the number associated with a given aspect.
2414 *
2415 * The hardware requires that the depth buffer and stencil buffer be
2416 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2417 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2418 * allocate the depth and stencil buffers as separate surfaces in the same
2419 * bo.
2420 *
2421 * Memory layout :
2422 *
2423 * -----------------------
2424 * | surface0 | /|\
2425 * ----------------------- |
2426 * | shadow surface0 | |
2427 * ----------------------- | Plane 0
2428 * | aux surface0 | |
2429 * ----------------------- |
2430 * | fast clear colors0 | \|/
2431 * -----------------------
2432 * | surface1 | /|\
2433 * ----------------------- |
2434 * | shadow surface1 | |
2435 * ----------------------- | Plane 1
2436 * | aux surface1 | |
2437 * ----------------------- |
2438 * | fast clear colors1 | \|/
2439 * -----------------------
2440 * | ... |
2441 * | |
2442 * -----------------------
2443 */
2444 struct {
2445 /**
2446 * Offset of the entire plane (whenever the image is disjoint this is
2447 * set to 0).
2448 */
2449 uint32_t offset;
2450
2451 VkDeviceSize size;
2452 uint32_t alignment;
2453
2454 struct anv_surface surface;
2455
2456 /**
2457 * A surface which shadows the main surface and may have different
2458 * tiling. This is used for sampling using a tiling that isn't supported
2459 * for other operations.
2460 */
2461 struct anv_surface shadow_surface;
2462
2463 /**
2464 * For color images, this is the aux usage for this image when not used
2465 * as a color attachment.
2466 *
2467 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2468 * image has a HiZ buffer.
2469 */
2470 enum isl_aux_usage aux_usage;
2471
2472 struct anv_surface aux_surface;
2473
2474 /**
2475 * Offset of the fast clear state (used to compute the
2476 * fast_clear_state_offset of the following planes).
2477 */
2478 uint32_t fast_clear_state_offset;
2479
2480 /**
2481 * BO associated with this plane, set when bound.
2482 */
2483 struct anv_bo *bo;
2484 VkDeviceSize bo_offset;
2485
2486 /**
2487 * When destroying the image, also free the bo.
2488 * */
2489 bool bo_is_owned;
2490 } planes[3];
2491 };
2492
2493 /* The ordering of this enum is important */
2494 enum anv_fast_clear_type {
2495 /** Image does not have/support any fast-clear blocks */
2496 ANV_FAST_CLEAR_NONE = 0,
2497 /** Image has/supports fast-clear but only to the default value */
2498 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
2499 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2500 ANV_FAST_CLEAR_ANY = 2,
2501 };
2502
2503 /* Returns the number of auxiliary buffer levels attached to an image. */
2504 static inline uint8_t
2505 anv_image_aux_levels(const struct anv_image * const image,
2506 VkImageAspectFlagBits aspect)
2507 {
2508 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2509 return image->planes[plane].aux_surface.isl.size > 0 ?
2510 image->planes[plane].aux_surface.isl.levels : 0;
2511 }
2512
2513 /* Returns the number of auxiliary buffer layers attached to an image. */
2514 static inline uint32_t
2515 anv_image_aux_layers(const struct anv_image * const image,
2516 VkImageAspectFlagBits aspect,
2517 const uint8_t miplevel)
2518 {
2519 assert(image);
2520
2521 /* The miplevel must exist in the main buffer. */
2522 assert(miplevel < image->levels);
2523
2524 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2525 /* There are no layers with auxiliary data because the miplevel has no
2526 * auxiliary data.
2527 */
2528 return 0;
2529 } else {
2530 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2531 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2532 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2533 }
2534 }
2535
2536 static inline unsigned
2537 anv_fast_clear_state_entry_size(const struct anv_device *device)
2538 {
2539 assert(device);
2540 /* Entry contents:
2541 * +--------------------------------------------+
2542 * | clear value dword(s) | needs resolve dword |
2543 * +--------------------------------------------+
2544 */
2545
2546 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2547 * GPU memcpy operations.
2548 */
2549 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2550 return device->isl_dev.ss.clear_value_size + 4;
2551 }
2552
2553 static inline struct anv_address
2554 anv_image_get_clear_color_addr(const struct anv_device *device,
2555 const struct anv_image *image,
2556 VkImageAspectFlagBits aspect,
2557 unsigned level)
2558 {
2559 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2560 return (struct anv_address) {
2561 .bo = image->planes[plane].bo,
2562 .offset = image->planes[plane].bo_offset +
2563 image->planes[plane].fast_clear_state_offset +
2564 anv_fast_clear_state_entry_size(device) * level,
2565 };
2566 }
2567
2568 static inline struct anv_address
2569 anv_image_get_needs_resolve_addr(const struct anv_device *device,
2570 const struct anv_image *image,
2571 VkImageAspectFlagBits aspect,
2572 unsigned level)
2573 {
2574 struct anv_address addr =
2575 anv_image_get_clear_color_addr(device, image, aspect, level);
2576 addr.offset += device->isl_dev.ss.clear_value_size;
2577 return addr;
2578 }
2579
2580 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2581 static inline bool
2582 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2583 const struct anv_image *image)
2584 {
2585 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2586 return false;
2587
2588 if (devinfo->gen < 8)
2589 return false;
2590
2591 return image->samples == 1;
2592 }
2593
2594 void
2595 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
2596 const struct anv_image *image,
2597 VkImageAspectFlagBits aspect,
2598 enum isl_aux_usage aux_usage,
2599 uint32_t level,
2600 uint32_t base_layer,
2601 uint32_t layer_count);
2602
2603 void
2604 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
2605 const struct anv_image *image,
2606 VkImageAspectFlagBits aspect, uint32_t level,
2607 uint32_t base_layer, uint32_t layer_count,
2608 enum isl_aux_op hiz_op);
2609 void
2610 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
2611 const struct anv_image *image,
2612 VkImageAspectFlagBits aspect,
2613 uint32_t base_layer, uint32_t layer_count,
2614 enum isl_aux_op mcs_op, bool predicate);
2615 void
2616 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
2617 const struct anv_image *image,
2618 VkImageAspectFlagBits aspect, uint32_t level,
2619 uint32_t base_layer, uint32_t layer_count,
2620 enum isl_aux_op ccs_op, bool predicate);
2621
2622 void
2623 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2624 const struct anv_image *image,
2625 uint32_t base_level, uint32_t level_count,
2626 uint32_t base_layer, uint32_t layer_count);
2627
2628 enum isl_aux_usage
2629 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2630 const struct anv_image *image,
2631 const VkImageAspectFlagBits aspect,
2632 const VkImageLayout layout);
2633
2634 enum anv_fast_clear_type
2635 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
2636 const struct anv_image * const image,
2637 const VkImageAspectFlagBits aspect,
2638 const VkImageLayout layout);
2639
2640 /* This is defined as a macro so that it works for both
2641 * VkImageSubresourceRange and VkImageSubresourceLayers
2642 */
2643 #define anv_get_layerCount(_image, _range) \
2644 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2645 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2646
2647 static inline uint32_t
2648 anv_get_levelCount(const struct anv_image *image,
2649 const VkImageSubresourceRange *range)
2650 {
2651 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2652 image->levels - range->baseMipLevel : range->levelCount;
2653 }
2654
2655 static inline VkImageAspectFlags
2656 anv_image_expand_aspects(const struct anv_image *image,
2657 VkImageAspectFlags aspects)
2658 {
2659 /* If the underlying image has color plane aspects and
2660 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2661 * the underlying image. */
2662 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2663 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2664 return image->aspects;
2665
2666 return aspects;
2667 }
2668
2669 static inline bool
2670 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2671 VkImageAspectFlags aspects2)
2672 {
2673 if (aspects1 == aspects2)
2674 return true;
2675
2676 /* Only 1 color aspects are compatibles. */
2677 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2678 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2679 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2680 return true;
2681
2682 return false;
2683 }
2684
2685 struct anv_image_view {
2686 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2687
2688 VkImageAspectFlags aspect_mask;
2689 VkFormat vk_format;
2690 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2691
2692 unsigned n_planes;
2693 struct {
2694 uint32_t image_plane;
2695
2696 struct isl_view isl;
2697
2698 /**
2699 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2700 * image layout of SHADER_READ_ONLY_OPTIMAL or
2701 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2702 */
2703 struct anv_surface_state optimal_sampler_surface_state;
2704
2705 /**
2706 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2707 * image layout of GENERAL.
2708 */
2709 struct anv_surface_state general_sampler_surface_state;
2710
2711 /**
2712 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2713 * states for write-only and readable, using the real format for
2714 * write-only and the lowered format for readable.
2715 */
2716 struct anv_surface_state storage_surface_state;
2717 struct anv_surface_state writeonly_storage_surface_state;
2718
2719 struct brw_image_param storage_image_param;
2720 } planes[3];
2721 };
2722
2723 enum anv_image_view_state_flags {
2724 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2725 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2726 };
2727
2728 void anv_image_fill_surface_state(struct anv_device *device,
2729 const struct anv_image *image,
2730 VkImageAspectFlagBits aspect,
2731 const struct isl_view *view,
2732 isl_surf_usage_flags_t view_usage,
2733 enum isl_aux_usage aux_usage,
2734 const union isl_color_value *clear_color,
2735 enum anv_image_view_state_flags flags,
2736 struct anv_surface_state *state_inout,
2737 struct brw_image_param *image_param_out);
2738
2739 struct anv_image_create_info {
2740 const VkImageCreateInfo *vk_info;
2741
2742 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2743 isl_tiling_flags_t isl_tiling_flags;
2744
2745 /** These flags will be added to any derived from VkImageCreateInfo. */
2746 isl_surf_usage_flags_t isl_extra_usage_flags;
2747
2748 uint32_t stride;
2749 };
2750
2751 VkResult anv_image_create(VkDevice _device,
2752 const struct anv_image_create_info *info,
2753 const VkAllocationCallbacks* alloc,
2754 VkImage *pImage);
2755
2756 #ifdef ANDROID
2757 VkResult anv_image_from_gralloc(VkDevice device_h,
2758 const VkImageCreateInfo *base_info,
2759 const VkNativeBufferANDROID *gralloc_info,
2760 const VkAllocationCallbacks *alloc,
2761 VkImage *pImage);
2762 #endif
2763
2764 const struct anv_surface *
2765 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2766 VkImageAspectFlags aspect_mask);
2767
2768 enum isl_format
2769 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2770
2771 static inline struct VkExtent3D
2772 anv_sanitize_image_extent(const VkImageType imageType,
2773 const struct VkExtent3D imageExtent)
2774 {
2775 switch (imageType) {
2776 case VK_IMAGE_TYPE_1D:
2777 return (VkExtent3D) { imageExtent.width, 1, 1 };
2778 case VK_IMAGE_TYPE_2D:
2779 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2780 case VK_IMAGE_TYPE_3D:
2781 return imageExtent;
2782 default:
2783 unreachable("invalid image type");
2784 }
2785 }
2786
2787 static inline struct VkOffset3D
2788 anv_sanitize_image_offset(const VkImageType imageType,
2789 const struct VkOffset3D imageOffset)
2790 {
2791 switch (imageType) {
2792 case VK_IMAGE_TYPE_1D:
2793 return (VkOffset3D) { imageOffset.x, 0, 0 };
2794 case VK_IMAGE_TYPE_2D:
2795 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2796 case VK_IMAGE_TYPE_3D:
2797 return imageOffset;
2798 default:
2799 unreachable("invalid image type");
2800 }
2801 }
2802
2803
2804 void anv_fill_buffer_surface_state(struct anv_device *device,
2805 struct anv_state state,
2806 enum isl_format format,
2807 uint32_t offset, uint32_t range,
2808 uint32_t stride);
2809
2810
2811 struct anv_ycbcr_conversion {
2812 const struct anv_format * format;
2813 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2814 VkSamplerYcbcrRangeKHR ycbcr_range;
2815 VkComponentSwizzle mapping[4];
2816 VkChromaLocationKHR chroma_offsets[2];
2817 VkFilter chroma_filter;
2818 bool chroma_reconstruction;
2819 };
2820
2821 struct anv_sampler {
2822 uint32_t state[3][4];
2823 uint32_t n_planes;
2824 struct anv_ycbcr_conversion *conversion;
2825 };
2826
2827 struct anv_framebuffer {
2828 uint32_t width;
2829 uint32_t height;
2830 uint32_t layers;
2831
2832 uint32_t attachment_count;
2833 struct anv_image_view * attachments[0];
2834 };
2835
2836 struct anv_subpass {
2837 uint32_t attachment_count;
2838
2839 /**
2840 * A pointer to all attachment references used in this subpass.
2841 * Only valid if ::attachment_count > 0.
2842 */
2843 VkAttachmentReference * attachments;
2844 uint32_t input_count;
2845 VkAttachmentReference * input_attachments;
2846 uint32_t color_count;
2847 VkAttachmentReference * color_attachments;
2848 VkAttachmentReference * resolve_attachments;
2849
2850 VkAttachmentReference depth_stencil_attachment;
2851
2852 uint32_t view_mask;
2853
2854 /** Subpass has a depth/stencil self-dependency */
2855 bool has_ds_self_dep;
2856
2857 /** Subpass has at least one resolve attachment */
2858 bool has_resolve;
2859 };
2860
2861 static inline unsigned
2862 anv_subpass_view_count(const struct anv_subpass *subpass)
2863 {
2864 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2865 }
2866
2867 struct anv_render_pass_attachment {
2868 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2869 * its members individually.
2870 */
2871 VkFormat format;
2872 uint32_t samples;
2873 VkImageUsageFlags usage;
2874 VkAttachmentLoadOp load_op;
2875 VkAttachmentStoreOp store_op;
2876 VkAttachmentLoadOp stencil_load_op;
2877 VkImageLayout initial_layout;
2878 VkImageLayout final_layout;
2879 VkImageLayout first_subpass_layout;
2880
2881 /* The subpass id in which the attachment will be used last. */
2882 uint32_t last_subpass_idx;
2883 };
2884
2885 struct anv_render_pass {
2886 uint32_t attachment_count;
2887 uint32_t subpass_count;
2888 /* An array of subpass_count+1 flushes, one per subpass boundary */
2889 enum anv_pipe_bits * subpass_flushes;
2890 struct anv_render_pass_attachment * attachments;
2891 struct anv_subpass subpasses[0];
2892 };
2893
2894 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2895
2896 struct anv_query_pool {
2897 VkQueryType type;
2898 VkQueryPipelineStatisticFlags pipeline_statistics;
2899 /** Stride between slots, in bytes */
2900 uint32_t stride;
2901 /** Number of slots in this query pool */
2902 uint32_t slots;
2903 struct anv_bo bo;
2904 };
2905
2906 int anv_get_entrypoint_index(const char *name);
2907
2908 bool
2909 anv_entrypoint_is_enabled(int index, uint32_t core_version,
2910 const struct anv_instance_extension_table *instance,
2911 const struct anv_device_extension_table *device);
2912
2913 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2914 const char *name);
2915
2916 void anv_dump_image_to_ppm(struct anv_device *device,
2917 struct anv_image *image, unsigned miplevel,
2918 unsigned array_layer, VkImageAspectFlagBits aspect,
2919 const char *filename);
2920
2921 enum anv_dump_action {
2922 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2923 };
2924
2925 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2926 void anv_dump_finish(void);
2927
2928 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2929 struct anv_framebuffer *fb);
2930
2931 static inline uint32_t
2932 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2933 {
2934 /* This function must be called from within a subpass. */
2935 assert(cmd_state->pass && cmd_state->subpass);
2936
2937 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2938
2939 /* The id of this subpass shouldn't exceed the number of subpasses in this
2940 * render pass minus 1.
2941 */
2942 assert(subpass_id < cmd_state->pass->subpass_count);
2943 return subpass_id;
2944 }
2945
2946 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2947 \
2948 static inline struct __anv_type * \
2949 __anv_type ## _from_handle(__VkType _handle) \
2950 { \
2951 return (struct __anv_type *) _handle; \
2952 } \
2953 \
2954 static inline __VkType \
2955 __anv_type ## _to_handle(struct __anv_type *_obj) \
2956 { \
2957 return (__VkType) _obj; \
2958 }
2959
2960 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2961 \
2962 static inline struct __anv_type * \
2963 __anv_type ## _from_handle(__VkType _handle) \
2964 { \
2965 return (struct __anv_type *)(uintptr_t) _handle; \
2966 } \
2967 \
2968 static inline __VkType \
2969 __anv_type ## _to_handle(struct __anv_type *_obj) \
2970 { \
2971 return (__VkType)(uintptr_t) _obj; \
2972 }
2973
2974 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2975 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2976
2977 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2978 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2979 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2980 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2981 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2982
2983 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2984 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2985 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2986 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2987 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2988 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2989 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2990 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2991 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2992 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2993 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2994 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2995 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2996 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2997 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2998 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2999 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
3000 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
3001 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
3002 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
3003 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
3004 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
3005 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
3006
3007 /* Gen-specific function declarations */
3008 #ifdef genX
3009 # include "anv_genX.h"
3010 #else
3011 # define genX(x) gen7_##x
3012 # include "anv_genX.h"
3013 # undef genX
3014 # define genX(x) gen75_##x
3015 # include "anv_genX.h"
3016 # undef genX
3017 # define genX(x) gen8_##x
3018 # include "anv_genX.h"
3019 # undef genX
3020 # define genX(x) gen9_##x
3021 # include "anv_genX.h"
3022 # undef genX
3023 # define genX(x) gen10_##x
3024 # include "anv_genX.h"
3025 # undef genX
3026 #endif
3027
3028 #endif /* ANV_PRIVATE_H */