2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
61 #include "vk_debug_report.h"
63 /* Pre-declarations needed for WSI entrypoints */
66 typedef struct xcb_connection_t xcb_connection_t
;
67 typedef uint32_t xcb_visualid_t
;
68 typedef uint32_t xcb_window_t
;
71 struct anv_buffer_view
;
72 struct anv_image_view
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
81 #include "anv_android.h"
82 #include "anv_entrypoints.h"
83 #include "anv_extensions.h"
86 #include "common/gen_debug.h"
87 #include "common/intel_log.h"
88 #include "wsi_common.h"
90 /* anv Virtual Memory Layout
91 * =========================
93 * When the anv driver is determining the virtual graphics addresses of memory
94 * objects itself using the softpin mechanism, the following memory ranges
97 * Three special considerations to notice:
99 * (1) the dynamic state pool is located within the same 4 GiB as the low
100 * heap. This is to work around a VF cache issue described in a comment in
101 * anv_physical_device_init_heaps.
103 * (2) the binding table pool is located at lower addresses than the surface
104 * state pool, within a 4 GiB range. This allows surface state base addresses
105 * to cover both binding tables (16 bit offsets) and surface states (32 bit
108 * (3) the last 4 GiB of the address space is withheld from the high
109 * heap. Various hardware units will read past the end of an object for
110 * various reasons. This healthy margin prevents reads from wrapping around
113 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
114 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
115 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
116 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
117 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
118 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
119 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
120 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
121 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
122 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
123 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
124 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
126 #define LOW_HEAP_SIZE \
127 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
128 #define HIGH_HEAP_SIZE \
129 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
130 #define DYNAMIC_STATE_POOL_SIZE \
131 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
132 #define BINDING_TABLE_POOL_SIZE \
133 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
134 #define SURFACE_STATE_POOL_SIZE \
135 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
136 #define INSTRUCTION_STATE_POOL_SIZE \
137 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
139 /* Allowing different clear colors requires us to perform a depth resolve at
140 * the end of certain render passes. This is because while slow clears store
141 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
142 * See the PRMs for examples describing when additional resolves would be
143 * necessary. To enable fast clears without requiring extra resolves, we set
144 * the clear value to a globally-defined one. We could allow different values
145 * if the user doesn't expect coherent data during or after a render passes
146 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
147 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
148 * 1.0f seems to be the only value used. The only application that doesn't set
149 * this value does so through the usage of an seemingly uninitialized clear
152 #define ANV_HZ_FC_VAL 1.0f
155 #define MAX_XFB_BUFFERS 4
156 #define MAX_XFB_STREAMS 4
159 #define MAX_VIEWPORTS 16
160 #define MAX_SCISSORS 16
161 #define MAX_PUSH_CONSTANTS_SIZE 128
162 #define MAX_DYNAMIC_BUFFERS 16
163 #define MAX_IMAGES 64
164 #define MAX_GEN8_IMAGES 8
165 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
167 /* The kernel relocation API has a limitation of a 32-bit delta value
168 * applied to the address before it is written which, in spite of it being
169 * unsigned, is treated as signed . Because of the way that this maps to
170 * the Vulkan API, we cannot handle an offset into a buffer that does not
171 * fit into a signed 32 bits. The only mechanism we have for dealing with
172 * this at the moment is to limit all VkDeviceMemory objects to a maximum
173 * of 2GB each. The Vulkan spec allows us to do this:
175 * "Some platforms may have a limit on the maximum size of a single
176 * allocation. For example, certain systems may fail to create
177 * allocations with a size greater than or equal to 4GB. Such a limit is
178 * implementation-dependent, and if such a failure occurs then the error
179 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
181 * We don't use vk_error here because it's not an error so much as an
182 * indication to the application that the allocation is too large.
184 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
186 #define ANV_SVGS_VB_INDEX MAX_VBS
187 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
189 /* We reserve this MI ALU register for the purpose of handling predication.
190 * Other code which uses the MI ALU should leave it alone.
192 #define ANV_PREDICATE_RESULT_REG MI_ALU_REG15
194 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
196 static inline uint32_t
197 align_down_npot_u32(uint32_t v
, uint32_t a
)
202 static inline uint32_t
203 align_u32(uint32_t v
, uint32_t a
)
205 assert(a
!= 0 && a
== (a
& -a
));
206 return (v
+ a
- 1) & ~(a
- 1);
209 static inline uint64_t
210 align_u64(uint64_t v
, uint64_t a
)
212 assert(a
!= 0 && a
== (a
& -a
));
213 return (v
+ a
- 1) & ~(a
- 1);
216 static inline int32_t
217 align_i32(int32_t v
, int32_t a
)
219 assert(a
!= 0 && a
== (a
& -a
));
220 return (v
+ a
- 1) & ~(a
- 1);
223 /** Alignment must be a power of 2. */
225 anv_is_aligned(uintmax_t n
, uintmax_t a
)
227 assert(a
== (a
& -a
));
228 return (n
& (a
- 1)) == 0;
231 static inline uint32_t
232 anv_minify(uint32_t n
, uint32_t levels
)
234 if (unlikely(n
== 0))
237 return MAX2(n
>> levels
, 1);
241 anv_clamp_f(float f
, float min
, float max
)
254 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
256 if (*inout_mask
& clear_mask
) {
257 *inout_mask
&= ~clear_mask
;
264 static inline union isl_color_value
265 vk_to_isl_color(VkClearColorValue color
)
267 return (union isl_color_value
) {
277 #define for_each_bit(b, dword) \
278 for (uint32_t __dword = (dword); \
279 (b) = __builtin_ffs(__dword) - 1, __dword; \
280 __dword &= ~(1 << (b)))
282 #define typed_memcpy(dest, src, count) ({ \
283 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
284 memcpy((dest), (src), (count) * sizeof(*(src))); \
287 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
288 * to be added here in order to utilize mapping in debug/error/perf macros.
290 #define REPORT_OBJECT_TYPE(o) \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
300 __builtin_choose_expr ( \
301 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
302 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
303 __builtin_choose_expr ( \
304 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
305 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
306 __builtin_choose_expr ( \
307 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
308 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
309 __builtin_choose_expr ( \
310 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
311 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
312 __builtin_choose_expr ( \
313 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
314 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
315 __builtin_choose_expr ( \
316 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
317 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
318 __builtin_choose_expr ( \
319 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
320 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
321 __builtin_choose_expr ( \
322 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
323 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
324 __builtin_choose_expr ( \
325 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
326 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
327 __builtin_choose_expr ( \
328 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
329 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
330 __builtin_choose_expr ( \
331 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
332 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
333 __builtin_choose_expr ( \
334 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
335 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
336 __builtin_choose_expr ( \
337 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
338 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
339 __builtin_choose_expr ( \
340 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
341 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
342 __builtin_choose_expr ( \
343 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
344 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
345 __builtin_choose_expr ( \
346 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
347 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
348 __builtin_choose_expr ( \
349 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
350 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
351 __builtin_choose_expr ( \
352 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
353 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
354 __builtin_choose_expr ( \
355 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
356 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
372 __builtin_choose_expr ( \
373 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
374 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
375 __builtin_choose_expr ( \
376 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
377 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
378 __builtin_choose_expr ( \
379 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
380 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
381 __builtin_choose_expr ( \
382 __builtin_types_compatible_p (__typeof (o), void*), \
383 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
384 /* The void expression results in a compile-time error \
385 when assigning the result to something. */ \
386 (void)0)))))))))))))))))))))))))))))))
388 /* Whenever we generate an error, pass it through this function. Useful for
389 * debugging, where we can break on it. Only call at error site, not when
390 * propagating errors. Might be useful to plug in a stack trace here.
393 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
394 VkDebugReportObjectTypeEXT type
, VkResult error
,
395 const char *file
, int line
, const char *format
,
398 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
399 VkDebugReportObjectTypeEXT type
, VkResult error
,
400 const char *file
, int line
, const char *format
, ...);
403 #define vk_error(error) __vk_errorf(NULL, NULL,\
404 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
405 error, __FILE__, __LINE__, NULL)
406 #define vk_errorv(instance, obj, error, format, args)\
407 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
408 __FILE__, __LINE__, format, args)
409 #define vk_errorf(instance, obj, error, format, ...)\
410 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
411 __FILE__, __LINE__, format, ## __VA_ARGS__)
413 #define vk_error(error) error
414 #define vk_errorf(instance, obj, error, format, ...) error
418 * Warn on ignored extension structs.
420 * The Vulkan spec requires us to ignore unsupported or unknown structs in
421 * a pNext chain. In debug mode, emitting warnings for ignored structs may
422 * help us discover structs that we should not have ignored.
425 * From the Vulkan 1.0.38 spec:
427 * Any component of the implementation (the loader, any enabled layers,
428 * and drivers) must skip over, without processing (other than reading the
429 * sType and pNext members) any chained structures with sType values not
430 * defined by extensions supported by that component.
432 #define anv_debug_ignored_stype(sType) \
433 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
435 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
436 VkDebugReportObjectTypeEXT type
, const char *file
,
437 int line
, const char *format
, ...)
438 anv_printflike(6, 7);
439 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
440 void anv_loge_v(const char *format
, va_list va
);
443 * Print a FINISHME message, including its source location.
445 #define anv_finishme(format, ...) \
447 static bool reported = false; \
449 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
456 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
458 #define anv_perf_warn(instance, obj, format, ...) \
460 static bool reported = false; \
461 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
462 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
463 format, ##__VA_ARGS__); \
468 /* A non-fatal assert. Useful for debugging. */
470 #define anv_assert(x) ({ \
471 if (unlikely(!(x))) \
472 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
475 #define anv_assert(x)
478 /* A multi-pointer allocator
480 * When copying data structures from the user (such as a render pass), it's
481 * common to need to allocate data for a bunch of different things. Instead
482 * of doing several allocations and having to handle all of the error checking
483 * that entails, it can be easier to do a single allocation. This struct
484 * helps facilitate that. The intended usage looks like this:
487 * anv_multialloc_add(&ma, &main_ptr, 1);
488 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
489 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
491 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
492 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
494 struct anv_multialloc
{
502 #define ANV_MULTIALLOC_INIT \
503 ((struct anv_multialloc) { 0, })
505 #define ANV_MULTIALLOC(_name) \
506 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
508 __attribute__((always_inline
))
510 _anv_multialloc_add(struct anv_multialloc
*ma
,
511 void **ptr
, size_t size
, size_t align
)
513 size_t offset
= align_u64(ma
->size
, align
);
514 ma
->size
= offset
+ size
;
515 ma
->align
= MAX2(ma
->align
, align
);
517 /* Store the offset in the pointer. */
518 *ptr
= (void *)(uintptr_t)offset
;
520 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
521 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
524 #define anv_multialloc_add_size(_ma, _ptr, _size) \
525 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
527 #define anv_multialloc_add(_ma, _ptr, _count) \
528 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
530 __attribute__((always_inline
))
532 anv_multialloc_alloc(struct anv_multialloc
*ma
,
533 const VkAllocationCallbacks
*alloc
,
534 VkSystemAllocationScope scope
)
536 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
540 /* Fill out each of the pointers with their final value.
542 * for (uint32_t i = 0; i < ma->ptr_count; i++)
543 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
545 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
546 * constant, GCC is incapable of figuring this out and unrolling the loop
547 * so we have to give it a little help.
549 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
550 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
551 if ((_i) < ma->ptr_count) \
552 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
553 _ANV_MULTIALLOC_UPDATE_POINTER(0);
554 _ANV_MULTIALLOC_UPDATE_POINTER(1);
555 _ANV_MULTIALLOC_UPDATE_POINTER(2);
556 _ANV_MULTIALLOC_UPDATE_POINTER(3);
557 _ANV_MULTIALLOC_UPDATE_POINTER(4);
558 _ANV_MULTIALLOC_UPDATE_POINTER(5);
559 _ANV_MULTIALLOC_UPDATE_POINTER(6);
560 _ANV_MULTIALLOC_UPDATE_POINTER(7);
561 #undef _ANV_MULTIALLOC_UPDATE_POINTER
566 __attribute__((always_inline
))
568 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
569 const VkAllocationCallbacks
*parent_alloc
,
570 const VkAllocationCallbacks
*alloc
,
571 VkSystemAllocationScope scope
)
573 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
576 /* Extra ANV-defined BO flags which won't be passed to the kernel */
577 #define ANV_BO_EXTERNAL (1ull << 31)
578 #define ANV_BO_FLAG_MASK (1ull << 31)
583 /* Index into the current validation list. This is used by the
584 * validation list building alrogithm to track which buffers are already
585 * in the validation list so that we can ensure uniqueness.
589 /* Last known offset. This value is provided by the kernel when we
590 * execbuf and is used as the presumed offset for the next bunch of
598 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
603 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
605 bo
->gem_handle
= gem_handle
;
613 /* Represents a lock-free linked list of "free" things. This is used by
614 * both the block pool and the state pools. Unfortunately, in order to
615 * solve the ABA problem, we can't use a single uint32_t head.
617 union anv_free_list
{
621 /* A simple count that is incremented every time the head changes. */
627 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
629 struct anv_block_state
{
639 #define anv_block_pool_foreach_bo(bo, pool) \
640 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
642 #define ANV_MAX_BLOCK_POOL_BOS 20
644 struct anv_block_pool
{
645 struct anv_device
*device
;
649 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
655 /* The address where the start of the pool is pinned. The various bos that
656 * are created as the pool grows will have addresses in the range
657 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
659 uint64_t start_address
;
661 /* The offset from the start of the bo to the "center" of the block
662 * pool. Pointers to allocated blocks are given by
663 * bo.map + center_bo_offset + offsets.
665 uint32_t center_bo_offset
;
667 /* Current memory map of the block pool. This pointer may or may not
668 * point to the actual beginning of the block pool memory. If
669 * anv_block_pool_alloc_back has ever been called, then this pointer
670 * will point to the "center" position of the buffer and all offsets
671 * (negative or positive) given out by the block pool alloc functions
672 * will be valid relative to this pointer.
674 * In particular, map == bo.map + center_offset
676 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
677 * since it will handle the softpin case as well, where this points to NULL.
683 * Array of mmaps and gem handles owned by the block pool, reclaimed when
684 * the block pool is destroyed.
686 struct u_vector mmap_cleanups
;
688 struct anv_block_state state
;
690 struct anv_block_state back_state
;
693 /* Block pools are backed by a fixed-size 1GB memfd */
694 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
696 /* The center of the block pool is also the middle of the memfd. This may
697 * change in the future if we decide differently for some reason.
699 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
701 static inline uint32_t
702 anv_block_pool_size(struct anv_block_pool
*pool
)
704 return pool
->state
.end
+ pool
->back_state
.end
;
714 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
716 struct anv_fixed_size_state_pool
{
717 union anv_free_list free_list
;
718 struct anv_block_state block
;
721 #define ANV_MIN_STATE_SIZE_LOG2 6
722 #define ANV_MAX_STATE_SIZE_LOG2 20
724 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
726 struct anv_free_entry
{
728 struct anv_state state
;
731 struct anv_state_table
{
732 struct anv_device
*device
;
734 struct anv_free_entry
*map
;
736 struct anv_block_state state
;
737 struct u_vector mmap_cleanups
;
740 struct anv_state_pool
{
741 struct anv_block_pool block_pool
;
743 struct anv_state_table table
;
745 /* The size of blocks which will be allocated from the block pool */
748 /** Free list for "back" allocations */
749 union anv_free_list back_alloc_free_list
;
751 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
754 struct anv_state_stream_block
;
756 struct anv_state_stream
{
757 struct anv_state_pool
*state_pool
;
759 /* The size of blocks to allocate from the state pool */
762 /* Current block we're allocating from */
763 struct anv_state block
;
765 /* Offset into the current block at which to allocate the next state */
768 /* List of all blocks allocated from this pool */
769 struct anv_state_stream_block
*block_list
;
772 /* The block_pool functions exported for testing only. The block pool should
773 * only be used via a state pool (see below).
775 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
776 struct anv_device
*device
,
777 uint64_t start_address
,
778 uint32_t initial_size
,
780 void anv_block_pool_finish(struct anv_block_pool
*pool
);
781 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
782 uint32_t block_size
, uint32_t *padding
);
783 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
784 uint32_t block_size
);
785 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
787 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
788 struct anv_device
*device
,
789 uint64_t start_address
,
792 void anv_state_pool_finish(struct anv_state_pool
*pool
);
793 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
794 uint32_t state_size
, uint32_t alignment
);
795 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
796 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
797 void anv_state_stream_init(struct anv_state_stream
*stream
,
798 struct anv_state_pool
*state_pool
,
799 uint32_t block_size
);
800 void anv_state_stream_finish(struct anv_state_stream
*stream
);
801 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
802 uint32_t size
, uint32_t alignment
);
804 VkResult
anv_state_table_init(struct anv_state_table
*table
,
805 struct anv_device
*device
,
806 uint32_t initial_entries
);
807 void anv_state_table_finish(struct anv_state_table
*table
);
808 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
810 void anv_free_list_push(union anv_free_list
*list
,
811 struct anv_state_table
*table
,
812 uint32_t idx
, uint32_t count
);
813 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
814 struct anv_state_table
*table
);
817 static inline struct anv_state
*
818 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
820 return &table
->map
[idx
].state
;
823 * Implements a pool of re-usable BOs. The interface is identical to that
824 * of block_pool except that each block is its own BO.
827 struct anv_device
*device
;
834 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
836 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
837 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
839 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
841 struct anv_scratch_bo
{
846 struct anv_scratch_pool
{
847 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
848 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
851 void anv_scratch_pool_init(struct anv_device
*device
,
852 struct anv_scratch_pool
*pool
);
853 void anv_scratch_pool_finish(struct anv_device
*device
,
854 struct anv_scratch_pool
*pool
);
855 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
856 struct anv_scratch_pool
*pool
,
857 gl_shader_stage stage
,
858 unsigned per_thread_scratch
);
860 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
861 struct anv_bo_cache
{
862 struct hash_table
*bo_map
;
863 pthread_mutex_t mutex
;
866 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
867 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
868 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
869 struct anv_bo_cache
*cache
,
870 uint64_t size
, uint64_t bo_flags
,
872 VkResult
anv_bo_cache_import(struct anv_device
*device
,
873 struct anv_bo_cache
*cache
,
874 int fd
, uint64_t bo_flags
,
876 VkResult
anv_bo_cache_export(struct anv_device
*device
,
877 struct anv_bo_cache
*cache
,
878 struct anv_bo
*bo_in
, int *fd_out
);
879 void anv_bo_cache_release(struct anv_device
*device
,
880 struct anv_bo_cache
*cache
,
883 struct anv_memory_type
{
884 /* Standard bits passed on to the client */
885 VkMemoryPropertyFlags propertyFlags
;
888 /* Driver-internal book-keeping */
889 VkBufferUsageFlags valid_buffer_usage
;
892 struct anv_memory_heap
{
893 /* Standard bits passed on to the client */
895 VkMemoryHeapFlags flags
;
897 /* Driver-internal book-keeping */
898 bool supports_48bit_addresses
;
901 struct anv_physical_device
{
902 VK_LOADER_DATA _loader_data
;
904 struct anv_instance
* instance
;
915 struct gen_device_info info
;
916 /** Amount of "GPU memory" we want to advertise
918 * Clearly, this value is bogus since Intel is a UMA architecture. On
919 * gen7 platforms, we are limited by GTT size unless we want to implement
920 * fine-grained tracking and GTT splitting. On Broadwell and above we are
921 * practically unlimited. However, we will never report more than 3/4 of
922 * the total system ram to try and avoid running out of RAM.
924 bool supports_48bit_addresses
;
925 struct brw_compiler
* compiler
;
926 struct isl_device isl_dev
;
927 int cmd_parser_version
;
929 bool has_exec_capture
;
932 bool has_syncobj_wait
;
933 bool has_context_priority
;
935 bool has_context_isolation
;
937 struct anv_device_extension_table supported_extensions
;
940 uint32_t subslice_total
;
944 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
946 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
949 uint8_t driver_build_sha1
[20];
950 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
951 uint8_t driver_uuid
[VK_UUID_SIZE
];
952 uint8_t device_uuid
[VK_UUID_SIZE
];
954 struct disk_cache
* disk_cache
;
956 struct wsi_device wsi_device
;
961 struct anv_app_info
{
962 const char* app_name
;
963 uint32_t app_version
;
964 const char* engine_name
;
965 uint32_t engine_version
;
966 uint32_t api_version
;
969 struct anv_instance
{
970 VK_LOADER_DATA _loader_data
;
972 VkAllocationCallbacks alloc
;
974 struct anv_app_info app_info
;
976 struct anv_instance_extension_table enabled_extensions
;
977 struct anv_instance_dispatch_table dispatch
;
978 struct anv_device_dispatch_table device_dispatch
;
980 int physicalDeviceCount
;
981 struct anv_physical_device physicalDevice
;
983 bool pipeline_cache_enabled
;
985 struct vk_debug_report_instance debug_report_callbacks
;
988 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
989 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
991 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
992 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
996 VK_LOADER_DATA _loader_data
;
998 struct anv_device
* device
;
1000 VkDeviceQueueCreateFlags flags
;
1003 struct anv_pipeline_cache
{
1004 struct anv_device
* device
;
1005 pthread_mutex_t mutex
;
1007 struct hash_table
* nir_cache
;
1009 struct hash_table
* cache
;
1012 struct nir_xfb_info
;
1013 struct anv_pipeline_bind_map
;
1015 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1016 struct anv_device
*device
,
1017 bool cache_enabled
);
1018 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1020 struct anv_shader_bin
*
1021 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1022 const void *key
, uint32_t key_size
);
1023 struct anv_shader_bin
*
1024 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1025 const void *key_data
, uint32_t key_size
,
1026 const void *kernel_data
, uint32_t kernel_size
,
1027 const void *constant_data
,
1028 uint32_t constant_data_size
,
1029 const struct brw_stage_prog_data
*prog_data
,
1030 uint32_t prog_data_size
,
1031 const struct nir_xfb_info
*xfb_info
,
1032 const struct anv_pipeline_bind_map
*bind_map
);
1034 struct anv_shader_bin
*
1035 anv_device_search_for_kernel(struct anv_device
*device
,
1036 struct anv_pipeline_cache
*cache
,
1037 const void *key_data
, uint32_t key_size
);
1039 struct anv_shader_bin
*
1040 anv_device_upload_kernel(struct anv_device
*device
,
1041 struct anv_pipeline_cache
*cache
,
1042 const void *key_data
, uint32_t key_size
,
1043 const void *kernel_data
, uint32_t kernel_size
,
1044 const void *constant_data
,
1045 uint32_t constant_data_size
,
1046 const struct brw_stage_prog_data
*prog_data
,
1047 uint32_t prog_data_size
,
1048 const struct nir_xfb_info
*xfb_info
,
1049 const struct anv_pipeline_bind_map
*bind_map
);
1052 struct nir_shader_compiler_options
;
1055 anv_device_search_for_nir(struct anv_device
*device
,
1056 struct anv_pipeline_cache
*cache
,
1057 const struct nir_shader_compiler_options
*nir_options
,
1058 unsigned char sha1_key
[20],
1062 anv_device_upload_nir(struct anv_device
*device
,
1063 struct anv_pipeline_cache
*cache
,
1064 const struct nir_shader
*nir
,
1065 unsigned char sha1_key
[20]);
1068 VK_LOADER_DATA _loader_data
;
1070 VkAllocationCallbacks alloc
;
1072 struct anv_instance
* instance
;
1073 uint32_t chipset_id
;
1075 struct gen_device_info info
;
1076 struct isl_device isl_dev
;
1079 bool can_chain_batches
;
1080 bool robust_buffer_access
;
1081 struct anv_device_extension_table enabled_extensions
;
1082 struct anv_device_dispatch_table dispatch
;
1084 pthread_mutex_t vma_mutex
;
1085 struct util_vma_heap vma_lo
;
1086 struct util_vma_heap vma_hi
;
1087 uint64_t vma_lo_available
;
1088 uint64_t vma_hi_available
;
1090 struct anv_bo_pool batch_bo_pool
;
1092 struct anv_bo_cache bo_cache
;
1094 struct anv_state_pool dynamic_state_pool
;
1095 struct anv_state_pool instruction_state_pool
;
1096 struct anv_state_pool binding_table_pool
;
1097 struct anv_state_pool surface_state_pool
;
1099 struct anv_bo workaround_bo
;
1100 struct anv_bo trivial_batch_bo
;
1101 struct anv_bo hiz_clear_bo
;
1103 /* Set of pointers to anv_buffer objects for all pinned buffers. Pinned
1104 * buffers are always resident because they could be used at any time via
1105 * VK_EXT_buffer_device_address.
1107 struct set
* pinned_buffers
;
1109 struct anv_pipeline_cache default_pipeline_cache
;
1110 struct blorp_context blorp
;
1112 struct anv_state border_colors
;
1114 struct anv_queue queue
;
1116 struct anv_scratch_pool scratch_pool
;
1118 uint32_t default_mocs
;
1119 uint32_t external_mocs
;
1121 pthread_mutex_t mutex
;
1122 pthread_cond_t queue_submit
;
1125 struct gen_batch_decode_ctx decoder_ctx
;
1127 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1128 * the cmd_buffer's list.
1130 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1133 static inline struct anv_state_pool
*
1134 anv_binding_table_pool(struct anv_device
*device
)
1136 if (device
->instance
->physicalDevice
.use_softpin
)
1137 return &device
->binding_table_pool
;
1139 return &device
->surface_state_pool
;
1142 static inline struct anv_state
1143 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1144 if (device
->instance
->physicalDevice
.use_softpin
)
1145 return anv_state_pool_alloc(&device
->binding_table_pool
,
1146 device
->binding_table_pool
.block_size
, 0);
1148 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1152 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1153 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1156 static inline uint32_t
1157 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1159 if (bo
->flags
& ANV_BO_EXTERNAL
)
1160 return device
->external_mocs
;
1162 return device
->default_mocs
;
1165 void anv_device_init_blorp(struct anv_device
*device
);
1166 void anv_device_finish_blorp(struct anv_device
*device
);
1168 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1169 const char *file
, int line
,
1170 const char *msg
, ...);
1171 #define anv_device_set_lost(dev, ...) \
1172 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1175 anv_device_is_lost(struct anv_device
*device
)
1177 return unlikely(device
->_lost
);
1180 VkResult
anv_device_execbuf(struct anv_device
*device
,
1181 struct drm_i915_gem_execbuffer2
*execbuf
,
1182 struct anv_bo
**execbuf_bos
);
1183 VkResult
anv_device_query_status(struct anv_device
*device
);
1184 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1185 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1188 void* anv_gem_mmap(struct anv_device
*device
,
1189 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1190 void anv_gem_munmap(void *p
, uint64_t size
);
1191 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1192 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1193 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1194 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1195 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1196 int anv_gem_execbuffer(struct anv_device
*device
,
1197 struct drm_i915_gem_execbuffer2
*execbuf
);
1198 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1199 uint32_t stride
, uint32_t tiling
);
1200 int anv_gem_create_context(struct anv_device
*device
);
1201 bool anv_gem_has_context_priority(int fd
);
1202 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1203 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1205 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1207 int anv_gem_get_param(int fd
, uint32_t param
);
1208 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1209 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1210 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1211 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1212 uint32_t *active
, uint32_t *pending
);
1213 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1214 int anv_gem_reg_read(struct anv_device
*device
,
1215 uint32_t offset
, uint64_t *result
);
1216 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1217 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1218 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1219 uint32_t read_domains
, uint32_t write_domain
);
1220 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1221 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1222 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1223 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1224 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1225 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1227 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1228 uint32_t handle
, int fd
);
1229 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1230 bool anv_gem_supports_syncobj_wait(int fd
);
1231 int anv_gem_syncobj_wait(struct anv_device
*device
,
1232 uint32_t *handles
, uint32_t num_handles
,
1233 int64_t abs_timeout_ns
, bool wait_all
);
1235 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1236 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1238 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1240 struct anv_reloc_list
{
1241 uint32_t num_relocs
;
1242 uint32_t array_length
;
1243 struct drm_i915_gem_relocation_entry
* relocs
;
1244 struct anv_bo
** reloc_bos
;
1248 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1249 const VkAllocationCallbacks
*alloc
);
1250 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1251 const VkAllocationCallbacks
*alloc
);
1253 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1254 const VkAllocationCallbacks
*alloc
,
1255 uint32_t offset
, struct anv_bo
*target_bo
,
1258 struct anv_batch_bo
{
1259 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1260 struct list_head link
;
1264 /* Bytes actually consumed in this batch BO */
1267 struct anv_reloc_list relocs
;
1271 const VkAllocationCallbacks
* alloc
;
1277 struct anv_reloc_list
* relocs
;
1279 /* This callback is called (with the associated user data) in the event
1280 * that the batch runs out of space.
1282 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1286 * Current error status of the command buffer. Used to track inconsistent
1287 * or incomplete command buffer states that are the consequence of run-time
1288 * errors such as out of memory scenarios. We want to track this in the
1289 * batch because the command buffer object is not visible to some parts
1295 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1296 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1297 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1298 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1299 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1300 struct anv_batch
*batch
);
1302 static inline VkResult
1303 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1305 assert(error
!= VK_SUCCESS
);
1306 if (batch
->status
== VK_SUCCESS
)
1307 batch
->status
= error
;
1308 return batch
->status
;
1312 anv_batch_has_error(struct anv_batch
*batch
)
1314 return batch
->status
!= VK_SUCCESS
;
1317 struct anv_address
{
1322 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1325 anv_address_is_null(struct anv_address addr
)
1327 return addr
.bo
== NULL
&& addr
.offset
== 0;
1330 static inline uint64_t
1331 anv_address_physical(struct anv_address addr
)
1333 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1334 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1336 return gen_canonical_address(addr
.offset
);
1339 static inline struct anv_address
1340 anv_address_add(struct anv_address addr
, uint64_t offset
)
1342 addr
.offset
+= offset
;
1347 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1349 unsigned reloc_size
= 0;
1350 if (device
->info
.gen
>= 8) {
1351 reloc_size
= sizeof(uint64_t);
1352 *(uint64_t *)p
= gen_canonical_address(v
);
1354 reloc_size
= sizeof(uint32_t);
1358 if (flush
&& !device
->info
.has_llc
)
1359 gen_flush_range(p
, reloc_size
);
1362 static inline uint64_t
1363 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1364 const struct anv_address address
, uint32_t delta
)
1366 if (address
.bo
== NULL
) {
1367 return address
.offset
+ delta
;
1369 assert(batch
->start
<= location
&& location
< batch
->end
);
1371 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1375 #define __gen_address_type struct anv_address
1376 #define __gen_user_data struct anv_batch
1377 #define __gen_combine_address _anv_combine_address
1379 /* Wrapper macros needed to work around preprocessor argument issues. In
1380 * particular, arguments don't get pre-evaluated if they are concatenated.
1381 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1382 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1383 * We can work around this easily enough with these helpers.
1385 #define __anv_cmd_length(cmd) cmd ## _length
1386 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1387 #define __anv_cmd_header(cmd) cmd ## _header
1388 #define __anv_cmd_pack(cmd) cmd ## _pack
1389 #define __anv_reg_num(reg) reg ## _num
1391 #define anv_pack_struct(dst, struc, ...) do { \
1392 struct struc __template = { \
1395 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1396 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1399 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1400 void *__dst = anv_batch_emit_dwords(batch, n); \
1402 struct cmd __template = { \
1403 __anv_cmd_header(cmd), \
1404 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1407 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1412 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1416 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1417 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1420 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1421 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1422 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1425 #define anv_batch_emit(batch, cmd, name) \
1426 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1427 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1428 __builtin_expect(_dst != NULL, 1); \
1429 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1430 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1434 /* MEMORY_OBJECT_CONTROL_STATE:
1435 * .GraphicsDataTypeGFDT = 0,
1436 * .LLCCacheabilityControlLLCCC = 0,
1437 * .L3CacheabilityControlL3CC = 1,
1441 /* MEMORY_OBJECT_CONTROL_STATE:
1442 * .LLCeLLCCacheabilityControlLLCCC = 0,
1443 * .L3CacheabilityControlL3CC = 1,
1445 #define GEN75_MOCS 1
1447 /* MEMORY_OBJECT_CONTROL_STATE:
1448 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1449 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1450 * .AgeforQUADLRU = 0
1452 #define GEN8_MOCS 0x78
1454 /* MEMORY_OBJECT_CONTROL_STATE:
1455 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1456 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1457 * .AgeforQUADLRU = 0
1459 #define GEN8_EXTERNAL_MOCS 0x18
1461 /* Skylake: MOCS is now an index into an array of 62 different caching
1462 * configurations programmed by the kernel.
1465 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1466 #define GEN9_MOCS (2 << 1)
1468 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1469 #define GEN9_EXTERNAL_MOCS (1 << 1)
1471 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1472 #define GEN10_MOCS GEN9_MOCS
1473 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1475 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1476 #define GEN11_MOCS GEN9_MOCS
1477 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1479 struct anv_device_memory
{
1481 struct anv_memory_type
* type
;
1482 VkDeviceSize map_size
;
1485 /* If set, we are holding reference to AHardwareBuffer
1486 * which we must release when memory is freed.
1488 struct AHardwareBuffer
* ahw
;
1492 * Header for Vertex URB Entry (VUE)
1494 struct anv_vue_header
{
1496 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1497 uint32_t ViewportIndex
;
1501 struct anv_descriptor_set_binding_layout
{
1503 /* The type of the descriptors in this binding */
1504 VkDescriptorType type
;
1507 /* Number of array elements in this binding */
1508 uint16_t array_size
;
1510 /* Index into the flattend descriptor set */
1511 uint16_t descriptor_index
;
1513 /* Index into the dynamic state array for a dynamic buffer */
1514 int16_t dynamic_offset_index
;
1516 /* Index into the descriptor set buffer views */
1517 int16_t buffer_index
;
1520 /* Index into the binding table for the associated surface */
1521 int16_t surface_index
;
1523 /* Index into the sampler table for the associated sampler */
1524 int16_t sampler_index
;
1526 /* Index into the image table for the associated image */
1527 int16_t image_index
;
1528 } stage
[MESA_SHADER_STAGES
];
1530 /* Immutable samplers (or NULL if no immutable samplers) */
1531 struct anv_sampler
**immutable_samplers
;
1534 struct anv_descriptor_set_layout
{
1535 /* Descriptor set layouts can be destroyed at almost any time */
1538 /* Number of bindings in this descriptor set */
1539 uint16_t binding_count
;
1541 /* Total size of the descriptor set with room for all array entries */
1544 /* Shader stages affected by this descriptor set */
1545 uint16_t shader_stages
;
1547 /* Number of buffers in this descriptor set */
1548 uint16_t buffer_count
;
1550 /* Number of dynamic offsets used by this descriptor set */
1551 uint16_t dynamic_offset_count
;
1553 /* Bindings in this descriptor set */
1554 struct anv_descriptor_set_binding_layout binding
[0];
1558 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1560 assert(layout
&& layout
->ref_cnt
>= 1);
1561 p_atomic_inc(&layout
->ref_cnt
);
1565 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1566 struct anv_descriptor_set_layout
*layout
)
1568 assert(layout
&& layout
->ref_cnt
>= 1);
1569 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1570 vk_free(&device
->alloc
, layout
);
1573 struct anv_descriptor
{
1574 VkDescriptorType type
;
1578 VkImageLayout layout
;
1579 struct anv_image_view
*image_view
;
1580 struct anv_sampler
*sampler
;
1584 struct anv_buffer
*buffer
;
1589 struct anv_buffer_view
*buffer_view
;
1593 struct anv_descriptor_set
{
1594 struct anv_descriptor_set_layout
*layout
;
1596 uint32_t buffer_count
;
1597 struct anv_buffer_view
*buffer_views
;
1598 struct anv_descriptor descriptors
[0];
1601 struct anv_buffer_view
{
1602 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1603 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1605 struct anv_address address
;
1607 struct anv_state surface_state
;
1608 struct anv_state storage_surface_state
;
1609 struct anv_state writeonly_storage_surface_state
;
1611 struct brw_image_param storage_image_param
;
1614 struct anv_push_descriptor_set
{
1615 struct anv_descriptor_set set
;
1617 /* Put this field right behind anv_descriptor_set so it fills up the
1618 * descriptors[0] field. */
1619 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1620 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1623 struct anv_descriptor_pool
{
1628 struct anv_state_stream surface_state_stream
;
1629 void *surface_state_free_list
;
1634 enum anv_descriptor_template_entry_type
{
1635 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1636 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1637 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1640 struct anv_descriptor_template_entry
{
1641 /* The type of descriptor in this entry */
1642 VkDescriptorType type
;
1644 /* Binding in the descriptor set */
1647 /* Offset at which to write into the descriptor set binding */
1648 uint32_t array_element
;
1650 /* Number of elements to write into the descriptor set binding */
1651 uint32_t array_count
;
1653 /* Offset into the user provided data */
1656 /* Stride between elements into the user provided data */
1660 struct anv_descriptor_update_template
{
1661 VkPipelineBindPoint bind_point
;
1663 /* The descriptor set this template corresponds to. This value is only
1664 * valid if the template was created with the templateType
1665 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1669 /* Number of entries in this template */
1670 uint32_t entry_count
;
1672 /* Entries of the template */
1673 struct anv_descriptor_template_entry entries
[0];
1677 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1680 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1681 const struct gen_device_info
* const devinfo
,
1682 const VkDescriptorImageInfo
* const info
,
1683 VkDescriptorType type
,
1688 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1689 VkDescriptorType type
,
1690 struct anv_buffer_view
*buffer_view
,
1695 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1696 struct anv_device
*device
,
1697 struct anv_state_stream
*alloc_stream
,
1698 VkDescriptorType type
,
1699 struct anv_buffer
*buffer
,
1702 VkDeviceSize offset
,
1703 VkDeviceSize range
);
1706 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1707 struct anv_device
*device
,
1708 struct anv_state_stream
*alloc_stream
,
1709 const struct anv_descriptor_update_template
*template,
1713 anv_descriptor_set_create(struct anv_device
*device
,
1714 struct anv_descriptor_pool
*pool
,
1715 struct anv_descriptor_set_layout
*layout
,
1716 struct anv_descriptor_set
**out_set
);
1719 anv_descriptor_set_destroy(struct anv_device
*device
,
1720 struct anv_descriptor_pool
*pool
,
1721 struct anv_descriptor_set
*set
);
1723 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1724 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1725 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1727 struct anv_pipeline_binding
{
1728 /* The descriptor set this surface corresponds to. The special value of
1729 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1730 * to a color attachment and not a regular descriptor.
1734 /* Binding in the descriptor set */
1737 /* Index in the binding */
1740 /* Plane in the binding index */
1743 /* Input attachment index (relative to the subpass) */
1744 uint8_t input_attachment_index
;
1746 /* For a storage image, whether it is write-only */
1750 struct anv_pipeline_layout
{
1752 struct anv_descriptor_set_layout
*layout
;
1753 uint32_t dynamic_offset_start
;
1759 bool has_dynamic_offsets
;
1760 } stage
[MESA_SHADER_STAGES
];
1762 unsigned char sha1
[20];
1766 struct anv_device
* device
;
1769 VkBufferUsageFlags usage
;
1771 /* Set when bound */
1772 struct anv_address address
;
1775 static inline uint64_t
1776 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1778 assert(offset
<= buffer
->size
);
1779 if (range
== VK_WHOLE_SIZE
) {
1780 return buffer
->size
- offset
;
1782 assert(range
+ offset
>= range
);
1783 assert(range
+ offset
<= buffer
->size
);
1788 enum anv_cmd_dirty_bits
{
1789 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1790 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1791 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1792 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1793 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1794 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1795 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1796 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1797 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1798 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1799 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1800 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1801 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1802 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1804 typedef uint32_t anv_cmd_dirty_mask_t
;
1806 enum anv_pipe_bits
{
1807 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1808 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1809 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1810 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1811 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1812 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1813 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1814 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1815 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1816 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1817 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1819 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1820 * a flush has happened but not a CS stall. The next time we do any sort
1821 * of invalidation we need to insert a CS stall at that time. Otherwise,
1822 * we would have to CS stall on every flush which could be bad.
1824 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1826 /* This bit does not exist directly in PIPE_CONTROL. It means that render
1827 * target operations related to transfer commands with VkBuffer as
1828 * destination are ongoing. Some operations like copies on the command
1829 * streamer might need to be aware of this to trigger the appropriate stall
1830 * before they can proceed with the copy.
1832 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
1835 #define ANV_PIPE_FLUSH_BITS ( \
1836 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1837 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1838 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1840 #define ANV_PIPE_STALL_BITS ( \
1841 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1842 ANV_PIPE_DEPTH_STALL_BIT | \
1843 ANV_PIPE_CS_STALL_BIT)
1845 #define ANV_PIPE_INVALIDATE_BITS ( \
1846 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1847 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1848 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1849 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1850 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1851 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1853 static inline enum anv_pipe_bits
1854 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1856 enum anv_pipe_bits pipe_bits
= 0;
1859 for_each_bit(b
, flags
) {
1860 switch ((VkAccessFlagBits
)(1 << b
)) {
1861 case VK_ACCESS_SHADER_WRITE_BIT
:
1862 /* We're transitioning a buffer that was previously used as write
1863 * destination through the data port. To make its content available
1864 * to future operations, flush the data cache.
1866 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1868 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1869 /* We're transitioning a buffer that was previously used as render
1870 * target. To make its content available to future operations, flush
1871 * the render target cache.
1873 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1875 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1876 /* We're transitioning a buffer that was previously used as depth
1877 * buffer. To make its content available to future operations, flush
1880 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1882 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1883 /* We're transitioning a buffer that was previously used as a
1884 * transfer write destination. Generic write operations include color
1885 * & depth operations as well as buffer operations like :
1886 * - vkCmdClearColorImage()
1887 * - vkCmdClearDepthStencilImage()
1888 * - vkCmdBlitImage()
1889 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
1891 * Most of these operations are implemented using Blorp which writes
1892 * through the render target, so flush that cache to make it visible
1893 * to future operations. And for depth related operations we also
1894 * need to flush the depth cache.
1896 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1897 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1899 case VK_ACCESS_MEMORY_WRITE_BIT
:
1900 /* We're transitioning a buffer for generic write operations. Flush
1903 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1906 break; /* Nothing to do */
1913 static inline enum anv_pipe_bits
1914 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1916 enum anv_pipe_bits pipe_bits
= 0;
1919 for_each_bit(b
, flags
) {
1920 switch ((VkAccessFlagBits
)(1 << b
)) {
1921 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1922 /* Indirect draw commands take a buffer as input that we're going to
1923 * read from the command streamer to load some of the HW registers
1924 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
1925 * command streamer stall so that all the cache flushes have
1926 * completed before the command streamer loads from memory.
1928 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1929 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
1930 * through a vertex buffer, so invalidate that cache.
1932 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1933 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
1934 * UBO from the buffer, so we need to invalidate constant cache.
1936 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1938 case VK_ACCESS_INDEX_READ_BIT
:
1939 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1940 /* We transitioning a buffer to be used for as input for vkCmdDraw*
1941 * commands, so we invalidate the VF cache to make sure there is no
1942 * stale data when we start rendering.
1944 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1946 case VK_ACCESS_UNIFORM_READ_BIT
:
1947 /* We transitioning a buffer to be used as uniform data. Because
1948 * uniform is accessed through the data port & sampler, we need to
1949 * invalidate the texture cache (sampler) & constant cache (data
1950 * port) to avoid stale data.
1952 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1953 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1955 case VK_ACCESS_SHADER_READ_BIT
:
1956 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1957 case VK_ACCESS_TRANSFER_READ_BIT
:
1958 /* Transitioning a buffer to be read through the sampler, so
1959 * invalidate the texture cache, we don't want any stale data.
1961 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1963 case VK_ACCESS_MEMORY_READ_BIT
:
1964 /* Transitioning a buffer for generic read, invalidate all the
1967 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
1969 case VK_ACCESS_MEMORY_WRITE_BIT
:
1970 /* Generic write, make sure all previously written things land in
1973 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1975 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
1976 /* Transitioning a buffer for conditional rendering. We'll load the
1977 * content of this buffer into HW registers using the command
1978 * streamer, so we need to stall the command streamer to make sure
1979 * any in-flight flush operations have completed.
1981 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1984 break; /* Nothing to do */
1991 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1992 VK_IMAGE_ASPECT_COLOR_BIT | \
1993 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1994 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1995 VK_IMAGE_ASPECT_PLANE_2_BIT)
1996 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1997 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1998 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1999 VK_IMAGE_ASPECT_PLANE_2_BIT)
2001 struct anv_vertex_binding
{
2002 struct anv_buffer
* buffer
;
2003 VkDeviceSize offset
;
2006 struct anv_xfb_binding
{
2007 struct anv_buffer
* buffer
;
2008 VkDeviceSize offset
;
2012 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2013 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2015 struct anv_push_constants
{
2016 /* Current allocated size of this push constants data structure.
2017 * Because a decent chunk of it may not be used (images on SKL, for
2018 * instance), we won't actually allocate the entire structure up-front.
2022 /* Push constant data provided by the client through vkPushConstants */
2023 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2025 /* Used for vkCmdDispatchBase */
2026 uint32_t base_work_group_id
[3];
2028 /* Image data for image_load_store on pre-SKL */
2029 struct brw_image_param images
[MAX_GEN8_IMAGES
];
2032 struct anv_dynamic_state
{
2035 VkViewport viewports
[MAX_VIEWPORTS
];
2040 VkRect2D scissors
[MAX_SCISSORS
];
2051 float blend_constants
[4];
2061 } stencil_compare_mask
;
2066 } stencil_write_mask
;
2071 } stencil_reference
;
2074 extern const struct anv_dynamic_state default_dynamic_state
;
2076 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2077 const struct anv_dynamic_state
*src
,
2078 uint32_t copy_mask
);
2080 struct anv_surface_state
{
2081 struct anv_state state
;
2082 /** Address of the surface referred to by this state
2084 * This address is relative to the start of the BO.
2086 struct anv_address address
;
2087 /* Address of the aux surface, if any
2089 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2091 * With the exception of gen8, the bottom 12 bits of this address' offset
2092 * include extra aux information.
2094 struct anv_address aux_address
;
2095 /* Address of the clear color, if any
2097 * This address is relative to the start of the BO.
2099 struct anv_address clear_address
;
2103 * Attachment state when recording a renderpass instance.
2105 * The clear value is valid only if there exists a pending clear.
2107 struct anv_attachment_state
{
2108 enum isl_aux_usage aux_usage
;
2109 enum isl_aux_usage input_aux_usage
;
2110 struct anv_surface_state color
;
2111 struct anv_surface_state input
;
2113 VkImageLayout current_layout
;
2114 VkImageAspectFlags pending_clear_aspects
;
2115 VkImageAspectFlags pending_load_aspects
;
2117 VkClearValue clear_value
;
2118 bool clear_color_is_zero_one
;
2119 bool clear_color_is_zero
;
2121 /* When multiview is active, attachments with a renderpass clear
2122 * operation have their respective layers cleared on the first
2123 * subpass that uses them, and only in that subpass. We keep track
2124 * of this using a bitfield to indicate which layers of an attachment
2125 * have not been cleared yet when multiview is active.
2127 uint32_t pending_clear_views
;
2130 /** State tracking for particular pipeline bind point
2132 * This struct is the base struct for anv_cmd_graphics_state and
2133 * anv_cmd_compute_state. These are used to track state which is bound to a
2134 * particular type of pipeline. Generic state that applies per-stage such as
2135 * binding table offsets and push constants is tracked generically with a
2136 * per-stage array in anv_cmd_state.
2138 struct anv_cmd_pipeline_state
{
2139 struct anv_pipeline
*pipeline
;
2140 struct anv_pipeline_layout
*layout
;
2142 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2143 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2145 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2148 /** State tracking for graphics pipeline
2150 * This has anv_cmd_pipeline_state as a base struct to track things which get
2151 * bound to a graphics pipeline. Along with general pipeline bind point state
2152 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2153 * state which is graphics-specific.
2155 struct anv_cmd_graphics_state
{
2156 struct anv_cmd_pipeline_state base
;
2158 anv_cmd_dirty_mask_t dirty
;
2161 struct anv_dynamic_state dynamic
;
2164 struct anv_buffer
*index_buffer
;
2165 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2166 uint32_t index_offset
;
2170 /** State tracking for compute pipeline
2172 * This has anv_cmd_pipeline_state as a base struct to track things which get
2173 * bound to a compute pipeline. Along with general pipeline bind point state
2174 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2175 * state which is compute-specific.
2177 struct anv_cmd_compute_state
{
2178 struct anv_cmd_pipeline_state base
;
2180 bool pipeline_dirty
;
2182 struct anv_address num_workgroups
;
2185 /** State required while building cmd buffer */
2186 struct anv_cmd_state
{
2187 /* PIPELINE_SELECT.PipelineSelection */
2188 uint32_t current_pipeline
;
2189 const struct gen_l3_config
* current_l3_config
;
2191 struct anv_cmd_graphics_state gfx
;
2192 struct anv_cmd_compute_state compute
;
2194 enum anv_pipe_bits pending_pipe_bits
;
2195 VkShaderStageFlags descriptors_dirty
;
2196 VkShaderStageFlags push_constants_dirty
;
2198 struct anv_framebuffer
* framebuffer
;
2199 struct anv_render_pass
* pass
;
2200 struct anv_subpass
* subpass
;
2201 VkRect2D render_area
;
2202 uint32_t restart_index
;
2203 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2205 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2206 VkShaderStageFlags push_constant_stages
;
2207 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
2208 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2209 struct anv_state samplers
[MESA_SHADER_STAGES
];
2212 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2213 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2214 * and before invoking the secondary in ExecuteCommands.
2216 bool pma_fix_enabled
;
2219 * Whether or not we know for certain that HiZ is enabled for the current
2220 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2221 * enabled or not, this will be false.
2225 bool conditional_render_enabled
;
2228 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2229 * valid only when recording a render pass instance.
2231 struct anv_attachment_state
* attachments
;
2234 * Surface states for color render targets. These are stored in a single
2235 * flat array. For depth-stencil attachments, the surface state is simply
2238 struct anv_state render_pass_states
;
2241 * A null surface state of the right size to match the framebuffer. This
2242 * is one of the states in render_pass_states.
2244 struct anv_state null_surface_state
;
2247 struct anv_cmd_pool
{
2248 VkAllocationCallbacks alloc
;
2249 struct list_head cmd_buffers
;
2252 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2254 enum anv_cmd_buffer_exec_mode
{
2255 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2256 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2257 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2258 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2259 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2262 struct anv_cmd_buffer
{
2263 VK_LOADER_DATA _loader_data
;
2265 struct anv_device
* device
;
2267 struct anv_cmd_pool
* pool
;
2268 struct list_head pool_link
;
2270 struct anv_batch batch
;
2272 /* Fields required for the actual chain of anv_batch_bo's.
2274 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2276 struct list_head batch_bos
;
2277 enum anv_cmd_buffer_exec_mode exec_mode
;
2279 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2280 * referenced by this command buffer
2282 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2284 struct u_vector seen_bbos
;
2286 /* A vector of int32_t's for every block of binding tables.
2288 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2290 struct u_vector bt_block_states
;
2293 struct anv_reloc_list surface_relocs
;
2294 /** Last seen surface state block pool center bo offset */
2295 uint32_t last_ss_pool_center
;
2297 /* Serial for tracking buffer completion */
2300 /* Stream objects for storing temporary data */
2301 struct anv_state_stream surface_state_stream
;
2302 struct anv_state_stream dynamic_state_stream
;
2304 VkCommandBufferUsageFlags usage_flags
;
2305 VkCommandBufferLevel level
;
2307 struct anv_cmd_state state
;
2310 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2311 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2312 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2313 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2314 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2315 struct anv_cmd_buffer
*secondary
);
2316 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2317 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2318 struct anv_cmd_buffer
*cmd_buffer
,
2319 const VkSemaphore
*in_semaphores
,
2320 uint32_t num_in_semaphores
,
2321 const VkSemaphore
*out_semaphores
,
2322 uint32_t num_out_semaphores
,
2325 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2328 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2329 gl_shader_stage stage
, uint32_t size
);
2330 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2331 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2332 (offsetof(struct anv_push_constants, field) + \
2333 sizeof(cmd_buffer->state.push_constants[0]->field)))
2335 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2336 const void *data
, uint32_t size
, uint32_t alignment
);
2337 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2338 uint32_t *a
, uint32_t *b
,
2339 uint32_t dwords
, uint32_t alignment
);
2342 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2344 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2345 uint32_t entries
, uint32_t *state_offset
);
2347 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2349 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2350 uint32_t size
, uint32_t alignment
);
2353 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2355 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2356 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2357 bool depth_clamp_enable
);
2358 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2360 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2361 struct anv_render_pass
*pass
,
2362 struct anv_framebuffer
*framebuffer
,
2363 const VkClearValue
*clear_values
);
2365 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2368 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2369 gl_shader_stage stage
);
2371 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2373 const struct anv_image_view
*
2374 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2377 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2378 uint32_t num_entries
,
2379 uint32_t *state_offset
,
2380 struct anv_state
*bt_state
);
2382 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2384 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2386 enum anv_fence_type
{
2387 ANV_FENCE_TYPE_NONE
= 0,
2389 ANV_FENCE_TYPE_SYNCOBJ
,
2393 enum anv_bo_fence_state
{
2394 /** Indicates that this is a new (or newly reset fence) */
2395 ANV_BO_FENCE_STATE_RESET
,
2397 /** Indicates that this fence has been submitted to the GPU but is still
2398 * (as far as we know) in use by the GPU.
2400 ANV_BO_FENCE_STATE_SUBMITTED
,
2402 ANV_BO_FENCE_STATE_SIGNALED
,
2405 struct anv_fence_impl
{
2406 enum anv_fence_type type
;
2409 /** Fence implementation for BO fences
2411 * These fences use a BO and a set of CPU-tracked state flags. The BO
2412 * is added to the object list of the last execbuf call in a QueueSubmit
2413 * and is marked EXEC_WRITE. The state flags track when the BO has been
2414 * submitted to the kernel. We need to do this because Vulkan lets you
2415 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2416 * will say it's idle in this case.
2420 enum anv_bo_fence_state state
;
2423 /** DRM syncobj handle for syncobj-based fences */
2427 struct wsi_fence
*fence_wsi
;
2432 /* Permanent fence state. Every fence has some form of permanent state
2433 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2434 * cross-process fences) or it could just be a dummy for use internally.
2436 struct anv_fence_impl permanent
;
2438 /* Temporary fence state. A fence *may* have temporary state. That state
2439 * is added to the fence by an import operation and is reset back to
2440 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2441 * state cannot be signaled because the fence must already be signaled
2442 * before the temporary state can be exported from the fence in the other
2443 * process and imported here.
2445 struct anv_fence_impl temporary
;
2450 struct anv_state state
;
2453 enum anv_semaphore_type
{
2454 ANV_SEMAPHORE_TYPE_NONE
= 0,
2455 ANV_SEMAPHORE_TYPE_DUMMY
,
2456 ANV_SEMAPHORE_TYPE_BO
,
2457 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2458 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2461 struct anv_semaphore_impl
{
2462 enum anv_semaphore_type type
;
2465 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2466 * This BO will be added to the object list on any execbuf2 calls for
2467 * which this semaphore is used as a wait or signal fence. When used as
2468 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2472 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2473 * If the semaphore is in the unsignaled state due to either just being
2474 * created or because it has been used for a wait, fd will be -1.
2478 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2479 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2480 * import so we don't need to bother with a userspace cache.
2486 struct anv_semaphore
{
2487 /* Permanent semaphore state. Every semaphore has some form of permanent
2488 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2489 * (for cross-process semaphores0 or it could just be a dummy for use
2492 struct anv_semaphore_impl permanent
;
2494 /* Temporary semaphore state. A semaphore *may* have temporary state.
2495 * That state is added to the semaphore by an import operation and is reset
2496 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2497 * semaphore with temporary state cannot be signaled because the semaphore
2498 * must already be signaled before the temporary state can be exported from
2499 * the semaphore in the other process and imported here.
2501 struct anv_semaphore_impl temporary
;
2504 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2505 struct anv_semaphore
*semaphore
);
2507 struct anv_shader_module
{
2508 unsigned char sha1
[20];
2513 static inline gl_shader_stage
2514 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2516 assert(__builtin_popcount(vk_stage
) == 1);
2517 return ffs(vk_stage
) - 1;
2520 static inline VkShaderStageFlagBits
2521 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2523 return (1 << mesa_stage
);
2526 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2528 #define anv_foreach_stage(stage, stage_bits) \
2529 for (gl_shader_stage stage, \
2530 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2531 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2532 __tmp &= ~(1 << (stage)))
2534 struct anv_pipeline_bind_map
{
2535 uint32_t surface_count
;
2536 uint32_t sampler_count
;
2537 uint32_t image_count
;
2539 struct anv_pipeline_binding
* surface_to_descriptor
;
2540 struct anv_pipeline_binding
* sampler_to_descriptor
;
2543 struct anv_shader_bin_key
{
2548 struct anv_shader_bin
{
2551 const struct anv_shader_bin_key
*key
;
2553 struct anv_state kernel
;
2554 uint32_t kernel_size
;
2556 struct anv_state constant_data
;
2557 uint32_t constant_data_size
;
2559 const struct brw_stage_prog_data
*prog_data
;
2560 uint32_t prog_data_size
;
2562 struct nir_xfb_info
*xfb_info
;
2564 struct anv_pipeline_bind_map bind_map
;
2567 struct anv_shader_bin
*
2568 anv_shader_bin_create(struct anv_device
*device
,
2569 const void *key
, uint32_t key_size
,
2570 const void *kernel
, uint32_t kernel_size
,
2571 const void *constant_data
, uint32_t constant_data_size
,
2572 const struct brw_stage_prog_data
*prog_data
,
2573 uint32_t prog_data_size
, const void *prog_data_param
,
2574 const struct nir_xfb_info
*xfb_info
,
2575 const struct anv_pipeline_bind_map
*bind_map
);
2578 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2581 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2583 assert(shader
&& shader
->ref_cnt
>= 1);
2584 p_atomic_inc(&shader
->ref_cnt
);
2588 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2590 assert(shader
&& shader
->ref_cnt
>= 1);
2591 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2592 anv_shader_bin_destroy(device
, shader
);
2595 struct anv_pipeline
{
2596 struct anv_device
* device
;
2597 struct anv_batch batch
;
2598 uint32_t batch_data
[512];
2599 struct anv_reloc_list batch_relocs
;
2600 uint32_t dynamic_state_mask
;
2601 struct anv_dynamic_state dynamic_state
;
2603 struct anv_subpass
* subpass
;
2605 bool needs_data_cache
;
2607 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2610 const struct gen_l3_config
* l3_config
;
2611 uint32_t total_size
;
2614 VkShaderStageFlags active_stages
;
2615 struct anv_state blend_state
;
2618 struct anv_pipeline_vertex_binding
{
2621 uint32_t instance_divisor
;
2626 bool primitive_restart
;
2629 uint32_t cs_right_mask
;
2632 bool depth_test_enable
;
2633 bool writes_stencil
;
2634 bool stencil_test_enable
;
2635 bool depth_clamp_enable
;
2636 bool depth_clip_enable
;
2637 bool sample_shading_enable
;
2642 uint32_t depth_stencil_state
[3];
2648 uint32_t wm_depth_stencil
[3];
2652 uint32_t wm_depth_stencil
[4];
2655 uint32_t interface_descriptor_data
[8];
2659 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2660 gl_shader_stage stage
)
2662 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2665 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2666 static inline const struct brw_##prefix##_prog_data * \
2667 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2669 if (anv_pipeline_has_stage(pipeline, stage)) { \
2670 return (const struct brw_##prefix##_prog_data *) \
2671 pipeline->shaders[stage]->prog_data; \
2677 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2678 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2679 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2680 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2681 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2682 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2684 static inline const struct brw_vue_prog_data
*
2685 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2687 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2688 return &get_gs_prog_data(pipeline
)->base
;
2689 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2690 return &get_tes_prog_data(pipeline
)->base
;
2692 return &get_vs_prog_data(pipeline
)->base
;
2696 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2697 struct anv_pipeline_cache
*cache
,
2698 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2699 const VkAllocationCallbacks
*alloc
);
2702 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2703 struct anv_pipeline_cache
*cache
,
2704 const VkComputePipelineCreateInfo
*info
,
2705 const struct anv_shader_module
*module
,
2706 const char *entrypoint
,
2707 const VkSpecializationInfo
*spec_info
);
2709 struct anv_format_plane
{
2710 enum isl_format isl_format
:16;
2711 struct isl_swizzle swizzle
;
2713 /* Whether this plane contains chroma channels */
2716 /* For downscaling of YUV planes */
2717 uint8_t denominator_scales
[2];
2719 /* How to map sampled ycbcr planes to a single 4 component element. */
2720 struct isl_swizzle ycbcr_swizzle
;
2722 /* What aspect is associated to this plane */
2723 VkImageAspectFlags aspect
;
2728 struct anv_format_plane planes
[3];
2734 static inline uint32_t
2735 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2736 VkImageAspectFlags aspect_mask
)
2738 switch (aspect_mask
) {
2739 case VK_IMAGE_ASPECT_COLOR_BIT
:
2740 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2741 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2743 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2744 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2747 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2749 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2752 /* Purposefully assert with depth/stencil aspects. */
2753 unreachable("invalid image aspect");
2757 static inline VkImageAspectFlags
2758 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2761 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2762 if (util_bitcount(image_aspects
) > 1)
2763 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2764 return VK_IMAGE_ASPECT_COLOR_BIT
;
2766 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2767 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2768 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2769 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2772 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2773 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2775 const struct anv_format
*
2776 anv_get_format(VkFormat format
);
2778 static inline uint32_t
2779 anv_get_format_planes(VkFormat vk_format
)
2781 const struct anv_format
*format
= anv_get_format(vk_format
);
2783 return format
!= NULL
? format
->n_planes
: 0;
2786 struct anv_format_plane
2787 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2788 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2790 static inline enum isl_format
2791 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2792 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2794 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2797 static inline struct isl_swizzle
2798 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2800 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2801 * RGB as RGBA for texturing
2803 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2804 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2806 /* But it doesn't matter what we render to that channel */
2807 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2813 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2816 * Subsurface of an anv_image.
2818 struct anv_surface
{
2819 /** Valid only if isl_surf::size_B > 0. */
2820 struct isl_surf isl
;
2823 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2830 /* The original VkFormat provided by the client. This may not match any
2831 * of the actual surface formats.
2834 const struct anv_format
*format
;
2836 VkImageAspectFlags aspects
;
2839 uint32_t array_size
;
2840 uint32_t samples
; /**< VkImageCreateInfo::samples */
2842 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2843 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
2844 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2846 /** True if this is needs to be bound to an appropriately tiled BO.
2848 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2849 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2850 * we require a dedicated allocation so that we can know to allocate a
2853 bool needs_set_tiling
;
2856 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2857 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2859 uint64_t drm_format_mod
;
2864 /* Whether the image is made of several underlying buffer objects rather a
2865 * single one with different offsets.
2869 /* All the formats that can be used when creating views of this image
2870 * are CCS_E compatible.
2872 bool ccs_e_compatible
;
2874 /* Image was created with external format. */
2875 bool external_format
;
2880 * For each foo, anv_image::planes[x].surface is valid if and only if
2881 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2882 * to figure the number associated with a given aspect.
2884 * The hardware requires that the depth buffer and stencil buffer be
2885 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2886 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2887 * allocate the depth and stencil buffers as separate surfaces in the same
2892 * -----------------------
2894 * ----------------------- |
2895 * | shadow surface0 | |
2896 * ----------------------- | Plane 0
2897 * | aux surface0 | |
2898 * ----------------------- |
2899 * | fast clear colors0 | \|/
2900 * -----------------------
2902 * ----------------------- |
2903 * | shadow surface1 | |
2904 * ----------------------- | Plane 1
2905 * | aux surface1 | |
2906 * ----------------------- |
2907 * | fast clear colors1 | \|/
2908 * -----------------------
2911 * -----------------------
2915 * Offset of the entire plane (whenever the image is disjoint this is
2923 struct anv_surface surface
;
2926 * A surface which shadows the main surface and may have different
2927 * tiling. This is used for sampling using a tiling that isn't supported
2928 * for other operations.
2930 struct anv_surface shadow_surface
;
2933 * For color images, this is the aux usage for this image when not used
2934 * as a color attachment.
2936 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2937 * image has a HiZ buffer.
2939 enum isl_aux_usage aux_usage
;
2941 struct anv_surface aux_surface
;
2944 * Offset of the fast clear state (used to compute the
2945 * fast_clear_state_offset of the following planes).
2947 uint32_t fast_clear_state_offset
;
2950 * BO associated with this plane, set when bound.
2952 struct anv_address address
;
2955 * When destroying the image, also free the bo.
2961 /* The ordering of this enum is important */
2962 enum anv_fast_clear_type
{
2963 /** Image does not have/support any fast-clear blocks */
2964 ANV_FAST_CLEAR_NONE
= 0,
2965 /** Image has/supports fast-clear but only to the default value */
2966 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
2967 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2968 ANV_FAST_CLEAR_ANY
= 2,
2971 /* Returns the number of auxiliary buffer levels attached to an image. */
2972 static inline uint8_t
2973 anv_image_aux_levels(const struct anv_image
* const image
,
2974 VkImageAspectFlagBits aspect
)
2976 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2977 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
2978 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
2981 /* Returns the number of auxiliary buffer layers attached to an image. */
2982 static inline uint32_t
2983 anv_image_aux_layers(const struct anv_image
* const image
,
2984 VkImageAspectFlagBits aspect
,
2985 const uint8_t miplevel
)
2989 /* The miplevel must exist in the main buffer. */
2990 assert(miplevel
< image
->levels
);
2992 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
2993 /* There are no layers with auxiliary data because the miplevel has no
2998 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2999 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
3000 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
3004 static inline struct anv_address
3005 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3006 const struct anv_image
*image
,
3007 VkImageAspectFlagBits aspect
)
3009 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3011 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3012 return anv_address_add(image
->planes
[plane
].address
,
3013 image
->planes
[plane
].fast_clear_state_offset
);
3016 static inline struct anv_address
3017 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3018 const struct anv_image
*image
,
3019 VkImageAspectFlagBits aspect
)
3021 struct anv_address addr
=
3022 anv_image_get_clear_color_addr(device
, image
, aspect
);
3024 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3025 device
->isl_dev
.ss
.clear_color_state_size
:
3026 device
->isl_dev
.ss
.clear_value_size
;
3027 return anv_address_add(addr
, clear_color_state_size
);
3030 static inline struct anv_address
3031 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3032 const struct anv_image
*image
,
3033 VkImageAspectFlagBits aspect
,
3034 uint32_t level
, uint32_t array_layer
)
3036 assert(level
< anv_image_aux_levels(image
, aspect
));
3037 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3038 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3039 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3041 struct anv_address addr
=
3042 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3043 addr
.offset
+= 4; /* Go past the fast clear type */
3045 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3046 for (uint32_t l
= 0; l
< level
; l
++)
3047 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3049 addr
.offset
+= level
* image
->array_size
* 4;
3051 addr
.offset
+= array_layer
* 4;
3056 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3058 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3059 const struct anv_image
*image
)
3061 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3064 if (devinfo
->gen
< 8)
3067 return image
->samples
== 1;
3071 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3072 const struct anv_image
*image
,
3073 VkImageAspectFlagBits aspect
,
3074 enum isl_aux_usage aux_usage
,
3076 uint32_t base_layer
,
3077 uint32_t layer_count
);
3080 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3081 const struct anv_image
*image
,
3082 VkImageAspectFlagBits aspect
,
3083 enum isl_aux_usage aux_usage
,
3084 enum isl_format format
, struct isl_swizzle swizzle
,
3085 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3086 VkRect2D area
, union isl_color_value clear_color
);
3088 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3089 const struct anv_image
*image
,
3090 VkImageAspectFlags aspects
,
3091 enum isl_aux_usage depth_aux_usage
,
3093 uint32_t base_layer
, uint32_t layer_count
,
3095 float depth_value
, uint8_t stencil_value
);
3097 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3098 const struct anv_image
*src_image
,
3099 enum isl_aux_usage src_aux_usage
,
3100 uint32_t src_level
, uint32_t src_base_layer
,
3101 const struct anv_image
*dst_image
,
3102 enum isl_aux_usage dst_aux_usage
,
3103 uint32_t dst_level
, uint32_t dst_base_layer
,
3104 VkImageAspectFlagBits aspect
,
3105 uint32_t src_x
, uint32_t src_y
,
3106 uint32_t dst_x
, uint32_t dst_y
,
3107 uint32_t width
, uint32_t height
,
3108 uint32_t layer_count
,
3109 enum blorp_filter filter
);
3111 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3112 const struct anv_image
*image
,
3113 VkImageAspectFlagBits aspect
, uint32_t level
,
3114 uint32_t base_layer
, uint32_t layer_count
,
3115 enum isl_aux_op hiz_op
);
3117 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3118 const struct anv_image
*image
,
3119 VkImageAspectFlags aspects
,
3121 uint32_t base_layer
, uint32_t layer_count
,
3122 VkRect2D area
, uint8_t stencil_value
);
3124 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3125 const struct anv_image
*image
,
3126 enum isl_format format
,
3127 VkImageAspectFlagBits aspect
,
3128 uint32_t base_layer
, uint32_t layer_count
,
3129 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3132 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3133 const struct anv_image
*image
,
3134 enum isl_format format
,
3135 VkImageAspectFlagBits aspect
, uint32_t level
,
3136 uint32_t base_layer
, uint32_t layer_count
,
3137 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3141 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3142 const struct anv_image
*image
,
3143 uint32_t base_level
, uint32_t level_count
,
3144 uint32_t base_layer
, uint32_t layer_count
);
3147 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3148 const struct anv_image
*image
,
3149 const VkImageAspectFlagBits aspect
,
3150 const VkImageLayout layout
);
3152 enum anv_fast_clear_type
3153 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3154 const struct anv_image
* const image
,
3155 const VkImageAspectFlagBits aspect
,
3156 const VkImageLayout layout
);
3158 /* This is defined as a macro so that it works for both
3159 * VkImageSubresourceRange and VkImageSubresourceLayers
3161 #define anv_get_layerCount(_image, _range) \
3162 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3163 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3165 static inline uint32_t
3166 anv_get_levelCount(const struct anv_image
*image
,
3167 const VkImageSubresourceRange
*range
)
3169 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3170 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3173 static inline VkImageAspectFlags
3174 anv_image_expand_aspects(const struct anv_image
*image
,
3175 VkImageAspectFlags aspects
)
3177 /* If the underlying image has color plane aspects and
3178 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3179 * the underlying image. */
3180 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3181 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3182 return image
->aspects
;
3188 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3189 VkImageAspectFlags aspects2
)
3191 if (aspects1
== aspects2
)
3194 /* Only 1 color aspects are compatibles. */
3195 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3196 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3197 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3203 struct anv_image_view
{
3204 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3206 VkImageAspectFlags aspect_mask
;
3208 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3212 uint32_t image_plane
;
3214 struct isl_view isl
;
3217 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3218 * image layout of SHADER_READ_ONLY_OPTIMAL or
3219 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3221 struct anv_surface_state optimal_sampler_surface_state
;
3224 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3225 * image layout of GENERAL.
3227 struct anv_surface_state general_sampler_surface_state
;
3230 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3231 * states for write-only and readable, using the real format for
3232 * write-only and the lowered format for readable.
3234 struct anv_surface_state storage_surface_state
;
3235 struct anv_surface_state writeonly_storage_surface_state
;
3237 struct brw_image_param storage_image_param
;
3241 enum anv_image_view_state_flags
{
3242 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3243 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3246 void anv_image_fill_surface_state(struct anv_device
*device
,
3247 const struct anv_image
*image
,
3248 VkImageAspectFlagBits aspect
,
3249 const struct isl_view
*view
,
3250 isl_surf_usage_flags_t view_usage
,
3251 enum isl_aux_usage aux_usage
,
3252 const union isl_color_value
*clear_color
,
3253 enum anv_image_view_state_flags flags
,
3254 struct anv_surface_state
*state_inout
,
3255 struct brw_image_param
*image_param_out
);
3257 struct anv_image_create_info
{
3258 const VkImageCreateInfo
*vk_info
;
3260 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3261 isl_tiling_flags_t isl_tiling_flags
;
3263 /** These flags will be added to any derived from VkImageCreateInfo. */
3264 isl_surf_usage_flags_t isl_extra_usage_flags
;
3267 bool external_format
;
3270 VkResult
anv_image_create(VkDevice _device
,
3271 const struct anv_image_create_info
*info
,
3272 const VkAllocationCallbacks
* alloc
,
3275 const struct anv_surface
*
3276 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3277 VkImageAspectFlags aspect_mask
);
3280 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3282 static inline struct VkExtent3D
3283 anv_sanitize_image_extent(const VkImageType imageType
,
3284 const struct VkExtent3D imageExtent
)
3286 switch (imageType
) {
3287 case VK_IMAGE_TYPE_1D
:
3288 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3289 case VK_IMAGE_TYPE_2D
:
3290 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3291 case VK_IMAGE_TYPE_3D
:
3294 unreachable("invalid image type");
3298 static inline struct VkOffset3D
3299 anv_sanitize_image_offset(const VkImageType imageType
,
3300 const struct VkOffset3D imageOffset
)
3302 switch (imageType
) {
3303 case VK_IMAGE_TYPE_1D
:
3304 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3305 case VK_IMAGE_TYPE_2D
:
3306 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3307 case VK_IMAGE_TYPE_3D
:
3310 unreachable("invalid image type");
3314 VkFormatFeatureFlags
3315 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3317 const struct anv_format
*anv_format
,
3318 VkImageTiling vk_tiling
);
3320 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3321 struct anv_state state
,
3322 enum isl_format format
,
3323 struct anv_address address
,
3324 uint32_t range
, uint32_t stride
);
3327 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3328 const struct anv_attachment_state
*att_state
,
3329 const struct anv_image_view
*iview
)
3331 const struct isl_format_layout
*view_fmtl
=
3332 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3334 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3335 if (view_fmtl->channels.c.bits) \
3336 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3338 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3339 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3340 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3341 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3343 #undef COPY_CLEAR_COLOR_CHANNEL
3347 struct anv_ycbcr_conversion
{
3348 const struct anv_format
* format
;
3349 VkSamplerYcbcrModelConversion ycbcr_model
;
3350 VkSamplerYcbcrRange ycbcr_range
;
3351 VkComponentSwizzle mapping
[4];
3352 VkChromaLocation chroma_offsets
[2];
3353 VkFilter chroma_filter
;
3354 bool chroma_reconstruction
;
3357 struct anv_sampler
{
3358 uint32_t state
[3][4];
3360 struct anv_ycbcr_conversion
*conversion
;
3363 struct anv_framebuffer
{
3368 uint32_t attachment_count
;
3369 struct anv_image_view
* attachments
[0];
3372 struct anv_subpass_attachment
{
3373 VkImageUsageFlagBits usage
;
3374 uint32_t attachment
;
3375 VkImageLayout layout
;
3378 struct anv_subpass
{
3379 uint32_t attachment_count
;
3382 * A pointer to all attachment references used in this subpass.
3383 * Only valid if ::attachment_count > 0.
3385 struct anv_subpass_attachment
* attachments
;
3386 uint32_t input_count
;
3387 struct anv_subpass_attachment
* input_attachments
;
3388 uint32_t color_count
;
3389 struct anv_subpass_attachment
* color_attachments
;
3390 struct anv_subpass_attachment
* resolve_attachments
;
3392 struct anv_subpass_attachment
* depth_stencil_attachment
;
3393 struct anv_subpass_attachment
* ds_resolve_attachment
;
3394 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3395 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3399 /** Subpass has a depth/stencil self-dependency */
3400 bool has_ds_self_dep
;
3402 /** Subpass has at least one color resolve attachment */
3403 bool has_color_resolve
;
3406 static inline unsigned
3407 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3409 return MAX2(1, util_bitcount(subpass
->view_mask
));
3412 struct anv_render_pass_attachment
{
3413 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3414 * its members individually.
3418 VkImageUsageFlags usage
;
3419 VkAttachmentLoadOp load_op
;
3420 VkAttachmentStoreOp store_op
;
3421 VkAttachmentLoadOp stencil_load_op
;
3422 VkImageLayout initial_layout
;
3423 VkImageLayout final_layout
;
3424 VkImageLayout first_subpass_layout
;
3426 /* The subpass id in which the attachment will be used last. */
3427 uint32_t last_subpass_idx
;
3430 struct anv_render_pass
{
3431 uint32_t attachment_count
;
3432 uint32_t subpass_count
;
3433 /* An array of subpass_count+1 flushes, one per subpass boundary */
3434 enum anv_pipe_bits
* subpass_flushes
;
3435 struct anv_render_pass_attachment
* attachments
;
3436 struct anv_subpass subpasses
[0];
3439 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3441 struct anv_query_pool
{
3443 VkQueryPipelineStatisticFlags pipeline_statistics
;
3444 /** Stride between slots, in bytes */
3446 /** Number of slots in this query pool */
3451 int anv_get_instance_entrypoint_index(const char *name
);
3452 int anv_get_device_entrypoint_index(const char *name
);
3455 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3456 const struct anv_instance_extension_table
*instance
);
3459 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3460 const struct anv_instance_extension_table
*instance
,
3461 const struct anv_device_extension_table
*device
);
3463 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3466 void anv_dump_image_to_ppm(struct anv_device
*device
,
3467 struct anv_image
*image
, unsigned miplevel
,
3468 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3469 const char *filename
);
3471 enum anv_dump_action
{
3472 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3475 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3476 void anv_dump_finish(void);
3478 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3479 struct anv_framebuffer
*fb
);
3481 static inline uint32_t
3482 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3484 /* This function must be called from within a subpass. */
3485 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3487 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3489 /* The id of this subpass shouldn't exceed the number of subpasses in this
3490 * render pass minus 1.
3492 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3496 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3498 static inline struct __anv_type * \
3499 __anv_type ## _from_handle(__VkType _handle) \
3501 return (struct __anv_type *) _handle; \
3504 static inline __VkType \
3505 __anv_type ## _to_handle(struct __anv_type *_obj) \
3507 return (__VkType) _obj; \
3510 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3512 static inline struct __anv_type * \
3513 __anv_type ## _from_handle(__VkType _handle) \
3515 return (struct __anv_type *)(uintptr_t) _handle; \
3518 static inline __VkType \
3519 __anv_type ## _to_handle(struct __anv_type *_obj) \
3521 return (__VkType)(uintptr_t) _obj; \
3524 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3525 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3527 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3528 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3529 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3530 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3531 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3533 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3534 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3535 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3536 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3537 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3538 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3539 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3540 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3541 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3542 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3543 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3544 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3545 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3546 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3547 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3548 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3549 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3550 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3551 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3552 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3553 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3554 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3555 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3557 /* Gen-specific function declarations */
3559 # include "anv_genX.h"
3561 # define genX(x) gen7_##x
3562 # include "anv_genX.h"
3564 # define genX(x) gen75_##x
3565 # include "anv_genX.h"
3567 # define genX(x) gen8_##x
3568 # include "anv_genX.h"
3570 # define genX(x) gen9_##x
3571 # include "anv_genX.h"
3573 # define genX(x) gen10_##x
3574 # include "anv_genX.h"
3576 # define genX(x) gen11_##x
3577 # include "anv_genX.h"
3581 #endif /* ANV_PRIVATE_H */