2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/bitset.h"
53 #include "util/macros.h"
54 #include "util/hash_table.h"
55 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
74 struct anv_buffer_view
;
75 struct anv_image_view
;
78 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
131 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
132 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134 #define LOW_HEAP_SIZE \
135 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
136 #define DYNAMIC_STATE_POOL_SIZE \
137 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
138 #define BINDING_TABLE_POOL_SIZE \
139 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
140 #define SURFACE_STATE_POOL_SIZE \
141 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
142 #define INSTRUCTION_STATE_POOL_SIZE \
143 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
144 #define CLIENT_VISIBLE_HEAP_SIZE \
145 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147 /* Allowing different clear colors requires us to perform a depth resolve at
148 * the end of certain render passes. This is because while slow clears store
149 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
150 * See the PRMs for examples describing when additional resolves would be
151 * necessary. To enable fast clears without requiring extra resolves, we set
152 * the clear value to a globally-defined one. We could allow different values
153 * if the user doesn't expect coherent data during or after a render passes
154 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
155 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
156 * 1.0f seems to be the only value used. The only application that doesn't set
157 * this value does so through the usage of an seemingly uninitialized clear
160 #define ANV_HZ_FC_VAL 1.0f
163 #define MAX_XFB_BUFFERS 4
164 #define MAX_XFB_STREAMS 4
167 #define MAX_VIEWPORTS 16
168 #define MAX_SCISSORS 16
169 #define MAX_PUSH_CONSTANTS_SIZE 128
170 #define MAX_DYNAMIC_BUFFERS 16
171 #define MAX_IMAGES 64
172 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
173 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
174 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
178 * "The surface state model is used when a Binding Table Index (specified
179 * in the message descriptor) of less than 240 is specified. In this model,
180 * the Binding Table Index is used to index into the binding table, and the
181 * binding table entry contains a pointer to the SURFACE_STATE."
183 * Binding table values above 240 are used for various things in the hardware
184 * such as stateless, stateless with incoherent cache, SLM, and bindless.
186 #define MAX_BINDING_TABLE_SIZE 240
188 /* The kernel relocation API has a limitation of a 32-bit delta value
189 * applied to the address before it is written which, in spite of it being
190 * unsigned, is treated as signed . Because of the way that this maps to
191 * the Vulkan API, we cannot handle an offset into a buffer that does not
192 * fit into a signed 32 bits. The only mechanism we have for dealing with
193 * this at the moment is to limit all VkDeviceMemory objects to a maximum
194 * of 2GB each. The Vulkan spec allows us to do this:
196 * "Some platforms may have a limit on the maximum size of a single
197 * allocation. For example, certain systems may fail to create
198 * allocations with a size greater than or equal to 4GB. Such a limit is
199 * implementation-dependent, and if such a failure occurs then the error
200 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
202 * We don't use vk_error here because it's not an error so much as an
203 * indication to the application that the allocation is too large.
205 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
207 #define ANV_SVGS_VB_INDEX MAX_VBS
208 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
210 /* We reserve this MI ALU register for the purpose of handling predication.
211 * Other code which uses the MI ALU should leave it alone.
213 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
215 /* For gen12 we set the streamout buffers using 4 separate commands
216 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
217 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
218 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
219 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
220 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
221 * 3DSTATE_SO_BUFFER_INDEX_0.
223 #define SO_BUFFER_INDEX_0_CMD 0x60
224 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
226 static inline uint32_t
227 align_down_npot_u32(uint32_t v
, uint32_t a
)
232 static inline uint32_t
233 align_u32(uint32_t v
, uint32_t a
)
235 assert(a
!= 0 && a
== (a
& -a
));
236 return (v
+ a
- 1) & ~(a
- 1);
239 static inline uint64_t
240 align_u64(uint64_t v
, uint64_t a
)
242 assert(a
!= 0 && a
== (a
& -a
));
243 return (v
+ a
- 1) & ~(a
- 1);
246 static inline int32_t
247 align_i32(int32_t v
, int32_t a
)
249 assert(a
!= 0 && a
== (a
& -a
));
250 return (v
+ a
- 1) & ~(a
- 1);
253 /** Alignment must be a power of 2. */
255 anv_is_aligned(uintmax_t n
, uintmax_t a
)
257 assert(a
== (a
& -a
));
258 return (n
& (a
- 1)) == 0;
261 static inline uint32_t
262 anv_minify(uint32_t n
, uint32_t levels
)
264 if (unlikely(n
== 0))
267 return MAX2(n
>> levels
, 1);
271 anv_clamp_f(float f
, float min
, float max
)
284 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
286 if (*inout_mask
& clear_mask
) {
287 *inout_mask
&= ~clear_mask
;
294 static inline union isl_color_value
295 vk_to_isl_color(VkClearColorValue color
)
297 return (union isl_color_value
) {
307 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
309 uintptr_t mask
= (1ull << bits
) - 1;
311 return (void *) (ptr
& ~mask
);
314 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
316 uintptr_t value
= (uintptr_t) ptr
;
317 uintptr_t mask
= (1ull << bits
) - 1;
318 return value
| (mask
& flags
);
321 #define for_each_bit(b, dword) \
322 for (uint32_t __dword = (dword); \
323 (b) = __builtin_ffs(__dword) - 1, __dword; \
324 __dword &= ~(1 << (b)))
326 #define typed_memcpy(dest, src, count) ({ \
327 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
328 memcpy((dest), (src), (count) * sizeof(*(src))); \
331 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
332 * to be added here in order to utilize mapping in debug/error/perf macros.
334 #define REPORT_OBJECT_TYPE(o) \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), void*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
428 /* The void expression results in a compile-time error \
429 when assigning the result to something. */ \
430 (void)0)))))))))))))))))))))))))))))))
432 /* Whenever we generate an error, pass it through this function. Useful for
433 * debugging, where we can break on it. Only call at error site, not when
434 * propagating errors. Might be useful to plug in a stack trace here.
437 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
438 VkDebugReportObjectTypeEXT type
, VkResult error
,
439 const char *file
, int line
, const char *format
,
442 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
443 VkDebugReportObjectTypeEXT type
, VkResult error
,
444 const char *file
, int line
, const char *format
, ...)
445 anv_printflike(7, 8);
448 #define vk_error(error) __vk_errorf(NULL, NULL,\
449 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
450 error, __FILE__, __LINE__, NULL)
451 #define vk_errorv(instance, obj, error, format, args)\
452 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
453 __FILE__, __LINE__, format, args)
454 #define vk_errorf(instance, obj, error, format, ...)\
455 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
456 __FILE__, __LINE__, format, ## __VA_ARGS__)
458 #define vk_error(error) error
459 #define vk_errorf(instance, obj, error, format, ...) error
463 * Warn on ignored extension structs.
465 * The Vulkan spec requires us to ignore unsupported or unknown structs in
466 * a pNext chain. In debug mode, emitting warnings for ignored structs may
467 * help us discover structs that we should not have ignored.
470 * From the Vulkan 1.0.38 spec:
472 * Any component of the implementation (the loader, any enabled layers,
473 * and drivers) must skip over, without processing (other than reading the
474 * sType and pNext members) any chained structures with sType values not
475 * defined by extensions supported by that component.
477 #define anv_debug_ignored_stype(sType) \
478 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
480 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
481 VkDebugReportObjectTypeEXT type
, const char *file
,
482 int line
, const char *format
, ...)
483 anv_printflike(6, 7);
484 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
485 void anv_loge_v(const char *format
, va_list va
);
488 * Print a FINISHME message, including its source location.
490 #define anv_finishme(format, ...) \
492 static bool reported = false; \
494 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
501 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
503 #define anv_perf_warn(instance, obj, format, ...) \
505 static bool reported = false; \
506 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
507 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
508 format, ##__VA_ARGS__); \
513 /* A non-fatal assert. Useful for debugging. */
515 #define anv_assert(x) ({ \
516 if (unlikely(!(x))) \
517 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
520 #define anv_assert(x)
523 /* A multi-pointer allocator
525 * When copying data structures from the user (such as a render pass), it's
526 * common to need to allocate data for a bunch of different things. Instead
527 * of doing several allocations and having to handle all of the error checking
528 * that entails, it can be easier to do a single allocation. This struct
529 * helps facilitate that. The intended usage looks like this:
532 * anv_multialloc_add(&ma, &main_ptr, 1);
533 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
534 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
536 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
537 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
539 struct anv_multialloc
{
547 #define ANV_MULTIALLOC_INIT \
548 ((struct anv_multialloc) { 0, })
550 #define ANV_MULTIALLOC(_name) \
551 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
553 __attribute__((always_inline
))
555 _anv_multialloc_add(struct anv_multialloc
*ma
,
556 void **ptr
, size_t size
, size_t align
)
558 size_t offset
= align_u64(ma
->size
, align
);
559 ma
->size
= offset
+ size
;
560 ma
->align
= MAX2(ma
->align
, align
);
562 /* Store the offset in the pointer. */
563 *ptr
= (void *)(uintptr_t)offset
;
565 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
566 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
569 #define anv_multialloc_add_size(_ma, _ptr, _size) \
570 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
572 #define anv_multialloc_add(_ma, _ptr, _count) \
573 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
575 __attribute__((always_inline
))
577 anv_multialloc_alloc(struct anv_multialloc
*ma
,
578 const VkAllocationCallbacks
*alloc
,
579 VkSystemAllocationScope scope
)
581 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
585 /* Fill out each of the pointers with their final value.
587 * for (uint32_t i = 0; i < ma->ptr_count; i++)
588 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
590 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
591 * constant, GCC is incapable of figuring this out and unrolling the loop
592 * so we have to give it a little help.
594 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
595 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
596 if ((_i) < ma->ptr_count) \
597 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
598 _ANV_MULTIALLOC_UPDATE_POINTER(0);
599 _ANV_MULTIALLOC_UPDATE_POINTER(1);
600 _ANV_MULTIALLOC_UPDATE_POINTER(2);
601 _ANV_MULTIALLOC_UPDATE_POINTER(3);
602 _ANV_MULTIALLOC_UPDATE_POINTER(4);
603 _ANV_MULTIALLOC_UPDATE_POINTER(5);
604 _ANV_MULTIALLOC_UPDATE_POINTER(6);
605 _ANV_MULTIALLOC_UPDATE_POINTER(7);
606 #undef _ANV_MULTIALLOC_UPDATE_POINTER
611 __attribute__((always_inline
))
613 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
614 const VkAllocationCallbacks
*parent_alloc
,
615 const VkAllocationCallbacks
*alloc
,
616 VkSystemAllocationScope scope
)
618 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
626 /* Index into the current validation list. This is used by the
627 * validation list building alrogithm to track which buffers are already
628 * in the validation list so that we can ensure uniqueness.
632 /* Index for use with util_sparse_array_free_list */
635 /* Last known offset. This value is provided by the kernel when we
636 * execbuf and is used as the presumed offset for the next bunch of
643 /* Map for internally mapped BOs.
645 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
649 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
652 /** True if this BO may be shared with other processes */
655 /** True if this BO is a wrapper
657 * When set to true, none of the fields in this BO are meaningful except
658 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
659 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
660 * is set in the physical device.
664 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
665 bool has_fixed_address
:1;
667 /** True if this BO wraps a host pointer */
668 bool from_host_ptr
:1;
670 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
671 bool has_client_visible_address
:1;
674 static inline struct anv_bo
*
675 anv_bo_ref(struct anv_bo
*bo
)
677 p_atomic_inc(&bo
->refcount
);
681 static inline struct anv_bo
*
682 anv_bo_unwrap(struct anv_bo
*bo
)
684 while (bo
->is_wrapper
)
689 /* Represents a lock-free linked list of "free" things. This is used by
690 * both the block pool and the state pools. Unfortunately, in order to
691 * solve the ABA problem, we can't use a single uint32_t head.
693 union anv_free_list
{
697 /* A simple count that is incremented every time the head changes. */
700 /* Make sure it's aligned to 64 bits. This will make atomic operations
701 * faster on 32 bit platforms.
703 uint64_t u64
__attribute__ ((aligned (8)));
706 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
708 struct anv_block_state
{
714 /* Make sure it's aligned to 64 bits. This will make atomic operations
715 * faster on 32 bit platforms.
717 uint64_t u64
__attribute__ ((aligned (8)));
721 #define anv_block_pool_foreach_bo(bo, pool) \
722 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
723 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
726 #define ANV_MAX_BLOCK_POOL_BOS 20
728 struct anv_block_pool
{
729 struct anv_device
*device
;
732 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
733 * around the actual BO so that we grow the pool after the wrapper BO has
734 * been put in a relocation list. This is only used in the non-softpin
737 struct anv_bo wrapper_bo
;
739 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
745 /* The address where the start of the pool is pinned. The various bos that
746 * are created as the pool grows will have addresses in the range
747 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
749 uint64_t start_address
;
751 /* The offset from the start of the bo to the "center" of the block
752 * pool. Pointers to allocated blocks are given by
753 * bo.map + center_bo_offset + offsets.
755 uint32_t center_bo_offset
;
757 /* Current memory map of the block pool. This pointer may or may not
758 * point to the actual beginning of the block pool memory. If
759 * anv_block_pool_alloc_back has ever been called, then this pointer
760 * will point to the "center" position of the buffer and all offsets
761 * (negative or positive) given out by the block pool alloc functions
762 * will be valid relative to this pointer.
764 * In particular, map == bo.map + center_offset
766 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
767 * since it will handle the softpin case as well, where this points to NULL.
773 * Array of mmaps and gem handles owned by the block pool, reclaimed when
774 * the block pool is destroyed.
776 struct u_vector mmap_cleanups
;
778 struct anv_block_state state
;
780 struct anv_block_state back_state
;
783 /* Block pools are backed by a fixed-size 1GB memfd */
784 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
786 /* The center of the block pool is also the middle of the memfd. This may
787 * change in the future if we decide differently for some reason.
789 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
791 static inline uint32_t
792 anv_block_pool_size(struct anv_block_pool
*pool
)
794 return pool
->state
.end
+ pool
->back_state
.end
;
804 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
806 struct anv_fixed_size_state_pool
{
807 union anv_free_list free_list
;
808 struct anv_block_state block
;
811 #define ANV_MIN_STATE_SIZE_LOG2 6
812 #define ANV_MAX_STATE_SIZE_LOG2 21
814 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
816 struct anv_free_entry
{
818 struct anv_state state
;
821 struct anv_state_table
{
822 struct anv_device
*device
;
824 struct anv_free_entry
*map
;
826 struct anv_block_state state
;
827 struct u_vector cleanups
;
830 struct anv_state_pool
{
831 struct anv_block_pool block_pool
;
833 struct anv_state_table table
;
835 /* The size of blocks which will be allocated from the block pool */
838 /** Free list for "back" allocations */
839 union anv_free_list back_alloc_free_list
;
841 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
844 struct anv_state_stream_block
;
846 struct anv_state_stream
{
847 struct anv_state_pool
*state_pool
;
849 /* The size of blocks to allocate from the state pool */
852 /* Current block we're allocating from */
853 struct anv_state block
;
855 /* Offset into the current block at which to allocate the next state */
858 /* List of all blocks allocated from this pool */
859 struct anv_state_stream_block
*block_list
;
862 /* The block_pool functions exported for testing only. The block pool should
863 * only be used via a state pool (see below).
865 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
866 struct anv_device
*device
,
867 uint64_t start_address
,
868 uint32_t initial_size
);
869 void anv_block_pool_finish(struct anv_block_pool
*pool
);
870 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
871 uint32_t block_size
, uint32_t *padding
);
872 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
873 uint32_t block_size
);
874 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
876 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
877 struct anv_device
*device
,
878 uint64_t start_address
,
879 uint32_t block_size
);
880 void anv_state_pool_finish(struct anv_state_pool
*pool
);
881 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
882 uint32_t state_size
, uint32_t alignment
);
883 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
884 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
885 void anv_state_stream_init(struct anv_state_stream
*stream
,
886 struct anv_state_pool
*state_pool
,
887 uint32_t block_size
);
888 void anv_state_stream_finish(struct anv_state_stream
*stream
);
889 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
890 uint32_t size
, uint32_t alignment
);
892 VkResult
anv_state_table_init(struct anv_state_table
*table
,
893 struct anv_device
*device
,
894 uint32_t initial_entries
);
895 void anv_state_table_finish(struct anv_state_table
*table
);
896 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
898 void anv_free_list_push(union anv_free_list
*list
,
899 struct anv_state_table
*table
,
900 uint32_t idx
, uint32_t count
);
901 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
902 struct anv_state_table
*table
);
905 static inline struct anv_state
*
906 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
908 return &table
->map
[idx
].state
;
911 * Implements a pool of re-usable BOs. The interface is identical to that
912 * of block_pool except that each block is its own BO.
915 struct anv_device
*device
;
917 struct util_sparse_array_free_list free_list
[16];
920 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
921 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
922 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
923 struct anv_bo
**bo_out
);
924 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
926 struct anv_scratch_pool
{
927 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
928 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
931 void anv_scratch_pool_init(struct anv_device
*device
,
932 struct anv_scratch_pool
*pool
);
933 void anv_scratch_pool_finish(struct anv_device
*device
,
934 struct anv_scratch_pool
*pool
);
935 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
936 struct anv_scratch_pool
*pool
,
937 gl_shader_stage stage
,
938 unsigned per_thread_scratch
);
940 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
941 struct anv_bo_cache
{
942 struct util_sparse_array bo_map
;
943 pthread_mutex_t mutex
;
946 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
947 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
949 struct anv_memory_type
{
950 /* Standard bits passed on to the client */
951 VkMemoryPropertyFlags propertyFlags
;
955 struct anv_memory_heap
{
956 /* Standard bits passed on to the client */
958 VkMemoryHeapFlags flags
;
960 /* Driver-internal book-keeping */
964 struct anv_physical_device
{
965 VK_LOADER_DATA _loader_data
;
967 struct anv_instance
* instance
;
978 struct gen_device_info info
;
979 /** Amount of "GPU memory" we want to advertise
981 * Clearly, this value is bogus since Intel is a UMA architecture. On
982 * gen7 platforms, we are limited by GTT size unless we want to implement
983 * fine-grained tracking and GTT splitting. On Broadwell and above we are
984 * practically unlimited. However, we will never report more than 3/4 of
985 * the total system ram to try and avoid running out of RAM.
987 bool supports_48bit_addresses
;
988 struct brw_compiler
* compiler
;
989 struct isl_device isl_dev
;
990 struct gen_perf_config
* perf
;
991 int cmd_parser_version
;
994 bool has_exec_capture
;
997 bool has_syncobj_wait
;
998 bool has_context_priority
;
999 bool has_context_isolation
;
1000 bool has_mem_available
;
1004 bool always_use_bindless
;
1006 /** True if we can access buffers using A64 messages */
1007 bool has_a64_buffer_access
;
1008 /** True if we can use bindless access for images */
1009 bool has_bindless_images
;
1010 /** True if we can use bindless access for samplers */
1011 bool has_bindless_samplers
;
1013 bool always_flush_cache
;
1015 struct anv_device_extension_table supported_extensions
;
1016 struct anv_physical_device_dispatch_table dispatch
;
1019 uint32_t subslice_total
;
1022 uint32_t type_count
;
1023 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1024 uint32_t heap_count
;
1025 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1028 uint8_t driver_build_sha1
[20];
1029 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1030 uint8_t driver_uuid
[VK_UUID_SIZE
];
1031 uint8_t device_uuid
[VK_UUID_SIZE
];
1033 struct disk_cache
* disk_cache
;
1035 struct wsi_device wsi_device
;
1040 struct anv_app_info
{
1041 const char* app_name
;
1042 uint32_t app_version
;
1043 const char* engine_name
;
1044 uint32_t engine_version
;
1045 uint32_t api_version
;
1048 struct anv_instance
{
1049 VK_LOADER_DATA _loader_data
;
1051 VkAllocationCallbacks alloc
;
1053 struct anv_app_info app_info
;
1055 struct anv_instance_extension_table enabled_extensions
;
1056 struct anv_instance_dispatch_table dispatch
;
1057 struct anv_device_dispatch_table device_dispatch
;
1059 int physicalDeviceCount
;
1060 struct anv_physical_device physicalDevice
;
1062 bool pipeline_cache_enabled
;
1064 struct vk_debug_report_instance debug_report_callbacks
;
1066 struct driOptionCache dri_options
;
1067 struct driOptionCache available_dri_options
;
1070 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1071 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1073 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1074 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1077 struct anv_queue_submit
{
1078 struct anv_cmd_buffer
* cmd_buffer
;
1080 uint32_t fence_count
;
1081 uint32_t fence_array_length
;
1082 struct drm_i915_gem_exec_fence
* fences
;
1084 uint32_t temporary_semaphore_count
;
1085 uint32_t temporary_semaphore_array_length
;
1086 struct anv_semaphore_impl
* temporary_semaphores
;
1088 /* Semaphores to be signaled with a SYNC_FD. */
1089 struct anv_semaphore
** sync_fd_semaphores
;
1090 uint32_t sync_fd_semaphore_count
;
1091 uint32_t sync_fd_semaphore_array_length
;
1093 /* Allocated only with non shareable timelines. */
1094 struct anv_timeline
** wait_timelines
;
1095 uint32_t wait_timeline_count
;
1096 uint32_t wait_timeline_array_length
;
1097 uint64_t * wait_timeline_values
;
1099 struct anv_timeline
** signal_timelines
;
1100 uint32_t signal_timeline_count
;
1101 uint32_t signal_timeline_array_length
;
1102 uint64_t * signal_timeline_values
;
1105 bool need_out_fence
;
1108 uint32_t fence_bo_count
;
1109 uint32_t fence_bo_array_length
;
1110 /* An array of struct anv_bo pointers with lower bit used as a flag to
1111 * signal we will wait on that BO (see anv_(un)pack_ptr).
1113 uintptr_t * fence_bos
;
1115 const VkAllocationCallbacks
* alloc
;
1116 VkSystemAllocationScope alloc_scope
;
1118 struct anv_bo
* simple_bo
;
1119 uint32_t simple_bo_size
;
1121 struct list_head link
;
1125 VK_LOADER_DATA _loader_data
;
1127 struct anv_device
* device
;
1130 * A list of struct anv_queue_submit to be submitted to i915.
1132 struct list_head queued_submits
;
1134 VkDeviceQueueCreateFlags flags
;
1137 struct anv_pipeline_cache
{
1138 struct anv_device
* device
;
1139 pthread_mutex_t mutex
;
1141 struct hash_table
* nir_cache
;
1143 struct hash_table
* cache
;
1146 struct nir_xfb_info
;
1147 struct anv_pipeline_bind_map
;
1149 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1150 struct anv_device
*device
,
1151 bool cache_enabled
);
1152 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1154 struct anv_shader_bin
*
1155 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1156 const void *key
, uint32_t key_size
);
1157 struct anv_shader_bin
*
1158 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1159 const void *key_data
, uint32_t key_size
,
1160 const void *kernel_data
, uint32_t kernel_size
,
1161 const void *constant_data
,
1162 uint32_t constant_data_size
,
1163 const struct brw_stage_prog_data
*prog_data
,
1164 uint32_t prog_data_size
,
1165 const struct brw_compile_stats
*stats
,
1167 const struct nir_xfb_info
*xfb_info
,
1168 const struct anv_pipeline_bind_map
*bind_map
);
1170 struct anv_shader_bin
*
1171 anv_device_search_for_kernel(struct anv_device
*device
,
1172 struct anv_pipeline_cache
*cache
,
1173 const void *key_data
, uint32_t key_size
,
1174 bool *user_cache_bit
);
1176 struct anv_shader_bin
*
1177 anv_device_upload_kernel(struct anv_device
*device
,
1178 struct anv_pipeline_cache
*cache
,
1179 const void *key_data
, uint32_t key_size
,
1180 const void *kernel_data
, uint32_t kernel_size
,
1181 const void *constant_data
,
1182 uint32_t constant_data_size
,
1183 const struct brw_stage_prog_data
*prog_data
,
1184 uint32_t prog_data_size
,
1185 const struct brw_compile_stats
*stats
,
1187 const struct nir_xfb_info
*xfb_info
,
1188 const struct anv_pipeline_bind_map
*bind_map
);
1191 struct nir_shader_compiler_options
;
1194 anv_device_search_for_nir(struct anv_device
*device
,
1195 struct anv_pipeline_cache
*cache
,
1196 const struct nir_shader_compiler_options
*nir_options
,
1197 unsigned char sha1_key
[20],
1201 anv_device_upload_nir(struct anv_device
*device
,
1202 struct anv_pipeline_cache
*cache
,
1203 const struct nir_shader
*nir
,
1204 unsigned char sha1_key
[20]);
1207 VK_LOADER_DATA _loader_data
;
1209 VkAllocationCallbacks alloc
;
1211 struct anv_instance
* instance
;
1212 uint32_t chipset_id
;
1214 struct gen_device_info info
;
1215 struct isl_device isl_dev
;
1218 bool can_chain_batches
;
1219 bool robust_buffer_access
;
1220 struct anv_device_extension_table enabled_extensions
;
1221 struct anv_device_dispatch_table dispatch
;
1223 pthread_mutex_t vma_mutex
;
1224 struct util_vma_heap vma_lo
;
1225 struct util_vma_heap vma_cva
;
1226 struct util_vma_heap vma_hi
;
1228 /** List of all anv_device_memory objects */
1229 struct list_head memory_objects
;
1231 struct anv_bo_pool batch_bo_pool
;
1233 struct anv_bo_cache bo_cache
;
1235 struct anv_state_pool dynamic_state_pool
;
1236 struct anv_state_pool instruction_state_pool
;
1237 struct anv_state_pool binding_table_pool
;
1238 struct anv_state_pool surface_state_pool
;
1240 struct anv_bo
* workaround_bo
;
1241 struct anv_bo
* trivial_batch_bo
;
1242 struct anv_bo
* hiz_clear_bo
;
1244 struct anv_pipeline_cache default_pipeline_cache
;
1245 struct blorp_context blorp
;
1247 struct anv_state border_colors
;
1249 struct anv_state slice_hash
;
1251 struct anv_queue queue
;
1253 struct anv_scratch_pool scratch_pool
;
1255 pthread_mutex_t mutex
;
1256 pthread_cond_t queue_submit
;
1259 struct gen_batch_decode_ctx decoder_ctx
;
1261 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1262 * the cmd_buffer's list.
1264 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1266 int perf_fd
; /* -1 if no opened */
1267 uint64_t perf_metric
; /* 0 if unset */
1269 struct gen_aux_map_context
*aux_map_ctx
;
1272 static inline struct anv_state_pool
*
1273 anv_binding_table_pool(struct anv_device
*device
)
1275 if (device
->instance
->physicalDevice
.use_softpin
)
1276 return &device
->binding_table_pool
;
1278 return &device
->surface_state_pool
;
1281 static inline struct anv_state
1282 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1283 if (device
->instance
->physicalDevice
.use_softpin
)
1284 return anv_state_pool_alloc(&device
->binding_table_pool
,
1285 device
->binding_table_pool
.block_size
, 0);
1287 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1291 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1292 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1295 static inline uint32_t
1296 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1298 if (bo
->is_external
)
1299 return device
->isl_dev
.mocs
.external
;
1301 return device
->isl_dev
.mocs
.internal
;
1304 void anv_device_init_blorp(struct anv_device
*device
);
1305 void anv_device_finish_blorp(struct anv_device
*device
);
1307 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1308 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1309 const char *file
, int line
,
1310 const char *msg
, ...)
1311 anv_printflike(4, 5);
1312 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1313 const char *file
, int line
,
1314 const char *msg
, ...)
1315 anv_printflike(4, 5);
1316 #define anv_device_set_lost(dev, ...) \
1317 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1318 #define anv_queue_set_lost(queue, ...) \
1319 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1322 anv_device_is_lost(struct anv_device
*device
)
1324 return unlikely(p_atomic_read(&device
->_lost
));
1327 VkResult
anv_device_query_status(struct anv_device
*device
);
1330 enum anv_bo_alloc_flags
{
1331 /** Specifies that the BO must have a 32-bit address
1333 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1335 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1337 /** Specifies that the BO may be shared externally */
1338 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1340 /** Specifies that the BO should be mapped */
1341 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1343 /** Specifies that the BO should be snooped so we get coherency */
1344 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1346 /** Specifies that the BO should be captured in error states */
1347 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1349 /** Specifies that the BO will have an address assigned by the caller
1351 * Such BOs do not exist in any VMA heap.
1353 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1355 /** Enables implicit synchronization on the BO
1357 * This is the opposite of EXEC_OBJECT_ASYNC.
1359 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1361 /** Enables implicit synchronization on the BO
1363 * This is equivalent to EXEC_OBJECT_WRITE.
1365 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1367 /** Has an address which is visible to the client */
1368 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1371 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1372 enum anv_bo_alloc_flags alloc_flags
,
1373 uint64_t explicit_address
,
1374 struct anv_bo
**bo
);
1375 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1376 void *host_ptr
, uint32_t size
,
1377 enum anv_bo_alloc_flags alloc_flags
,
1378 uint64_t client_address
,
1379 struct anv_bo
**bo_out
);
1380 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1381 enum anv_bo_alloc_flags alloc_flags
,
1382 uint64_t client_address
,
1383 struct anv_bo
**bo
);
1384 VkResult
anv_device_export_bo(struct anv_device
*device
,
1385 struct anv_bo
*bo
, int *fd_out
);
1386 void anv_device_release_bo(struct anv_device
*device
,
1389 static inline struct anv_bo
*
1390 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1392 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1395 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1396 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1399 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1400 void anv_queue_finish(struct anv_queue
*queue
);
1402 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1403 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1404 struct anv_batch
*batch
);
1406 uint64_t anv_gettime_ns(void);
1407 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1409 void* anv_gem_mmap(struct anv_device
*device
,
1410 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1411 void anv_gem_munmap(void *p
, uint64_t size
);
1412 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1413 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1414 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1415 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1416 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1417 int anv_gem_execbuffer(struct anv_device
*device
,
1418 struct drm_i915_gem_execbuffer2
*execbuf
);
1419 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1420 uint32_t stride
, uint32_t tiling
);
1421 int anv_gem_create_context(struct anv_device
*device
);
1422 bool anv_gem_has_context_priority(int fd
);
1423 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1424 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1426 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1428 int anv_gem_get_param(int fd
, uint32_t param
);
1429 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1430 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1431 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1432 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1433 uint32_t *active
, uint32_t *pending
);
1434 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1435 int anv_gem_reg_read(struct anv_device
*device
,
1436 uint32_t offset
, uint64_t *result
);
1437 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1438 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1439 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1440 uint32_t read_domains
, uint32_t write_domain
);
1441 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1442 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1443 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1444 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1445 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1446 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1448 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1449 uint32_t handle
, int fd
);
1450 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1451 bool anv_gem_supports_syncobj_wait(int fd
);
1452 int anv_gem_syncobj_wait(struct anv_device
*device
,
1453 uint32_t *handles
, uint32_t num_handles
,
1454 int64_t abs_timeout_ns
, bool wait_all
);
1456 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
,
1457 uint64_t client_address
);
1458 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1460 struct anv_reloc_list
{
1461 uint32_t num_relocs
;
1462 uint32_t array_length
;
1463 struct drm_i915_gem_relocation_entry
* relocs
;
1464 struct anv_bo
** reloc_bos
;
1469 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1470 const VkAllocationCallbacks
*alloc
);
1471 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1472 const VkAllocationCallbacks
*alloc
);
1474 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1475 const VkAllocationCallbacks
*alloc
,
1476 uint32_t offset
, struct anv_bo
*target_bo
,
1477 uint32_t delta
, uint64_t *address_u64_out
);
1479 struct anv_batch_bo
{
1480 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1481 struct list_head link
;
1485 /* Bytes actually consumed in this batch BO */
1488 struct anv_reloc_list relocs
;
1492 const VkAllocationCallbacks
* alloc
;
1498 struct anv_reloc_list
* relocs
;
1500 /* This callback is called (with the associated user data) in the event
1501 * that the batch runs out of space.
1503 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1507 * Current error status of the command buffer. Used to track inconsistent
1508 * or incomplete command buffer states that are the consequence of run-time
1509 * errors such as out of memory scenarios. We want to track this in the
1510 * batch because the command buffer object is not visible to some parts
1516 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1517 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1518 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1519 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1521 static inline VkResult
1522 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1524 assert(error
!= VK_SUCCESS
);
1525 if (batch
->status
== VK_SUCCESS
)
1526 batch
->status
= error
;
1527 return batch
->status
;
1531 anv_batch_has_error(struct anv_batch
*batch
)
1533 return batch
->status
!= VK_SUCCESS
;
1536 struct anv_address
{
1541 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1544 anv_address_is_null(struct anv_address addr
)
1546 return addr
.bo
== NULL
&& addr
.offset
== 0;
1549 static inline uint64_t
1550 anv_address_physical(struct anv_address addr
)
1552 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1553 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1555 return gen_canonical_address(addr
.offset
);
1558 static inline struct anv_address
1559 anv_address_add(struct anv_address addr
, uint64_t offset
)
1561 addr
.offset
+= offset
;
1566 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1568 unsigned reloc_size
= 0;
1569 if (device
->info
.gen
>= 8) {
1570 reloc_size
= sizeof(uint64_t);
1571 *(uint64_t *)p
= gen_canonical_address(v
);
1573 reloc_size
= sizeof(uint32_t);
1577 if (flush
&& !device
->info
.has_llc
)
1578 gen_flush_range(p
, reloc_size
);
1581 static inline uint64_t
1582 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1583 const struct anv_address address
, uint32_t delta
)
1585 if (address
.bo
== NULL
) {
1586 return address
.offset
+ delta
;
1588 assert(batch
->start
<= location
&& location
< batch
->end
);
1590 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1594 #define __gen_address_type struct anv_address
1595 #define __gen_user_data struct anv_batch
1596 #define __gen_combine_address _anv_combine_address
1598 /* Wrapper macros needed to work around preprocessor argument issues. In
1599 * particular, arguments don't get pre-evaluated if they are concatenated.
1600 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1601 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1602 * We can work around this easily enough with these helpers.
1604 #define __anv_cmd_length(cmd) cmd ## _length
1605 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1606 #define __anv_cmd_header(cmd) cmd ## _header
1607 #define __anv_cmd_pack(cmd) cmd ## _pack
1608 #define __anv_reg_num(reg) reg ## _num
1610 #define anv_pack_struct(dst, struc, ...) do { \
1611 struct struc __template = { \
1614 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1615 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1618 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1619 void *__dst = anv_batch_emit_dwords(batch, n); \
1621 struct cmd __template = { \
1622 __anv_cmd_header(cmd), \
1623 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1626 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1631 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1635 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1636 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1639 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1640 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1641 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1644 #define anv_batch_emit(batch, cmd, name) \
1645 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1646 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1647 __builtin_expect(_dst != NULL, 1); \
1648 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1649 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1653 struct anv_device_memory
{
1654 struct list_head link
;
1657 struct anv_memory_type
* type
;
1658 VkDeviceSize map_size
;
1661 /* If set, we are holding reference to AHardwareBuffer
1662 * which we must release when memory is freed.
1664 struct AHardwareBuffer
* ahw
;
1666 /* If set, this memory comes from a host pointer. */
1671 * Header for Vertex URB Entry (VUE)
1673 struct anv_vue_header
{
1675 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1676 uint32_t ViewportIndex
;
1680 /** Struct representing a sampled image descriptor
1682 * This descriptor layout is used for sampled images, bare sampler, and
1683 * combined image/sampler descriptors.
1685 struct anv_sampled_image_descriptor
{
1686 /** Bindless image handle
1688 * This is expected to already be shifted such that the 20-bit
1689 * SURFACE_STATE table index is in the top 20 bits.
1693 /** Bindless sampler handle
1695 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1696 * to the dynamic state base address.
1701 struct anv_texture_swizzle_descriptor
{
1704 * See also nir_intrinsic_channel_select_intel
1708 /** Unused padding to ensure the struct is a multiple of 64 bits */
1712 /** Struct representing a storage image descriptor */
1713 struct anv_storage_image_descriptor
{
1714 /** Bindless image handles
1716 * These are expected to already be shifted such that the 20-bit
1717 * SURFACE_STATE table index is in the top 20 bits.
1719 uint32_t read_write
;
1720 uint32_t write_only
;
1723 /** Struct representing a address/range descriptor
1725 * The fields of this struct correspond directly to the data layout of
1726 * nir_address_format_64bit_bounded_global addresses. The last field is the
1727 * offset in the NIR address so it must be zero so that when you load the
1728 * descriptor you get a pointer to the start of the range.
1730 struct anv_address_range_descriptor
{
1736 enum anv_descriptor_data
{
1737 /** The descriptor contains a BTI reference to a surface state */
1738 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1739 /** The descriptor contains a BTI reference to a sampler state */
1740 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1741 /** The descriptor contains an actual buffer view */
1742 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1743 /** The descriptor contains auxiliary image layout data */
1744 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1745 /** The descriptor contains auxiliary image layout data */
1746 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1747 /** anv_address_range_descriptor with a buffer address and range */
1748 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1749 /** Bindless surface handle */
1750 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1751 /** Storage image handles */
1752 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1753 /** Storage image handles */
1754 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1757 struct anv_descriptor_set_binding_layout
{
1759 /* The type of the descriptors in this binding */
1760 VkDescriptorType type
;
1763 /* Flags provided when this binding was created */
1764 VkDescriptorBindingFlagsEXT flags
;
1766 /* Bitfield representing the type of data this descriptor contains */
1767 enum anv_descriptor_data data
;
1769 /* Maximum number of YCbCr texture/sampler planes */
1770 uint8_t max_plane_count
;
1772 /* Number of array elements in this binding (or size in bytes for inline
1775 uint16_t array_size
;
1777 /* Index into the flattend descriptor set */
1778 uint16_t descriptor_index
;
1780 /* Index into the dynamic state array for a dynamic buffer */
1781 int16_t dynamic_offset_index
;
1783 /* Index into the descriptor set buffer views */
1784 int16_t buffer_view_index
;
1786 /* Offset into the descriptor buffer where this descriptor lives */
1787 uint32_t descriptor_offset
;
1789 /* Immutable samplers (or NULL if no immutable samplers) */
1790 struct anv_sampler
**immutable_samplers
;
1793 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1795 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1796 VkDescriptorType type
);
1798 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1799 const struct anv_descriptor_set_binding_layout
*binding
,
1802 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1803 const struct anv_descriptor_set_binding_layout
*binding
,
1806 struct anv_descriptor_set_layout
{
1807 /* Descriptor set layouts can be destroyed at almost any time */
1810 /* Number of bindings in this descriptor set */
1811 uint16_t binding_count
;
1813 /* Total size of the descriptor set with room for all array entries */
1816 /* Shader stages affected by this descriptor set */
1817 uint16_t shader_stages
;
1819 /* Number of buffer views in this descriptor set */
1820 uint16_t buffer_view_count
;
1822 /* Number of dynamic offsets used by this descriptor set */
1823 uint16_t dynamic_offset_count
;
1825 /* For each shader stage, which offsets apply to that stage */
1826 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1828 /* Size of the descriptor buffer for this descriptor set */
1829 uint32_t descriptor_buffer_size
;
1831 /* Bindings in this descriptor set */
1832 struct anv_descriptor_set_binding_layout binding
[0];
1836 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1838 assert(layout
&& layout
->ref_cnt
>= 1);
1839 p_atomic_inc(&layout
->ref_cnt
);
1843 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1844 struct anv_descriptor_set_layout
*layout
)
1846 assert(layout
&& layout
->ref_cnt
>= 1);
1847 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1848 vk_free(&device
->alloc
, layout
);
1851 struct anv_descriptor
{
1852 VkDescriptorType type
;
1856 VkImageLayout layout
;
1857 struct anv_image_view
*image_view
;
1858 struct anv_sampler
*sampler
;
1862 struct anv_buffer
*buffer
;
1867 struct anv_buffer_view
*buffer_view
;
1871 struct anv_descriptor_set
{
1872 struct anv_descriptor_pool
*pool
;
1873 struct anv_descriptor_set_layout
*layout
;
1876 /* State relative to anv_descriptor_pool::bo */
1877 struct anv_state desc_mem
;
1878 /* Surface state for the descriptor buffer */
1879 struct anv_state desc_surface_state
;
1881 uint32_t buffer_view_count
;
1882 struct anv_buffer_view
*buffer_views
;
1884 /* Link to descriptor pool's desc_sets list . */
1885 struct list_head pool_link
;
1887 struct anv_descriptor descriptors
[0];
1890 struct anv_buffer_view
{
1891 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1892 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1894 struct anv_address address
;
1896 struct anv_state surface_state
;
1897 struct anv_state storage_surface_state
;
1898 struct anv_state writeonly_storage_surface_state
;
1900 struct brw_image_param storage_image_param
;
1903 struct anv_push_descriptor_set
{
1904 struct anv_descriptor_set set
;
1906 /* Put this field right behind anv_descriptor_set so it fills up the
1907 * descriptors[0] field. */
1908 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1910 /** True if the descriptor set buffer has been referenced by a draw or
1913 bool set_used_on_gpu
;
1915 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1918 struct anv_descriptor_pool
{
1924 struct util_vma_heap bo_heap
;
1926 struct anv_state_stream surface_state_stream
;
1927 void *surface_state_free_list
;
1929 struct list_head desc_sets
;
1934 enum anv_descriptor_template_entry_type
{
1935 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1936 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1937 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1940 struct anv_descriptor_template_entry
{
1941 /* The type of descriptor in this entry */
1942 VkDescriptorType type
;
1944 /* Binding in the descriptor set */
1947 /* Offset at which to write into the descriptor set binding */
1948 uint32_t array_element
;
1950 /* Number of elements to write into the descriptor set binding */
1951 uint32_t array_count
;
1953 /* Offset into the user provided data */
1956 /* Stride between elements into the user provided data */
1960 struct anv_descriptor_update_template
{
1961 VkPipelineBindPoint bind_point
;
1963 /* The descriptor set this template corresponds to. This value is only
1964 * valid if the template was created with the templateType
1965 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1969 /* Number of entries in this template */
1970 uint32_t entry_count
;
1972 /* Entries of the template */
1973 struct anv_descriptor_template_entry entries
[0];
1977 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1980 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1981 struct anv_descriptor_set
*set
,
1982 const VkDescriptorImageInfo
* const info
,
1983 VkDescriptorType type
,
1988 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1989 struct anv_descriptor_set
*set
,
1990 VkDescriptorType type
,
1991 struct anv_buffer_view
*buffer_view
,
1996 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1997 struct anv_descriptor_set
*set
,
1998 struct anv_state_stream
*alloc_stream
,
1999 VkDescriptorType type
,
2000 struct anv_buffer
*buffer
,
2003 VkDeviceSize offset
,
2004 VkDeviceSize range
);
2006 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2007 struct anv_descriptor_set
*set
,
2014 anv_descriptor_set_write_template(struct anv_device
*device
,
2015 struct anv_descriptor_set
*set
,
2016 struct anv_state_stream
*alloc_stream
,
2017 const struct anv_descriptor_update_template
*template,
2021 anv_descriptor_set_create(struct anv_device
*device
,
2022 struct anv_descriptor_pool
*pool
,
2023 struct anv_descriptor_set_layout
*layout
,
2024 struct anv_descriptor_set
**out_set
);
2027 anv_descriptor_set_destroy(struct anv_device
*device
,
2028 struct anv_descriptor_pool
*pool
,
2029 struct anv_descriptor_set
*set
);
2031 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2032 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2033 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2034 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2035 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2036 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2038 struct anv_pipeline_binding
{
2039 /** Index in the descriptor set
2041 * This is a flattened index; the descriptor set layout is already taken
2046 /** The descriptor set this surface corresponds to.
2048 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2049 * binding is not a normal descriptor set but something else.
2054 /** Plane in the binding index for images */
2057 /** Input attachment index (relative to the subpass) */
2058 uint8_t input_attachment_index
;
2060 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2061 uint8_t dynamic_offset_index
;
2064 /** For a storage image, whether it is write-only */
2067 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2068 * assuming POD zero-initialization.
2073 struct anv_push_range
{
2074 /** Index in the descriptor set */
2077 /** Descriptor set index */
2080 /** Dynamic offset index (for dynamic UBOs) */
2081 uint8_t dynamic_offset_index
;
2083 /** Start offset in units of 32B */
2086 /** Range in units of 32B */
2090 struct anv_pipeline_layout
{
2092 struct anv_descriptor_set_layout
*layout
;
2093 uint32_t dynamic_offset_start
;
2098 unsigned char sha1
[20];
2102 struct anv_device
* device
;
2105 VkBufferUsageFlags usage
;
2107 /* Set when bound */
2108 struct anv_address address
;
2111 static inline uint64_t
2112 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2114 assert(offset
<= buffer
->size
);
2115 if (range
== VK_WHOLE_SIZE
) {
2116 return buffer
->size
- offset
;
2118 assert(range
+ offset
>= range
);
2119 assert(range
+ offset
<= buffer
->size
);
2124 enum anv_cmd_dirty_bits
{
2125 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2126 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2127 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2128 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2129 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2130 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2131 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2132 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2133 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2134 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2135 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2136 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2137 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2138 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2140 typedef uint32_t anv_cmd_dirty_mask_t
;
2142 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2143 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2144 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2145 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2146 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2147 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2148 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2149 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2150 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2151 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2152 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2154 static inline enum anv_cmd_dirty_bits
2155 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2158 case VK_DYNAMIC_STATE_VIEWPORT
:
2159 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2160 case VK_DYNAMIC_STATE_SCISSOR
:
2161 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2162 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2163 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2164 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2165 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2166 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2167 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2168 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2169 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2170 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2171 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2172 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2173 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2174 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2175 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2176 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2177 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2179 assert(!"Unsupported dynamic state");
2185 enum anv_pipe_bits
{
2186 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2187 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2188 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2189 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2190 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2191 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2192 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2193 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2194 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2195 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2196 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2197 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2199 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2200 * a flush has happened but not a CS stall. The next time we do any sort
2201 * of invalidation we need to insert a CS stall at that time. Otherwise,
2202 * we would have to CS stall on every flush which could be bad.
2204 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2206 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2207 * target operations related to transfer commands with VkBuffer as
2208 * destination are ongoing. Some operations like copies on the command
2209 * streamer might need to be aware of this to trigger the appropriate stall
2210 * before they can proceed with the copy.
2212 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2215 #define ANV_PIPE_FLUSH_BITS ( \
2216 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2217 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2218 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2219 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2221 #define ANV_PIPE_STALL_BITS ( \
2222 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2223 ANV_PIPE_DEPTH_STALL_BIT | \
2224 ANV_PIPE_CS_STALL_BIT)
2226 #define ANV_PIPE_INVALIDATE_BITS ( \
2227 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2228 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2229 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2230 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2231 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2232 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2234 static inline enum anv_pipe_bits
2235 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2237 enum anv_pipe_bits pipe_bits
= 0;
2240 for_each_bit(b
, flags
) {
2241 switch ((VkAccessFlagBits
)(1 << b
)) {
2242 case VK_ACCESS_SHADER_WRITE_BIT
:
2243 /* We're transitioning a buffer that was previously used as write
2244 * destination through the data port. To make its content available
2245 * to future operations, flush the data cache.
2247 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2249 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2250 /* We're transitioning a buffer that was previously used as render
2251 * target. To make its content available to future operations, flush
2252 * the render target cache.
2254 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2256 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2257 /* We're transitioning a buffer that was previously used as depth
2258 * buffer. To make its content available to future operations, flush
2261 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2263 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2264 /* We're transitioning a buffer that was previously used as a
2265 * transfer write destination. Generic write operations include color
2266 * & depth operations as well as buffer operations like :
2267 * - vkCmdClearColorImage()
2268 * - vkCmdClearDepthStencilImage()
2269 * - vkCmdBlitImage()
2270 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2272 * Most of these operations are implemented using Blorp which writes
2273 * through the render target, so flush that cache to make it visible
2274 * to future operations. And for depth related operations we also
2275 * need to flush the depth cache.
2277 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2278 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2280 case VK_ACCESS_MEMORY_WRITE_BIT
:
2281 /* We're transitioning a buffer for generic write operations. Flush
2284 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2287 break; /* Nothing to do */
2294 static inline enum anv_pipe_bits
2295 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2297 enum anv_pipe_bits pipe_bits
= 0;
2300 for_each_bit(b
, flags
) {
2301 switch ((VkAccessFlagBits
)(1 << b
)) {
2302 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2303 /* Indirect draw commands take a buffer as input that we're going to
2304 * read from the command streamer to load some of the HW registers
2305 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2306 * command streamer stall so that all the cache flushes have
2307 * completed before the command streamer loads from memory.
2309 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2310 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2311 * through a vertex buffer, so invalidate that cache.
2313 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2314 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2315 * UBO from the buffer, so we need to invalidate constant cache.
2317 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2319 case VK_ACCESS_INDEX_READ_BIT
:
2320 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2321 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2322 * commands, so we invalidate the VF cache to make sure there is no
2323 * stale data when we start rendering.
2325 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2327 case VK_ACCESS_UNIFORM_READ_BIT
:
2328 /* We transitioning a buffer to be used as uniform data. Because
2329 * uniform is accessed through the data port & sampler, we need to
2330 * invalidate the texture cache (sampler) & constant cache (data
2331 * port) to avoid stale data.
2333 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2334 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2336 case VK_ACCESS_SHADER_READ_BIT
:
2337 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2338 case VK_ACCESS_TRANSFER_READ_BIT
:
2339 /* Transitioning a buffer to be read through the sampler, so
2340 * invalidate the texture cache, we don't want any stale data.
2342 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2344 case VK_ACCESS_MEMORY_READ_BIT
:
2345 /* Transitioning a buffer for generic read, invalidate all the
2348 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2350 case VK_ACCESS_MEMORY_WRITE_BIT
:
2351 /* Generic write, make sure all previously written things land in
2354 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2356 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2357 /* Transitioning a buffer for conditional rendering. We'll load the
2358 * content of this buffer into HW registers using the command
2359 * streamer, so we need to stall the command streamer to make sure
2360 * any in-flight flush operations have completed.
2362 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2365 break; /* Nothing to do */
2372 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2373 VK_IMAGE_ASPECT_COLOR_BIT | \
2374 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2375 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2376 VK_IMAGE_ASPECT_PLANE_2_BIT)
2377 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2378 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2379 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2380 VK_IMAGE_ASPECT_PLANE_2_BIT)
2382 struct anv_vertex_binding
{
2383 struct anv_buffer
* buffer
;
2384 VkDeviceSize offset
;
2387 struct anv_xfb_binding
{
2388 struct anv_buffer
* buffer
;
2389 VkDeviceSize offset
;
2393 struct anv_push_constants
{
2394 /** Push constant data provided by the client through vkPushConstants */
2395 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2397 /** Dynamic offsets for dynamic UBOs and SSBOs */
2398 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2401 /** Base workgroup ID
2403 * Used for vkCmdDispatchBase.
2405 uint32_t base_work_group_id
[3];
2409 * This is never set by software but is implicitly filled out when
2410 * uploading the push constants for compute shaders.
2412 uint32_t subgroup_id
;
2414 /** Pad out to a multiple of 32 bytes */
2419 struct anv_dynamic_state
{
2422 VkViewport viewports
[MAX_VIEWPORTS
];
2427 VkRect2D scissors
[MAX_SCISSORS
];
2438 float blend_constants
[4];
2448 } stencil_compare_mask
;
2453 } stencil_write_mask
;
2458 } stencil_reference
;
2466 extern const struct anv_dynamic_state default_dynamic_state
;
2468 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2469 const struct anv_dynamic_state
*src
,
2470 uint32_t copy_mask
);
2472 struct anv_surface_state
{
2473 struct anv_state state
;
2474 /** Address of the surface referred to by this state
2476 * This address is relative to the start of the BO.
2478 struct anv_address address
;
2479 /* Address of the aux surface, if any
2481 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2483 * With the exception of gen8, the bottom 12 bits of this address' offset
2484 * include extra aux information.
2486 struct anv_address aux_address
;
2487 /* Address of the clear color, if any
2489 * This address is relative to the start of the BO.
2491 struct anv_address clear_address
;
2495 * Attachment state when recording a renderpass instance.
2497 * The clear value is valid only if there exists a pending clear.
2499 struct anv_attachment_state
{
2500 enum isl_aux_usage aux_usage
;
2501 enum isl_aux_usage input_aux_usage
;
2502 struct anv_surface_state color
;
2503 struct anv_surface_state input
;
2505 VkImageLayout current_layout
;
2506 VkImageLayout current_stencil_layout
;
2507 VkImageAspectFlags pending_clear_aspects
;
2508 VkImageAspectFlags pending_load_aspects
;
2510 VkClearValue clear_value
;
2511 bool clear_color_is_zero_one
;
2512 bool clear_color_is_zero
;
2514 /* When multiview is active, attachments with a renderpass clear
2515 * operation have their respective layers cleared on the first
2516 * subpass that uses them, and only in that subpass. We keep track
2517 * of this using a bitfield to indicate which layers of an attachment
2518 * have not been cleared yet when multiview is active.
2520 uint32_t pending_clear_views
;
2521 struct anv_image_view
* image_view
;
2524 /** State tracking for vertex buffer flushes
2526 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2527 * addresses. If you happen to have two vertex buffers which get placed
2528 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2529 * collisions. In order to solve this problem, we track vertex address ranges
2530 * which are live in the cache and invalidate the cache if one ever exceeds 32
2533 struct anv_vb_cache_range
{
2534 /* Virtual address at which the live vertex buffer cache range starts for
2535 * this vertex buffer index.
2539 /* Virtual address of the byte after where vertex buffer cache range ends.
2540 * This is exclusive such that end - start is the size of the range.
2545 /** State tracking for particular pipeline bind point
2547 * This struct is the base struct for anv_cmd_graphics_state and
2548 * anv_cmd_compute_state. These are used to track state which is bound to a
2549 * particular type of pipeline. Generic state that applies per-stage such as
2550 * binding table offsets and push constants is tracked generically with a
2551 * per-stage array in anv_cmd_state.
2553 struct anv_cmd_pipeline_state
{
2554 struct anv_pipeline
*pipeline
;
2556 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2557 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2560 /** State tracking for graphics pipeline
2562 * This has anv_cmd_pipeline_state as a base struct to track things which get
2563 * bound to a graphics pipeline. Along with general pipeline bind point state
2564 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2565 * state which is graphics-specific.
2567 struct anv_cmd_graphics_state
{
2568 struct anv_cmd_pipeline_state base
;
2570 anv_cmd_dirty_mask_t dirty
;
2573 struct anv_vb_cache_range ib_bound_range
;
2574 struct anv_vb_cache_range ib_dirty_range
;
2575 struct anv_vb_cache_range vb_bound_ranges
[33];
2576 struct anv_vb_cache_range vb_dirty_ranges
[33];
2578 struct anv_dynamic_state dynamic
;
2581 struct anv_buffer
*index_buffer
;
2582 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2583 uint32_t index_offset
;
2587 /** State tracking for compute pipeline
2589 * This has anv_cmd_pipeline_state as a base struct to track things which get
2590 * bound to a compute pipeline. Along with general pipeline bind point state
2591 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2592 * state which is compute-specific.
2594 struct anv_cmd_compute_state
{
2595 struct anv_cmd_pipeline_state base
;
2597 bool pipeline_dirty
;
2599 struct anv_address num_workgroups
;
2602 /** State required while building cmd buffer */
2603 struct anv_cmd_state
{
2604 /* PIPELINE_SELECT.PipelineSelection */
2605 uint32_t current_pipeline
;
2606 const struct gen_l3_config
* current_l3_config
;
2607 uint32_t last_aux_map_state
;
2609 struct anv_cmd_graphics_state gfx
;
2610 struct anv_cmd_compute_state compute
;
2612 enum anv_pipe_bits pending_pipe_bits
;
2613 VkShaderStageFlags descriptors_dirty
;
2614 VkShaderStageFlags push_constants_dirty
;
2616 struct anv_framebuffer
* framebuffer
;
2617 struct anv_render_pass
* pass
;
2618 struct anv_subpass
* subpass
;
2619 VkRect2D render_area
;
2620 uint32_t restart_index
;
2621 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2623 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2624 VkShaderStageFlags push_constant_stages
;
2625 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2626 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2627 struct anv_state samplers
[MESA_SHADER_STAGES
];
2629 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2630 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2631 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2634 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2635 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2636 * and before invoking the secondary in ExecuteCommands.
2638 bool pma_fix_enabled
;
2641 * Whether or not we know for certain that HiZ is enabled for the current
2642 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2643 * enabled or not, this will be false.
2647 bool conditional_render_enabled
;
2650 * Last rendering scale argument provided to
2651 * genX(cmd_buffer_emit_hashing_mode)().
2653 unsigned current_hash_scale
;
2656 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2657 * valid only when recording a render pass instance.
2659 struct anv_attachment_state
* attachments
;
2662 * Surface states for color render targets. These are stored in a single
2663 * flat array. For depth-stencil attachments, the surface state is simply
2666 struct anv_state render_pass_states
;
2669 * A null surface state of the right size to match the framebuffer. This
2670 * is one of the states in render_pass_states.
2672 struct anv_state null_surface_state
;
2675 struct anv_cmd_pool
{
2676 VkAllocationCallbacks alloc
;
2677 struct list_head cmd_buffers
;
2680 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2682 enum anv_cmd_buffer_exec_mode
{
2683 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2684 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2685 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2686 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2687 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2690 struct anv_cmd_buffer
{
2691 VK_LOADER_DATA _loader_data
;
2693 struct anv_device
* device
;
2695 struct anv_cmd_pool
* pool
;
2696 struct list_head pool_link
;
2698 struct anv_batch batch
;
2700 /* Fields required for the actual chain of anv_batch_bo's.
2702 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2704 struct list_head batch_bos
;
2705 enum anv_cmd_buffer_exec_mode exec_mode
;
2707 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2708 * referenced by this command buffer
2710 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2712 struct u_vector seen_bbos
;
2714 /* A vector of int32_t's for every block of binding tables.
2716 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2718 struct u_vector bt_block_states
;
2719 struct anv_state bt_next
;
2721 struct anv_reloc_list surface_relocs
;
2722 /** Last seen surface state block pool center bo offset */
2723 uint32_t last_ss_pool_center
;
2725 /* Serial for tracking buffer completion */
2728 /* Stream objects for storing temporary data */
2729 struct anv_state_stream surface_state_stream
;
2730 struct anv_state_stream dynamic_state_stream
;
2732 VkCommandBufferUsageFlags usage_flags
;
2733 VkCommandBufferLevel level
;
2735 struct anv_cmd_state state
;
2737 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2738 uint64_t intel_perf_marker
;
2741 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2742 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2743 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2744 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2745 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2746 struct anv_cmd_buffer
*secondary
);
2747 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2748 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2749 struct anv_cmd_buffer
*cmd_buffer
,
2750 const VkSemaphore
*in_semaphores
,
2751 const uint64_t *in_wait_values
,
2752 uint32_t num_in_semaphores
,
2753 const VkSemaphore
*out_semaphores
,
2754 const uint64_t *out_signal_values
,
2755 uint32_t num_out_semaphores
,
2758 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2760 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2761 const void *data
, uint32_t size
, uint32_t alignment
);
2762 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2763 uint32_t *a
, uint32_t *b
,
2764 uint32_t dwords
, uint32_t alignment
);
2767 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2769 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2770 uint32_t entries
, uint32_t *state_offset
);
2772 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2774 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2775 uint32_t size
, uint32_t alignment
);
2778 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2780 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2781 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2782 bool depth_clamp_enable
);
2783 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2785 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2786 struct anv_render_pass
*pass
,
2787 struct anv_framebuffer
*framebuffer
,
2788 const VkClearValue
*clear_values
);
2790 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2793 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2794 gl_shader_stage stage
);
2796 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2798 const struct anv_image_view
*
2799 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2802 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2803 uint32_t num_entries
,
2804 uint32_t *state_offset
,
2805 struct anv_state
*bt_state
);
2807 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2809 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2811 enum anv_fence_type
{
2812 ANV_FENCE_TYPE_NONE
= 0,
2814 ANV_FENCE_TYPE_WSI_BO
,
2815 ANV_FENCE_TYPE_SYNCOBJ
,
2819 enum anv_bo_fence_state
{
2820 /** Indicates that this is a new (or newly reset fence) */
2821 ANV_BO_FENCE_STATE_RESET
,
2823 /** Indicates that this fence has been submitted to the GPU but is still
2824 * (as far as we know) in use by the GPU.
2826 ANV_BO_FENCE_STATE_SUBMITTED
,
2828 ANV_BO_FENCE_STATE_SIGNALED
,
2831 struct anv_fence_impl
{
2832 enum anv_fence_type type
;
2835 /** Fence implementation for BO fences
2837 * These fences use a BO and a set of CPU-tracked state flags. The BO
2838 * is added to the object list of the last execbuf call in a QueueSubmit
2839 * and is marked EXEC_WRITE. The state flags track when the BO has been
2840 * submitted to the kernel. We need to do this because Vulkan lets you
2841 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2842 * will say it's idle in this case.
2846 enum anv_bo_fence_state state
;
2849 /** DRM syncobj handle for syncobj-based fences */
2853 struct wsi_fence
*fence_wsi
;
2858 /* Permanent fence state. Every fence has some form of permanent state
2859 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2860 * cross-process fences) or it could just be a dummy for use internally.
2862 struct anv_fence_impl permanent
;
2864 /* Temporary fence state. A fence *may* have temporary state. That state
2865 * is added to the fence by an import operation and is reset back to
2866 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2867 * state cannot be signaled because the fence must already be signaled
2868 * before the temporary state can be exported from the fence in the other
2869 * process and imported here.
2871 struct anv_fence_impl temporary
;
2874 void anv_fence_reset_temporary(struct anv_device
*device
,
2875 struct anv_fence
*fence
);
2879 struct anv_state state
;
2882 enum anv_semaphore_type
{
2883 ANV_SEMAPHORE_TYPE_NONE
= 0,
2884 ANV_SEMAPHORE_TYPE_DUMMY
,
2885 ANV_SEMAPHORE_TYPE_BO
,
2886 ANV_SEMAPHORE_TYPE_WSI_BO
,
2887 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2888 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2889 ANV_SEMAPHORE_TYPE_TIMELINE
,
2892 struct anv_timeline_point
{
2893 struct list_head link
;
2897 /* Number of waiter on this point, when > 0 the point should not be garbage
2902 /* BO used for synchronization. */
2906 struct anv_timeline
{
2907 pthread_mutex_t mutex
;
2908 pthread_cond_t cond
;
2910 uint64_t highest_past
;
2911 uint64_t highest_pending
;
2913 struct list_head points
;
2914 struct list_head free_points
;
2917 struct anv_semaphore_impl
{
2918 enum anv_semaphore_type type
;
2921 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
2922 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
2923 * object list on any execbuf2 calls for which this semaphore is used as
2924 * a wait or signal fence. When used as a signal fence or when type ==
2925 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
2929 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2930 * If the semaphore is in the unsignaled state due to either just being
2931 * created or because it has been used for a wait, fd will be -1.
2935 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2936 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2937 * import so we don't need to bother with a userspace cache.
2941 /* Non shareable timeline semaphore
2943 * Used when kernel don't have support for timeline semaphores.
2945 struct anv_timeline timeline
;
2949 struct anv_semaphore
{
2952 /* Permanent semaphore state. Every semaphore has some form of permanent
2953 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2954 * (for cross-process semaphores0 or it could just be a dummy for use
2957 struct anv_semaphore_impl permanent
;
2959 /* Temporary semaphore state. A semaphore *may* have temporary state.
2960 * That state is added to the semaphore by an import operation and is reset
2961 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2962 * semaphore with temporary state cannot be signaled because the semaphore
2963 * must already be signaled before the temporary state can be exported from
2964 * the semaphore in the other process and imported here.
2966 struct anv_semaphore_impl temporary
;
2969 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2970 struct anv_semaphore
*semaphore
);
2972 struct anv_shader_module
{
2973 unsigned char sha1
[20];
2978 static inline gl_shader_stage
2979 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2981 assert(__builtin_popcount(vk_stage
) == 1);
2982 return ffs(vk_stage
) - 1;
2985 static inline VkShaderStageFlagBits
2986 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2988 return (1 << mesa_stage
);
2991 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2993 #define anv_foreach_stage(stage, stage_bits) \
2994 for (gl_shader_stage stage, \
2995 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2996 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2997 __tmp &= ~(1 << (stage)))
2999 struct anv_pipeline_bind_map
{
3000 unsigned char surface_sha1
[20];
3001 unsigned char sampler_sha1
[20];
3002 unsigned char push_sha1
[20];
3004 uint32_t surface_count
;
3005 uint32_t sampler_count
;
3007 struct anv_pipeline_binding
* surface_to_descriptor
;
3008 struct anv_pipeline_binding
* sampler_to_descriptor
;
3010 struct anv_push_range push_ranges
[4];
3013 struct anv_shader_bin_key
{
3018 struct anv_shader_bin
{
3021 const struct anv_shader_bin_key
*key
;
3023 struct anv_state kernel
;
3024 uint32_t kernel_size
;
3026 struct anv_state constant_data
;
3027 uint32_t constant_data_size
;
3029 const struct brw_stage_prog_data
*prog_data
;
3030 uint32_t prog_data_size
;
3032 struct brw_compile_stats stats
[3];
3035 struct nir_xfb_info
*xfb_info
;
3037 struct anv_pipeline_bind_map bind_map
;
3040 struct anv_shader_bin
*
3041 anv_shader_bin_create(struct anv_device
*device
,
3042 const void *key
, uint32_t key_size
,
3043 const void *kernel
, uint32_t kernel_size
,
3044 const void *constant_data
, uint32_t constant_data_size
,
3045 const struct brw_stage_prog_data
*prog_data
,
3046 uint32_t prog_data_size
, const void *prog_data_param
,
3047 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3048 const struct nir_xfb_info
*xfb_info
,
3049 const struct anv_pipeline_bind_map
*bind_map
);
3052 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3055 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3057 assert(shader
&& shader
->ref_cnt
>= 1);
3058 p_atomic_inc(&shader
->ref_cnt
);
3062 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3064 assert(shader
&& shader
->ref_cnt
>= 1);
3065 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3066 anv_shader_bin_destroy(device
, shader
);
3069 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
3070 #define MAX_PIPELINE_EXECUTABLES 7
3072 struct anv_pipeline_executable
{
3073 gl_shader_stage stage
;
3075 struct brw_compile_stats stats
;
3081 struct anv_pipeline
{
3082 struct anv_device
* device
;
3083 struct anv_batch batch
;
3084 uint32_t batch_data
[512];
3085 struct anv_reloc_list batch_relocs
;
3086 anv_cmd_dirty_mask_t dynamic_state_mask
;
3087 struct anv_dynamic_state dynamic_state
;
3091 VkPipelineCreateFlags flags
;
3092 struct anv_subpass
* subpass
;
3094 bool needs_data_cache
;
3096 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3098 uint32_t num_executables
;
3099 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
3102 const struct gen_l3_config
* l3_config
;
3103 uint32_t total_size
;
3106 VkShaderStageFlags active_stages
;
3107 struct anv_state blend_state
;
3110 struct anv_pipeline_vertex_binding
{
3113 uint32_t instance_divisor
;
3118 bool primitive_restart
;
3121 uint32_t cs_right_mask
;
3124 bool depth_test_enable
;
3125 bool writes_stencil
;
3126 bool stencil_test_enable
;
3127 bool depth_clamp_enable
;
3128 bool depth_clip_enable
;
3129 bool sample_shading_enable
;
3131 bool depth_bounds_test_enable
;
3135 uint32_t depth_stencil_state
[3];
3141 uint32_t wm_depth_stencil
[3];
3145 uint32_t wm_depth_stencil
[4];
3148 uint32_t interface_descriptor_data
[8];
3152 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3153 gl_shader_stage stage
)
3155 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3158 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3159 static inline const struct brw_##prefix##_prog_data * \
3160 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3162 if (anv_pipeline_has_stage(pipeline, stage)) { \
3163 return (const struct brw_##prefix##_prog_data *) \
3164 pipeline->shaders[stage]->prog_data; \
3170 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3171 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3172 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3173 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3174 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3175 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3177 static inline const struct brw_vue_prog_data
*
3178 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3180 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3181 return &get_gs_prog_data(pipeline
)->base
;
3182 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3183 return &get_tes_prog_data(pipeline
)->base
;
3185 return &get_vs_prog_data(pipeline
)->base
;
3189 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3190 struct anv_pipeline_cache
*cache
,
3191 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3192 const VkAllocationCallbacks
*alloc
);
3195 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3196 struct anv_pipeline_cache
*cache
,
3197 const VkComputePipelineCreateInfo
*info
,
3198 const struct anv_shader_module
*module
,
3199 const char *entrypoint
,
3200 const VkSpecializationInfo
*spec_info
);
3202 struct anv_format_plane
{
3203 enum isl_format isl_format
:16;
3204 struct isl_swizzle swizzle
;
3206 /* Whether this plane contains chroma channels */
3209 /* For downscaling of YUV planes */
3210 uint8_t denominator_scales
[2];
3212 /* How to map sampled ycbcr planes to a single 4 component element. */
3213 struct isl_swizzle ycbcr_swizzle
;
3215 /* What aspect is associated to this plane */
3216 VkImageAspectFlags aspect
;
3221 struct anv_format_plane planes
[3];
3227 static inline uint32_t
3228 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3229 VkImageAspectFlags aspect_mask
)
3231 switch (aspect_mask
) {
3232 case VK_IMAGE_ASPECT_COLOR_BIT
:
3233 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3234 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3236 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3237 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3240 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3242 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3245 /* Purposefully assert with depth/stencil aspects. */
3246 unreachable("invalid image aspect");
3250 static inline VkImageAspectFlags
3251 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3254 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3255 if (util_bitcount(image_aspects
) > 1)
3256 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3257 return VK_IMAGE_ASPECT_COLOR_BIT
;
3259 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3260 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3261 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3262 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3265 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3266 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3268 const struct anv_format
*
3269 anv_get_format(VkFormat format
);
3271 static inline uint32_t
3272 anv_get_format_planes(VkFormat vk_format
)
3274 const struct anv_format
*format
= anv_get_format(vk_format
);
3276 return format
!= NULL
? format
->n_planes
: 0;
3279 struct anv_format_plane
3280 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3281 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3283 static inline enum isl_format
3284 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3285 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3287 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3290 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3291 VkImageCreateFlags create_flags
,
3293 VkImageTiling vk_tiling
,
3294 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3296 static inline struct isl_swizzle
3297 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3299 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3300 * RGB as RGBA for texturing
3302 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3303 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3305 /* But it doesn't matter what we render to that channel */
3306 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3312 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3315 * Subsurface of an anv_image.
3317 struct anv_surface
{
3318 /** Valid only if isl_surf::size_B > 0. */
3319 struct isl_surf isl
;
3322 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3328 VkImageType type
; /**< VkImageCreateInfo::imageType */
3329 /* The original VkFormat provided by the client. This may not match any
3330 * of the actual surface formats.
3333 const struct anv_format
*format
;
3335 VkImageAspectFlags aspects
;
3338 uint32_t array_size
;
3339 uint32_t samples
; /**< VkImageCreateInfo::samples */
3341 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3342 VkImageUsageFlags stencil_usage
;
3343 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3344 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3346 /** True if this is needs to be bound to an appropriately tiled BO.
3348 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3349 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3350 * we require a dedicated allocation so that we can know to allocate a
3353 bool needs_set_tiling
;
3356 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3357 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3359 uint64_t drm_format_mod
;
3364 /* Whether the image is made of several underlying buffer objects rather a
3365 * single one with different offsets.
3369 /* All the formats that can be used when creating views of this image
3370 * are CCS_E compatible.
3372 bool ccs_e_compatible
;
3374 /* Image was created with external format. */
3375 bool external_format
;
3380 * For each foo, anv_image::planes[x].surface is valid if and only if
3381 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3382 * to figure the number associated with a given aspect.
3384 * The hardware requires that the depth buffer and stencil buffer be
3385 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3386 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3387 * allocate the depth and stencil buffers as separate surfaces in the same
3392 * -----------------------
3394 * ----------------------- |
3395 * | shadow surface0 | |
3396 * ----------------------- | Plane 0
3397 * | aux surface0 | |
3398 * ----------------------- |
3399 * | fast clear colors0 | \|/
3400 * -----------------------
3402 * ----------------------- |
3403 * | shadow surface1 | |
3404 * ----------------------- | Plane 1
3405 * | aux surface1 | |
3406 * ----------------------- |
3407 * | fast clear colors1 | \|/
3408 * -----------------------
3411 * -----------------------
3415 * Offset of the entire plane (whenever the image is disjoint this is
3423 struct anv_surface surface
;
3426 * A surface which shadows the main surface and may have different
3427 * tiling. This is used for sampling using a tiling that isn't supported
3428 * for other operations.
3430 struct anv_surface shadow_surface
;
3433 * For color images, this is the aux usage for this image when not used
3434 * as a color attachment.
3436 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3437 * image has a HiZ buffer.
3439 enum isl_aux_usage aux_usage
;
3441 struct anv_surface aux_surface
;
3444 * Offset of the fast clear state (used to compute the
3445 * fast_clear_state_offset of the following planes).
3447 uint32_t fast_clear_state_offset
;
3450 * BO associated with this plane, set when bound.
3452 struct anv_address address
;
3455 * Address of the main surface used to fill the aux map table. This is
3456 * used at destruction of the image since the Vulkan spec does not
3457 * guarantee that the address.bo field we still be valid at destruction.
3459 uint64_t aux_map_surface_address
;
3462 * When destroying the image, also free the bo.
3468 /* The ordering of this enum is important */
3469 enum anv_fast_clear_type
{
3470 /** Image does not have/support any fast-clear blocks */
3471 ANV_FAST_CLEAR_NONE
= 0,
3472 /** Image has/supports fast-clear but only to the default value */
3473 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3474 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3475 ANV_FAST_CLEAR_ANY
= 2,
3478 /* Returns the number of auxiliary buffer levels attached to an image. */
3479 static inline uint8_t
3480 anv_image_aux_levels(const struct anv_image
* const image
,
3481 VkImageAspectFlagBits aspect
)
3483 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3485 /* The Gen12 CCS aux surface is represented with only one level. */
3486 const uint8_t aux_logical_levels
=
3487 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3488 image
->planes
[plane
].surface
.isl
.levels
:
3489 image
->planes
[plane
].aux_surface
.isl
.levels
;
3491 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3492 aux_logical_levels
: 0;
3495 /* Returns the number of auxiliary buffer layers attached to an image. */
3496 static inline uint32_t
3497 anv_image_aux_layers(const struct anv_image
* const image
,
3498 VkImageAspectFlagBits aspect
,
3499 const uint8_t miplevel
)
3503 /* The miplevel must exist in the main buffer. */
3504 assert(miplevel
< image
->levels
);
3506 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3507 /* There are no layers with auxiliary data because the miplevel has no
3512 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3514 /* The Gen12 CCS aux surface is represented with only one layer. */
3515 const struct isl_extent4d
*aux_logical_level0_px
=
3516 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3517 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3518 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3520 return MAX2(aux_logical_level0_px
->array_len
,
3521 aux_logical_level0_px
->depth
>> miplevel
);
3525 static inline struct anv_address
3526 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3527 const struct anv_image
*image
,
3528 VkImageAspectFlagBits aspect
)
3530 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3532 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3533 return anv_address_add(image
->planes
[plane
].address
,
3534 image
->planes
[plane
].fast_clear_state_offset
);
3537 static inline struct anv_address
3538 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3539 const struct anv_image
*image
,
3540 VkImageAspectFlagBits aspect
)
3542 struct anv_address addr
=
3543 anv_image_get_clear_color_addr(device
, image
, aspect
);
3545 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3546 device
->isl_dev
.ss
.clear_color_state_size
:
3547 device
->isl_dev
.ss
.clear_value_size
;
3548 return anv_address_add(addr
, clear_color_state_size
);
3551 static inline struct anv_address
3552 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3553 const struct anv_image
*image
,
3554 VkImageAspectFlagBits aspect
,
3555 uint32_t level
, uint32_t array_layer
)
3557 assert(level
< anv_image_aux_levels(image
, aspect
));
3558 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3559 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3560 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3562 struct anv_address addr
=
3563 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3564 addr
.offset
+= 4; /* Go past the fast clear type */
3566 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3567 for (uint32_t l
= 0; l
< level
; l
++)
3568 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3570 addr
.offset
+= level
* image
->array_size
* 4;
3572 addr
.offset
+= array_layer
* 4;
3574 assert(addr
.offset
<
3575 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3579 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3581 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3582 const struct anv_image
*image
)
3584 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3587 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3588 * struct. There's documentation which suggests that this feature actually
3589 * reduces performance on BDW, but it has only been observed to help so
3590 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3591 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3593 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3596 return image
->samples
== 1;
3600 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3601 const struct anv_image
*image
,
3604 return device
->info
.has_aux_map
&&
3605 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3609 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3610 const struct anv_image
*image
,
3611 VkImageAspectFlagBits aspect
,
3612 enum isl_aux_usage aux_usage
,
3614 uint32_t base_layer
,
3615 uint32_t layer_count
);
3618 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3619 const struct anv_image
*image
,
3620 VkImageAspectFlagBits aspect
,
3621 enum isl_aux_usage aux_usage
,
3622 enum isl_format format
, struct isl_swizzle swizzle
,
3623 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3624 VkRect2D area
, union isl_color_value clear_color
);
3626 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3627 const struct anv_image
*image
,
3628 VkImageAspectFlags aspects
,
3629 enum isl_aux_usage depth_aux_usage
,
3631 uint32_t base_layer
, uint32_t layer_count
,
3633 float depth_value
, uint8_t stencil_value
);
3635 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3636 const struct anv_image
*src_image
,
3637 enum isl_aux_usage src_aux_usage
,
3638 uint32_t src_level
, uint32_t src_base_layer
,
3639 const struct anv_image
*dst_image
,
3640 enum isl_aux_usage dst_aux_usage
,
3641 uint32_t dst_level
, uint32_t dst_base_layer
,
3642 VkImageAspectFlagBits aspect
,
3643 uint32_t src_x
, uint32_t src_y
,
3644 uint32_t dst_x
, uint32_t dst_y
,
3645 uint32_t width
, uint32_t height
,
3646 uint32_t layer_count
,
3647 enum blorp_filter filter
);
3649 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3650 const struct anv_image
*image
,
3651 VkImageAspectFlagBits aspect
, uint32_t level
,
3652 uint32_t base_layer
, uint32_t layer_count
,
3653 enum isl_aux_op hiz_op
);
3655 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3656 const struct anv_image
*image
,
3657 VkImageAspectFlags aspects
,
3659 uint32_t base_layer
, uint32_t layer_count
,
3660 VkRect2D area
, uint8_t stencil_value
);
3662 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3663 const struct anv_image
*image
,
3664 enum isl_format format
,
3665 VkImageAspectFlagBits aspect
,
3666 uint32_t base_layer
, uint32_t layer_count
,
3667 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3670 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3671 const struct anv_image
*image
,
3672 enum isl_format format
,
3673 VkImageAspectFlagBits aspect
, uint32_t level
,
3674 uint32_t base_layer
, uint32_t layer_count
,
3675 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3679 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3680 const struct anv_image
*image
,
3681 VkImageAspectFlagBits aspect
,
3682 uint32_t base_level
, uint32_t level_count
,
3683 uint32_t base_layer
, uint32_t layer_count
);
3686 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3687 const struct anv_image
*image
,
3688 const VkImageAspectFlagBits aspect
,
3689 const VkImageLayout layout
);
3691 enum anv_fast_clear_type
3692 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3693 const struct anv_image
* const image
,
3694 const VkImageAspectFlagBits aspect
,
3695 const VkImageLayout layout
);
3697 /* This is defined as a macro so that it works for both
3698 * VkImageSubresourceRange and VkImageSubresourceLayers
3700 #define anv_get_layerCount(_image, _range) \
3701 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3702 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3704 static inline uint32_t
3705 anv_get_levelCount(const struct anv_image
*image
,
3706 const VkImageSubresourceRange
*range
)
3708 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3709 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3712 static inline VkImageAspectFlags
3713 anv_image_expand_aspects(const struct anv_image
*image
,
3714 VkImageAspectFlags aspects
)
3716 /* If the underlying image has color plane aspects and
3717 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3718 * the underlying image. */
3719 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3720 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3721 return image
->aspects
;
3727 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3728 VkImageAspectFlags aspects2
)
3730 if (aspects1
== aspects2
)
3733 /* Only 1 color aspects are compatibles. */
3734 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3735 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3736 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3742 struct anv_image_view
{
3743 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3745 VkImageAspectFlags aspect_mask
;
3747 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3751 uint32_t image_plane
;
3753 struct isl_view isl
;
3756 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3757 * image layout of SHADER_READ_ONLY_OPTIMAL or
3758 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3760 struct anv_surface_state optimal_sampler_surface_state
;
3763 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3764 * image layout of GENERAL.
3766 struct anv_surface_state general_sampler_surface_state
;
3769 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3770 * states for write-only and readable, using the real format for
3771 * write-only and the lowered format for readable.
3773 struct anv_surface_state storage_surface_state
;
3774 struct anv_surface_state writeonly_storage_surface_state
;
3776 struct brw_image_param storage_image_param
;
3780 enum anv_image_view_state_flags
{
3781 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3782 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3785 void anv_image_fill_surface_state(struct anv_device
*device
,
3786 const struct anv_image
*image
,
3787 VkImageAspectFlagBits aspect
,
3788 const struct isl_view
*view
,
3789 isl_surf_usage_flags_t view_usage
,
3790 enum isl_aux_usage aux_usage
,
3791 const union isl_color_value
*clear_color
,
3792 enum anv_image_view_state_flags flags
,
3793 struct anv_surface_state
*state_inout
,
3794 struct brw_image_param
*image_param_out
);
3796 struct anv_image_create_info
{
3797 const VkImageCreateInfo
*vk_info
;
3799 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3800 isl_tiling_flags_t isl_tiling_flags
;
3802 /** These flags will be added to any derived from VkImageCreateInfo. */
3803 isl_surf_usage_flags_t isl_extra_usage_flags
;
3806 bool external_format
;
3809 VkResult
anv_image_create(VkDevice _device
,
3810 const struct anv_image_create_info
*info
,
3811 const VkAllocationCallbacks
* alloc
,
3814 const struct anv_surface
*
3815 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3816 VkImageAspectFlags aspect_mask
);
3819 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3821 static inline VkExtent3D
3822 anv_sanitize_image_extent(const VkImageType imageType
,
3823 const VkExtent3D imageExtent
)
3825 switch (imageType
) {
3826 case VK_IMAGE_TYPE_1D
:
3827 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3828 case VK_IMAGE_TYPE_2D
:
3829 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3830 case VK_IMAGE_TYPE_3D
:
3833 unreachable("invalid image type");
3837 static inline VkOffset3D
3838 anv_sanitize_image_offset(const VkImageType imageType
,
3839 const VkOffset3D imageOffset
)
3841 switch (imageType
) {
3842 case VK_IMAGE_TYPE_1D
:
3843 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3844 case VK_IMAGE_TYPE_2D
:
3845 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3846 case VK_IMAGE_TYPE_3D
:
3849 unreachable("invalid image type");
3853 VkFormatFeatureFlags
3854 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3856 const struct anv_format
*anv_format
,
3857 VkImageTiling vk_tiling
);
3859 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3860 struct anv_state state
,
3861 enum isl_format format
,
3862 struct anv_address address
,
3863 uint32_t range
, uint32_t stride
);
3866 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3867 const struct anv_attachment_state
*att_state
,
3868 const struct anv_image_view
*iview
)
3870 const struct isl_format_layout
*view_fmtl
=
3871 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3873 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3874 if (view_fmtl->channels.c.bits) \
3875 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3877 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3878 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3879 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3880 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3882 #undef COPY_CLEAR_COLOR_CHANNEL
3886 struct anv_ycbcr_conversion
{
3887 const struct anv_format
* format
;
3888 VkSamplerYcbcrModelConversion ycbcr_model
;
3889 VkSamplerYcbcrRange ycbcr_range
;
3890 VkComponentSwizzle mapping
[4];
3891 VkChromaLocation chroma_offsets
[2];
3892 VkFilter chroma_filter
;
3893 bool chroma_reconstruction
;
3896 struct anv_sampler
{
3897 uint32_t state
[3][4];
3899 struct anv_ycbcr_conversion
*conversion
;
3901 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3902 * and with a 32-byte stride for use as bindless samplers.
3904 struct anv_state bindless_state
;
3907 struct anv_framebuffer
{
3912 uint32_t attachment_count
;
3913 struct anv_image_view
* attachments
[0];
3916 struct anv_subpass_attachment
{
3917 VkImageUsageFlagBits usage
;
3918 uint32_t attachment
;
3919 VkImageLayout layout
;
3921 /* Used only with attachment containing stencil data. */
3922 VkImageLayout stencil_layout
;
3925 struct anv_subpass
{
3926 uint32_t attachment_count
;
3929 * A pointer to all attachment references used in this subpass.
3930 * Only valid if ::attachment_count > 0.
3932 struct anv_subpass_attachment
* attachments
;
3933 uint32_t input_count
;
3934 struct anv_subpass_attachment
* input_attachments
;
3935 uint32_t color_count
;
3936 struct anv_subpass_attachment
* color_attachments
;
3937 struct anv_subpass_attachment
* resolve_attachments
;
3939 struct anv_subpass_attachment
* depth_stencil_attachment
;
3940 struct anv_subpass_attachment
* ds_resolve_attachment
;
3941 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3942 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3946 /** Subpass has a depth/stencil self-dependency */
3947 bool has_ds_self_dep
;
3949 /** Subpass has at least one color resolve attachment */
3950 bool has_color_resolve
;
3953 static inline unsigned
3954 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3956 return MAX2(1, util_bitcount(subpass
->view_mask
));
3959 struct anv_render_pass_attachment
{
3960 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3961 * its members individually.
3965 VkImageUsageFlags usage
;
3966 VkAttachmentLoadOp load_op
;
3967 VkAttachmentStoreOp store_op
;
3968 VkAttachmentLoadOp stencil_load_op
;
3969 VkImageLayout initial_layout
;
3970 VkImageLayout final_layout
;
3971 VkImageLayout first_subpass_layout
;
3973 VkImageLayout stencil_initial_layout
;
3974 VkImageLayout stencil_final_layout
;
3976 /* The subpass id in which the attachment will be used last. */
3977 uint32_t last_subpass_idx
;
3980 struct anv_render_pass
{
3981 uint32_t attachment_count
;
3982 uint32_t subpass_count
;
3983 /* An array of subpass_count+1 flushes, one per subpass boundary */
3984 enum anv_pipe_bits
* subpass_flushes
;
3985 struct anv_render_pass_attachment
* attachments
;
3986 struct anv_subpass subpasses
[0];
3989 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3991 struct anv_query_pool
{
3993 VkQueryPipelineStatisticFlags pipeline_statistics
;
3994 /** Stride between slots, in bytes */
3996 /** Number of slots in this query pool */
4001 int anv_get_instance_entrypoint_index(const char *name
);
4002 int anv_get_device_entrypoint_index(const char *name
);
4003 int anv_get_physical_device_entrypoint_index(const char *name
);
4005 const char *anv_get_instance_entry_name(int index
);
4006 const char *anv_get_physical_device_entry_name(int index
);
4007 const char *anv_get_device_entry_name(int index
);
4010 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4011 const struct anv_instance_extension_table
*instance
);
4013 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4014 const struct anv_instance_extension_table
*instance
);
4016 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4017 const struct anv_instance_extension_table
*instance
,
4018 const struct anv_device_extension_table
*device
);
4020 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4023 void anv_dump_image_to_ppm(struct anv_device
*device
,
4024 struct anv_image
*image
, unsigned miplevel
,
4025 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4026 const char *filename
);
4028 enum anv_dump_action
{
4029 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4032 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4033 void anv_dump_finish(void);
4035 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4037 static inline uint32_t
4038 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4040 /* This function must be called from within a subpass. */
4041 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4043 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4045 /* The id of this subpass shouldn't exceed the number of subpasses in this
4046 * render pass minus 1.
4048 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4052 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4053 void anv_device_perf_init(struct anv_device
*device
);
4055 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4057 static inline struct __anv_type * \
4058 __anv_type ## _from_handle(__VkType _handle) \
4060 return (struct __anv_type *) _handle; \
4063 static inline __VkType \
4064 __anv_type ## _to_handle(struct __anv_type *_obj) \
4066 return (__VkType) _obj; \
4069 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4071 static inline struct __anv_type * \
4072 __anv_type ## _from_handle(__VkType _handle) \
4074 return (struct __anv_type *)(uintptr_t) _handle; \
4077 static inline __VkType \
4078 __anv_type ## _to_handle(struct __anv_type *_obj) \
4080 return (__VkType)(uintptr_t) _obj; \
4083 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4084 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4086 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4087 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4088 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4089 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4090 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4092 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4093 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4094 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4095 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4096 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4097 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4098 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4099 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4100 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4101 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4102 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4103 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4104 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4105 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4106 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4107 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4108 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4109 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4110 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4111 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4112 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4113 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4114 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4116 /* Gen-specific function declarations */
4118 # include "anv_genX.h"
4120 # define genX(x) gen7_##x
4121 # include "anv_genX.h"
4123 # define genX(x) gen75_##x
4124 # include "anv_genX.h"
4126 # define genX(x) gen8_##x
4127 # include "anv_genX.h"
4129 # define genX(x) gen9_##x
4130 # include "anv_genX.h"
4132 # define genX(x) gen10_##x
4133 # include "anv_genX.h"
4135 # define genX(x) gen11_##x
4136 # include "anv_genX.h"
4138 # define genX(x) gen12_##x
4139 # include "anv_genX.h"
4143 #endif /* ANV_PRIVATE_H */