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anv/image: Add a drm_format_mod field
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53
54 /* Pre-declarations needed for WSI entrypoints */
55 struct wl_surface;
56 struct wl_display;
57 typedef struct xcb_connection_t xcb_connection_t;
58 typedef uint32_t xcb_visualid_t;
59 typedef uint32_t xcb_window_t;
60
61 struct anv_buffer;
62 struct anv_buffer_view;
63 struct anv_image_view;
64 struct anv_instance;
65 struct anv_debug_report_callback;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "isl/isl.h"
76
77 #include "common/gen_debug.h"
78 #include "common/intel_log.h"
79 #include "wsi_common.h"
80
81 /* Allowing different clear colors requires us to perform a depth resolve at
82 * the end of certain render passes. This is because while slow clears store
83 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
84 * See the PRMs for examples describing when additional resolves would be
85 * necessary. To enable fast clears without requiring extra resolves, we set
86 * the clear value to a globally-defined one. We could allow different values
87 * if the user doesn't expect coherent data during or after a render passes
88 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
89 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
90 * 1.0f seems to be the only value used. The only application that doesn't set
91 * this value does so through the usage of an seemingly uninitialized clear
92 * value.
93 */
94 #define ANV_HZ_FC_VAL 1.0f
95
96 #define MAX_VBS 28
97 #define MAX_SETS 8
98 #define MAX_RTS 8
99 #define MAX_VIEWPORTS 16
100 #define MAX_SCISSORS 16
101 #define MAX_PUSH_CONSTANTS_SIZE 128
102 #define MAX_DYNAMIC_BUFFERS 16
103 #define MAX_IMAGES 8
104 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
105
106 #define ANV_SVGS_VB_INDEX MAX_VBS
107 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
108
109 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_down_npot_u32(uint32_t v, uint32_t a)
113 {
114 return v - (v % a);
115 }
116
117 static inline uint32_t
118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 anv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 anv_minify(uint32_t n, uint32_t levels)
148 {
149 if (unlikely(n == 0))
150 return 0;
151 else
152 return MAX2(n >> levels, 1);
153 }
154
155 static inline float
156 anv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 static inline union isl_color_value
180 vk_to_isl_color(VkClearColorValue color)
181 {
182 return (union isl_color_value) {
183 .u32 = {
184 color.uint32[0],
185 color.uint32[1],
186 color.uint32[2],
187 color.uint32[3],
188 },
189 };
190 }
191
192 #define for_each_bit(b, dword) \
193 for (uint32_t __dword = (dword); \
194 (b) = __builtin_ffs(__dword) - 1, __dword; \
195 __dword &= ~(1 << (b)))
196
197 #define typed_memcpy(dest, src, count) ({ \
198 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
199 memcpy((dest), (src), (count) * sizeof(*(src))); \
200 })
201
202 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
203 * to be added here in order to utilize mapping in debug/error/perf macros.
204 */
205 #define REPORT_OBJECT_TYPE(o) \
206 __builtin_choose_expr ( \
207 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
208 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
209 __builtin_choose_expr ( \
210 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
211 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
212 __builtin_choose_expr ( \
213 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
214 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
215 __builtin_choose_expr ( \
216 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
217 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
218 __builtin_choose_expr ( \
219 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
220 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
221 __builtin_choose_expr ( \
222 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
223 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
224 __builtin_choose_expr ( \
225 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
226 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
227 __builtin_choose_expr ( \
228 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
229 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
230 __builtin_choose_expr ( \
231 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
232 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
233 __builtin_choose_expr ( \
234 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
235 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
236 __builtin_choose_expr ( \
237 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
238 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
239 __builtin_choose_expr ( \
240 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
241 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
242 __builtin_choose_expr ( \
243 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
244 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
245 __builtin_choose_expr ( \
246 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
247 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
248 __builtin_choose_expr ( \
249 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
250 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
251 __builtin_choose_expr ( \
252 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
253 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
254 __builtin_choose_expr ( \
255 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
256 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
257 __builtin_choose_expr ( \
258 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
259 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
260 __builtin_choose_expr ( \
261 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
262 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
263 __builtin_choose_expr ( \
264 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
265 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
266 __builtin_choose_expr ( \
267 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
268 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
269 __builtin_choose_expr ( \
270 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
271 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
272 __builtin_choose_expr ( \
273 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
274 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
275 __builtin_choose_expr ( \
276 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
277 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
278 __builtin_choose_expr ( \
279 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
280 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
281 __builtin_choose_expr ( \
282 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
283 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
284 __builtin_choose_expr ( \
285 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
286 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
287 __builtin_choose_expr ( \
288 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
289 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
290 __builtin_choose_expr ( \
291 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
292 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
293 __builtin_choose_expr ( \
294 __builtin_types_compatible_p (__typeof (o), struct anv_debug_callback*), \
295 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
296 __builtin_choose_expr ( \
297 __builtin_types_compatible_p (__typeof (o), void*), \
298 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
299 /* The void expression results in a compile-time error \
300 when assigning the result to something. */ \
301 (void)0)))))))))))))))))))))))))))))))
302
303 /* Whenever we generate an error, pass it through this function. Useful for
304 * debugging, where we can break on it. Only call at error site, not when
305 * propagating errors. Might be useful to plug in a stack trace here.
306 */
307
308 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
309 VkDebugReportObjectTypeEXT type, VkResult error,
310 const char *file, int line, const char *format, ...);
311
312 #ifdef DEBUG
313 #define vk_error(error) __vk_errorf(NULL, NULL,\
314 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
315 error, __FILE__, __LINE__, NULL);
316 #define vk_errorf(instance, obj, error, format, ...)\
317 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
318 __FILE__, __LINE__, format, ## __VA_ARGS__);
319 #else
320 #define vk_error(error) error
321 #define vk_errorf(instance, obj, error, format, ...) error
322 #endif
323
324 /**
325 * Warn on ignored extension structs.
326 *
327 * The Vulkan spec requires us to ignore unsupported or unknown structs in
328 * a pNext chain. In debug mode, emitting warnings for ignored structs may
329 * help us discover structs that we should not have ignored.
330 *
331 *
332 * From the Vulkan 1.0.38 spec:
333 *
334 * Any component of the implementation (the loader, any enabled layers,
335 * and drivers) must skip over, without processing (other than reading the
336 * sType and pNext members) any chained structures with sType values not
337 * defined by extensions supported by that component.
338 */
339 #define anv_debug_ignored_stype(sType) \
340 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
341
342 void __anv_perf_warn(struct anv_instance *instance, const void *object,
343 VkDebugReportObjectTypeEXT type, const char *file,
344 int line, const char *format, ...)
345 anv_printflike(6, 7);
346 void anv_loge(const char *format, ...) anv_printflike(1, 2);
347 void anv_loge_v(const char *format, va_list va);
348
349 void anv_debug_report(struct anv_instance *instance,
350 VkDebugReportFlagsEXT flags,
351 VkDebugReportObjectTypeEXT object_type,
352 uint64_t handle,
353 size_t location,
354 int32_t messageCode,
355 const char* pLayerPrefix,
356 const char *pMessage);
357
358 /**
359 * Print a FINISHME message, including its source location.
360 */
361 #define anv_finishme(format, ...) \
362 do { \
363 static bool reported = false; \
364 if (!reported) { \
365 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
366 ##__VA_ARGS__); \
367 reported = true; \
368 } \
369 } while (0)
370
371 /**
372 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
373 */
374 #define anv_perf_warn(instance, obj, format, ...) \
375 do { \
376 static bool reported = false; \
377 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
378 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
379 format, ##__VA_ARGS__); \
380 reported = true; \
381 } \
382 } while (0)
383
384 /* A non-fatal assert. Useful for debugging. */
385 #ifdef DEBUG
386 #define anv_assert(x) ({ \
387 if (unlikely(!(x))) \
388 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
389 })
390 #else
391 #define anv_assert(x)
392 #endif
393
394 /* A multi-pointer allocator
395 *
396 * When copying data structures from the user (such as a render pass), it's
397 * common to need to allocate data for a bunch of different things. Instead
398 * of doing several allocations and having to handle all of the error checking
399 * that entails, it can be easier to do a single allocation. This struct
400 * helps facilitate that. The intended usage looks like this:
401 *
402 * ANV_MULTIALLOC(ma)
403 * anv_multialloc_add(&ma, &main_ptr, 1);
404 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
405 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
406 *
407 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
408 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
409 */
410 struct anv_multialloc {
411 size_t size;
412 size_t align;
413
414 uint32_t ptr_count;
415 void **ptrs[8];
416 };
417
418 #define ANV_MULTIALLOC_INIT \
419 ((struct anv_multialloc) { 0, })
420
421 #define ANV_MULTIALLOC(_name) \
422 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
423
424 __attribute__((always_inline))
425 static inline void
426 _anv_multialloc_add(struct anv_multialloc *ma,
427 void **ptr, size_t size, size_t align)
428 {
429 size_t offset = align_u64(ma->size, align);
430 ma->size = offset + size;
431 ma->align = MAX2(ma->align, align);
432
433 /* Store the offset in the pointer. */
434 *ptr = (void *)(uintptr_t)offset;
435
436 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
437 ma->ptrs[ma->ptr_count++] = ptr;
438 }
439
440 #define anv_multialloc_add_size(_ma, _ptr, _size) \
441 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
442
443 #define anv_multialloc_add(_ma, _ptr, _count) \
444 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
445
446 __attribute__((always_inline))
447 static inline void *
448 anv_multialloc_alloc(struct anv_multialloc *ma,
449 const VkAllocationCallbacks *alloc,
450 VkSystemAllocationScope scope)
451 {
452 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
453 if (!ptr)
454 return NULL;
455
456 /* Fill out each of the pointers with their final value.
457 *
458 * for (uint32_t i = 0; i < ma->ptr_count; i++)
459 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
460 *
461 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
462 * constant, GCC is incapable of figuring this out and unrolling the loop
463 * so we have to give it a little help.
464 */
465 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
466 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
467 if ((_i) < ma->ptr_count) \
468 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
469 _ANV_MULTIALLOC_UPDATE_POINTER(0);
470 _ANV_MULTIALLOC_UPDATE_POINTER(1);
471 _ANV_MULTIALLOC_UPDATE_POINTER(2);
472 _ANV_MULTIALLOC_UPDATE_POINTER(3);
473 _ANV_MULTIALLOC_UPDATE_POINTER(4);
474 _ANV_MULTIALLOC_UPDATE_POINTER(5);
475 _ANV_MULTIALLOC_UPDATE_POINTER(6);
476 _ANV_MULTIALLOC_UPDATE_POINTER(7);
477 #undef _ANV_MULTIALLOC_UPDATE_POINTER
478
479 return ptr;
480 }
481
482 __attribute__((always_inline))
483 static inline void *
484 anv_multialloc_alloc2(struct anv_multialloc *ma,
485 const VkAllocationCallbacks *parent_alloc,
486 const VkAllocationCallbacks *alloc,
487 VkSystemAllocationScope scope)
488 {
489 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
490 }
491
492 struct anv_bo {
493 uint32_t gem_handle;
494
495 /* Index into the current validation list. This is used by the
496 * validation list building alrogithm to track which buffers are already
497 * in the validation list so that we can ensure uniqueness.
498 */
499 uint32_t index;
500
501 /* Last known offset. This value is provided by the kernel when we
502 * execbuf and is used as the presumed offset for the next bunch of
503 * relocations.
504 */
505 uint64_t offset;
506
507 uint64_t size;
508 void *map;
509
510 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
511 uint32_t flags;
512 };
513
514 static inline void
515 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
516 {
517 bo->gem_handle = gem_handle;
518 bo->index = 0;
519 bo->offset = -1;
520 bo->size = size;
521 bo->map = NULL;
522 bo->flags = 0;
523 }
524
525 /* Represents a lock-free linked list of "free" things. This is used by
526 * both the block pool and the state pools. Unfortunately, in order to
527 * solve the ABA problem, we can't use a single uint32_t head.
528 */
529 union anv_free_list {
530 struct {
531 int32_t offset;
532
533 /* A simple count that is incremented every time the head changes. */
534 uint32_t count;
535 };
536 uint64_t u64;
537 };
538
539 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
540
541 struct anv_block_state {
542 union {
543 struct {
544 uint32_t next;
545 uint32_t end;
546 };
547 uint64_t u64;
548 };
549 };
550
551 struct anv_block_pool {
552 struct anv_device *device;
553
554 uint64_t bo_flags;
555
556 struct anv_bo bo;
557
558 /* The offset from the start of the bo to the "center" of the block
559 * pool. Pointers to allocated blocks are given by
560 * bo.map + center_bo_offset + offsets.
561 */
562 uint32_t center_bo_offset;
563
564 /* Current memory map of the block pool. This pointer may or may not
565 * point to the actual beginning of the block pool memory. If
566 * anv_block_pool_alloc_back has ever been called, then this pointer
567 * will point to the "center" position of the buffer and all offsets
568 * (negative or positive) given out by the block pool alloc functions
569 * will be valid relative to this pointer.
570 *
571 * In particular, map == bo.map + center_offset
572 */
573 void *map;
574 int fd;
575
576 /**
577 * Array of mmaps and gem handles owned by the block pool, reclaimed when
578 * the block pool is destroyed.
579 */
580 struct u_vector mmap_cleanups;
581
582 struct anv_block_state state;
583
584 struct anv_block_state back_state;
585 };
586
587 /* Block pools are backed by a fixed-size 1GB memfd */
588 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
589
590 /* The center of the block pool is also the middle of the memfd. This may
591 * change in the future if we decide differently for some reason.
592 */
593 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
594
595 static inline uint32_t
596 anv_block_pool_size(struct anv_block_pool *pool)
597 {
598 return pool->state.end + pool->back_state.end;
599 }
600
601 struct anv_state {
602 int32_t offset;
603 uint32_t alloc_size;
604 void *map;
605 };
606
607 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
608
609 struct anv_fixed_size_state_pool {
610 union anv_free_list free_list;
611 struct anv_block_state block;
612 };
613
614 #define ANV_MIN_STATE_SIZE_LOG2 6
615 #define ANV_MAX_STATE_SIZE_LOG2 20
616
617 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
618
619 struct anv_state_pool {
620 struct anv_block_pool block_pool;
621
622 /* The size of blocks which will be allocated from the block pool */
623 uint32_t block_size;
624
625 /** Free list for "back" allocations */
626 union anv_free_list back_alloc_free_list;
627
628 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
629 };
630
631 struct anv_state_stream_block;
632
633 struct anv_state_stream {
634 struct anv_state_pool *state_pool;
635
636 /* The size of blocks to allocate from the state pool */
637 uint32_t block_size;
638
639 /* Current block we're allocating from */
640 struct anv_state block;
641
642 /* Offset into the current block at which to allocate the next state */
643 uint32_t next;
644
645 /* List of all blocks allocated from this pool */
646 struct anv_state_stream_block *block_list;
647 };
648
649 /* The block_pool functions exported for testing only. The block pool should
650 * only be used via a state pool (see below).
651 */
652 VkResult anv_block_pool_init(struct anv_block_pool *pool,
653 struct anv_device *device,
654 uint32_t initial_size,
655 uint64_t bo_flags);
656 void anv_block_pool_finish(struct anv_block_pool *pool);
657 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
658 uint32_t block_size);
659 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
660 uint32_t block_size);
661
662 VkResult anv_state_pool_init(struct anv_state_pool *pool,
663 struct anv_device *device,
664 uint32_t block_size,
665 uint64_t bo_flags);
666 void anv_state_pool_finish(struct anv_state_pool *pool);
667 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
668 uint32_t state_size, uint32_t alignment);
669 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
670 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
671 void anv_state_stream_init(struct anv_state_stream *stream,
672 struct anv_state_pool *state_pool,
673 uint32_t block_size);
674 void anv_state_stream_finish(struct anv_state_stream *stream);
675 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
676 uint32_t size, uint32_t alignment);
677
678 /**
679 * Implements a pool of re-usable BOs. The interface is identical to that
680 * of block_pool except that each block is its own BO.
681 */
682 struct anv_bo_pool {
683 struct anv_device *device;
684
685 uint64_t bo_flags;
686
687 void *free_list[16];
688 };
689
690 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
691 uint64_t bo_flags);
692 void anv_bo_pool_finish(struct anv_bo_pool *pool);
693 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
694 uint32_t size);
695 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
696
697 struct anv_scratch_bo {
698 bool exists;
699 struct anv_bo bo;
700 };
701
702 struct anv_scratch_pool {
703 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
704 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
705 };
706
707 void anv_scratch_pool_init(struct anv_device *device,
708 struct anv_scratch_pool *pool);
709 void anv_scratch_pool_finish(struct anv_device *device,
710 struct anv_scratch_pool *pool);
711 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
712 struct anv_scratch_pool *pool,
713 gl_shader_stage stage,
714 unsigned per_thread_scratch);
715
716 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
717 struct anv_bo_cache {
718 struct hash_table *bo_map;
719 pthread_mutex_t mutex;
720 };
721
722 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
723 void anv_bo_cache_finish(struct anv_bo_cache *cache);
724 VkResult anv_bo_cache_alloc(struct anv_device *device,
725 struct anv_bo_cache *cache,
726 uint64_t size, struct anv_bo **bo);
727 VkResult anv_bo_cache_import(struct anv_device *device,
728 struct anv_bo_cache *cache,
729 int fd, struct anv_bo **bo);
730 VkResult anv_bo_cache_export(struct anv_device *device,
731 struct anv_bo_cache *cache,
732 struct anv_bo *bo_in, int *fd_out);
733 void anv_bo_cache_release(struct anv_device *device,
734 struct anv_bo_cache *cache,
735 struct anv_bo *bo);
736
737 struct anv_memory_type {
738 /* Standard bits passed on to the client */
739 VkMemoryPropertyFlags propertyFlags;
740 uint32_t heapIndex;
741
742 /* Driver-internal book-keeping */
743 VkBufferUsageFlags valid_buffer_usage;
744 };
745
746 struct anv_memory_heap {
747 /* Standard bits passed on to the client */
748 VkDeviceSize size;
749 VkMemoryHeapFlags flags;
750
751 /* Driver-internal book-keeping */
752 bool supports_48bit_addresses;
753 };
754
755 struct anv_physical_device {
756 VK_LOADER_DATA _loader_data;
757
758 struct anv_instance * instance;
759 uint32_t chipset_id;
760 char path[20];
761 const char * name;
762 struct gen_device_info info;
763 /** Amount of "GPU memory" we want to advertise
764 *
765 * Clearly, this value is bogus since Intel is a UMA architecture. On
766 * gen7 platforms, we are limited by GTT size unless we want to implement
767 * fine-grained tracking and GTT splitting. On Broadwell and above we are
768 * practically unlimited. However, we will never report more than 3/4 of
769 * the total system ram to try and avoid running out of RAM.
770 */
771 bool supports_48bit_addresses;
772 struct brw_compiler * compiler;
773 struct isl_device isl_dev;
774 int cmd_parser_version;
775 bool has_exec_async;
776 bool has_exec_capture;
777 bool has_exec_fence;
778 bool has_syncobj;
779 bool has_syncobj_wait;
780
781 uint32_t eu_total;
782 uint32_t subslice_total;
783
784 struct {
785 uint32_t type_count;
786 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
787 uint32_t heap_count;
788 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
789 } memory;
790
791 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
792 uint8_t driver_uuid[VK_UUID_SIZE];
793 uint8_t device_uuid[VK_UUID_SIZE];
794
795 struct wsi_device wsi_device;
796 int local_fd;
797 };
798
799 struct anv_debug_report_callback {
800 /* Link in the 'callbacks' list in anv_instance struct. */
801 struct list_head link;
802 VkDebugReportFlagsEXT flags;
803 PFN_vkDebugReportCallbackEXT callback;
804 void * data;
805 };
806
807 struct anv_instance {
808 VK_LOADER_DATA _loader_data;
809
810 VkAllocationCallbacks alloc;
811
812 uint32_t apiVersion;
813 int physicalDeviceCount;
814 struct anv_physical_device physicalDevice;
815
816 /* VK_EXT_debug_report debug callbacks */
817 pthread_mutex_t callbacks_mutex;
818 struct list_head callbacks;
819 struct anv_debug_report_callback destroy_debug_cb;
820 };
821
822 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
823 void anv_finish_wsi(struct anv_physical_device *physical_device);
824
825 bool anv_instance_extension_supported(const char *name);
826 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
827 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
828 const char *name);
829
830 struct anv_queue {
831 VK_LOADER_DATA _loader_data;
832
833 struct anv_device * device;
834
835 struct anv_state_pool * pool;
836 };
837
838 struct anv_pipeline_cache {
839 struct anv_device * device;
840 pthread_mutex_t mutex;
841
842 struct hash_table * cache;
843 };
844
845 struct anv_pipeline_bind_map;
846
847 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
848 struct anv_device *device,
849 bool cache_enabled);
850 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
851
852 struct anv_shader_bin *
853 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
854 const void *key, uint32_t key_size);
855 struct anv_shader_bin *
856 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
857 const void *key_data, uint32_t key_size,
858 const void *kernel_data, uint32_t kernel_size,
859 const struct brw_stage_prog_data *prog_data,
860 uint32_t prog_data_size,
861 const struct anv_pipeline_bind_map *bind_map);
862
863 struct anv_device {
864 VK_LOADER_DATA _loader_data;
865
866 VkAllocationCallbacks alloc;
867
868 struct anv_instance * instance;
869 uint32_t chipset_id;
870 struct gen_device_info info;
871 struct isl_device isl_dev;
872 int context_id;
873 int fd;
874 bool can_chain_batches;
875 bool robust_buffer_access;
876
877 struct anv_bo_pool batch_bo_pool;
878
879 struct anv_bo_cache bo_cache;
880
881 struct anv_state_pool dynamic_state_pool;
882 struct anv_state_pool instruction_state_pool;
883 struct anv_state_pool surface_state_pool;
884
885 struct anv_bo workaround_bo;
886 struct anv_bo trivial_batch_bo;
887
888 struct anv_pipeline_cache blorp_shader_cache;
889 struct blorp_context blorp;
890
891 struct anv_state border_colors;
892
893 struct anv_queue queue;
894
895 struct anv_scratch_pool scratch_pool;
896
897 uint32_t default_mocs;
898
899 pthread_mutex_t mutex;
900 pthread_cond_t queue_submit;
901 bool lost;
902 };
903
904 static void inline
905 anv_state_flush(struct anv_device *device, struct anv_state state)
906 {
907 if (device->info.has_llc)
908 return;
909
910 gen_flush_range(state.map, state.alloc_size);
911 }
912
913 void anv_device_init_blorp(struct anv_device *device);
914 void anv_device_finish_blorp(struct anv_device *device);
915
916 VkResult anv_device_execbuf(struct anv_device *device,
917 struct drm_i915_gem_execbuffer2 *execbuf,
918 struct anv_bo **execbuf_bos);
919 VkResult anv_device_query_status(struct anv_device *device);
920 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
921 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
922 int64_t timeout);
923
924 void* anv_gem_mmap(struct anv_device *device,
925 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
926 void anv_gem_munmap(void *p, uint64_t size);
927 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
928 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
929 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
930 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
931 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
932 int anv_gem_execbuffer(struct anv_device *device,
933 struct drm_i915_gem_execbuffer2 *execbuf);
934 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
935 uint32_t stride, uint32_t tiling);
936 int anv_gem_create_context(struct anv_device *device);
937 int anv_gem_destroy_context(struct anv_device *device, int context);
938 int anv_gem_get_context_param(int fd, int context, uint32_t param,
939 uint64_t *value);
940 int anv_gem_get_param(int fd, uint32_t param);
941 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
942 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
943 int anv_gem_get_aperture(int fd, uint64_t *size);
944 bool anv_gem_supports_48b_addresses(int fd);
945 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
946 uint32_t *active, uint32_t *pending);
947 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
948 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
949 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
950 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
951 uint32_t read_domains, uint32_t write_domain);
952 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
953 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
954 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
955 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
956 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
957 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
958 uint32_t handle);
959 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
960 uint32_t handle, int fd);
961 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
962 bool anv_gem_supports_syncobj_wait(int fd);
963 int anv_gem_syncobj_wait(struct anv_device *device,
964 uint32_t *handles, uint32_t num_handles,
965 int64_t abs_timeout_ns, bool wait_all);
966
967 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
968
969 struct anv_reloc_list {
970 uint32_t num_relocs;
971 uint32_t array_length;
972 struct drm_i915_gem_relocation_entry * relocs;
973 struct anv_bo ** reloc_bos;
974 };
975
976 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
977 const VkAllocationCallbacks *alloc);
978 void anv_reloc_list_finish(struct anv_reloc_list *list,
979 const VkAllocationCallbacks *alloc);
980
981 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
982 const VkAllocationCallbacks *alloc,
983 uint32_t offset, struct anv_bo *target_bo,
984 uint32_t delta);
985
986 struct anv_batch_bo {
987 /* Link in the anv_cmd_buffer.owned_batch_bos list */
988 struct list_head link;
989
990 struct anv_bo bo;
991
992 /* Bytes actually consumed in this batch BO */
993 uint32_t length;
994
995 struct anv_reloc_list relocs;
996 };
997
998 struct anv_batch {
999 const VkAllocationCallbacks * alloc;
1000
1001 void * start;
1002 void * end;
1003 void * next;
1004
1005 struct anv_reloc_list * relocs;
1006
1007 /* This callback is called (with the associated user data) in the event
1008 * that the batch runs out of space.
1009 */
1010 VkResult (*extend_cb)(struct anv_batch *, void *);
1011 void * user_data;
1012
1013 /**
1014 * Current error status of the command buffer. Used to track inconsistent
1015 * or incomplete command buffer states that are the consequence of run-time
1016 * errors such as out of memory scenarios. We want to track this in the
1017 * batch because the command buffer object is not visible to some parts
1018 * of the driver.
1019 */
1020 VkResult status;
1021 };
1022
1023 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1024 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1025 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1026 void *location, struct anv_bo *bo, uint32_t offset);
1027 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1028 struct anv_batch *batch);
1029
1030 static inline VkResult
1031 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1032 {
1033 assert(error != VK_SUCCESS);
1034 if (batch->status == VK_SUCCESS)
1035 batch->status = error;
1036 return batch->status;
1037 }
1038
1039 static inline bool
1040 anv_batch_has_error(struct anv_batch *batch)
1041 {
1042 return batch->status != VK_SUCCESS;
1043 }
1044
1045 struct anv_address {
1046 struct anv_bo *bo;
1047 uint32_t offset;
1048 };
1049
1050 static inline uint64_t
1051 _anv_combine_address(struct anv_batch *batch, void *location,
1052 const struct anv_address address, uint32_t delta)
1053 {
1054 if (address.bo == NULL) {
1055 return address.offset + delta;
1056 } else {
1057 assert(batch->start <= location && location < batch->end);
1058
1059 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1060 }
1061 }
1062
1063 #define __gen_address_type struct anv_address
1064 #define __gen_user_data struct anv_batch
1065 #define __gen_combine_address _anv_combine_address
1066
1067 /* Wrapper macros needed to work around preprocessor argument issues. In
1068 * particular, arguments don't get pre-evaluated if they are concatenated.
1069 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1070 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1071 * We can work around this easily enough with these helpers.
1072 */
1073 #define __anv_cmd_length(cmd) cmd ## _length
1074 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1075 #define __anv_cmd_header(cmd) cmd ## _header
1076 #define __anv_cmd_pack(cmd) cmd ## _pack
1077 #define __anv_reg_num(reg) reg ## _num
1078
1079 #define anv_pack_struct(dst, struc, ...) do { \
1080 struct struc __template = { \
1081 __VA_ARGS__ \
1082 }; \
1083 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1084 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1085 } while (0)
1086
1087 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1088 void *__dst = anv_batch_emit_dwords(batch, n); \
1089 if (__dst) { \
1090 struct cmd __template = { \
1091 __anv_cmd_header(cmd), \
1092 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1093 __VA_ARGS__ \
1094 }; \
1095 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1096 } \
1097 __dst; \
1098 })
1099
1100 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1101 do { \
1102 uint32_t *dw; \
1103 \
1104 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1105 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1106 if (!dw) \
1107 break; \
1108 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1109 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1110 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1111 } while (0)
1112
1113 #define anv_batch_emit(batch, cmd, name) \
1114 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1115 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1116 __builtin_expect(_dst != NULL, 1); \
1117 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1118 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1119 _dst = NULL; \
1120 }))
1121
1122 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1123 .GraphicsDataTypeGFDT = 0, \
1124 .LLCCacheabilityControlLLCCC = 0, \
1125 .L3CacheabilityControlL3CC = 1, \
1126 }
1127
1128 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1129 .LLCeLLCCacheabilityControlLLCCC = 0, \
1130 .L3CacheabilityControlL3CC = 1, \
1131 }
1132
1133 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1134 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1135 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1136 .AgeforQUADLRU = 0 \
1137 }
1138
1139 /* Skylake: MOCS is now an index into an array of 62 different caching
1140 * configurations programmed by the kernel.
1141 */
1142
1143 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1144 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1145 .IndextoMOCSTables = 2 \
1146 }
1147
1148 #define GEN9_MOCS_PTE { \
1149 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1150 .IndextoMOCSTables = 1 \
1151 }
1152
1153 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1154 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1155 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1156 .IndextoMOCSTables = 2 \
1157 }
1158
1159 #define GEN10_MOCS_PTE { \
1160 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1161 .IndextoMOCSTables = 1 \
1162 }
1163
1164 struct anv_device_memory {
1165 struct anv_bo * bo;
1166 struct anv_memory_type * type;
1167 VkDeviceSize map_size;
1168 void * map;
1169 };
1170
1171 /**
1172 * Header for Vertex URB Entry (VUE)
1173 */
1174 struct anv_vue_header {
1175 uint32_t Reserved;
1176 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1177 uint32_t ViewportIndex;
1178 float PointWidth;
1179 };
1180
1181 struct anv_descriptor_set_binding_layout {
1182 #ifndef NDEBUG
1183 /* The type of the descriptors in this binding */
1184 VkDescriptorType type;
1185 #endif
1186
1187 /* Number of array elements in this binding */
1188 uint16_t array_size;
1189
1190 /* Index into the flattend descriptor set */
1191 uint16_t descriptor_index;
1192
1193 /* Index into the dynamic state array for a dynamic buffer */
1194 int16_t dynamic_offset_index;
1195
1196 /* Index into the descriptor set buffer views */
1197 int16_t buffer_index;
1198
1199 struct {
1200 /* Index into the binding table for the associated surface */
1201 int16_t surface_index;
1202
1203 /* Index into the sampler table for the associated sampler */
1204 int16_t sampler_index;
1205
1206 /* Index into the image table for the associated image */
1207 int16_t image_index;
1208 } stage[MESA_SHADER_STAGES];
1209
1210 /* Immutable samplers (or NULL if no immutable samplers) */
1211 struct anv_sampler **immutable_samplers;
1212 };
1213
1214 struct anv_descriptor_set_layout {
1215 /* Number of bindings in this descriptor set */
1216 uint16_t binding_count;
1217
1218 /* Total size of the descriptor set with room for all array entries */
1219 uint16_t size;
1220
1221 /* Shader stages affected by this descriptor set */
1222 uint16_t shader_stages;
1223
1224 /* Number of buffers in this descriptor set */
1225 uint16_t buffer_count;
1226
1227 /* Number of dynamic offsets used by this descriptor set */
1228 uint16_t dynamic_offset_count;
1229
1230 /* Bindings in this descriptor set */
1231 struct anv_descriptor_set_binding_layout binding[0];
1232 };
1233
1234 struct anv_descriptor {
1235 VkDescriptorType type;
1236
1237 union {
1238 struct {
1239 VkImageLayout layout;
1240 struct anv_image_view *image_view;
1241 struct anv_sampler *sampler;
1242 };
1243
1244 struct {
1245 struct anv_buffer *buffer;
1246 uint64_t offset;
1247 uint64_t range;
1248 };
1249
1250 struct anv_buffer_view *buffer_view;
1251 };
1252 };
1253
1254 struct anv_descriptor_set {
1255 const struct anv_descriptor_set_layout *layout;
1256 uint32_t size;
1257 uint32_t buffer_count;
1258 struct anv_buffer_view *buffer_views;
1259 struct anv_descriptor descriptors[0];
1260 };
1261
1262 struct anv_buffer_view {
1263 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1264 struct anv_bo *bo;
1265 uint32_t offset; /**< Offset into bo. */
1266 uint64_t range; /**< VkBufferViewCreateInfo::range */
1267
1268 struct anv_state surface_state;
1269 struct anv_state storage_surface_state;
1270 struct anv_state writeonly_storage_surface_state;
1271
1272 struct brw_image_param storage_image_param;
1273 };
1274
1275 struct anv_push_descriptor_set {
1276 struct anv_descriptor_set set;
1277
1278 /* Put this field right behind anv_descriptor_set so it fills up the
1279 * descriptors[0] field. */
1280 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1281 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1282 };
1283
1284 struct anv_descriptor_pool {
1285 uint32_t size;
1286 uint32_t next;
1287 uint32_t free_list;
1288
1289 struct anv_state_stream surface_state_stream;
1290 void *surface_state_free_list;
1291
1292 char data[0];
1293 };
1294
1295 enum anv_descriptor_template_entry_type {
1296 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1297 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1298 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1299 };
1300
1301 struct anv_descriptor_template_entry {
1302 /* The type of descriptor in this entry */
1303 VkDescriptorType type;
1304
1305 /* Binding in the descriptor set */
1306 uint32_t binding;
1307
1308 /* Offset at which to write into the descriptor set binding */
1309 uint32_t array_element;
1310
1311 /* Number of elements to write into the descriptor set binding */
1312 uint32_t array_count;
1313
1314 /* Offset into the user provided data */
1315 size_t offset;
1316
1317 /* Stride between elements into the user provided data */
1318 size_t stride;
1319 };
1320
1321 struct anv_descriptor_update_template {
1322 /* The descriptor set this template corresponds to. This value is only
1323 * valid if the template was created with the templateType
1324 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1325 */
1326 uint8_t set;
1327
1328 /* Number of entries in this template */
1329 uint32_t entry_count;
1330
1331 /* Entries of the template */
1332 struct anv_descriptor_template_entry entries[0];
1333 };
1334
1335 size_t
1336 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1337
1338 size_t
1339 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1340
1341 void
1342 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1343 const struct gen_device_info * const devinfo,
1344 const VkDescriptorImageInfo * const info,
1345 VkDescriptorType type,
1346 uint32_t binding,
1347 uint32_t element);
1348
1349 void
1350 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1351 VkDescriptorType type,
1352 struct anv_buffer_view *buffer_view,
1353 uint32_t binding,
1354 uint32_t element);
1355
1356 void
1357 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1358 struct anv_device *device,
1359 struct anv_state_stream *alloc_stream,
1360 VkDescriptorType type,
1361 struct anv_buffer *buffer,
1362 uint32_t binding,
1363 uint32_t element,
1364 VkDeviceSize offset,
1365 VkDeviceSize range);
1366
1367 void
1368 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1369 struct anv_device *device,
1370 struct anv_state_stream *alloc_stream,
1371 const struct anv_descriptor_update_template *template,
1372 const void *data);
1373
1374 VkResult
1375 anv_descriptor_set_create(struct anv_device *device,
1376 struct anv_descriptor_pool *pool,
1377 const struct anv_descriptor_set_layout *layout,
1378 struct anv_descriptor_set **out_set);
1379
1380 void
1381 anv_descriptor_set_destroy(struct anv_device *device,
1382 struct anv_descriptor_pool *pool,
1383 struct anv_descriptor_set *set);
1384
1385 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1386
1387 struct anv_pipeline_binding {
1388 /* The descriptor set this surface corresponds to. The special value of
1389 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1390 * to a color attachment and not a regular descriptor.
1391 */
1392 uint8_t set;
1393
1394 /* Binding in the descriptor set */
1395 uint32_t binding;
1396
1397 /* Index in the binding */
1398 uint32_t index;
1399
1400 /* Plane in the binding index */
1401 uint8_t plane;
1402
1403 /* Input attachment index (relative to the subpass) */
1404 uint8_t input_attachment_index;
1405
1406 /* For a storage image, whether it is write-only */
1407 bool write_only;
1408 };
1409
1410 struct anv_pipeline_layout {
1411 struct {
1412 struct anv_descriptor_set_layout *layout;
1413 uint32_t dynamic_offset_start;
1414 } set[MAX_SETS];
1415
1416 uint32_t num_sets;
1417
1418 struct {
1419 bool has_dynamic_offsets;
1420 } stage[MESA_SHADER_STAGES];
1421
1422 unsigned char sha1[20];
1423 };
1424
1425 struct anv_buffer {
1426 struct anv_device * device;
1427 VkDeviceSize size;
1428
1429 VkBufferUsageFlags usage;
1430
1431 /* Set when bound */
1432 struct anv_bo * bo;
1433 VkDeviceSize offset;
1434 };
1435
1436 static inline uint64_t
1437 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1438 {
1439 assert(offset <= buffer->size);
1440 if (range == VK_WHOLE_SIZE) {
1441 return buffer->size - offset;
1442 } else {
1443 assert(range <= buffer->size);
1444 return range;
1445 }
1446 }
1447
1448 enum anv_cmd_dirty_bits {
1449 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1450 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1451 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1452 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1453 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1454 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1455 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1456 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1457 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1458 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1459 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1460 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1461 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1462 };
1463 typedef uint32_t anv_cmd_dirty_mask_t;
1464
1465 enum anv_pipe_bits {
1466 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1467 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1468 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1469 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1470 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1471 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1472 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1473 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1474 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1475 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1476 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1477
1478 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1479 * a flush has happened but not a CS stall. The next time we do any sort
1480 * of invalidation we need to insert a CS stall at that time. Otherwise,
1481 * we would have to CS stall on every flush which could be bad.
1482 */
1483 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1484 };
1485
1486 #define ANV_PIPE_FLUSH_BITS ( \
1487 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1488 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1489 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1490
1491 #define ANV_PIPE_STALL_BITS ( \
1492 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1493 ANV_PIPE_DEPTH_STALL_BIT | \
1494 ANV_PIPE_CS_STALL_BIT)
1495
1496 #define ANV_PIPE_INVALIDATE_BITS ( \
1497 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1498 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1499 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1500 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1501 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1502 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1503
1504 static inline enum anv_pipe_bits
1505 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1506 {
1507 enum anv_pipe_bits pipe_bits = 0;
1508
1509 unsigned b;
1510 for_each_bit(b, flags) {
1511 switch ((VkAccessFlagBits)(1 << b)) {
1512 case VK_ACCESS_SHADER_WRITE_BIT:
1513 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1514 break;
1515 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1516 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1517 break;
1518 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1519 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1520 break;
1521 case VK_ACCESS_TRANSFER_WRITE_BIT:
1522 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1523 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1524 break;
1525 default:
1526 break; /* Nothing to do */
1527 }
1528 }
1529
1530 return pipe_bits;
1531 }
1532
1533 static inline enum anv_pipe_bits
1534 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1535 {
1536 enum anv_pipe_bits pipe_bits = 0;
1537
1538 unsigned b;
1539 for_each_bit(b, flags) {
1540 switch ((VkAccessFlagBits)(1 << b)) {
1541 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1542 case VK_ACCESS_INDEX_READ_BIT:
1543 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1544 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1545 break;
1546 case VK_ACCESS_UNIFORM_READ_BIT:
1547 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1548 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1549 break;
1550 case VK_ACCESS_SHADER_READ_BIT:
1551 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1552 case VK_ACCESS_TRANSFER_READ_BIT:
1553 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1554 break;
1555 default:
1556 break; /* Nothing to do */
1557 }
1558 }
1559
1560 return pipe_bits;
1561 }
1562
1563 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1564 VK_IMAGE_ASPECT_COLOR_BIT | \
1565 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1566 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1567 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1568 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1569 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1570 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1571 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1572
1573 struct anv_vertex_binding {
1574 struct anv_buffer * buffer;
1575 VkDeviceSize offset;
1576 };
1577
1578 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1579 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1580
1581 struct anv_push_constants {
1582 /* Current allocated size of this push constants data structure.
1583 * Because a decent chunk of it may not be used (images on SKL, for
1584 * instance), we won't actually allocate the entire structure up-front.
1585 */
1586 uint32_t size;
1587
1588 /* Push constant data provided by the client through vkPushConstants */
1589 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1590
1591 /* Image data for image_load_store on pre-SKL */
1592 struct brw_image_param images[MAX_IMAGES];
1593 };
1594
1595 struct anv_dynamic_state {
1596 struct {
1597 uint32_t count;
1598 VkViewport viewports[MAX_VIEWPORTS];
1599 } viewport;
1600
1601 struct {
1602 uint32_t count;
1603 VkRect2D scissors[MAX_SCISSORS];
1604 } scissor;
1605
1606 float line_width;
1607
1608 struct {
1609 float bias;
1610 float clamp;
1611 float slope;
1612 } depth_bias;
1613
1614 float blend_constants[4];
1615
1616 struct {
1617 float min;
1618 float max;
1619 } depth_bounds;
1620
1621 struct {
1622 uint32_t front;
1623 uint32_t back;
1624 } stencil_compare_mask;
1625
1626 struct {
1627 uint32_t front;
1628 uint32_t back;
1629 } stencil_write_mask;
1630
1631 struct {
1632 uint32_t front;
1633 uint32_t back;
1634 } stencil_reference;
1635 };
1636
1637 extern const struct anv_dynamic_state default_dynamic_state;
1638
1639 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1640 const struct anv_dynamic_state *src,
1641 uint32_t copy_mask);
1642
1643 struct anv_surface_state {
1644 struct anv_state state;
1645 /** Address of the surface referred to by this state
1646 *
1647 * This address is relative to the start of the BO.
1648 */
1649 uint64_t address;
1650 /* Address of the aux surface, if any
1651 *
1652 * This field is 0 if and only if no aux surface exists.
1653 *
1654 * This address is relative to the start of the BO. On gen7, the bottom 12
1655 * bits of this address include extra aux information.
1656 */
1657 uint64_t aux_address;
1658 };
1659
1660 /**
1661 * Attachment state when recording a renderpass instance.
1662 *
1663 * The clear value is valid only if there exists a pending clear.
1664 */
1665 struct anv_attachment_state {
1666 enum isl_aux_usage aux_usage;
1667 enum isl_aux_usage input_aux_usage;
1668 struct anv_surface_state color;
1669 struct anv_surface_state input;
1670
1671 VkImageLayout current_layout;
1672 VkImageAspectFlags pending_clear_aspects;
1673 bool fast_clear;
1674 VkClearValue clear_value;
1675 bool clear_color_is_zero_one;
1676 bool clear_color_is_zero;
1677 };
1678
1679 /** State required while building cmd buffer */
1680 struct anv_cmd_state {
1681 /* PIPELINE_SELECT.PipelineSelection */
1682 uint32_t current_pipeline;
1683 const struct gen_l3_config * current_l3_config;
1684 uint32_t vb_dirty;
1685 anv_cmd_dirty_mask_t dirty;
1686 anv_cmd_dirty_mask_t compute_dirty;
1687 enum anv_pipe_bits pending_pipe_bits;
1688 uint32_t num_workgroups_offset;
1689 struct anv_bo *num_workgroups_bo;
1690 VkShaderStageFlags descriptors_dirty;
1691 VkShaderStageFlags push_constants_dirty;
1692 uint32_t scratch_size;
1693 struct anv_pipeline * pipeline;
1694 struct anv_pipeline * compute_pipeline;
1695 struct anv_framebuffer * framebuffer;
1696 struct anv_render_pass * pass;
1697 struct anv_subpass * subpass;
1698 VkRect2D render_area;
1699 uint32_t restart_index;
1700 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1701 struct anv_descriptor_set * descriptors[MAX_SETS];
1702 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1703 VkShaderStageFlags push_constant_stages;
1704 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1705 struct anv_state binding_tables[MESA_SHADER_STAGES];
1706 struct anv_state samplers[MESA_SHADER_STAGES];
1707 struct anv_dynamic_state dynamic;
1708 bool need_query_wa;
1709
1710 struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
1711
1712 /**
1713 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1714 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1715 * and before invoking the secondary in ExecuteCommands.
1716 */
1717 bool pma_fix_enabled;
1718
1719 /**
1720 * Whether or not we know for certain that HiZ is enabled for the current
1721 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1722 * enabled or not, this will be false.
1723 */
1724 bool hiz_enabled;
1725
1726 /**
1727 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1728 * valid only when recording a render pass instance.
1729 */
1730 struct anv_attachment_state * attachments;
1731
1732 /**
1733 * Surface states for color render targets. These are stored in a single
1734 * flat array. For depth-stencil attachments, the surface state is simply
1735 * left blank.
1736 */
1737 struct anv_state render_pass_states;
1738
1739 /**
1740 * A null surface state of the right size to match the framebuffer. This
1741 * is one of the states in render_pass_states.
1742 */
1743 struct anv_state null_surface_state;
1744
1745 struct {
1746 struct anv_buffer * index_buffer;
1747 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1748 uint32_t index_offset;
1749 } gen7;
1750 };
1751
1752 struct anv_cmd_pool {
1753 VkAllocationCallbacks alloc;
1754 struct list_head cmd_buffers;
1755 };
1756
1757 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1758
1759 enum anv_cmd_buffer_exec_mode {
1760 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1761 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1762 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1763 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1764 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1765 };
1766
1767 struct anv_cmd_buffer {
1768 VK_LOADER_DATA _loader_data;
1769
1770 struct anv_device * device;
1771
1772 struct anv_cmd_pool * pool;
1773 struct list_head pool_link;
1774
1775 struct anv_batch batch;
1776
1777 /* Fields required for the actual chain of anv_batch_bo's.
1778 *
1779 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1780 */
1781 struct list_head batch_bos;
1782 enum anv_cmd_buffer_exec_mode exec_mode;
1783
1784 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1785 * referenced by this command buffer
1786 *
1787 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1788 */
1789 struct u_vector seen_bbos;
1790
1791 /* A vector of int32_t's for every block of binding tables.
1792 *
1793 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1794 */
1795 struct u_vector bt_block_states;
1796 uint32_t bt_next;
1797
1798 struct anv_reloc_list surface_relocs;
1799 /** Last seen surface state block pool center bo offset */
1800 uint32_t last_ss_pool_center;
1801
1802 /* Serial for tracking buffer completion */
1803 uint32_t serial;
1804
1805 /* Stream objects for storing temporary data */
1806 struct anv_state_stream surface_state_stream;
1807 struct anv_state_stream dynamic_state_stream;
1808
1809 VkCommandBufferUsageFlags usage_flags;
1810 VkCommandBufferLevel level;
1811
1812 struct anv_cmd_state state;
1813 };
1814
1815 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1816 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1817 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1818 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1819 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1820 struct anv_cmd_buffer *secondary);
1821 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1822 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1823 struct anv_cmd_buffer *cmd_buffer,
1824 const VkSemaphore *in_semaphores,
1825 uint32_t num_in_semaphores,
1826 const VkSemaphore *out_semaphores,
1827 uint32_t num_out_semaphores,
1828 VkFence fence);
1829
1830 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1831
1832 VkResult
1833 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1834 gl_shader_stage stage, uint32_t size);
1835 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1836 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1837 (offsetof(struct anv_push_constants, field) + \
1838 sizeof(cmd_buffer->state.push_constants[0]->field)))
1839
1840 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1841 const void *data, uint32_t size, uint32_t alignment);
1842 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1843 uint32_t *a, uint32_t *b,
1844 uint32_t dwords, uint32_t alignment);
1845
1846 struct anv_address
1847 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1848 struct anv_state
1849 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1850 uint32_t entries, uint32_t *state_offset);
1851 struct anv_state
1852 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1853 struct anv_state
1854 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1855 uint32_t size, uint32_t alignment);
1856
1857 VkResult
1858 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1859
1860 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1861 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1862 bool depth_clamp_enable);
1863 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1864
1865 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1866 struct anv_render_pass *pass,
1867 struct anv_framebuffer *framebuffer,
1868 const VkClearValue *clear_values);
1869
1870 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1871
1872 struct anv_state
1873 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1874 gl_shader_stage stage);
1875 struct anv_state
1876 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1877
1878 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1879 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1880
1881 const struct anv_image_view *
1882 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1883
1884 VkResult
1885 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1886 uint32_t num_entries,
1887 uint32_t *state_offset,
1888 struct anv_state *bt_state);
1889
1890 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1891
1892 enum anv_fence_type {
1893 ANV_FENCE_TYPE_NONE = 0,
1894 ANV_FENCE_TYPE_BO,
1895 ANV_FENCE_TYPE_SYNCOBJ,
1896 };
1897
1898 enum anv_bo_fence_state {
1899 /** Indicates that this is a new (or newly reset fence) */
1900 ANV_BO_FENCE_STATE_RESET,
1901
1902 /** Indicates that this fence has been submitted to the GPU but is still
1903 * (as far as we know) in use by the GPU.
1904 */
1905 ANV_BO_FENCE_STATE_SUBMITTED,
1906
1907 ANV_BO_FENCE_STATE_SIGNALED,
1908 };
1909
1910 struct anv_fence_impl {
1911 enum anv_fence_type type;
1912
1913 union {
1914 /** Fence implementation for BO fences
1915 *
1916 * These fences use a BO and a set of CPU-tracked state flags. The BO
1917 * is added to the object list of the last execbuf call in a QueueSubmit
1918 * and is marked EXEC_WRITE. The state flags track when the BO has been
1919 * submitted to the kernel. We need to do this because Vulkan lets you
1920 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1921 * will say it's idle in this case.
1922 */
1923 struct {
1924 struct anv_bo bo;
1925 enum anv_bo_fence_state state;
1926 } bo;
1927
1928 /** DRM syncobj handle for syncobj-based fences */
1929 uint32_t syncobj;
1930 };
1931 };
1932
1933 struct anv_fence {
1934 /* Permanent fence state. Every fence has some form of permanent state
1935 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1936 * cross-process fences) or it could just be a dummy for use internally.
1937 */
1938 struct anv_fence_impl permanent;
1939
1940 /* Temporary fence state. A fence *may* have temporary state. That state
1941 * is added to the fence by an import operation and is reset back to
1942 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1943 * state cannot be signaled because the fence must already be signaled
1944 * before the temporary state can be exported from the fence in the other
1945 * process and imported here.
1946 */
1947 struct anv_fence_impl temporary;
1948 };
1949
1950 struct anv_event {
1951 uint64_t semaphore;
1952 struct anv_state state;
1953 };
1954
1955 enum anv_semaphore_type {
1956 ANV_SEMAPHORE_TYPE_NONE = 0,
1957 ANV_SEMAPHORE_TYPE_DUMMY,
1958 ANV_SEMAPHORE_TYPE_BO,
1959 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1960 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1961 };
1962
1963 struct anv_semaphore_impl {
1964 enum anv_semaphore_type type;
1965
1966 union {
1967 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1968 * This BO will be added to the object list on any execbuf2 calls for
1969 * which this semaphore is used as a wait or signal fence. When used as
1970 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1971 */
1972 struct anv_bo *bo;
1973
1974 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
1975 * If the semaphore is in the unsignaled state due to either just being
1976 * created or because it has been used for a wait, fd will be -1.
1977 */
1978 int fd;
1979
1980 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1981 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1982 * import so we don't need to bother with a userspace cache.
1983 */
1984 uint32_t syncobj;
1985 };
1986 };
1987
1988 struct anv_semaphore {
1989 /* Permanent semaphore state. Every semaphore has some form of permanent
1990 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1991 * (for cross-process semaphores0 or it could just be a dummy for use
1992 * internally.
1993 */
1994 struct anv_semaphore_impl permanent;
1995
1996 /* Temporary semaphore state. A semaphore *may* have temporary state.
1997 * That state is added to the semaphore by an import operation and is reset
1998 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1999 * semaphore with temporary state cannot be signaled because the semaphore
2000 * must already be signaled before the temporary state can be exported from
2001 * the semaphore in the other process and imported here.
2002 */
2003 struct anv_semaphore_impl temporary;
2004 };
2005
2006 void anv_semaphore_reset_temporary(struct anv_device *device,
2007 struct anv_semaphore *semaphore);
2008
2009 struct anv_shader_module {
2010 unsigned char sha1[20];
2011 uint32_t size;
2012 char data[0];
2013 };
2014
2015 static inline gl_shader_stage
2016 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2017 {
2018 assert(__builtin_popcount(vk_stage) == 1);
2019 return ffs(vk_stage) - 1;
2020 }
2021
2022 static inline VkShaderStageFlagBits
2023 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2024 {
2025 return (1 << mesa_stage);
2026 }
2027
2028 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2029
2030 #define anv_foreach_stage(stage, stage_bits) \
2031 for (gl_shader_stage stage, \
2032 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2033 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2034 __tmp &= ~(1 << (stage)))
2035
2036 struct anv_pipeline_bind_map {
2037 uint32_t surface_count;
2038 uint32_t sampler_count;
2039 uint32_t image_count;
2040
2041 struct anv_pipeline_binding * surface_to_descriptor;
2042 struct anv_pipeline_binding * sampler_to_descriptor;
2043 };
2044
2045 struct anv_shader_bin_key {
2046 uint32_t size;
2047 uint8_t data[0];
2048 };
2049
2050 struct anv_shader_bin {
2051 uint32_t ref_cnt;
2052
2053 const struct anv_shader_bin_key *key;
2054
2055 struct anv_state kernel;
2056 uint32_t kernel_size;
2057
2058 const struct brw_stage_prog_data *prog_data;
2059 uint32_t prog_data_size;
2060
2061 struct anv_pipeline_bind_map bind_map;
2062 };
2063
2064 struct anv_shader_bin *
2065 anv_shader_bin_create(struct anv_device *device,
2066 const void *key, uint32_t key_size,
2067 const void *kernel, uint32_t kernel_size,
2068 const struct brw_stage_prog_data *prog_data,
2069 uint32_t prog_data_size, const void *prog_data_param,
2070 const struct anv_pipeline_bind_map *bind_map);
2071
2072 void
2073 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2074
2075 static inline void
2076 anv_shader_bin_ref(struct anv_shader_bin *shader)
2077 {
2078 assert(shader && shader->ref_cnt >= 1);
2079 p_atomic_inc(&shader->ref_cnt);
2080 }
2081
2082 static inline void
2083 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2084 {
2085 assert(shader && shader->ref_cnt >= 1);
2086 if (p_atomic_dec_zero(&shader->ref_cnt))
2087 anv_shader_bin_destroy(device, shader);
2088 }
2089
2090 struct anv_pipeline {
2091 struct anv_device * device;
2092 struct anv_batch batch;
2093 uint32_t batch_data[512];
2094 struct anv_reloc_list batch_relocs;
2095 uint32_t dynamic_state_mask;
2096 struct anv_dynamic_state dynamic_state;
2097
2098 struct anv_subpass * subpass;
2099 struct anv_pipeline_layout * layout;
2100
2101 bool needs_data_cache;
2102
2103 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2104
2105 struct {
2106 const struct gen_l3_config * l3_config;
2107 uint32_t total_size;
2108 } urb;
2109
2110 VkShaderStageFlags active_stages;
2111 struct anv_state blend_state;
2112
2113 uint32_t vb_used;
2114 uint32_t binding_stride[MAX_VBS];
2115 bool instancing_enable[MAX_VBS];
2116 bool primitive_restart;
2117 uint32_t topology;
2118
2119 uint32_t cs_right_mask;
2120
2121 bool writes_depth;
2122 bool depth_test_enable;
2123 bool writes_stencil;
2124 bool stencil_test_enable;
2125 bool depth_clamp_enable;
2126 bool sample_shading_enable;
2127 bool kill_pixel;
2128
2129 struct {
2130 uint32_t sf[7];
2131 uint32_t depth_stencil_state[3];
2132 } gen7;
2133
2134 struct {
2135 uint32_t sf[4];
2136 uint32_t raster[5];
2137 uint32_t wm_depth_stencil[3];
2138 } gen8;
2139
2140 struct {
2141 uint32_t wm_depth_stencil[4];
2142 } gen9;
2143
2144 uint32_t interface_descriptor_data[8];
2145 };
2146
2147 static inline bool
2148 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2149 gl_shader_stage stage)
2150 {
2151 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2152 }
2153
2154 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2155 static inline const struct brw_##prefix##_prog_data * \
2156 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2157 { \
2158 if (anv_pipeline_has_stage(pipeline, stage)) { \
2159 return (const struct brw_##prefix##_prog_data *) \
2160 pipeline->shaders[stage]->prog_data; \
2161 } else { \
2162 return NULL; \
2163 } \
2164 }
2165
2166 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2167 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2168 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2169 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2170 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2171 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2172
2173 static inline const struct brw_vue_prog_data *
2174 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2175 {
2176 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2177 return &get_gs_prog_data(pipeline)->base;
2178 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2179 return &get_tes_prog_data(pipeline)->base;
2180 else
2181 return &get_vs_prog_data(pipeline)->base;
2182 }
2183
2184 VkResult
2185 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2186 struct anv_pipeline_cache *cache,
2187 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2188 const VkAllocationCallbacks *alloc);
2189
2190 VkResult
2191 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2192 struct anv_pipeline_cache *cache,
2193 const VkComputePipelineCreateInfo *info,
2194 struct anv_shader_module *module,
2195 const char *entrypoint,
2196 const VkSpecializationInfo *spec_info);
2197
2198 struct anv_format_plane {
2199 enum isl_format isl_format:16;
2200 struct isl_swizzle swizzle;
2201
2202 /* Whether this plane contains chroma channels */
2203 bool has_chroma;
2204
2205 /* For downscaling of YUV planes */
2206 uint8_t denominator_scales[2];
2207
2208 /* How to map sampled ycbcr planes to a single 4 component element. */
2209 struct isl_swizzle ycbcr_swizzle;
2210 };
2211
2212
2213 struct anv_format {
2214 struct anv_format_plane planes[3];
2215 uint8_t n_planes;
2216 bool can_ycbcr;
2217 };
2218
2219 static inline uint32_t
2220 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2221 VkImageAspectFlags aspect_mask)
2222 {
2223 switch (aspect_mask) {
2224 case VK_IMAGE_ASPECT_COLOR_BIT:
2225 case VK_IMAGE_ASPECT_DEPTH_BIT:
2226 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2227 return 0;
2228 case VK_IMAGE_ASPECT_STENCIL_BIT:
2229 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2230 return 0;
2231 /* Fall-through */
2232 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2233 return 1;
2234 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2235 return 2;
2236 default:
2237 /* Purposefully assert with depth/stencil aspects. */
2238 unreachable("invalid image aspect");
2239 }
2240 }
2241
2242 static inline uint32_t
2243 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2244 {
2245 uint32_t planes = 0;
2246
2247 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2248 VK_IMAGE_ASPECT_DEPTH_BIT |
2249 VK_IMAGE_ASPECT_STENCIL_BIT |
2250 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2251 planes++;
2252 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2253 planes++;
2254 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2255 planes++;
2256
2257 return planes;
2258 }
2259
2260 static inline VkImageAspectFlags
2261 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2262 uint32_t plane)
2263 {
2264 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2265 if (_mesa_bitcount(image_aspects) > 1)
2266 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2267 return VK_IMAGE_ASPECT_COLOR_BIT;
2268 }
2269 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2270 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2271 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2272 return VK_IMAGE_ASPECT_STENCIL_BIT;
2273 }
2274
2275 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2276 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2277
2278 const struct anv_format *
2279 anv_get_format(VkFormat format);
2280
2281 static inline uint32_t
2282 anv_get_format_planes(VkFormat vk_format)
2283 {
2284 const struct anv_format *format = anv_get_format(vk_format);
2285
2286 return format != NULL ? format->n_planes : 0;
2287 }
2288
2289 struct anv_format_plane
2290 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2291 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2292
2293 static inline enum isl_format
2294 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2295 VkImageAspectFlags aspect, VkImageTiling tiling)
2296 {
2297 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2298 }
2299
2300 static inline struct isl_swizzle
2301 anv_swizzle_for_render(struct isl_swizzle swizzle)
2302 {
2303 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2304 * RGB as RGBA for texturing
2305 */
2306 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2307 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2308
2309 /* But it doesn't matter what we render to that channel */
2310 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2311
2312 return swizzle;
2313 }
2314
2315 void
2316 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2317
2318 /**
2319 * Subsurface of an anv_image.
2320 */
2321 struct anv_surface {
2322 /** Valid only if isl_surf::size > 0. */
2323 struct isl_surf isl;
2324
2325 /**
2326 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2327 */
2328 uint32_t offset;
2329 };
2330
2331 struct anv_image {
2332 VkImageType type;
2333 /* The original VkFormat provided by the client. This may not match any
2334 * of the actual surface formats.
2335 */
2336 VkFormat vk_format;
2337 const struct anv_format *format;
2338
2339 VkImageAspectFlags aspects;
2340 VkExtent3D extent;
2341 uint32_t levels;
2342 uint32_t array_size;
2343 uint32_t samples; /**< VkImageCreateInfo::samples */
2344 uint32_t n_planes;
2345 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2346 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2347
2348 /**
2349 * DRM format modifier for this image or DRM_FORMAT_MOD_INVALID.
2350 */
2351 uint64_t drm_format_mod;
2352
2353 VkDeviceSize size;
2354 uint32_t alignment;
2355
2356 /* Whether the image is made of several underlying buffer objects rather a
2357 * single one with different offsets.
2358 */
2359 bool disjoint;
2360
2361 /**
2362 * Image subsurfaces
2363 *
2364 * For each foo, anv_image::planes[x].surface is valid if and only if
2365 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2366 * to figure the number associated with a given aspect.
2367 *
2368 * The hardware requires that the depth buffer and stencil buffer be
2369 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2370 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2371 * allocate the depth and stencil buffers as separate surfaces in the same
2372 * bo.
2373 *
2374 * Memory layout :
2375 *
2376 * -----------------------
2377 * | surface0 | /|\
2378 * ----------------------- |
2379 * | shadow surface0 | |
2380 * ----------------------- | Plane 0
2381 * | aux surface0 | |
2382 * ----------------------- |
2383 * | fast clear colors0 | \|/
2384 * -----------------------
2385 * | surface1 | /|\
2386 * ----------------------- |
2387 * | shadow surface1 | |
2388 * ----------------------- | Plane 1
2389 * | aux surface1 | |
2390 * ----------------------- |
2391 * | fast clear colors1 | \|/
2392 * -----------------------
2393 * | ... |
2394 * | |
2395 * -----------------------
2396 */
2397 struct {
2398 /**
2399 * Offset of the entire plane (whenever the image is disjoint this is
2400 * set to 0).
2401 */
2402 uint32_t offset;
2403
2404 VkDeviceSize size;
2405 uint32_t alignment;
2406
2407 struct anv_surface surface;
2408
2409 /**
2410 * A surface which shadows the main surface and may have different
2411 * tiling. This is used for sampling using a tiling that isn't supported
2412 * for other operations.
2413 */
2414 struct anv_surface shadow_surface;
2415
2416 /**
2417 * For color images, this is the aux usage for this image when not used
2418 * as a color attachment.
2419 *
2420 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2421 * image has a HiZ buffer.
2422 */
2423 enum isl_aux_usage aux_usage;
2424
2425 struct anv_surface aux_surface;
2426
2427 /**
2428 * Offset of the fast clear state (used to compute the
2429 * fast_clear_state_offset of the following planes).
2430 */
2431 uint32_t fast_clear_state_offset;
2432
2433 /**
2434 * BO associated with this plane, set when bound.
2435 */
2436 struct anv_bo *bo;
2437 VkDeviceSize bo_offset;
2438
2439 /**
2440 * When destroying the image, also free the bo.
2441 * */
2442 bool bo_is_owned;
2443 } planes[3];
2444 };
2445
2446 /* Returns the number of auxiliary buffer levels attached to an image. */
2447 static inline uint8_t
2448 anv_image_aux_levels(const struct anv_image * const image,
2449 VkImageAspectFlagBits aspect)
2450 {
2451 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2452 return image->planes[plane].aux_surface.isl.size > 0 ?
2453 image->planes[plane].aux_surface.isl.levels : 0;
2454 }
2455
2456 /* Returns the number of auxiliary buffer layers attached to an image. */
2457 static inline uint32_t
2458 anv_image_aux_layers(const struct anv_image * const image,
2459 VkImageAspectFlagBits aspect,
2460 const uint8_t miplevel)
2461 {
2462 assert(image);
2463
2464 /* The miplevel must exist in the main buffer. */
2465 assert(miplevel < image->levels);
2466
2467 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2468 /* There are no layers with auxiliary data because the miplevel has no
2469 * auxiliary data.
2470 */
2471 return 0;
2472 } else {
2473 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2474 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2475 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2476 }
2477 }
2478
2479 static inline unsigned
2480 anv_fast_clear_state_entry_size(const struct anv_device *device)
2481 {
2482 assert(device);
2483 /* Entry contents:
2484 * +--------------------------------------------+
2485 * | clear value dword(s) | needs resolve dword |
2486 * +--------------------------------------------+
2487 */
2488
2489 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2490 * GPU memcpy operations.
2491 */
2492 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2493 return device->isl_dev.ss.clear_value_size + 4;
2494 }
2495
2496 static inline struct anv_address
2497 anv_image_get_clear_color_addr(const struct anv_device *device,
2498 const struct anv_image *image,
2499 VkImageAspectFlagBits aspect,
2500 unsigned level)
2501 {
2502 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2503 return (struct anv_address) {
2504 .bo = image->planes[plane].bo,
2505 .offset = image->planes[plane].bo_offset +
2506 image->planes[plane].fast_clear_state_offset +
2507 anv_fast_clear_state_entry_size(device) * level,
2508 };
2509 }
2510
2511 static inline struct anv_address
2512 anv_image_get_needs_resolve_addr(const struct anv_device *device,
2513 const struct anv_image *image,
2514 VkImageAspectFlagBits aspect,
2515 unsigned level)
2516 {
2517 struct anv_address addr =
2518 anv_image_get_clear_color_addr(device, image, aspect, level);
2519 addr.offset += device->isl_dev.ss.clear_value_size;
2520 return addr;
2521 }
2522
2523 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2524 static inline bool
2525 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2526 const struct anv_image *image)
2527 {
2528 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2529 return false;
2530
2531 if (devinfo->gen < 8)
2532 return false;
2533
2534 return image->samples == 1;
2535 }
2536
2537 void
2538 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2539 const struct anv_image *image,
2540 enum blorp_hiz_op op);
2541 void
2542 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2543 const struct anv_image * const image,
2544 VkImageAspectFlagBits aspect,
2545 const uint8_t level,
2546 const uint32_t start_layer, const uint32_t layer_count,
2547 const enum blorp_fast_clear_op op);
2548
2549 void
2550 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2551 const struct anv_image *image,
2552 VkImageAspectFlagBits aspect,
2553 const uint32_t base_level, const uint32_t level_count,
2554 const uint32_t base_layer, uint32_t layer_count);
2555
2556 void
2557 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2558 const struct anv_image *image,
2559 uint32_t base_level, uint32_t level_count,
2560 uint32_t base_layer, uint32_t layer_count);
2561
2562 enum isl_aux_usage
2563 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2564 const struct anv_image *image,
2565 const VkImageAspectFlagBits aspect,
2566 const VkImageLayout layout);
2567
2568 /* This is defined as a macro so that it works for both
2569 * VkImageSubresourceRange and VkImageSubresourceLayers
2570 */
2571 #define anv_get_layerCount(_image, _range) \
2572 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2573 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2574
2575 static inline uint32_t
2576 anv_get_levelCount(const struct anv_image *image,
2577 const VkImageSubresourceRange *range)
2578 {
2579 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2580 image->levels - range->baseMipLevel : range->levelCount;
2581 }
2582
2583 static inline VkImageAspectFlags
2584 anv_image_expand_aspects(const struct anv_image *image,
2585 VkImageAspectFlags aspects)
2586 {
2587 /* If the underlying image has color plane aspects and
2588 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2589 * the underlying image. */
2590 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2591 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2592 return image->aspects;
2593
2594 return aspects;
2595 }
2596
2597 static inline bool
2598 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2599 VkImageAspectFlags aspects2)
2600 {
2601 if (aspects1 == aspects2)
2602 return true;
2603
2604 /* Only 1 color aspects are compatibles. */
2605 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2606 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2607 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2608 return true;
2609
2610 return false;
2611 }
2612
2613 struct anv_image_view {
2614 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2615
2616 VkImageAspectFlags aspect_mask;
2617 VkFormat vk_format;
2618 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2619
2620 unsigned n_planes;
2621 struct {
2622 uint32_t image_plane;
2623
2624 struct isl_view isl;
2625
2626 /**
2627 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2628 * image layout of SHADER_READ_ONLY_OPTIMAL or
2629 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2630 */
2631 struct anv_surface_state optimal_sampler_surface_state;
2632
2633 /**
2634 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2635 * image layout of GENERAL.
2636 */
2637 struct anv_surface_state general_sampler_surface_state;
2638
2639 /**
2640 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2641 * states for write-only and readable, using the real format for
2642 * write-only and the lowered format for readable.
2643 */
2644 struct anv_surface_state storage_surface_state;
2645 struct anv_surface_state writeonly_storage_surface_state;
2646
2647 struct brw_image_param storage_image_param;
2648 } planes[3];
2649 };
2650
2651 enum anv_image_view_state_flags {
2652 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2653 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2654 };
2655
2656 void anv_image_fill_surface_state(struct anv_device *device,
2657 const struct anv_image *image,
2658 VkImageAspectFlagBits aspect,
2659 const struct isl_view *view,
2660 isl_surf_usage_flags_t view_usage,
2661 enum isl_aux_usage aux_usage,
2662 const union isl_color_value *clear_color,
2663 enum anv_image_view_state_flags flags,
2664 struct anv_surface_state *state_inout,
2665 struct brw_image_param *image_param_out);
2666
2667 struct anv_image_create_info {
2668 const VkImageCreateInfo *vk_info;
2669
2670 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2671 isl_tiling_flags_t isl_tiling_flags;
2672
2673 /** These flags will be added to any derived from VkImageCreateInfo. */
2674 isl_surf_usage_flags_t isl_extra_usage_flags;
2675
2676 uint32_t stride;
2677 };
2678
2679 VkResult anv_image_create(VkDevice _device,
2680 const struct anv_image_create_info *info,
2681 const VkAllocationCallbacks* alloc,
2682 VkImage *pImage);
2683
2684 #ifdef ANDROID
2685 VkResult anv_image_from_gralloc(VkDevice device_h,
2686 const VkImageCreateInfo *base_info,
2687 const VkNativeBufferANDROID *gralloc_info,
2688 const VkAllocationCallbacks *alloc,
2689 VkImage *pImage);
2690 #endif
2691
2692 const struct anv_surface *
2693 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2694 VkImageAspectFlags aspect_mask);
2695
2696 enum isl_format
2697 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2698
2699 static inline struct VkExtent3D
2700 anv_sanitize_image_extent(const VkImageType imageType,
2701 const struct VkExtent3D imageExtent)
2702 {
2703 switch (imageType) {
2704 case VK_IMAGE_TYPE_1D:
2705 return (VkExtent3D) { imageExtent.width, 1, 1 };
2706 case VK_IMAGE_TYPE_2D:
2707 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2708 case VK_IMAGE_TYPE_3D:
2709 return imageExtent;
2710 default:
2711 unreachable("invalid image type");
2712 }
2713 }
2714
2715 static inline struct VkOffset3D
2716 anv_sanitize_image_offset(const VkImageType imageType,
2717 const struct VkOffset3D imageOffset)
2718 {
2719 switch (imageType) {
2720 case VK_IMAGE_TYPE_1D:
2721 return (VkOffset3D) { imageOffset.x, 0, 0 };
2722 case VK_IMAGE_TYPE_2D:
2723 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2724 case VK_IMAGE_TYPE_3D:
2725 return imageOffset;
2726 default:
2727 unreachable("invalid image type");
2728 }
2729 }
2730
2731
2732 void anv_fill_buffer_surface_state(struct anv_device *device,
2733 struct anv_state state,
2734 enum isl_format format,
2735 uint32_t offset, uint32_t range,
2736 uint32_t stride);
2737
2738
2739 struct anv_ycbcr_conversion {
2740 const struct anv_format * format;
2741 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2742 VkSamplerYcbcrRangeKHR ycbcr_range;
2743 VkComponentSwizzle mapping[4];
2744 VkChromaLocationKHR chroma_offsets[2];
2745 VkFilter chroma_filter;
2746 bool chroma_reconstruction;
2747 };
2748
2749 struct anv_sampler {
2750 uint32_t state[3][4];
2751 uint32_t n_planes;
2752 struct anv_ycbcr_conversion *conversion;
2753 };
2754
2755 struct anv_framebuffer {
2756 uint32_t width;
2757 uint32_t height;
2758 uint32_t layers;
2759
2760 uint32_t attachment_count;
2761 struct anv_image_view * attachments[0];
2762 };
2763
2764 struct anv_subpass {
2765 uint32_t attachment_count;
2766
2767 /**
2768 * A pointer to all attachment references used in this subpass.
2769 * Only valid if ::attachment_count > 0.
2770 */
2771 VkAttachmentReference * attachments;
2772 uint32_t input_count;
2773 VkAttachmentReference * input_attachments;
2774 uint32_t color_count;
2775 VkAttachmentReference * color_attachments;
2776 VkAttachmentReference * resolve_attachments;
2777
2778 VkAttachmentReference depth_stencil_attachment;
2779
2780 uint32_t view_mask;
2781
2782 /** Subpass has a depth/stencil self-dependency */
2783 bool has_ds_self_dep;
2784
2785 /** Subpass has at least one resolve attachment */
2786 bool has_resolve;
2787 };
2788
2789 static inline unsigned
2790 anv_subpass_view_count(const struct anv_subpass *subpass)
2791 {
2792 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2793 }
2794
2795 struct anv_render_pass_attachment {
2796 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2797 * its members individually.
2798 */
2799 VkFormat format;
2800 uint32_t samples;
2801 VkImageUsageFlags usage;
2802 VkAttachmentLoadOp load_op;
2803 VkAttachmentStoreOp store_op;
2804 VkAttachmentLoadOp stencil_load_op;
2805 VkImageLayout initial_layout;
2806 VkImageLayout final_layout;
2807 VkImageLayout first_subpass_layout;
2808
2809 /* The subpass id in which the attachment will be used last. */
2810 uint32_t last_subpass_idx;
2811 };
2812
2813 struct anv_render_pass {
2814 uint32_t attachment_count;
2815 uint32_t subpass_count;
2816 /* An array of subpass_count+1 flushes, one per subpass boundary */
2817 enum anv_pipe_bits * subpass_flushes;
2818 struct anv_render_pass_attachment * attachments;
2819 struct anv_subpass subpasses[0];
2820 };
2821
2822 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2823
2824 struct anv_query_pool {
2825 VkQueryType type;
2826 VkQueryPipelineStatisticFlags pipeline_statistics;
2827 /** Stride between slots, in bytes */
2828 uint32_t stride;
2829 /** Number of slots in this query pool */
2830 uint32_t slots;
2831 struct anv_bo bo;
2832 };
2833
2834 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2835 const char *name);
2836
2837 void anv_dump_image_to_ppm(struct anv_device *device,
2838 struct anv_image *image, unsigned miplevel,
2839 unsigned array_layer, VkImageAspectFlagBits aspect,
2840 const char *filename);
2841
2842 enum anv_dump_action {
2843 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2844 };
2845
2846 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2847 void anv_dump_finish(void);
2848
2849 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2850 struct anv_framebuffer *fb);
2851
2852 static inline uint32_t
2853 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2854 {
2855 /* This function must be called from within a subpass. */
2856 assert(cmd_state->pass && cmd_state->subpass);
2857
2858 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2859
2860 /* The id of this subpass shouldn't exceed the number of subpasses in this
2861 * render pass minus 1.
2862 */
2863 assert(subpass_id < cmd_state->pass->subpass_count);
2864 return subpass_id;
2865 }
2866
2867 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2868 \
2869 static inline struct __anv_type * \
2870 __anv_type ## _from_handle(__VkType _handle) \
2871 { \
2872 return (struct __anv_type *) _handle; \
2873 } \
2874 \
2875 static inline __VkType \
2876 __anv_type ## _to_handle(struct __anv_type *_obj) \
2877 { \
2878 return (__VkType) _obj; \
2879 }
2880
2881 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2882 \
2883 static inline struct __anv_type * \
2884 __anv_type ## _from_handle(__VkType _handle) \
2885 { \
2886 return (struct __anv_type *)(uintptr_t) _handle; \
2887 } \
2888 \
2889 static inline __VkType \
2890 __anv_type ## _to_handle(struct __anv_type *_obj) \
2891 { \
2892 return (__VkType)(uintptr_t) _obj; \
2893 }
2894
2895 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2896 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2897
2898 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2899 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2900 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2901 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2902 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2903
2904 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2905 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2906 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2907 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2908 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2909 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2910 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2911 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2912 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2913 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2914 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2915 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2916 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2917 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2918 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2919 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2920 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2921 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2922 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2923 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2924 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2925 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_debug_report_callback, VkDebugReportCallbackEXT)
2926 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
2927
2928 /* Gen-specific function declarations */
2929 #ifdef genX
2930 # include "anv_genX.h"
2931 #else
2932 # define genX(x) gen7_##x
2933 # include "anv_genX.h"
2934 # undef genX
2935 # define genX(x) gen75_##x
2936 # include "anv_genX.h"
2937 # undef genX
2938 # define genX(x) gen8_##x
2939 # include "anv_genX.h"
2940 # undef genX
2941 # define genX(x) gen9_##x
2942 # include "anv_genX.h"
2943 # undef genX
2944 # define genX(x) gen10_##x
2945 # include "anv_genX.h"
2946 # undef genX
2947 #endif
2948
2949 #endif /* ANV_PRIVATE_H */