2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/bitset.h"
53 #include "util/macros.h"
54 #include "util/hash_table.h"
55 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
74 struct anv_buffer_view
;
75 struct anv_image_view
;
78 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
131 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
132 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134 #define LOW_HEAP_SIZE \
135 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
136 #define DYNAMIC_STATE_POOL_SIZE \
137 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
138 #define BINDING_TABLE_POOL_SIZE \
139 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
140 #define SURFACE_STATE_POOL_SIZE \
141 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
142 #define INSTRUCTION_STATE_POOL_SIZE \
143 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
144 #define CLIENT_VISIBLE_HEAP_SIZE \
145 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147 /* Allowing different clear colors requires us to perform a depth resolve at
148 * the end of certain render passes. This is because while slow clears store
149 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
150 * See the PRMs for examples describing when additional resolves would be
151 * necessary. To enable fast clears without requiring extra resolves, we set
152 * the clear value to a globally-defined one. We could allow different values
153 * if the user doesn't expect coherent data during or after a render passes
154 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
155 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
156 * 1.0f seems to be the only value used. The only application that doesn't set
157 * this value does so through the usage of an seemingly uninitialized clear
160 #define ANV_HZ_FC_VAL 1.0f
163 #define MAX_XFB_BUFFERS 4
164 #define MAX_XFB_STREAMS 4
167 #define MAX_VIEWPORTS 16
168 #define MAX_SCISSORS 16
169 #define MAX_PUSH_CONSTANTS_SIZE 128
170 #define MAX_DYNAMIC_BUFFERS 16
171 #define MAX_IMAGES 64
172 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
173 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
174 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
178 * "The surface state model is used when a Binding Table Index (specified
179 * in the message descriptor) of less than 240 is specified. In this model,
180 * the Binding Table Index is used to index into the binding table, and the
181 * binding table entry contains a pointer to the SURFACE_STATE."
183 * Binding table values above 240 are used for various things in the hardware
184 * such as stateless, stateless with incoherent cache, SLM, and bindless.
186 #define MAX_BINDING_TABLE_SIZE 240
188 /* The kernel relocation API has a limitation of a 32-bit delta value
189 * applied to the address before it is written which, in spite of it being
190 * unsigned, is treated as signed . Because of the way that this maps to
191 * the Vulkan API, we cannot handle an offset into a buffer that does not
192 * fit into a signed 32 bits. The only mechanism we have for dealing with
193 * this at the moment is to limit all VkDeviceMemory objects to a maximum
194 * of 2GB each. The Vulkan spec allows us to do this:
196 * "Some platforms may have a limit on the maximum size of a single
197 * allocation. For example, certain systems may fail to create
198 * allocations with a size greater than or equal to 4GB. Such a limit is
199 * implementation-dependent, and if such a failure occurs then the error
200 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
202 * We don't use vk_error here because it's not an error so much as an
203 * indication to the application that the allocation is too large.
205 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
207 #define ANV_SVGS_VB_INDEX MAX_VBS
208 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
210 /* We reserve this MI ALU register for the purpose of handling predication.
211 * Other code which uses the MI ALU should leave it alone.
213 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
215 /* For gen12 we set the streamout buffers using 4 separate commands
216 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
217 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
218 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
219 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
220 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
221 * 3DSTATE_SO_BUFFER_INDEX_0.
223 #define SO_BUFFER_INDEX_0_CMD 0x60
224 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
226 static inline uint32_t
227 align_down_npot_u32(uint32_t v
, uint32_t a
)
232 static inline uint32_t
233 align_u32(uint32_t v
, uint32_t a
)
235 assert(a
!= 0 && a
== (a
& -a
));
236 return (v
+ a
- 1) & ~(a
- 1);
239 static inline uint64_t
240 align_u64(uint64_t v
, uint64_t a
)
242 assert(a
!= 0 && a
== (a
& -a
));
243 return (v
+ a
- 1) & ~(a
- 1);
246 static inline int32_t
247 align_i32(int32_t v
, int32_t a
)
249 assert(a
!= 0 && a
== (a
& -a
));
250 return (v
+ a
- 1) & ~(a
- 1);
253 /** Alignment must be a power of 2. */
255 anv_is_aligned(uintmax_t n
, uintmax_t a
)
257 assert(a
== (a
& -a
));
258 return (n
& (a
- 1)) == 0;
261 static inline uint32_t
262 anv_minify(uint32_t n
, uint32_t levels
)
264 if (unlikely(n
== 0))
267 return MAX2(n
>> levels
, 1);
271 anv_clamp_f(float f
, float min
, float max
)
284 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
286 if (*inout_mask
& clear_mask
) {
287 *inout_mask
&= ~clear_mask
;
294 static inline union isl_color_value
295 vk_to_isl_color(VkClearColorValue color
)
297 return (union isl_color_value
) {
307 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
309 uintptr_t mask
= (1ull << bits
) - 1;
311 return (void *) (ptr
& ~mask
);
314 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
316 uintptr_t value
= (uintptr_t) ptr
;
317 uintptr_t mask
= (1ull << bits
) - 1;
318 return value
| (mask
& flags
);
321 #define for_each_bit(b, dword) \
322 for (uint32_t __dword = (dword); \
323 (b) = __builtin_ffs(__dword) - 1, __dword; \
324 __dword &= ~(1 << (b)))
326 #define typed_memcpy(dest, src, count) ({ \
327 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
328 memcpy((dest), (src), (count) * sizeof(*(src))); \
331 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
332 * to be added here in order to utilize mapping in debug/error/perf macros.
334 #define REPORT_OBJECT_TYPE(o) \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), void*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
428 /* The void expression results in a compile-time error \
429 when assigning the result to something. */ \
430 (void)0)))))))))))))))))))))))))))))))
432 /* Whenever we generate an error, pass it through this function. Useful for
433 * debugging, where we can break on it. Only call at error site, not when
434 * propagating errors. Might be useful to plug in a stack trace here.
437 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
438 VkDebugReportObjectTypeEXT type
, VkResult error
,
439 const char *file
, int line
, const char *format
,
442 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
443 VkDebugReportObjectTypeEXT type
, VkResult error
,
444 const char *file
, int line
, const char *format
, ...)
445 anv_printflike(7, 8);
448 #define vk_error(error) __vk_errorf(NULL, NULL,\
449 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
450 error, __FILE__, __LINE__, NULL)
451 #define vk_errorv(instance, obj, error, format, args)\
452 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
453 __FILE__, __LINE__, format, args)
454 #define vk_errorf(instance, obj, error, format, ...)\
455 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
456 __FILE__, __LINE__, format, ## __VA_ARGS__)
458 #define vk_error(error) error
459 #define vk_errorf(instance, obj, error, format, ...) error
463 * Warn on ignored extension structs.
465 * The Vulkan spec requires us to ignore unsupported or unknown structs in
466 * a pNext chain. In debug mode, emitting warnings for ignored structs may
467 * help us discover structs that we should not have ignored.
470 * From the Vulkan 1.0.38 spec:
472 * Any component of the implementation (the loader, any enabled layers,
473 * and drivers) must skip over, without processing (other than reading the
474 * sType and pNext members) any chained structures with sType values not
475 * defined by extensions supported by that component.
477 #define anv_debug_ignored_stype(sType) \
478 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
480 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
481 VkDebugReportObjectTypeEXT type
, const char *file
,
482 int line
, const char *format
, ...)
483 anv_printflike(6, 7);
484 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
485 void anv_loge_v(const char *format
, va_list va
);
488 * Print a FINISHME message, including its source location.
490 #define anv_finishme(format, ...) \
492 static bool reported = false; \
494 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
501 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
503 #define anv_perf_warn(instance, obj, format, ...) \
505 static bool reported = false; \
506 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
507 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
508 format, ##__VA_ARGS__); \
513 /* A non-fatal assert. Useful for debugging. */
515 #define anv_assert(x) ({ \
516 if (unlikely(!(x))) \
517 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
520 #define anv_assert(x)
523 /* A multi-pointer allocator
525 * When copying data structures from the user (such as a render pass), it's
526 * common to need to allocate data for a bunch of different things. Instead
527 * of doing several allocations and having to handle all of the error checking
528 * that entails, it can be easier to do a single allocation. This struct
529 * helps facilitate that. The intended usage looks like this:
532 * anv_multialloc_add(&ma, &main_ptr, 1);
533 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
534 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
536 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
537 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
539 struct anv_multialloc
{
547 #define ANV_MULTIALLOC_INIT \
548 ((struct anv_multialloc) { 0, })
550 #define ANV_MULTIALLOC(_name) \
551 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
553 __attribute__((always_inline
))
555 _anv_multialloc_add(struct anv_multialloc
*ma
,
556 void **ptr
, size_t size
, size_t align
)
558 size_t offset
= align_u64(ma
->size
, align
);
559 ma
->size
= offset
+ size
;
560 ma
->align
= MAX2(ma
->align
, align
);
562 /* Store the offset in the pointer. */
563 *ptr
= (void *)(uintptr_t)offset
;
565 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
566 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
569 #define anv_multialloc_add_size(_ma, _ptr, _size) \
570 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
572 #define anv_multialloc_add(_ma, _ptr, _count) \
573 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
575 __attribute__((always_inline
))
577 anv_multialloc_alloc(struct anv_multialloc
*ma
,
578 const VkAllocationCallbacks
*alloc
,
579 VkSystemAllocationScope scope
)
581 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
585 /* Fill out each of the pointers with their final value.
587 * for (uint32_t i = 0; i < ma->ptr_count; i++)
588 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
590 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
591 * constant, GCC is incapable of figuring this out and unrolling the loop
592 * so we have to give it a little help.
594 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
595 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
596 if ((_i) < ma->ptr_count) \
597 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
598 _ANV_MULTIALLOC_UPDATE_POINTER(0);
599 _ANV_MULTIALLOC_UPDATE_POINTER(1);
600 _ANV_MULTIALLOC_UPDATE_POINTER(2);
601 _ANV_MULTIALLOC_UPDATE_POINTER(3);
602 _ANV_MULTIALLOC_UPDATE_POINTER(4);
603 _ANV_MULTIALLOC_UPDATE_POINTER(5);
604 _ANV_MULTIALLOC_UPDATE_POINTER(6);
605 _ANV_MULTIALLOC_UPDATE_POINTER(7);
606 #undef _ANV_MULTIALLOC_UPDATE_POINTER
611 __attribute__((always_inline
))
613 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
614 const VkAllocationCallbacks
*parent_alloc
,
615 const VkAllocationCallbacks
*alloc
,
616 VkSystemAllocationScope scope
)
618 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
626 /* Index into the current validation list. This is used by the
627 * validation list building alrogithm to track which buffers are already
628 * in the validation list so that we can ensure uniqueness.
632 /* Index for use with util_sparse_array_free_list */
635 /* Last known offset. This value is provided by the kernel when we
636 * execbuf and is used as the presumed offset for the next bunch of
643 /* Map for internally mapped BOs.
645 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
649 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
652 /** True if this BO may be shared with other processes */
655 /** True if this BO is a wrapper
657 * When set to true, none of the fields in this BO are meaningful except
658 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
659 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
660 * is set in the physical device.
664 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
665 bool has_fixed_address
:1;
667 /** True if this BO wraps a host pointer */
668 bool from_host_ptr
:1;
670 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
671 bool has_client_visible_address
:1;
674 static inline struct anv_bo
*
675 anv_bo_unwrap(struct anv_bo
*bo
)
677 while (bo
->is_wrapper
)
682 /* Represents a lock-free linked list of "free" things. This is used by
683 * both the block pool and the state pools. Unfortunately, in order to
684 * solve the ABA problem, we can't use a single uint32_t head.
686 union anv_free_list
{
690 /* A simple count that is incremented every time the head changes. */
693 /* Make sure it's aligned to 64 bits. This will make atomic operations
694 * faster on 32 bit platforms.
696 uint64_t u64
__attribute__ ((aligned (8)));
699 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
701 struct anv_block_state
{
707 /* Make sure it's aligned to 64 bits. This will make atomic operations
708 * faster on 32 bit platforms.
710 uint64_t u64
__attribute__ ((aligned (8)));
714 #define anv_block_pool_foreach_bo(bo, pool) \
715 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
716 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
719 #define ANV_MAX_BLOCK_POOL_BOS 20
721 struct anv_block_pool
{
722 struct anv_device
*device
;
725 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
726 * around the actual BO so that we grow the pool after the wrapper BO has
727 * been put in a relocation list. This is only used in the non-softpin
730 struct anv_bo wrapper_bo
;
732 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
738 /* The address where the start of the pool is pinned. The various bos that
739 * are created as the pool grows will have addresses in the range
740 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
742 uint64_t start_address
;
744 /* The offset from the start of the bo to the "center" of the block
745 * pool. Pointers to allocated blocks are given by
746 * bo.map + center_bo_offset + offsets.
748 uint32_t center_bo_offset
;
750 /* Current memory map of the block pool. This pointer may or may not
751 * point to the actual beginning of the block pool memory. If
752 * anv_block_pool_alloc_back has ever been called, then this pointer
753 * will point to the "center" position of the buffer and all offsets
754 * (negative or positive) given out by the block pool alloc functions
755 * will be valid relative to this pointer.
757 * In particular, map == bo.map + center_offset
759 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
760 * since it will handle the softpin case as well, where this points to NULL.
766 * Array of mmaps and gem handles owned by the block pool, reclaimed when
767 * the block pool is destroyed.
769 struct u_vector mmap_cleanups
;
771 struct anv_block_state state
;
773 struct anv_block_state back_state
;
776 /* Block pools are backed by a fixed-size 1GB memfd */
777 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
779 /* The center of the block pool is also the middle of the memfd. This may
780 * change in the future if we decide differently for some reason.
782 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
784 static inline uint32_t
785 anv_block_pool_size(struct anv_block_pool
*pool
)
787 return pool
->state
.end
+ pool
->back_state
.end
;
797 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
799 struct anv_fixed_size_state_pool
{
800 union anv_free_list free_list
;
801 struct anv_block_state block
;
804 #define ANV_MIN_STATE_SIZE_LOG2 6
805 #define ANV_MAX_STATE_SIZE_LOG2 21
807 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
809 struct anv_free_entry
{
811 struct anv_state state
;
814 struct anv_state_table
{
815 struct anv_device
*device
;
817 struct anv_free_entry
*map
;
819 struct anv_block_state state
;
820 struct u_vector cleanups
;
823 struct anv_state_pool
{
824 struct anv_block_pool block_pool
;
826 struct anv_state_table table
;
828 /* The size of blocks which will be allocated from the block pool */
831 /** Free list for "back" allocations */
832 union anv_free_list back_alloc_free_list
;
834 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
837 struct anv_state_stream_block
;
839 struct anv_state_stream
{
840 struct anv_state_pool
*state_pool
;
842 /* The size of blocks to allocate from the state pool */
845 /* Current block we're allocating from */
846 struct anv_state block
;
848 /* Offset into the current block at which to allocate the next state */
851 /* List of all blocks allocated from this pool */
852 struct anv_state_stream_block
*block_list
;
855 /* The block_pool functions exported for testing only. The block pool should
856 * only be used via a state pool (see below).
858 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
859 struct anv_device
*device
,
860 uint64_t start_address
,
861 uint32_t initial_size
);
862 void anv_block_pool_finish(struct anv_block_pool
*pool
);
863 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
864 uint32_t block_size
, uint32_t *padding
);
865 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
866 uint32_t block_size
);
867 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
869 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
870 struct anv_device
*device
,
871 uint64_t start_address
,
872 uint32_t block_size
);
873 void anv_state_pool_finish(struct anv_state_pool
*pool
);
874 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
875 uint32_t state_size
, uint32_t alignment
);
876 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
877 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
878 void anv_state_stream_init(struct anv_state_stream
*stream
,
879 struct anv_state_pool
*state_pool
,
880 uint32_t block_size
);
881 void anv_state_stream_finish(struct anv_state_stream
*stream
);
882 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
883 uint32_t size
, uint32_t alignment
);
885 VkResult
anv_state_table_init(struct anv_state_table
*table
,
886 struct anv_device
*device
,
887 uint32_t initial_entries
);
888 void anv_state_table_finish(struct anv_state_table
*table
);
889 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
891 void anv_free_list_push(union anv_free_list
*list
,
892 struct anv_state_table
*table
,
893 uint32_t idx
, uint32_t count
);
894 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
895 struct anv_state_table
*table
);
898 static inline struct anv_state
*
899 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
901 return &table
->map
[idx
].state
;
904 * Implements a pool of re-usable BOs. The interface is identical to that
905 * of block_pool except that each block is its own BO.
908 struct anv_device
*device
;
910 struct util_sparse_array_free_list free_list
[16];
913 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
914 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
915 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
916 struct anv_bo
**bo_out
);
917 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
919 struct anv_scratch_pool
{
920 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
921 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
924 void anv_scratch_pool_init(struct anv_device
*device
,
925 struct anv_scratch_pool
*pool
);
926 void anv_scratch_pool_finish(struct anv_device
*device
,
927 struct anv_scratch_pool
*pool
);
928 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
929 struct anv_scratch_pool
*pool
,
930 gl_shader_stage stage
,
931 unsigned per_thread_scratch
);
933 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
934 struct anv_bo_cache
{
935 struct util_sparse_array bo_map
;
936 pthread_mutex_t mutex
;
939 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
940 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
942 struct anv_memory_type
{
943 /* Standard bits passed on to the client */
944 VkMemoryPropertyFlags propertyFlags
;
948 struct anv_memory_heap
{
949 /* Standard bits passed on to the client */
951 VkMemoryHeapFlags flags
;
953 /* Driver-internal book-keeping */
957 struct anv_physical_device
{
958 VK_LOADER_DATA _loader_data
;
960 struct anv_instance
* instance
;
971 struct gen_device_info info
;
972 /** Amount of "GPU memory" we want to advertise
974 * Clearly, this value is bogus since Intel is a UMA architecture. On
975 * gen7 platforms, we are limited by GTT size unless we want to implement
976 * fine-grained tracking and GTT splitting. On Broadwell and above we are
977 * practically unlimited. However, we will never report more than 3/4 of
978 * the total system ram to try and avoid running out of RAM.
980 bool supports_48bit_addresses
;
981 struct brw_compiler
* compiler
;
982 struct isl_device isl_dev
;
983 struct gen_perf_config
* perf
;
984 int cmd_parser_version
;
987 bool has_exec_capture
;
990 bool has_syncobj_wait
;
991 bool has_context_priority
;
992 bool has_context_isolation
;
993 bool has_mem_available
;
997 bool always_use_bindless
;
999 /** True if we can access buffers using A64 messages */
1000 bool has_a64_buffer_access
;
1001 /** True if we can use bindless access for images */
1002 bool has_bindless_images
;
1003 /** True if we can use bindless access for samplers */
1004 bool has_bindless_samplers
;
1006 bool always_flush_cache
;
1008 struct anv_device_extension_table supported_extensions
;
1009 struct anv_physical_device_dispatch_table dispatch
;
1012 uint32_t subslice_total
;
1015 uint32_t type_count
;
1016 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1017 uint32_t heap_count
;
1018 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1021 uint8_t driver_build_sha1
[20];
1022 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1023 uint8_t driver_uuid
[VK_UUID_SIZE
];
1024 uint8_t device_uuid
[VK_UUID_SIZE
];
1026 struct disk_cache
* disk_cache
;
1028 struct wsi_device wsi_device
;
1033 struct anv_app_info
{
1034 const char* app_name
;
1035 uint32_t app_version
;
1036 const char* engine_name
;
1037 uint32_t engine_version
;
1038 uint32_t api_version
;
1041 struct anv_instance
{
1042 VK_LOADER_DATA _loader_data
;
1044 VkAllocationCallbacks alloc
;
1046 struct anv_app_info app_info
;
1048 struct anv_instance_extension_table enabled_extensions
;
1049 struct anv_instance_dispatch_table dispatch
;
1050 struct anv_device_dispatch_table device_dispatch
;
1052 int physicalDeviceCount
;
1053 struct anv_physical_device physicalDevice
;
1055 bool pipeline_cache_enabled
;
1057 struct vk_debug_report_instance debug_report_callbacks
;
1059 struct driOptionCache dri_options
;
1060 struct driOptionCache available_dri_options
;
1063 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1064 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1066 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1067 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1070 struct anv_queue_submit
{
1071 struct anv_cmd_buffer
* cmd_buffer
;
1073 uint32_t fence_count
;
1074 uint32_t fence_array_length
;
1075 struct drm_i915_gem_exec_fence
* fences
;
1077 uint32_t temporary_semaphore_count
;
1078 uint32_t temporary_semaphore_array_length
;
1079 struct anv_semaphore_impl
* temporary_semaphores
;
1081 /* Semaphores to be signaled with a SYNC_FD. */
1082 struct anv_semaphore
** sync_fd_semaphores
;
1083 uint32_t sync_fd_semaphore_count
;
1084 uint32_t sync_fd_semaphore_array_length
;
1086 /* Allocated only with non shareable timelines. */
1087 struct anv_timeline
** wait_timelines
;
1088 uint32_t wait_timeline_count
;
1089 uint32_t wait_timeline_array_length
;
1090 uint64_t * wait_timeline_values
;
1092 struct anv_timeline
** signal_timelines
;
1093 uint32_t signal_timeline_count
;
1094 uint32_t signal_timeline_array_length
;
1095 uint64_t * signal_timeline_values
;
1098 bool need_out_fence
;
1101 uint32_t fence_bo_count
;
1102 uint32_t fence_bo_array_length
;
1103 /* An array of struct anv_bo pointers with lower bit used as a flag to
1104 * signal we will wait on that BO (see anv_(un)pack_ptr).
1106 uintptr_t * fence_bos
;
1108 const VkAllocationCallbacks
* alloc
;
1109 VkSystemAllocationScope alloc_scope
;
1111 struct anv_bo
* simple_bo
;
1112 uint32_t simple_bo_size
;
1114 struct list_head link
;
1118 VK_LOADER_DATA _loader_data
;
1120 struct anv_device
* device
;
1123 * A list of struct anv_queue_submit to be submitted to i915.
1125 struct list_head queued_submits
;
1127 VkDeviceQueueCreateFlags flags
;
1130 struct anv_pipeline_cache
{
1131 struct anv_device
* device
;
1132 pthread_mutex_t mutex
;
1134 struct hash_table
* nir_cache
;
1136 struct hash_table
* cache
;
1139 struct nir_xfb_info
;
1140 struct anv_pipeline_bind_map
;
1142 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1143 struct anv_device
*device
,
1144 bool cache_enabled
);
1145 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1147 struct anv_shader_bin
*
1148 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1149 const void *key
, uint32_t key_size
);
1150 struct anv_shader_bin
*
1151 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1152 const void *key_data
, uint32_t key_size
,
1153 const void *kernel_data
, uint32_t kernel_size
,
1154 const void *constant_data
,
1155 uint32_t constant_data_size
,
1156 const struct brw_stage_prog_data
*prog_data
,
1157 uint32_t prog_data_size
,
1158 const struct brw_compile_stats
*stats
,
1160 const struct nir_xfb_info
*xfb_info
,
1161 const struct anv_pipeline_bind_map
*bind_map
);
1163 struct anv_shader_bin
*
1164 anv_device_search_for_kernel(struct anv_device
*device
,
1165 struct anv_pipeline_cache
*cache
,
1166 const void *key_data
, uint32_t key_size
,
1167 bool *user_cache_bit
);
1169 struct anv_shader_bin
*
1170 anv_device_upload_kernel(struct anv_device
*device
,
1171 struct anv_pipeline_cache
*cache
,
1172 const void *key_data
, uint32_t key_size
,
1173 const void *kernel_data
, uint32_t kernel_size
,
1174 const void *constant_data
,
1175 uint32_t constant_data_size
,
1176 const struct brw_stage_prog_data
*prog_data
,
1177 uint32_t prog_data_size
,
1178 const struct brw_compile_stats
*stats
,
1180 const struct nir_xfb_info
*xfb_info
,
1181 const struct anv_pipeline_bind_map
*bind_map
);
1184 struct nir_shader_compiler_options
;
1187 anv_device_search_for_nir(struct anv_device
*device
,
1188 struct anv_pipeline_cache
*cache
,
1189 const struct nir_shader_compiler_options
*nir_options
,
1190 unsigned char sha1_key
[20],
1194 anv_device_upload_nir(struct anv_device
*device
,
1195 struct anv_pipeline_cache
*cache
,
1196 const struct nir_shader
*nir
,
1197 unsigned char sha1_key
[20]);
1200 VK_LOADER_DATA _loader_data
;
1202 VkAllocationCallbacks alloc
;
1204 struct anv_instance
* instance
;
1205 uint32_t chipset_id
;
1207 struct gen_device_info info
;
1208 struct isl_device isl_dev
;
1211 bool can_chain_batches
;
1212 bool robust_buffer_access
;
1213 struct anv_device_extension_table enabled_extensions
;
1214 struct anv_device_dispatch_table dispatch
;
1216 pthread_mutex_t vma_mutex
;
1217 struct util_vma_heap vma_lo
;
1218 struct util_vma_heap vma_cva
;
1219 struct util_vma_heap vma_hi
;
1221 /** List of all anv_device_memory objects */
1222 struct list_head memory_objects
;
1224 struct anv_bo_pool batch_bo_pool
;
1226 struct anv_bo_cache bo_cache
;
1228 struct anv_state_pool dynamic_state_pool
;
1229 struct anv_state_pool instruction_state_pool
;
1230 struct anv_state_pool binding_table_pool
;
1231 struct anv_state_pool surface_state_pool
;
1233 struct anv_bo
* workaround_bo
;
1234 struct anv_bo
* trivial_batch_bo
;
1235 struct anv_bo
* hiz_clear_bo
;
1237 struct anv_pipeline_cache default_pipeline_cache
;
1238 struct blorp_context blorp
;
1240 struct anv_state border_colors
;
1242 struct anv_state slice_hash
;
1244 struct anv_queue queue
;
1246 struct anv_scratch_pool scratch_pool
;
1248 pthread_mutex_t mutex
;
1249 pthread_cond_t queue_submit
;
1252 struct gen_batch_decode_ctx decoder_ctx
;
1254 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1255 * the cmd_buffer's list.
1257 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1259 int perf_fd
; /* -1 if no opened */
1260 uint64_t perf_metric
; /* 0 if unset */
1262 struct gen_aux_map_context
*aux_map_ctx
;
1265 static inline struct anv_state_pool
*
1266 anv_binding_table_pool(struct anv_device
*device
)
1268 if (device
->instance
->physicalDevice
.use_softpin
)
1269 return &device
->binding_table_pool
;
1271 return &device
->surface_state_pool
;
1274 static inline struct anv_state
1275 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1276 if (device
->instance
->physicalDevice
.use_softpin
)
1277 return anv_state_pool_alloc(&device
->binding_table_pool
,
1278 device
->binding_table_pool
.block_size
, 0);
1280 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1284 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1285 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1288 static inline uint32_t
1289 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1291 if (bo
->is_external
)
1292 return device
->isl_dev
.mocs
.external
;
1294 return device
->isl_dev
.mocs
.internal
;
1297 void anv_device_init_blorp(struct anv_device
*device
);
1298 void anv_device_finish_blorp(struct anv_device
*device
);
1300 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1301 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1302 const char *file
, int line
,
1303 const char *msg
, ...)
1304 anv_printflike(4, 5);
1305 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1306 const char *file
, int line
,
1307 const char *msg
, ...)
1308 anv_printflike(4, 5);
1309 #define anv_device_set_lost(dev, ...) \
1310 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1311 #define anv_queue_set_lost(queue, ...) \
1312 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1315 anv_device_is_lost(struct anv_device
*device
)
1317 return unlikely(p_atomic_read(&device
->_lost
));
1320 VkResult
anv_device_query_status(struct anv_device
*device
);
1323 enum anv_bo_alloc_flags
{
1324 /** Specifies that the BO must have a 32-bit address
1326 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1328 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1330 /** Specifies that the BO may be shared externally */
1331 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1333 /** Specifies that the BO should be mapped */
1334 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1336 /** Specifies that the BO should be snooped so we get coherency */
1337 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1339 /** Specifies that the BO should be captured in error states */
1340 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1342 /** Specifies that the BO will have an address assigned by the caller
1344 * Such BOs do not exist in any VMA heap.
1346 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1348 /** Enables implicit synchronization on the BO
1350 * This is the opposite of EXEC_OBJECT_ASYNC.
1352 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1354 /** Enables implicit synchronization on the BO
1356 * This is equivalent to EXEC_OBJECT_WRITE.
1358 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1360 /** Has an address which is visible to the client */
1361 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1364 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1365 enum anv_bo_alloc_flags alloc_flags
,
1366 uint64_t explicit_address
,
1367 struct anv_bo
**bo
);
1368 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1369 void *host_ptr
, uint32_t size
,
1370 enum anv_bo_alloc_flags alloc_flags
,
1371 uint64_t client_address
,
1372 struct anv_bo
**bo_out
);
1373 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1374 enum anv_bo_alloc_flags alloc_flags
,
1375 uint64_t client_address
,
1376 struct anv_bo
**bo
);
1377 VkResult
anv_device_export_bo(struct anv_device
*device
,
1378 struct anv_bo
*bo
, int *fd_out
);
1379 void anv_device_release_bo(struct anv_device
*device
,
1382 static inline struct anv_bo
*
1383 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1385 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1388 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1389 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1392 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1393 void anv_queue_finish(struct anv_queue
*queue
);
1395 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1396 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1397 struct anv_batch
*batch
);
1399 uint64_t anv_gettime_ns(void);
1400 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1402 void* anv_gem_mmap(struct anv_device
*device
,
1403 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1404 void anv_gem_munmap(void *p
, uint64_t size
);
1405 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1406 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1407 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1408 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1409 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1410 int anv_gem_execbuffer(struct anv_device
*device
,
1411 struct drm_i915_gem_execbuffer2
*execbuf
);
1412 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1413 uint32_t stride
, uint32_t tiling
);
1414 int anv_gem_create_context(struct anv_device
*device
);
1415 bool anv_gem_has_context_priority(int fd
);
1416 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1417 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1419 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1421 int anv_gem_get_param(int fd
, uint32_t param
);
1422 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1423 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1424 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1425 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1426 uint32_t *active
, uint32_t *pending
);
1427 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1428 int anv_gem_reg_read(struct anv_device
*device
,
1429 uint32_t offset
, uint64_t *result
);
1430 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1431 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1432 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1433 uint32_t read_domains
, uint32_t write_domain
);
1434 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1435 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1436 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1437 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1438 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1439 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1441 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1442 uint32_t handle
, int fd
);
1443 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1444 bool anv_gem_supports_syncobj_wait(int fd
);
1445 int anv_gem_syncobj_wait(struct anv_device
*device
,
1446 uint32_t *handles
, uint32_t num_handles
,
1447 int64_t abs_timeout_ns
, bool wait_all
);
1449 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
,
1450 uint64_t client_address
);
1451 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1453 struct anv_reloc_list
{
1454 uint32_t num_relocs
;
1455 uint32_t array_length
;
1456 struct drm_i915_gem_relocation_entry
* relocs
;
1457 struct anv_bo
** reloc_bos
;
1462 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1463 const VkAllocationCallbacks
*alloc
);
1464 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1465 const VkAllocationCallbacks
*alloc
);
1467 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1468 const VkAllocationCallbacks
*alloc
,
1469 uint32_t offset
, struct anv_bo
*target_bo
,
1470 uint32_t delta
, uint64_t *address_u64_out
);
1472 struct anv_batch_bo
{
1473 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1474 struct list_head link
;
1478 /* Bytes actually consumed in this batch BO */
1481 struct anv_reloc_list relocs
;
1485 const VkAllocationCallbacks
* alloc
;
1491 struct anv_reloc_list
* relocs
;
1493 /* This callback is called (with the associated user data) in the event
1494 * that the batch runs out of space.
1496 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1500 * Current error status of the command buffer. Used to track inconsistent
1501 * or incomplete command buffer states that are the consequence of run-time
1502 * errors such as out of memory scenarios. We want to track this in the
1503 * batch because the command buffer object is not visible to some parts
1509 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1510 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1511 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1512 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1514 static inline VkResult
1515 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1517 assert(error
!= VK_SUCCESS
);
1518 if (batch
->status
== VK_SUCCESS
)
1519 batch
->status
= error
;
1520 return batch
->status
;
1524 anv_batch_has_error(struct anv_batch
*batch
)
1526 return batch
->status
!= VK_SUCCESS
;
1529 struct anv_address
{
1534 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1537 anv_address_is_null(struct anv_address addr
)
1539 return addr
.bo
== NULL
&& addr
.offset
== 0;
1542 static inline uint64_t
1543 anv_address_physical(struct anv_address addr
)
1545 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1546 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1548 return gen_canonical_address(addr
.offset
);
1551 static inline struct anv_address
1552 anv_address_add(struct anv_address addr
, uint64_t offset
)
1554 addr
.offset
+= offset
;
1559 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1561 unsigned reloc_size
= 0;
1562 if (device
->info
.gen
>= 8) {
1563 reloc_size
= sizeof(uint64_t);
1564 *(uint64_t *)p
= gen_canonical_address(v
);
1566 reloc_size
= sizeof(uint32_t);
1570 if (flush
&& !device
->info
.has_llc
)
1571 gen_flush_range(p
, reloc_size
);
1574 static inline uint64_t
1575 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1576 const struct anv_address address
, uint32_t delta
)
1578 if (address
.bo
== NULL
) {
1579 return address
.offset
+ delta
;
1581 assert(batch
->start
<= location
&& location
< batch
->end
);
1583 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1587 #define __gen_address_type struct anv_address
1588 #define __gen_user_data struct anv_batch
1589 #define __gen_combine_address _anv_combine_address
1591 /* Wrapper macros needed to work around preprocessor argument issues. In
1592 * particular, arguments don't get pre-evaluated if they are concatenated.
1593 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1594 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1595 * We can work around this easily enough with these helpers.
1597 #define __anv_cmd_length(cmd) cmd ## _length
1598 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1599 #define __anv_cmd_header(cmd) cmd ## _header
1600 #define __anv_cmd_pack(cmd) cmd ## _pack
1601 #define __anv_reg_num(reg) reg ## _num
1603 #define anv_pack_struct(dst, struc, ...) do { \
1604 struct struc __template = { \
1607 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1608 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1611 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1612 void *__dst = anv_batch_emit_dwords(batch, n); \
1614 struct cmd __template = { \
1615 __anv_cmd_header(cmd), \
1616 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1619 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1624 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1628 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1629 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1632 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1633 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1634 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1637 #define anv_batch_emit(batch, cmd, name) \
1638 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1639 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1640 __builtin_expect(_dst != NULL, 1); \
1641 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1642 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1646 struct anv_device_memory
{
1647 struct list_head link
;
1650 struct anv_memory_type
* type
;
1651 VkDeviceSize map_size
;
1654 /* If set, we are holding reference to AHardwareBuffer
1655 * which we must release when memory is freed.
1657 struct AHardwareBuffer
* ahw
;
1659 /* If set, this memory comes from a host pointer. */
1664 * Header for Vertex URB Entry (VUE)
1666 struct anv_vue_header
{
1668 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1669 uint32_t ViewportIndex
;
1673 /** Struct representing a sampled image descriptor
1675 * This descriptor layout is used for sampled images, bare sampler, and
1676 * combined image/sampler descriptors.
1678 struct anv_sampled_image_descriptor
{
1679 /** Bindless image handle
1681 * This is expected to already be shifted such that the 20-bit
1682 * SURFACE_STATE table index is in the top 20 bits.
1686 /** Bindless sampler handle
1688 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1689 * to the dynamic state base address.
1694 struct anv_texture_swizzle_descriptor
{
1697 * See also nir_intrinsic_channel_select_intel
1701 /** Unused padding to ensure the struct is a multiple of 64 bits */
1705 /** Struct representing a storage image descriptor */
1706 struct anv_storage_image_descriptor
{
1707 /** Bindless image handles
1709 * These are expected to already be shifted such that the 20-bit
1710 * SURFACE_STATE table index is in the top 20 bits.
1712 uint32_t read_write
;
1713 uint32_t write_only
;
1716 /** Struct representing a address/range descriptor
1718 * The fields of this struct correspond directly to the data layout of
1719 * nir_address_format_64bit_bounded_global addresses. The last field is the
1720 * offset in the NIR address so it must be zero so that when you load the
1721 * descriptor you get a pointer to the start of the range.
1723 struct anv_address_range_descriptor
{
1729 enum anv_descriptor_data
{
1730 /** The descriptor contains a BTI reference to a surface state */
1731 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1732 /** The descriptor contains a BTI reference to a sampler state */
1733 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1734 /** The descriptor contains an actual buffer view */
1735 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1736 /** The descriptor contains auxiliary image layout data */
1737 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1738 /** The descriptor contains auxiliary image layout data */
1739 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1740 /** anv_address_range_descriptor with a buffer address and range */
1741 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1742 /** Bindless surface handle */
1743 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1744 /** Storage image handles */
1745 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1746 /** Storage image handles */
1747 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1750 struct anv_descriptor_set_binding_layout
{
1752 /* The type of the descriptors in this binding */
1753 VkDescriptorType type
;
1756 /* Flags provided when this binding was created */
1757 VkDescriptorBindingFlagsEXT flags
;
1759 /* Bitfield representing the type of data this descriptor contains */
1760 enum anv_descriptor_data data
;
1762 /* Maximum number of YCbCr texture/sampler planes */
1763 uint8_t max_plane_count
;
1765 /* Number of array elements in this binding (or size in bytes for inline
1768 uint16_t array_size
;
1770 /* Index into the flattend descriptor set */
1771 uint16_t descriptor_index
;
1773 /* Index into the dynamic state array for a dynamic buffer */
1774 int16_t dynamic_offset_index
;
1776 /* Index into the descriptor set buffer views */
1777 int16_t buffer_view_index
;
1779 /* Offset into the descriptor buffer where this descriptor lives */
1780 uint32_t descriptor_offset
;
1782 /* Immutable samplers (or NULL if no immutable samplers) */
1783 struct anv_sampler
**immutable_samplers
;
1786 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1788 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1789 VkDescriptorType type
);
1791 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1792 const struct anv_descriptor_set_binding_layout
*binding
,
1795 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1796 const struct anv_descriptor_set_binding_layout
*binding
,
1799 struct anv_descriptor_set_layout
{
1800 /* Descriptor set layouts can be destroyed at almost any time */
1803 /* Number of bindings in this descriptor set */
1804 uint16_t binding_count
;
1806 /* Total size of the descriptor set with room for all array entries */
1809 /* Shader stages affected by this descriptor set */
1810 uint16_t shader_stages
;
1812 /* Number of buffer views in this descriptor set */
1813 uint16_t buffer_view_count
;
1815 /* Number of dynamic offsets used by this descriptor set */
1816 uint16_t dynamic_offset_count
;
1818 /* For each shader stage, which offsets apply to that stage */
1819 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1821 /* Size of the descriptor buffer for this descriptor set */
1822 uint32_t descriptor_buffer_size
;
1824 /* Bindings in this descriptor set */
1825 struct anv_descriptor_set_binding_layout binding
[0];
1829 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1831 assert(layout
&& layout
->ref_cnt
>= 1);
1832 p_atomic_inc(&layout
->ref_cnt
);
1836 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1837 struct anv_descriptor_set_layout
*layout
)
1839 assert(layout
&& layout
->ref_cnt
>= 1);
1840 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1841 vk_free(&device
->alloc
, layout
);
1844 struct anv_descriptor
{
1845 VkDescriptorType type
;
1849 VkImageLayout layout
;
1850 struct anv_image_view
*image_view
;
1851 struct anv_sampler
*sampler
;
1855 struct anv_buffer
*buffer
;
1860 struct anv_buffer_view
*buffer_view
;
1864 struct anv_descriptor_set
{
1865 struct anv_descriptor_pool
*pool
;
1866 struct anv_descriptor_set_layout
*layout
;
1869 /* State relative to anv_descriptor_pool::bo */
1870 struct anv_state desc_mem
;
1871 /* Surface state for the descriptor buffer */
1872 struct anv_state desc_surface_state
;
1874 uint32_t buffer_view_count
;
1875 struct anv_buffer_view
*buffer_views
;
1877 /* Link to descriptor pool's desc_sets list . */
1878 struct list_head pool_link
;
1880 struct anv_descriptor descriptors
[0];
1883 struct anv_buffer_view
{
1884 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1885 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1887 struct anv_address address
;
1889 struct anv_state surface_state
;
1890 struct anv_state storage_surface_state
;
1891 struct anv_state writeonly_storage_surface_state
;
1893 struct brw_image_param storage_image_param
;
1896 struct anv_push_descriptor_set
{
1897 struct anv_descriptor_set set
;
1899 /* Put this field right behind anv_descriptor_set so it fills up the
1900 * descriptors[0] field. */
1901 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1903 /** True if the descriptor set buffer has been referenced by a draw or
1906 bool set_used_on_gpu
;
1908 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1911 struct anv_descriptor_pool
{
1917 struct util_vma_heap bo_heap
;
1919 struct anv_state_stream surface_state_stream
;
1920 void *surface_state_free_list
;
1922 struct list_head desc_sets
;
1927 enum anv_descriptor_template_entry_type
{
1928 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1929 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1930 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1933 struct anv_descriptor_template_entry
{
1934 /* The type of descriptor in this entry */
1935 VkDescriptorType type
;
1937 /* Binding in the descriptor set */
1940 /* Offset at which to write into the descriptor set binding */
1941 uint32_t array_element
;
1943 /* Number of elements to write into the descriptor set binding */
1944 uint32_t array_count
;
1946 /* Offset into the user provided data */
1949 /* Stride between elements into the user provided data */
1953 struct anv_descriptor_update_template
{
1954 VkPipelineBindPoint bind_point
;
1956 /* The descriptor set this template corresponds to. This value is only
1957 * valid if the template was created with the templateType
1958 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1962 /* Number of entries in this template */
1963 uint32_t entry_count
;
1965 /* Entries of the template */
1966 struct anv_descriptor_template_entry entries
[0];
1970 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1973 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1974 struct anv_descriptor_set
*set
,
1975 const VkDescriptorImageInfo
* const info
,
1976 VkDescriptorType type
,
1981 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1982 struct anv_descriptor_set
*set
,
1983 VkDescriptorType type
,
1984 struct anv_buffer_view
*buffer_view
,
1989 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1990 struct anv_descriptor_set
*set
,
1991 struct anv_state_stream
*alloc_stream
,
1992 VkDescriptorType type
,
1993 struct anv_buffer
*buffer
,
1996 VkDeviceSize offset
,
1997 VkDeviceSize range
);
1999 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2000 struct anv_descriptor_set
*set
,
2007 anv_descriptor_set_write_template(struct anv_device
*device
,
2008 struct anv_descriptor_set
*set
,
2009 struct anv_state_stream
*alloc_stream
,
2010 const struct anv_descriptor_update_template
*template,
2014 anv_descriptor_set_create(struct anv_device
*device
,
2015 struct anv_descriptor_pool
*pool
,
2016 struct anv_descriptor_set_layout
*layout
,
2017 struct anv_descriptor_set
**out_set
);
2020 anv_descriptor_set_destroy(struct anv_device
*device
,
2021 struct anv_descriptor_pool
*pool
,
2022 struct anv_descriptor_set
*set
);
2024 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2025 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2026 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2027 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2028 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2029 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2031 struct anv_pipeline_binding
{
2032 /** Index in the descriptor set
2034 * This is a flattened index; the descriptor set layout is already taken
2039 /** The descriptor set this surface corresponds to.
2041 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2042 * binding is not a normal descriptor set but something else.
2047 /** Plane in the binding index for images */
2050 /** Input attachment index (relative to the subpass) */
2051 uint8_t input_attachment_index
;
2053 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2054 uint8_t dynamic_offset_index
;
2057 /** For a storage image, whether it is write-only */
2060 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2061 * assuming POD zero-initialization.
2066 struct anv_push_range
{
2067 /** Index in the descriptor set */
2070 /** Descriptor set index */
2073 /** Dynamic offset index (for dynamic UBOs) */
2074 uint8_t dynamic_offset_index
;
2076 /** Start offset in units of 32B */
2079 /** Range in units of 32B */
2083 struct anv_pipeline_layout
{
2085 struct anv_descriptor_set_layout
*layout
;
2086 uint32_t dynamic_offset_start
;
2091 unsigned char sha1
[20];
2095 struct anv_device
* device
;
2098 VkBufferUsageFlags usage
;
2100 /* Set when bound */
2101 struct anv_address address
;
2104 static inline uint64_t
2105 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2107 assert(offset
<= buffer
->size
);
2108 if (range
== VK_WHOLE_SIZE
) {
2109 return buffer
->size
- offset
;
2111 assert(range
+ offset
>= range
);
2112 assert(range
+ offset
<= buffer
->size
);
2117 enum anv_cmd_dirty_bits
{
2118 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2119 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2120 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2121 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2122 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2123 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2124 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2125 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2126 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2127 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2128 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2129 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2130 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2131 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2133 typedef uint32_t anv_cmd_dirty_mask_t
;
2135 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2136 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2137 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2138 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2139 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2140 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2141 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2142 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2143 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2144 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2145 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2147 static inline enum anv_cmd_dirty_bits
2148 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2151 case VK_DYNAMIC_STATE_VIEWPORT
:
2152 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2153 case VK_DYNAMIC_STATE_SCISSOR
:
2154 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2155 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2156 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2157 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2158 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2159 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2160 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2161 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2162 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2163 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2164 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2165 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2166 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2167 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2168 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2169 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2170 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2172 assert(!"Unsupported dynamic state");
2178 enum anv_pipe_bits
{
2179 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2180 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2181 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2182 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2183 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2184 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2185 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2186 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2187 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2188 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2189 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2190 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2192 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2193 * a flush has happened but not a CS stall. The next time we do any sort
2194 * of invalidation we need to insert a CS stall at that time. Otherwise,
2195 * we would have to CS stall on every flush which could be bad.
2197 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2199 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2200 * target operations related to transfer commands with VkBuffer as
2201 * destination are ongoing. Some operations like copies on the command
2202 * streamer might need to be aware of this to trigger the appropriate stall
2203 * before they can proceed with the copy.
2205 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2208 #define ANV_PIPE_FLUSH_BITS ( \
2209 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2210 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2211 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2212 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2214 #define ANV_PIPE_STALL_BITS ( \
2215 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2216 ANV_PIPE_DEPTH_STALL_BIT | \
2217 ANV_PIPE_CS_STALL_BIT)
2219 #define ANV_PIPE_INVALIDATE_BITS ( \
2220 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2221 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2222 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2223 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2224 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2225 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2227 static inline enum anv_pipe_bits
2228 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2230 enum anv_pipe_bits pipe_bits
= 0;
2233 for_each_bit(b
, flags
) {
2234 switch ((VkAccessFlagBits
)(1 << b
)) {
2235 case VK_ACCESS_SHADER_WRITE_BIT
:
2236 /* We're transitioning a buffer that was previously used as write
2237 * destination through the data port. To make its content available
2238 * to future operations, flush the data cache.
2240 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2242 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2243 /* We're transitioning a buffer that was previously used as render
2244 * target. To make its content available to future operations, flush
2245 * the render target cache.
2247 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2249 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2250 /* We're transitioning a buffer that was previously used as depth
2251 * buffer. To make its content available to future operations, flush
2254 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2256 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2257 /* We're transitioning a buffer that was previously used as a
2258 * transfer write destination. Generic write operations include color
2259 * & depth operations as well as buffer operations like :
2260 * - vkCmdClearColorImage()
2261 * - vkCmdClearDepthStencilImage()
2262 * - vkCmdBlitImage()
2263 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2265 * Most of these operations are implemented using Blorp which writes
2266 * through the render target, so flush that cache to make it visible
2267 * to future operations. And for depth related operations we also
2268 * need to flush the depth cache.
2270 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2271 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2273 case VK_ACCESS_MEMORY_WRITE_BIT
:
2274 /* We're transitioning a buffer for generic write operations. Flush
2277 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2280 break; /* Nothing to do */
2287 static inline enum anv_pipe_bits
2288 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2290 enum anv_pipe_bits pipe_bits
= 0;
2293 for_each_bit(b
, flags
) {
2294 switch ((VkAccessFlagBits
)(1 << b
)) {
2295 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2296 /* Indirect draw commands take a buffer as input that we're going to
2297 * read from the command streamer to load some of the HW registers
2298 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2299 * command streamer stall so that all the cache flushes have
2300 * completed before the command streamer loads from memory.
2302 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2303 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2304 * through a vertex buffer, so invalidate that cache.
2306 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2307 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2308 * UBO from the buffer, so we need to invalidate constant cache.
2310 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2312 case VK_ACCESS_INDEX_READ_BIT
:
2313 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2314 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2315 * commands, so we invalidate the VF cache to make sure there is no
2316 * stale data when we start rendering.
2318 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2320 case VK_ACCESS_UNIFORM_READ_BIT
:
2321 /* We transitioning a buffer to be used as uniform data. Because
2322 * uniform is accessed through the data port & sampler, we need to
2323 * invalidate the texture cache (sampler) & constant cache (data
2324 * port) to avoid stale data.
2326 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2327 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2329 case VK_ACCESS_SHADER_READ_BIT
:
2330 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2331 case VK_ACCESS_TRANSFER_READ_BIT
:
2332 /* Transitioning a buffer to be read through the sampler, so
2333 * invalidate the texture cache, we don't want any stale data.
2335 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2337 case VK_ACCESS_MEMORY_READ_BIT
:
2338 /* Transitioning a buffer for generic read, invalidate all the
2341 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2343 case VK_ACCESS_MEMORY_WRITE_BIT
:
2344 /* Generic write, make sure all previously written things land in
2347 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2349 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2350 /* Transitioning a buffer for conditional rendering. We'll load the
2351 * content of this buffer into HW registers using the command
2352 * streamer, so we need to stall the command streamer to make sure
2353 * any in-flight flush operations have completed.
2355 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2358 break; /* Nothing to do */
2365 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2366 VK_IMAGE_ASPECT_COLOR_BIT | \
2367 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2368 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2369 VK_IMAGE_ASPECT_PLANE_2_BIT)
2370 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2371 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2372 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2373 VK_IMAGE_ASPECT_PLANE_2_BIT)
2375 struct anv_vertex_binding
{
2376 struct anv_buffer
* buffer
;
2377 VkDeviceSize offset
;
2380 struct anv_xfb_binding
{
2381 struct anv_buffer
* buffer
;
2382 VkDeviceSize offset
;
2386 struct anv_push_constants
{
2387 /** Push constant data provided by the client through vkPushConstants */
2388 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2390 /** Dynamic offsets for dynamic UBOs and SSBOs */
2391 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2394 /** Base workgroup ID
2396 * Used for vkCmdDispatchBase.
2398 uint32_t base_work_group_id
[3];
2402 * This is never set by software but is implicitly filled out when
2403 * uploading the push constants for compute shaders.
2405 uint32_t subgroup_id
;
2407 /** Pad out to a multiple of 32 bytes */
2412 struct anv_dynamic_state
{
2415 VkViewport viewports
[MAX_VIEWPORTS
];
2420 VkRect2D scissors
[MAX_SCISSORS
];
2431 float blend_constants
[4];
2441 } stencil_compare_mask
;
2446 } stencil_write_mask
;
2451 } stencil_reference
;
2459 extern const struct anv_dynamic_state default_dynamic_state
;
2461 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2462 const struct anv_dynamic_state
*src
,
2463 uint32_t copy_mask
);
2465 struct anv_surface_state
{
2466 struct anv_state state
;
2467 /** Address of the surface referred to by this state
2469 * This address is relative to the start of the BO.
2471 struct anv_address address
;
2472 /* Address of the aux surface, if any
2474 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2476 * With the exception of gen8, the bottom 12 bits of this address' offset
2477 * include extra aux information.
2479 struct anv_address aux_address
;
2480 /* Address of the clear color, if any
2482 * This address is relative to the start of the BO.
2484 struct anv_address clear_address
;
2488 * Attachment state when recording a renderpass instance.
2490 * The clear value is valid only if there exists a pending clear.
2492 struct anv_attachment_state
{
2493 enum isl_aux_usage aux_usage
;
2494 enum isl_aux_usage input_aux_usage
;
2495 struct anv_surface_state color
;
2496 struct anv_surface_state input
;
2498 VkImageLayout current_layout
;
2499 VkImageLayout current_stencil_layout
;
2500 VkImageAspectFlags pending_clear_aspects
;
2501 VkImageAspectFlags pending_load_aspects
;
2503 VkClearValue clear_value
;
2504 bool clear_color_is_zero_one
;
2505 bool clear_color_is_zero
;
2507 /* When multiview is active, attachments with a renderpass clear
2508 * operation have their respective layers cleared on the first
2509 * subpass that uses them, and only in that subpass. We keep track
2510 * of this using a bitfield to indicate which layers of an attachment
2511 * have not been cleared yet when multiview is active.
2513 uint32_t pending_clear_views
;
2514 struct anv_image_view
* image_view
;
2517 /** State tracking for vertex buffer flushes
2519 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2520 * addresses. If you happen to have two vertex buffers which get placed
2521 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2522 * collisions. In order to solve this problem, we track vertex address ranges
2523 * which are live in the cache and invalidate the cache if one ever exceeds 32
2526 struct anv_vb_cache_range
{
2527 /* Virtual address at which the live vertex buffer cache range starts for
2528 * this vertex buffer index.
2532 /* Virtual address of the byte after where vertex buffer cache range ends.
2533 * This is exclusive such that end - start is the size of the range.
2538 /** State tracking for particular pipeline bind point
2540 * This struct is the base struct for anv_cmd_graphics_state and
2541 * anv_cmd_compute_state. These are used to track state which is bound to a
2542 * particular type of pipeline. Generic state that applies per-stage such as
2543 * binding table offsets and push constants is tracked generically with a
2544 * per-stage array in anv_cmd_state.
2546 struct anv_cmd_pipeline_state
{
2547 struct anv_pipeline
*pipeline
;
2549 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2550 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2553 /** State tracking for graphics pipeline
2555 * This has anv_cmd_pipeline_state as a base struct to track things which get
2556 * bound to a graphics pipeline. Along with general pipeline bind point state
2557 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2558 * state which is graphics-specific.
2560 struct anv_cmd_graphics_state
{
2561 struct anv_cmd_pipeline_state base
;
2563 anv_cmd_dirty_mask_t dirty
;
2566 struct anv_vb_cache_range ib_bound_range
;
2567 struct anv_vb_cache_range ib_dirty_range
;
2568 struct anv_vb_cache_range vb_bound_ranges
[33];
2569 struct anv_vb_cache_range vb_dirty_ranges
[33];
2571 struct anv_dynamic_state dynamic
;
2574 struct anv_buffer
*index_buffer
;
2575 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2576 uint32_t index_offset
;
2580 /** State tracking for compute pipeline
2582 * This has anv_cmd_pipeline_state as a base struct to track things which get
2583 * bound to a compute pipeline. Along with general pipeline bind point state
2584 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2585 * state which is compute-specific.
2587 struct anv_cmd_compute_state
{
2588 struct anv_cmd_pipeline_state base
;
2590 bool pipeline_dirty
;
2592 struct anv_address num_workgroups
;
2595 /** State required while building cmd buffer */
2596 struct anv_cmd_state
{
2597 /* PIPELINE_SELECT.PipelineSelection */
2598 uint32_t current_pipeline
;
2599 const struct gen_l3_config
* current_l3_config
;
2600 uint32_t last_aux_map_state
;
2602 struct anv_cmd_graphics_state gfx
;
2603 struct anv_cmd_compute_state compute
;
2605 enum anv_pipe_bits pending_pipe_bits
;
2606 VkShaderStageFlags descriptors_dirty
;
2607 VkShaderStageFlags push_constants_dirty
;
2609 struct anv_framebuffer
* framebuffer
;
2610 struct anv_render_pass
* pass
;
2611 struct anv_subpass
* subpass
;
2612 VkRect2D render_area
;
2613 uint32_t restart_index
;
2614 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2616 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2617 VkShaderStageFlags push_constant_stages
;
2618 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2619 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2620 struct anv_state samplers
[MESA_SHADER_STAGES
];
2622 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2623 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2624 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2627 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2628 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2629 * and before invoking the secondary in ExecuteCommands.
2631 bool pma_fix_enabled
;
2634 * Whether or not we know for certain that HiZ is enabled for the current
2635 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2636 * enabled or not, this will be false.
2640 bool conditional_render_enabled
;
2643 * Last rendering scale argument provided to
2644 * genX(cmd_buffer_emit_hashing_mode)().
2646 unsigned current_hash_scale
;
2649 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2650 * valid only when recording a render pass instance.
2652 struct anv_attachment_state
* attachments
;
2655 * Surface states for color render targets. These are stored in a single
2656 * flat array. For depth-stencil attachments, the surface state is simply
2659 struct anv_state render_pass_states
;
2662 * A null surface state of the right size to match the framebuffer. This
2663 * is one of the states in render_pass_states.
2665 struct anv_state null_surface_state
;
2668 struct anv_cmd_pool
{
2669 VkAllocationCallbacks alloc
;
2670 struct list_head cmd_buffers
;
2673 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2675 enum anv_cmd_buffer_exec_mode
{
2676 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2677 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2678 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2679 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2680 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2683 struct anv_cmd_buffer
{
2684 VK_LOADER_DATA _loader_data
;
2686 struct anv_device
* device
;
2688 struct anv_cmd_pool
* pool
;
2689 struct list_head pool_link
;
2691 struct anv_batch batch
;
2693 /* Fields required for the actual chain of anv_batch_bo's.
2695 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2697 struct list_head batch_bos
;
2698 enum anv_cmd_buffer_exec_mode exec_mode
;
2700 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2701 * referenced by this command buffer
2703 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2705 struct u_vector seen_bbos
;
2707 /* A vector of int32_t's for every block of binding tables.
2709 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2711 struct u_vector bt_block_states
;
2712 struct anv_state bt_next
;
2714 struct anv_reloc_list surface_relocs
;
2715 /** Last seen surface state block pool center bo offset */
2716 uint32_t last_ss_pool_center
;
2718 /* Serial for tracking buffer completion */
2721 /* Stream objects for storing temporary data */
2722 struct anv_state_stream surface_state_stream
;
2723 struct anv_state_stream dynamic_state_stream
;
2725 VkCommandBufferUsageFlags usage_flags
;
2726 VkCommandBufferLevel level
;
2728 struct anv_cmd_state state
;
2730 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2731 uint64_t intel_perf_marker
;
2734 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2735 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2736 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2737 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2738 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2739 struct anv_cmd_buffer
*secondary
);
2740 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2741 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2742 struct anv_cmd_buffer
*cmd_buffer
,
2743 const VkSemaphore
*in_semaphores
,
2744 const uint64_t *in_wait_values
,
2745 uint32_t num_in_semaphores
,
2746 const VkSemaphore
*out_semaphores
,
2747 const uint64_t *out_signal_values
,
2748 uint32_t num_out_semaphores
,
2751 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2753 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2754 const void *data
, uint32_t size
, uint32_t alignment
);
2755 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2756 uint32_t *a
, uint32_t *b
,
2757 uint32_t dwords
, uint32_t alignment
);
2760 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2762 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2763 uint32_t entries
, uint32_t *state_offset
);
2765 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2767 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2768 uint32_t size
, uint32_t alignment
);
2771 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2773 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2774 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2775 bool depth_clamp_enable
);
2776 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2778 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2779 struct anv_render_pass
*pass
,
2780 struct anv_framebuffer
*framebuffer
,
2781 const VkClearValue
*clear_values
);
2783 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2786 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2787 gl_shader_stage stage
);
2789 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2791 const struct anv_image_view
*
2792 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2795 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2796 uint32_t num_entries
,
2797 uint32_t *state_offset
,
2798 struct anv_state
*bt_state
);
2800 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2802 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2804 enum anv_fence_type
{
2805 ANV_FENCE_TYPE_NONE
= 0,
2807 ANV_FENCE_TYPE_SYNCOBJ
,
2811 enum anv_bo_fence_state
{
2812 /** Indicates that this is a new (or newly reset fence) */
2813 ANV_BO_FENCE_STATE_RESET
,
2815 /** Indicates that this fence has been submitted to the GPU but is still
2816 * (as far as we know) in use by the GPU.
2818 ANV_BO_FENCE_STATE_SUBMITTED
,
2820 ANV_BO_FENCE_STATE_SIGNALED
,
2823 struct anv_fence_impl
{
2824 enum anv_fence_type type
;
2827 /** Fence implementation for BO fences
2829 * These fences use a BO and a set of CPU-tracked state flags. The BO
2830 * is added to the object list of the last execbuf call in a QueueSubmit
2831 * and is marked EXEC_WRITE. The state flags track when the BO has been
2832 * submitted to the kernel. We need to do this because Vulkan lets you
2833 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2834 * will say it's idle in this case.
2838 enum anv_bo_fence_state state
;
2841 /** DRM syncobj handle for syncobj-based fences */
2845 struct wsi_fence
*fence_wsi
;
2850 /* Permanent fence state. Every fence has some form of permanent state
2851 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2852 * cross-process fences) or it could just be a dummy for use internally.
2854 struct anv_fence_impl permanent
;
2856 /* Temporary fence state. A fence *may* have temporary state. That state
2857 * is added to the fence by an import operation and is reset back to
2858 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2859 * state cannot be signaled because the fence must already be signaled
2860 * before the temporary state can be exported from the fence in the other
2861 * process and imported here.
2863 struct anv_fence_impl temporary
;
2868 struct anv_state state
;
2871 enum anv_semaphore_type
{
2872 ANV_SEMAPHORE_TYPE_NONE
= 0,
2873 ANV_SEMAPHORE_TYPE_DUMMY
,
2874 ANV_SEMAPHORE_TYPE_BO
,
2875 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2876 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2877 ANV_SEMAPHORE_TYPE_TIMELINE
,
2880 struct anv_timeline_point
{
2881 struct list_head link
;
2885 /* Number of waiter on this point, when > 0 the point should not be garbage
2890 /* BO used for synchronization. */
2894 struct anv_timeline
{
2895 pthread_mutex_t mutex
;
2896 pthread_cond_t cond
;
2898 uint64_t highest_past
;
2899 uint64_t highest_pending
;
2901 struct list_head points
;
2902 struct list_head free_points
;
2905 struct anv_semaphore_impl
{
2906 enum anv_semaphore_type type
;
2909 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2910 * This BO will be added to the object list on any execbuf2 calls for
2911 * which this semaphore is used as a wait or signal fence. When used as
2912 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2916 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2917 * If the semaphore is in the unsignaled state due to either just being
2918 * created or because it has been used for a wait, fd will be -1.
2922 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2923 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2924 * import so we don't need to bother with a userspace cache.
2928 /* Non shareable timeline semaphore
2930 * Used when kernel don't have support for timeline semaphores.
2932 struct anv_timeline timeline
;
2936 struct anv_semaphore
{
2939 /* Permanent semaphore state. Every semaphore has some form of permanent
2940 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2941 * (for cross-process semaphores0 or it could just be a dummy for use
2944 struct anv_semaphore_impl permanent
;
2946 /* Temporary semaphore state. A semaphore *may* have temporary state.
2947 * That state is added to the semaphore by an import operation and is reset
2948 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2949 * semaphore with temporary state cannot be signaled because the semaphore
2950 * must already be signaled before the temporary state can be exported from
2951 * the semaphore in the other process and imported here.
2953 struct anv_semaphore_impl temporary
;
2956 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2957 struct anv_semaphore
*semaphore
);
2959 struct anv_shader_module
{
2960 unsigned char sha1
[20];
2965 static inline gl_shader_stage
2966 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2968 assert(__builtin_popcount(vk_stage
) == 1);
2969 return ffs(vk_stage
) - 1;
2972 static inline VkShaderStageFlagBits
2973 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2975 return (1 << mesa_stage
);
2978 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2980 #define anv_foreach_stage(stage, stage_bits) \
2981 for (gl_shader_stage stage, \
2982 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2983 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2984 __tmp &= ~(1 << (stage)))
2986 struct anv_pipeline_bind_map
{
2987 unsigned char surface_sha1
[20];
2988 unsigned char sampler_sha1
[20];
2989 unsigned char push_sha1
[20];
2991 uint32_t surface_count
;
2992 uint32_t sampler_count
;
2994 struct anv_pipeline_binding
* surface_to_descriptor
;
2995 struct anv_pipeline_binding
* sampler_to_descriptor
;
2997 struct anv_push_range push_ranges
[4];
3000 struct anv_shader_bin_key
{
3005 struct anv_shader_bin
{
3008 const struct anv_shader_bin_key
*key
;
3010 struct anv_state kernel
;
3011 uint32_t kernel_size
;
3013 struct anv_state constant_data
;
3014 uint32_t constant_data_size
;
3016 const struct brw_stage_prog_data
*prog_data
;
3017 uint32_t prog_data_size
;
3019 struct brw_compile_stats stats
[3];
3022 struct nir_xfb_info
*xfb_info
;
3024 struct anv_pipeline_bind_map bind_map
;
3027 struct anv_shader_bin
*
3028 anv_shader_bin_create(struct anv_device
*device
,
3029 const void *key
, uint32_t key_size
,
3030 const void *kernel
, uint32_t kernel_size
,
3031 const void *constant_data
, uint32_t constant_data_size
,
3032 const struct brw_stage_prog_data
*prog_data
,
3033 uint32_t prog_data_size
, const void *prog_data_param
,
3034 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3035 const struct nir_xfb_info
*xfb_info
,
3036 const struct anv_pipeline_bind_map
*bind_map
);
3039 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3042 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3044 assert(shader
&& shader
->ref_cnt
>= 1);
3045 p_atomic_inc(&shader
->ref_cnt
);
3049 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3051 assert(shader
&& shader
->ref_cnt
>= 1);
3052 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3053 anv_shader_bin_destroy(device
, shader
);
3056 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
3057 #define MAX_PIPELINE_EXECUTABLES 7
3059 struct anv_pipeline_executable
{
3060 gl_shader_stage stage
;
3062 struct brw_compile_stats stats
;
3068 struct anv_pipeline
{
3069 struct anv_device
* device
;
3070 struct anv_batch batch
;
3071 uint32_t batch_data
[512];
3072 struct anv_reloc_list batch_relocs
;
3073 anv_cmd_dirty_mask_t dynamic_state_mask
;
3074 struct anv_dynamic_state dynamic_state
;
3078 VkPipelineCreateFlags flags
;
3079 struct anv_subpass
* subpass
;
3081 bool needs_data_cache
;
3083 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3085 uint32_t num_executables
;
3086 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
3089 const struct gen_l3_config
* l3_config
;
3090 uint32_t total_size
;
3093 VkShaderStageFlags active_stages
;
3094 struct anv_state blend_state
;
3097 struct anv_pipeline_vertex_binding
{
3100 uint32_t instance_divisor
;
3105 bool primitive_restart
;
3108 uint32_t cs_right_mask
;
3111 bool depth_test_enable
;
3112 bool writes_stencil
;
3113 bool stencil_test_enable
;
3114 bool depth_clamp_enable
;
3115 bool depth_clip_enable
;
3116 bool sample_shading_enable
;
3118 bool depth_bounds_test_enable
;
3122 uint32_t depth_stencil_state
[3];
3128 uint32_t wm_depth_stencil
[3];
3132 uint32_t wm_depth_stencil
[4];
3135 uint32_t interface_descriptor_data
[8];
3139 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3140 gl_shader_stage stage
)
3142 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3145 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3146 static inline const struct brw_##prefix##_prog_data * \
3147 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3149 if (anv_pipeline_has_stage(pipeline, stage)) { \
3150 return (const struct brw_##prefix##_prog_data *) \
3151 pipeline->shaders[stage]->prog_data; \
3157 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3158 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3159 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3160 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3161 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3162 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3164 static inline const struct brw_vue_prog_data
*
3165 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3167 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3168 return &get_gs_prog_data(pipeline
)->base
;
3169 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3170 return &get_tes_prog_data(pipeline
)->base
;
3172 return &get_vs_prog_data(pipeline
)->base
;
3176 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3177 struct anv_pipeline_cache
*cache
,
3178 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3179 const VkAllocationCallbacks
*alloc
);
3182 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3183 struct anv_pipeline_cache
*cache
,
3184 const VkComputePipelineCreateInfo
*info
,
3185 const struct anv_shader_module
*module
,
3186 const char *entrypoint
,
3187 const VkSpecializationInfo
*spec_info
);
3189 struct anv_format_plane
{
3190 enum isl_format isl_format
:16;
3191 struct isl_swizzle swizzle
;
3193 /* Whether this plane contains chroma channels */
3196 /* For downscaling of YUV planes */
3197 uint8_t denominator_scales
[2];
3199 /* How to map sampled ycbcr planes to a single 4 component element. */
3200 struct isl_swizzle ycbcr_swizzle
;
3202 /* What aspect is associated to this plane */
3203 VkImageAspectFlags aspect
;
3208 struct anv_format_plane planes
[3];
3214 static inline uint32_t
3215 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3216 VkImageAspectFlags aspect_mask
)
3218 switch (aspect_mask
) {
3219 case VK_IMAGE_ASPECT_COLOR_BIT
:
3220 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3221 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3223 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3224 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3227 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3229 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3232 /* Purposefully assert with depth/stencil aspects. */
3233 unreachable("invalid image aspect");
3237 static inline VkImageAspectFlags
3238 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3241 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3242 if (util_bitcount(image_aspects
) > 1)
3243 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3244 return VK_IMAGE_ASPECT_COLOR_BIT
;
3246 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3247 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3248 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3249 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3252 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3253 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3255 const struct anv_format
*
3256 anv_get_format(VkFormat format
);
3258 static inline uint32_t
3259 anv_get_format_planes(VkFormat vk_format
)
3261 const struct anv_format
*format
= anv_get_format(vk_format
);
3263 return format
!= NULL
? format
->n_planes
: 0;
3266 struct anv_format_plane
3267 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3268 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3270 static inline enum isl_format
3271 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3272 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3274 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3277 static inline struct isl_swizzle
3278 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3280 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3281 * RGB as RGBA for texturing
3283 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3284 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3286 /* But it doesn't matter what we render to that channel */
3287 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3293 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3296 * Subsurface of an anv_image.
3298 struct anv_surface
{
3299 /** Valid only if isl_surf::size_B > 0. */
3300 struct isl_surf isl
;
3303 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3309 VkImageType type
; /**< VkImageCreateInfo::imageType */
3310 /* The original VkFormat provided by the client. This may not match any
3311 * of the actual surface formats.
3314 const struct anv_format
*format
;
3316 VkImageAspectFlags aspects
;
3319 uint32_t array_size
;
3320 uint32_t samples
; /**< VkImageCreateInfo::samples */
3322 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3323 VkImageUsageFlags stencil_usage
;
3324 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3325 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3327 /** True if this is needs to be bound to an appropriately tiled BO.
3329 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3330 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3331 * we require a dedicated allocation so that we can know to allocate a
3334 bool needs_set_tiling
;
3337 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3338 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3340 uint64_t drm_format_mod
;
3345 /* Whether the image is made of several underlying buffer objects rather a
3346 * single one with different offsets.
3350 /* All the formats that can be used when creating views of this image
3351 * are CCS_E compatible.
3353 bool ccs_e_compatible
;
3355 /* Image was created with external format. */
3356 bool external_format
;
3361 * For each foo, anv_image::planes[x].surface is valid if and only if
3362 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3363 * to figure the number associated with a given aspect.
3365 * The hardware requires that the depth buffer and stencil buffer be
3366 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3367 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3368 * allocate the depth and stencil buffers as separate surfaces in the same
3373 * -----------------------
3375 * ----------------------- |
3376 * | shadow surface0 | |
3377 * ----------------------- | Plane 0
3378 * | aux surface0 | |
3379 * ----------------------- |
3380 * | fast clear colors0 | \|/
3381 * -----------------------
3383 * ----------------------- |
3384 * | shadow surface1 | |
3385 * ----------------------- | Plane 1
3386 * | aux surface1 | |
3387 * ----------------------- |
3388 * | fast clear colors1 | \|/
3389 * -----------------------
3392 * -----------------------
3396 * Offset of the entire plane (whenever the image is disjoint this is
3404 struct anv_surface surface
;
3407 * A surface which shadows the main surface and may have different
3408 * tiling. This is used for sampling using a tiling that isn't supported
3409 * for other operations.
3411 struct anv_surface shadow_surface
;
3414 * For color images, this is the aux usage for this image when not used
3415 * as a color attachment.
3417 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3418 * image has a HiZ buffer.
3420 enum isl_aux_usage aux_usage
;
3422 struct anv_surface aux_surface
;
3425 * Offset of the fast clear state (used to compute the
3426 * fast_clear_state_offset of the following planes).
3428 uint32_t fast_clear_state_offset
;
3431 * BO associated with this plane, set when bound.
3433 struct anv_address address
;
3436 * Address of the main surface used to fill the aux map table. This is
3437 * used at destruction of the image since the Vulkan spec does not
3438 * guarantee that the address.bo field we still be valid at destruction.
3440 uint64_t aux_map_surface_address
;
3443 * When destroying the image, also free the bo.
3449 /* The ordering of this enum is important */
3450 enum anv_fast_clear_type
{
3451 /** Image does not have/support any fast-clear blocks */
3452 ANV_FAST_CLEAR_NONE
= 0,
3453 /** Image has/supports fast-clear but only to the default value */
3454 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3455 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3456 ANV_FAST_CLEAR_ANY
= 2,
3459 /* Returns the number of auxiliary buffer levels attached to an image. */
3460 static inline uint8_t
3461 anv_image_aux_levels(const struct anv_image
* const image
,
3462 VkImageAspectFlagBits aspect
)
3464 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3466 /* The Gen12 CCS aux surface is represented with only one level. */
3467 const uint8_t aux_logical_levels
=
3468 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3469 image
->planes
[plane
].surface
.isl
.levels
:
3470 image
->planes
[plane
].aux_surface
.isl
.levels
;
3472 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3473 aux_logical_levels
: 0;
3476 /* Returns the number of auxiliary buffer layers attached to an image. */
3477 static inline uint32_t
3478 anv_image_aux_layers(const struct anv_image
* const image
,
3479 VkImageAspectFlagBits aspect
,
3480 const uint8_t miplevel
)
3484 /* The miplevel must exist in the main buffer. */
3485 assert(miplevel
< image
->levels
);
3487 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3488 /* There are no layers with auxiliary data because the miplevel has no
3493 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3495 /* The Gen12 CCS aux surface is represented with only one layer. */
3496 const struct isl_extent4d
*aux_logical_level0_px
=
3497 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3498 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3499 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3501 return MAX2(aux_logical_level0_px
->array_len
,
3502 aux_logical_level0_px
->depth
>> miplevel
);
3506 static inline struct anv_address
3507 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3508 const struct anv_image
*image
,
3509 VkImageAspectFlagBits aspect
)
3511 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3513 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3514 return anv_address_add(image
->planes
[plane
].address
,
3515 image
->planes
[plane
].fast_clear_state_offset
);
3518 static inline struct anv_address
3519 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3520 const struct anv_image
*image
,
3521 VkImageAspectFlagBits aspect
)
3523 struct anv_address addr
=
3524 anv_image_get_clear_color_addr(device
, image
, aspect
);
3526 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3527 device
->isl_dev
.ss
.clear_color_state_size
:
3528 device
->isl_dev
.ss
.clear_value_size
;
3529 return anv_address_add(addr
, clear_color_state_size
);
3532 static inline struct anv_address
3533 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3534 const struct anv_image
*image
,
3535 VkImageAspectFlagBits aspect
,
3536 uint32_t level
, uint32_t array_layer
)
3538 assert(level
< anv_image_aux_levels(image
, aspect
));
3539 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3540 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3541 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3543 struct anv_address addr
=
3544 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3545 addr
.offset
+= 4; /* Go past the fast clear type */
3547 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3548 for (uint32_t l
= 0; l
< level
; l
++)
3549 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3551 addr
.offset
+= level
* image
->array_size
* 4;
3553 addr
.offset
+= array_layer
* 4;
3555 assert(addr
.offset
<
3556 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3560 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3562 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3563 const struct anv_image
*image
)
3565 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3568 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3569 * struct. There's documentation which suggests that this feature actually
3570 * reduces performance on BDW, but it has only been observed to help so
3571 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3572 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3574 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3577 return image
->samples
== 1;
3581 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3582 const struct anv_image
*image
,
3585 return device
->info
.has_aux_map
&&
3586 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3590 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3591 const struct anv_image
*image
,
3592 VkImageAspectFlagBits aspect
,
3593 enum isl_aux_usage aux_usage
,
3595 uint32_t base_layer
,
3596 uint32_t layer_count
);
3599 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3600 const struct anv_image
*image
,
3601 VkImageAspectFlagBits aspect
,
3602 enum isl_aux_usage aux_usage
,
3603 enum isl_format format
, struct isl_swizzle swizzle
,
3604 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3605 VkRect2D area
, union isl_color_value clear_color
);
3607 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3608 const struct anv_image
*image
,
3609 VkImageAspectFlags aspects
,
3610 enum isl_aux_usage depth_aux_usage
,
3612 uint32_t base_layer
, uint32_t layer_count
,
3614 float depth_value
, uint8_t stencil_value
);
3616 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3617 const struct anv_image
*src_image
,
3618 enum isl_aux_usage src_aux_usage
,
3619 uint32_t src_level
, uint32_t src_base_layer
,
3620 const struct anv_image
*dst_image
,
3621 enum isl_aux_usage dst_aux_usage
,
3622 uint32_t dst_level
, uint32_t dst_base_layer
,
3623 VkImageAspectFlagBits aspect
,
3624 uint32_t src_x
, uint32_t src_y
,
3625 uint32_t dst_x
, uint32_t dst_y
,
3626 uint32_t width
, uint32_t height
,
3627 uint32_t layer_count
,
3628 enum blorp_filter filter
);
3630 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3631 const struct anv_image
*image
,
3632 VkImageAspectFlagBits aspect
, uint32_t level
,
3633 uint32_t base_layer
, uint32_t layer_count
,
3634 enum isl_aux_op hiz_op
);
3636 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3637 const struct anv_image
*image
,
3638 VkImageAspectFlags aspects
,
3640 uint32_t base_layer
, uint32_t layer_count
,
3641 VkRect2D area
, uint8_t stencil_value
);
3643 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3644 const struct anv_image
*image
,
3645 enum isl_format format
,
3646 VkImageAspectFlagBits aspect
,
3647 uint32_t base_layer
, uint32_t layer_count
,
3648 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3651 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3652 const struct anv_image
*image
,
3653 enum isl_format format
,
3654 VkImageAspectFlagBits aspect
, uint32_t level
,
3655 uint32_t base_layer
, uint32_t layer_count
,
3656 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3660 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3661 const struct anv_image
*image
,
3662 VkImageAspectFlagBits aspect
,
3663 uint32_t base_level
, uint32_t level_count
,
3664 uint32_t base_layer
, uint32_t layer_count
);
3667 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3668 const struct anv_image
*image
,
3669 const VkImageAspectFlagBits aspect
,
3670 const VkImageLayout layout
);
3672 enum anv_fast_clear_type
3673 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3674 const struct anv_image
* const image
,
3675 const VkImageAspectFlagBits aspect
,
3676 const VkImageLayout layout
);
3678 /* This is defined as a macro so that it works for both
3679 * VkImageSubresourceRange and VkImageSubresourceLayers
3681 #define anv_get_layerCount(_image, _range) \
3682 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3683 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3685 static inline uint32_t
3686 anv_get_levelCount(const struct anv_image
*image
,
3687 const VkImageSubresourceRange
*range
)
3689 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3690 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3693 static inline VkImageAspectFlags
3694 anv_image_expand_aspects(const struct anv_image
*image
,
3695 VkImageAspectFlags aspects
)
3697 /* If the underlying image has color plane aspects and
3698 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3699 * the underlying image. */
3700 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3701 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3702 return image
->aspects
;
3708 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3709 VkImageAspectFlags aspects2
)
3711 if (aspects1
== aspects2
)
3714 /* Only 1 color aspects are compatibles. */
3715 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3716 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3717 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3723 struct anv_image_view
{
3724 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3726 VkImageAspectFlags aspect_mask
;
3728 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3732 uint32_t image_plane
;
3734 struct isl_view isl
;
3737 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3738 * image layout of SHADER_READ_ONLY_OPTIMAL or
3739 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3741 struct anv_surface_state optimal_sampler_surface_state
;
3744 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3745 * image layout of GENERAL.
3747 struct anv_surface_state general_sampler_surface_state
;
3750 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3751 * states for write-only and readable, using the real format for
3752 * write-only and the lowered format for readable.
3754 struct anv_surface_state storage_surface_state
;
3755 struct anv_surface_state writeonly_storage_surface_state
;
3757 struct brw_image_param storage_image_param
;
3761 enum anv_image_view_state_flags
{
3762 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3763 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3766 void anv_image_fill_surface_state(struct anv_device
*device
,
3767 const struct anv_image
*image
,
3768 VkImageAspectFlagBits aspect
,
3769 const struct isl_view
*view
,
3770 isl_surf_usage_flags_t view_usage
,
3771 enum isl_aux_usage aux_usage
,
3772 const union isl_color_value
*clear_color
,
3773 enum anv_image_view_state_flags flags
,
3774 struct anv_surface_state
*state_inout
,
3775 struct brw_image_param
*image_param_out
);
3777 struct anv_image_create_info
{
3778 const VkImageCreateInfo
*vk_info
;
3780 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3781 isl_tiling_flags_t isl_tiling_flags
;
3783 /** These flags will be added to any derived from VkImageCreateInfo. */
3784 isl_surf_usage_flags_t isl_extra_usage_flags
;
3787 bool external_format
;
3790 VkResult
anv_image_create(VkDevice _device
,
3791 const struct anv_image_create_info
*info
,
3792 const VkAllocationCallbacks
* alloc
,
3795 const struct anv_surface
*
3796 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3797 VkImageAspectFlags aspect_mask
);
3800 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3802 static inline struct VkExtent3D
3803 anv_sanitize_image_extent(const VkImageType imageType
,
3804 const struct VkExtent3D imageExtent
)
3806 switch (imageType
) {
3807 case VK_IMAGE_TYPE_1D
:
3808 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3809 case VK_IMAGE_TYPE_2D
:
3810 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3811 case VK_IMAGE_TYPE_3D
:
3814 unreachable("invalid image type");
3818 static inline struct VkOffset3D
3819 anv_sanitize_image_offset(const VkImageType imageType
,
3820 const struct VkOffset3D imageOffset
)
3822 switch (imageType
) {
3823 case VK_IMAGE_TYPE_1D
:
3824 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3825 case VK_IMAGE_TYPE_2D
:
3826 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3827 case VK_IMAGE_TYPE_3D
:
3830 unreachable("invalid image type");
3834 VkFormatFeatureFlags
3835 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3837 const struct anv_format
*anv_format
,
3838 VkImageTiling vk_tiling
);
3840 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3841 struct anv_state state
,
3842 enum isl_format format
,
3843 struct anv_address address
,
3844 uint32_t range
, uint32_t stride
);
3847 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3848 const struct anv_attachment_state
*att_state
,
3849 const struct anv_image_view
*iview
)
3851 const struct isl_format_layout
*view_fmtl
=
3852 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3854 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3855 if (view_fmtl->channels.c.bits) \
3856 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3858 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3859 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3860 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3861 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3863 #undef COPY_CLEAR_COLOR_CHANNEL
3867 struct anv_ycbcr_conversion
{
3868 const struct anv_format
* format
;
3869 VkSamplerYcbcrModelConversion ycbcr_model
;
3870 VkSamplerYcbcrRange ycbcr_range
;
3871 VkComponentSwizzle mapping
[4];
3872 VkChromaLocation chroma_offsets
[2];
3873 VkFilter chroma_filter
;
3874 bool chroma_reconstruction
;
3877 struct anv_sampler
{
3878 uint32_t state
[3][4];
3880 struct anv_ycbcr_conversion
*conversion
;
3882 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3883 * and with a 32-byte stride for use as bindless samplers.
3885 struct anv_state bindless_state
;
3888 struct anv_framebuffer
{
3893 uint32_t attachment_count
;
3894 struct anv_image_view
* attachments
[0];
3897 struct anv_subpass_attachment
{
3898 VkImageUsageFlagBits usage
;
3899 uint32_t attachment
;
3900 VkImageLayout layout
;
3902 /* Used only with attachment containing stencil data. */
3903 VkImageLayout stencil_layout
;
3906 struct anv_subpass
{
3907 uint32_t attachment_count
;
3910 * A pointer to all attachment references used in this subpass.
3911 * Only valid if ::attachment_count > 0.
3913 struct anv_subpass_attachment
* attachments
;
3914 uint32_t input_count
;
3915 struct anv_subpass_attachment
* input_attachments
;
3916 uint32_t color_count
;
3917 struct anv_subpass_attachment
* color_attachments
;
3918 struct anv_subpass_attachment
* resolve_attachments
;
3920 struct anv_subpass_attachment
* depth_stencil_attachment
;
3921 struct anv_subpass_attachment
* ds_resolve_attachment
;
3922 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3923 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3927 /** Subpass has a depth/stencil self-dependency */
3928 bool has_ds_self_dep
;
3930 /** Subpass has at least one color resolve attachment */
3931 bool has_color_resolve
;
3934 static inline unsigned
3935 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3937 return MAX2(1, util_bitcount(subpass
->view_mask
));
3940 struct anv_render_pass_attachment
{
3941 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3942 * its members individually.
3946 VkImageUsageFlags usage
;
3947 VkAttachmentLoadOp load_op
;
3948 VkAttachmentStoreOp store_op
;
3949 VkAttachmentLoadOp stencil_load_op
;
3950 VkImageLayout initial_layout
;
3951 VkImageLayout final_layout
;
3952 VkImageLayout first_subpass_layout
;
3954 VkImageLayout stencil_initial_layout
;
3955 VkImageLayout stencil_final_layout
;
3957 /* The subpass id in which the attachment will be used last. */
3958 uint32_t last_subpass_idx
;
3961 struct anv_render_pass
{
3962 uint32_t attachment_count
;
3963 uint32_t subpass_count
;
3964 /* An array of subpass_count+1 flushes, one per subpass boundary */
3965 enum anv_pipe_bits
* subpass_flushes
;
3966 struct anv_render_pass_attachment
* attachments
;
3967 struct anv_subpass subpasses
[0];
3970 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3972 struct anv_query_pool
{
3974 VkQueryPipelineStatisticFlags pipeline_statistics
;
3975 /** Stride between slots, in bytes */
3977 /** Number of slots in this query pool */
3982 int anv_get_instance_entrypoint_index(const char *name
);
3983 int anv_get_device_entrypoint_index(const char *name
);
3984 int anv_get_physical_device_entrypoint_index(const char *name
);
3986 const char *anv_get_instance_entry_name(int index
);
3987 const char *anv_get_physical_device_entry_name(int index
);
3988 const char *anv_get_device_entry_name(int index
);
3991 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3992 const struct anv_instance_extension_table
*instance
);
3994 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3995 const struct anv_instance_extension_table
*instance
);
3997 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3998 const struct anv_instance_extension_table
*instance
,
3999 const struct anv_device_extension_table
*device
);
4001 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4004 void anv_dump_image_to_ppm(struct anv_device
*device
,
4005 struct anv_image
*image
, unsigned miplevel
,
4006 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4007 const char *filename
);
4009 enum anv_dump_action
{
4010 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4013 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4014 void anv_dump_finish(void);
4016 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4018 static inline uint32_t
4019 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4021 /* This function must be called from within a subpass. */
4022 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4024 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4026 /* The id of this subpass shouldn't exceed the number of subpasses in this
4027 * render pass minus 1.
4029 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4033 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4034 void anv_device_perf_init(struct anv_device
*device
);
4036 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4038 static inline struct __anv_type * \
4039 __anv_type ## _from_handle(__VkType _handle) \
4041 return (struct __anv_type *) _handle; \
4044 static inline __VkType \
4045 __anv_type ## _to_handle(struct __anv_type *_obj) \
4047 return (__VkType) _obj; \
4050 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4052 static inline struct __anv_type * \
4053 __anv_type ## _from_handle(__VkType _handle) \
4055 return (struct __anv_type *)(uintptr_t) _handle; \
4058 static inline __VkType \
4059 __anv_type ## _to_handle(struct __anv_type *_obj) \
4061 return (__VkType)(uintptr_t) _obj; \
4064 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4065 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4067 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4068 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4069 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4070 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4071 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4073 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4074 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4075 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4076 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4077 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4078 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4079 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4080 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4081 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4082 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4083 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4084 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4085 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4086 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4087 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4088 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4089 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4090 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4091 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4092 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4093 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4094 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4095 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4097 /* Gen-specific function declarations */
4099 # include "anv_genX.h"
4101 # define genX(x) gen7_##x
4102 # include "anv_genX.h"
4104 # define genX(x) gen75_##x
4105 # include "anv_genX.h"
4107 # define genX(x) gen8_##x
4108 # include "anv_genX.h"
4110 # define genX(x) gen9_##x
4111 # include "anv_genX.h"
4113 # define genX(x) gen10_##x
4114 # include "anv_genX.h"
4116 # define genX(x) gen11_##x
4117 # include "anv_genX.h"
4119 # define genX(x) gen12_##x
4120 # include "anv_genX.h"
4124 #endif /* ANV_PRIVATE_H */