projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
anv/image: Separate modifiers from legacy scanout
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 /* Pre-declarations needed for WSI entrypoints */
56 struct wl_surface;
57 struct wl_display;
58 typedef struct xcb_connection_t xcb_connection_t;
59 typedef uint32_t xcb_visualid_t;
60 typedef uint32_t xcb_window_t;
61
62 struct anv_buffer;
63 struct anv_buffer_view;
64 struct anv_image_view;
65 struct anv_instance;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "anv_extensions.h"
76 #include "isl/isl.h"
77
78 #include "common/gen_debug.h"
79 #include "common/intel_log.h"
80 #include "wsi_common.h"
81
82 /* Allowing different clear colors requires us to perform a depth resolve at
83 * the end of certain render passes. This is because while slow clears store
84 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
85 * See the PRMs for examples describing when additional resolves would be
86 * necessary. To enable fast clears without requiring extra resolves, we set
87 * the clear value to a globally-defined one. We could allow different values
88 * if the user doesn't expect coherent data during or after a render passes
89 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
90 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
91 * 1.0f seems to be the only value used. The only application that doesn't set
92 * this value does so through the usage of an seemingly uninitialized clear
93 * value.
94 */
95 #define ANV_HZ_FC_VAL 1.0f
96
97 #define MAX_VBS 28
98 #define MAX_SETS 8
99 #define MAX_RTS 8
100 #define MAX_VIEWPORTS 16
101 #define MAX_SCISSORS 16
102 #define MAX_PUSH_CONSTANTS_SIZE 128
103 #define MAX_DYNAMIC_BUFFERS 16
104 #define MAX_IMAGES 8
105 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
106
107 #define ANV_SVGS_VB_INDEX MAX_VBS
108 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
109
110 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111
112 static inline uint32_t
113 align_down_npot_u32(uint32_t v, uint32_t a)
114 {
115 return v - (v % a);
116 }
117
118 static inline uint32_t
119 align_u32(uint32_t v, uint32_t a)
120 {
121 assert(a != 0 && a == (a & -a));
122 return (v + a - 1) & ~(a - 1);
123 }
124
125 static inline uint64_t
126 align_u64(uint64_t v, uint64_t a)
127 {
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
130 }
131
132 static inline int32_t
133 align_i32(int32_t v, int32_t a)
134 {
135 assert(a != 0 && a == (a & -a));
136 return (v + a - 1) & ~(a - 1);
137 }
138
139 /** Alignment must be a power of 2. */
140 static inline bool
141 anv_is_aligned(uintmax_t n, uintmax_t a)
142 {
143 assert(a == (a & -a));
144 return (n & (a - 1)) == 0;
145 }
146
147 static inline uint32_t
148 anv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155
156 static inline float
157 anv_clamp_f(float f, float min, float max)
158 {
159 assert(min < max);
160
161 if (f > max)
162 return max;
163 else if (f < min)
164 return min;
165 else
166 return f;
167 }
168
169 static inline bool
170 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
171 {
172 if (*inout_mask & clear_mask) {
173 *inout_mask &= ~clear_mask;
174 return true;
175 } else {
176 return false;
177 }
178 }
179
180 static inline union isl_color_value
181 vk_to_isl_color(VkClearColorValue color)
182 {
183 return (union isl_color_value) {
184 .u32 = {
185 color.uint32[0],
186 color.uint32[1],
187 color.uint32[2],
188 color.uint32[3],
189 },
190 };
191 }
192
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
197
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 })
202
203 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
204 * to be added here in order to utilize mapping in debug/error/perf macros.
205 */
206 #define REPORT_OBJECT_TYPE(o) \
207 __builtin_choose_expr ( \
208 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
209 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
210 __builtin_choose_expr ( \
211 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
212 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
213 __builtin_choose_expr ( \
214 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
215 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
216 __builtin_choose_expr ( \
217 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
218 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
219 __builtin_choose_expr ( \
220 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
221 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
222 __builtin_choose_expr ( \
223 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
224 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
225 __builtin_choose_expr ( \
226 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
227 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
228 __builtin_choose_expr ( \
229 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
230 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
231 __builtin_choose_expr ( \
232 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
233 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
234 __builtin_choose_expr ( \
235 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
236 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
237 __builtin_choose_expr ( \
238 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
239 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
240 __builtin_choose_expr ( \
241 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
242 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
243 __builtin_choose_expr ( \
244 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
245 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
246 __builtin_choose_expr ( \
247 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
248 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
249 __builtin_choose_expr ( \
250 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
251 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
252 __builtin_choose_expr ( \
253 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
254 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
255 __builtin_choose_expr ( \
256 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
257 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
258 __builtin_choose_expr ( \
259 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
260 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
261 __builtin_choose_expr ( \
262 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
263 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
264 __builtin_choose_expr ( \
265 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
266 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
267 __builtin_choose_expr ( \
268 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
269 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
270 __builtin_choose_expr ( \
271 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
272 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
273 __builtin_choose_expr ( \
274 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
275 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
276 __builtin_choose_expr ( \
277 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
278 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), void*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
300 /* The void expression results in a compile-time error \
301 when assigning the result to something. */ \
302 (void)0)))))))))))))))))))))))))))))))
303
304 /* Whenever we generate an error, pass it through this function. Useful for
305 * debugging, where we can break on it. Only call at error site, not when
306 * propagating errors. Might be useful to plug in a stack trace here.
307 */
308
309 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
310 VkDebugReportObjectTypeEXT type, VkResult error,
311 const char *file, int line, const char *format, ...);
312
313 #ifdef DEBUG
314 #define vk_error(error) __vk_errorf(NULL, NULL,\
315 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
316 error, __FILE__, __LINE__, NULL)
317 #define vk_errorf(instance, obj, error, format, ...)\
318 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
319 __FILE__, __LINE__, format, ## __VA_ARGS__)
320 #else
321 #define vk_error(error) error
322 #define vk_errorf(instance, obj, error, format, ...) error
323 #endif
324
325 /**
326 * Warn on ignored extension structs.
327 *
328 * The Vulkan spec requires us to ignore unsupported or unknown structs in
329 * a pNext chain. In debug mode, emitting warnings for ignored structs may
330 * help us discover structs that we should not have ignored.
331 *
332 *
333 * From the Vulkan 1.0.38 spec:
334 *
335 * Any component of the implementation (the loader, any enabled layers,
336 * and drivers) must skip over, without processing (other than reading the
337 * sType and pNext members) any chained structures with sType values not
338 * defined by extensions supported by that component.
339 */
340 #define anv_debug_ignored_stype(sType) \
341 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
342
343 void __anv_perf_warn(struct anv_instance *instance, const void *object,
344 VkDebugReportObjectTypeEXT type, const char *file,
345 int line, const char *format, ...)
346 anv_printflike(6, 7);
347 void anv_loge(const char *format, ...) anv_printflike(1, 2);
348 void anv_loge_v(const char *format, va_list va);
349
350 /**
351 * Print a FINISHME message, including its source location.
352 */
353 #define anv_finishme(format, ...) \
354 do { \
355 static bool reported = false; \
356 if (!reported) { \
357 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
358 ##__VA_ARGS__); \
359 reported = true; \
360 } \
361 } while (0)
362
363 /**
364 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
365 */
366 #define anv_perf_warn(instance, obj, format, ...) \
367 do { \
368 static bool reported = false; \
369 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
370 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
371 format, ##__VA_ARGS__); \
372 reported = true; \
373 } \
374 } while (0)
375
376 /* A non-fatal assert. Useful for debugging. */
377 #ifdef DEBUG
378 #define anv_assert(x) ({ \
379 if (unlikely(!(x))) \
380 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
381 })
382 #else
383 #define anv_assert(x)
384 #endif
385
386 /* A multi-pointer allocator
387 *
388 * When copying data structures from the user (such as a render pass), it's
389 * common to need to allocate data for a bunch of different things. Instead
390 * of doing several allocations and having to handle all of the error checking
391 * that entails, it can be easier to do a single allocation. This struct
392 * helps facilitate that. The intended usage looks like this:
393 *
394 * ANV_MULTIALLOC(ma)
395 * anv_multialloc_add(&ma, &main_ptr, 1);
396 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
397 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
398 *
399 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
400 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
401 */
402 struct anv_multialloc {
403 size_t size;
404 size_t align;
405
406 uint32_t ptr_count;
407 void **ptrs[8];
408 };
409
410 #define ANV_MULTIALLOC_INIT \
411 ((struct anv_multialloc) { 0, })
412
413 #define ANV_MULTIALLOC(_name) \
414 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
415
416 __attribute__((always_inline))
417 static inline void
418 _anv_multialloc_add(struct anv_multialloc *ma,
419 void **ptr, size_t size, size_t align)
420 {
421 size_t offset = align_u64(ma->size, align);
422 ma->size = offset + size;
423 ma->align = MAX2(ma->align, align);
424
425 /* Store the offset in the pointer. */
426 *ptr = (void *)(uintptr_t)offset;
427
428 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
429 ma->ptrs[ma->ptr_count++] = ptr;
430 }
431
432 #define anv_multialloc_add_size(_ma, _ptr, _size) \
433 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
434
435 #define anv_multialloc_add(_ma, _ptr, _count) \
436 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
437
438 __attribute__((always_inline))
439 static inline void *
440 anv_multialloc_alloc(struct anv_multialloc *ma,
441 const VkAllocationCallbacks *alloc,
442 VkSystemAllocationScope scope)
443 {
444 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
445 if (!ptr)
446 return NULL;
447
448 /* Fill out each of the pointers with their final value.
449 *
450 * for (uint32_t i = 0; i < ma->ptr_count; i++)
451 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
452 *
453 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
454 * constant, GCC is incapable of figuring this out and unrolling the loop
455 * so we have to give it a little help.
456 */
457 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
458 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
459 if ((_i) < ma->ptr_count) \
460 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
461 _ANV_MULTIALLOC_UPDATE_POINTER(0);
462 _ANV_MULTIALLOC_UPDATE_POINTER(1);
463 _ANV_MULTIALLOC_UPDATE_POINTER(2);
464 _ANV_MULTIALLOC_UPDATE_POINTER(3);
465 _ANV_MULTIALLOC_UPDATE_POINTER(4);
466 _ANV_MULTIALLOC_UPDATE_POINTER(5);
467 _ANV_MULTIALLOC_UPDATE_POINTER(6);
468 _ANV_MULTIALLOC_UPDATE_POINTER(7);
469 #undef _ANV_MULTIALLOC_UPDATE_POINTER
470
471 return ptr;
472 }
473
474 __attribute__((always_inline))
475 static inline void *
476 anv_multialloc_alloc2(struct anv_multialloc *ma,
477 const VkAllocationCallbacks *parent_alloc,
478 const VkAllocationCallbacks *alloc,
479 VkSystemAllocationScope scope)
480 {
481 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
482 }
483
484 struct anv_bo {
485 uint32_t gem_handle;
486
487 /* Index into the current validation list. This is used by the
488 * validation list building alrogithm to track which buffers are already
489 * in the validation list so that we can ensure uniqueness.
490 */
491 uint32_t index;
492
493 /* Last known offset. This value is provided by the kernel when we
494 * execbuf and is used as the presumed offset for the next bunch of
495 * relocations.
496 */
497 uint64_t offset;
498
499 uint64_t size;
500 void *map;
501
502 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
503 uint32_t flags;
504 };
505
506 static inline void
507 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
508 {
509 bo->gem_handle = gem_handle;
510 bo->index = 0;
511 bo->offset = -1;
512 bo->size = size;
513 bo->map = NULL;
514 bo->flags = 0;
515 }
516
517 /* Represents a lock-free linked list of "free" things. This is used by
518 * both the block pool and the state pools. Unfortunately, in order to
519 * solve the ABA problem, we can't use a single uint32_t head.
520 */
521 union anv_free_list {
522 struct {
523 int32_t offset;
524
525 /* A simple count that is incremented every time the head changes. */
526 uint32_t count;
527 };
528 uint64_t u64;
529 };
530
531 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
532
533 struct anv_block_state {
534 union {
535 struct {
536 uint32_t next;
537 uint32_t end;
538 };
539 uint64_t u64;
540 };
541 };
542
543 struct anv_block_pool {
544 struct anv_device *device;
545
546 uint64_t bo_flags;
547
548 struct anv_bo bo;
549
550 /* The offset from the start of the bo to the "center" of the block
551 * pool. Pointers to allocated blocks are given by
552 * bo.map + center_bo_offset + offsets.
553 */
554 uint32_t center_bo_offset;
555
556 /* Current memory map of the block pool. This pointer may or may not
557 * point to the actual beginning of the block pool memory. If
558 * anv_block_pool_alloc_back has ever been called, then this pointer
559 * will point to the "center" position of the buffer and all offsets
560 * (negative or positive) given out by the block pool alloc functions
561 * will be valid relative to this pointer.
562 *
563 * In particular, map == bo.map + center_offset
564 */
565 void *map;
566 int fd;
567
568 /**
569 * Array of mmaps and gem handles owned by the block pool, reclaimed when
570 * the block pool is destroyed.
571 */
572 struct u_vector mmap_cleanups;
573
574 struct anv_block_state state;
575
576 struct anv_block_state back_state;
577 };
578
579 /* Block pools are backed by a fixed-size 1GB memfd */
580 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
581
582 /* The center of the block pool is also the middle of the memfd. This may
583 * change in the future if we decide differently for some reason.
584 */
585 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
586
587 static inline uint32_t
588 anv_block_pool_size(struct anv_block_pool *pool)
589 {
590 return pool->state.end + pool->back_state.end;
591 }
592
593 struct anv_state {
594 int32_t offset;
595 uint32_t alloc_size;
596 void *map;
597 };
598
599 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
600
601 struct anv_fixed_size_state_pool {
602 union anv_free_list free_list;
603 struct anv_block_state block;
604 };
605
606 #define ANV_MIN_STATE_SIZE_LOG2 6
607 #define ANV_MAX_STATE_SIZE_LOG2 20
608
609 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
610
611 struct anv_state_pool {
612 struct anv_block_pool block_pool;
613
614 /* The size of blocks which will be allocated from the block pool */
615 uint32_t block_size;
616
617 /** Free list for "back" allocations */
618 union anv_free_list back_alloc_free_list;
619
620 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
621 };
622
623 struct anv_state_stream_block;
624
625 struct anv_state_stream {
626 struct anv_state_pool *state_pool;
627
628 /* The size of blocks to allocate from the state pool */
629 uint32_t block_size;
630
631 /* Current block we're allocating from */
632 struct anv_state block;
633
634 /* Offset into the current block at which to allocate the next state */
635 uint32_t next;
636
637 /* List of all blocks allocated from this pool */
638 struct anv_state_stream_block *block_list;
639 };
640
641 /* The block_pool functions exported for testing only. The block pool should
642 * only be used via a state pool (see below).
643 */
644 VkResult anv_block_pool_init(struct anv_block_pool *pool,
645 struct anv_device *device,
646 uint32_t initial_size,
647 uint64_t bo_flags);
648 void anv_block_pool_finish(struct anv_block_pool *pool);
649 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
650 uint32_t block_size);
651 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
652 uint32_t block_size);
653
654 VkResult anv_state_pool_init(struct anv_state_pool *pool,
655 struct anv_device *device,
656 uint32_t block_size,
657 uint64_t bo_flags);
658 void anv_state_pool_finish(struct anv_state_pool *pool);
659 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
660 uint32_t state_size, uint32_t alignment);
661 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
662 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
663 void anv_state_stream_init(struct anv_state_stream *stream,
664 struct anv_state_pool *state_pool,
665 uint32_t block_size);
666 void anv_state_stream_finish(struct anv_state_stream *stream);
667 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
668 uint32_t size, uint32_t alignment);
669
670 /**
671 * Implements a pool of re-usable BOs. The interface is identical to that
672 * of block_pool except that each block is its own BO.
673 */
674 struct anv_bo_pool {
675 struct anv_device *device;
676
677 uint64_t bo_flags;
678
679 void *free_list[16];
680 };
681
682 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
683 uint64_t bo_flags);
684 void anv_bo_pool_finish(struct anv_bo_pool *pool);
685 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
686 uint32_t size);
687 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
688
689 struct anv_scratch_bo {
690 bool exists;
691 struct anv_bo bo;
692 };
693
694 struct anv_scratch_pool {
695 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
696 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
697 };
698
699 void anv_scratch_pool_init(struct anv_device *device,
700 struct anv_scratch_pool *pool);
701 void anv_scratch_pool_finish(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
704 struct anv_scratch_pool *pool,
705 gl_shader_stage stage,
706 unsigned per_thread_scratch);
707
708 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
709 struct anv_bo_cache {
710 struct hash_table *bo_map;
711 pthread_mutex_t mutex;
712 };
713
714 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
715 void anv_bo_cache_finish(struct anv_bo_cache *cache);
716 VkResult anv_bo_cache_alloc(struct anv_device *device,
717 struct anv_bo_cache *cache,
718 uint64_t size, struct anv_bo **bo);
719 VkResult anv_bo_cache_import(struct anv_device *device,
720 struct anv_bo_cache *cache,
721 int fd, struct anv_bo **bo);
722 VkResult anv_bo_cache_export(struct anv_device *device,
723 struct anv_bo_cache *cache,
724 struct anv_bo *bo_in, int *fd_out);
725 void anv_bo_cache_release(struct anv_device *device,
726 struct anv_bo_cache *cache,
727 struct anv_bo *bo);
728
729 struct anv_memory_type {
730 /* Standard bits passed on to the client */
731 VkMemoryPropertyFlags propertyFlags;
732 uint32_t heapIndex;
733
734 /* Driver-internal book-keeping */
735 VkBufferUsageFlags valid_buffer_usage;
736 };
737
738 struct anv_memory_heap {
739 /* Standard bits passed on to the client */
740 VkDeviceSize size;
741 VkMemoryHeapFlags flags;
742
743 /* Driver-internal book-keeping */
744 bool supports_48bit_addresses;
745 };
746
747 struct anv_physical_device {
748 VK_LOADER_DATA _loader_data;
749
750 struct anv_instance * instance;
751 uint32_t chipset_id;
752 char path[20];
753 const char * name;
754 struct gen_device_info info;
755 /** Amount of "GPU memory" we want to advertise
756 *
757 * Clearly, this value is bogus since Intel is a UMA architecture. On
758 * gen7 platforms, we are limited by GTT size unless we want to implement
759 * fine-grained tracking and GTT splitting. On Broadwell and above we are
760 * practically unlimited. However, we will never report more than 3/4 of
761 * the total system ram to try and avoid running out of RAM.
762 */
763 bool supports_48bit_addresses;
764 struct brw_compiler * compiler;
765 struct isl_device isl_dev;
766 int cmd_parser_version;
767 bool has_exec_async;
768 bool has_exec_capture;
769 bool has_exec_fence;
770 bool has_syncobj;
771 bool has_syncobj_wait;
772
773 struct anv_device_extension_table supported_extensions;
774
775 uint32_t eu_total;
776 uint32_t subslice_total;
777
778 struct {
779 uint32_t type_count;
780 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
781 uint32_t heap_count;
782 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
783 } memory;
784
785 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
786 uint8_t driver_uuid[VK_UUID_SIZE];
787 uint8_t device_uuid[VK_UUID_SIZE];
788
789 struct wsi_device wsi_device;
790 int local_fd;
791 };
792
793 struct anv_instance {
794 VK_LOADER_DATA _loader_data;
795
796 VkAllocationCallbacks alloc;
797
798 uint32_t apiVersion;
799 struct anv_instance_extension_table enabled_extensions;
800 struct anv_dispatch_table dispatch;
801
802 int physicalDeviceCount;
803 struct anv_physical_device physicalDevice;
804
805 struct vk_debug_report_instance debug_report_callbacks;
806 };
807
808 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
809 void anv_finish_wsi(struct anv_physical_device *physical_device);
810
811 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
812 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
813 const char *name);
814
815 struct anv_queue {
816 VK_LOADER_DATA _loader_data;
817
818 struct anv_device * device;
819
820 struct anv_state_pool * pool;
821 };
822
823 struct anv_pipeline_cache {
824 struct anv_device * device;
825 pthread_mutex_t mutex;
826
827 struct hash_table * cache;
828 };
829
830 struct anv_pipeline_bind_map;
831
832 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
833 struct anv_device *device,
834 bool cache_enabled);
835 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
836
837 struct anv_shader_bin *
838 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
839 const void *key, uint32_t key_size);
840 struct anv_shader_bin *
841 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
842 const void *key_data, uint32_t key_size,
843 const void *kernel_data, uint32_t kernel_size,
844 const struct brw_stage_prog_data *prog_data,
845 uint32_t prog_data_size,
846 const struct anv_pipeline_bind_map *bind_map);
847
848 struct anv_device {
849 VK_LOADER_DATA _loader_data;
850
851 VkAllocationCallbacks alloc;
852
853 struct anv_instance * instance;
854 uint32_t chipset_id;
855 struct gen_device_info info;
856 struct isl_device isl_dev;
857 int context_id;
858 int fd;
859 bool can_chain_batches;
860 bool robust_buffer_access;
861 struct anv_device_extension_table enabled_extensions;
862 struct anv_dispatch_table dispatch;
863
864 struct anv_bo_pool batch_bo_pool;
865
866 struct anv_bo_cache bo_cache;
867
868 struct anv_state_pool dynamic_state_pool;
869 struct anv_state_pool instruction_state_pool;
870 struct anv_state_pool surface_state_pool;
871
872 struct anv_bo workaround_bo;
873 struct anv_bo trivial_batch_bo;
874
875 struct anv_pipeline_cache blorp_shader_cache;
876 struct blorp_context blorp;
877
878 struct anv_state border_colors;
879
880 struct anv_queue queue;
881
882 struct anv_scratch_pool scratch_pool;
883
884 uint32_t default_mocs;
885
886 pthread_mutex_t mutex;
887 pthread_cond_t queue_submit;
888 bool lost;
889 };
890
891 static void inline
892 anv_state_flush(struct anv_device *device, struct anv_state state)
893 {
894 if (device->info.has_llc)
895 return;
896
897 gen_flush_range(state.map, state.alloc_size);
898 }
899
900 void anv_device_init_blorp(struct anv_device *device);
901 void anv_device_finish_blorp(struct anv_device *device);
902
903 VkResult anv_device_execbuf(struct anv_device *device,
904 struct drm_i915_gem_execbuffer2 *execbuf,
905 struct anv_bo **execbuf_bos);
906 VkResult anv_device_query_status(struct anv_device *device);
907 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
908 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
909 int64_t timeout);
910
911 void* anv_gem_mmap(struct anv_device *device,
912 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
913 void anv_gem_munmap(void *p, uint64_t size);
914 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
915 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
916 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
917 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
918 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
919 int anv_gem_execbuffer(struct anv_device *device,
920 struct drm_i915_gem_execbuffer2 *execbuf);
921 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
922 uint32_t stride, uint32_t tiling);
923 int anv_gem_create_context(struct anv_device *device);
924 int anv_gem_destroy_context(struct anv_device *device, int context);
925 int anv_gem_get_context_param(int fd, int context, uint32_t param,
926 uint64_t *value);
927 int anv_gem_get_param(int fd, uint32_t param);
928 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
929 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
930 int anv_gem_get_aperture(int fd, uint64_t *size);
931 bool anv_gem_supports_48b_addresses(int fd);
932 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
933 uint32_t *active, uint32_t *pending);
934 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
935 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
936 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
937 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
938 uint32_t read_domains, uint32_t write_domain);
939 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
940 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
941 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
942 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
943 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
944 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
945 uint32_t handle);
946 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
947 uint32_t handle, int fd);
948 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
949 bool anv_gem_supports_syncobj_wait(int fd);
950 int anv_gem_syncobj_wait(struct anv_device *device,
951 uint32_t *handles, uint32_t num_handles,
952 int64_t abs_timeout_ns, bool wait_all);
953
954 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
955
956 struct anv_reloc_list {
957 uint32_t num_relocs;
958 uint32_t array_length;
959 struct drm_i915_gem_relocation_entry * relocs;
960 struct anv_bo ** reloc_bos;
961 };
962
963 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
964 const VkAllocationCallbacks *alloc);
965 void anv_reloc_list_finish(struct anv_reloc_list *list,
966 const VkAllocationCallbacks *alloc);
967
968 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
969 const VkAllocationCallbacks *alloc,
970 uint32_t offset, struct anv_bo *target_bo,
971 uint32_t delta);
972
973 struct anv_batch_bo {
974 /* Link in the anv_cmd_buffer.owned_batch_bos list */
975 struct list_head link;
976
977 struct anv_bo bo;
978
979 /* Bytes actually consumed in this batch BO */
980 uint32_t length;
981
982 struct anv_reloc_list relocs;
983 };
984
985 struct anv_batch {
986 const VkAllocationCallbacks * alloc;
987
988 void * start;
989 void * end;
990 void * next;
991
992 struct anv_reloc_list * relocs;
993
994 /* This callback is called (with the associated user data) in the event
995 * that the batch runs out of space.
996 */
997 VkResult (*extend_cb)(struct anv_batch *, void *);
998 void * user_data;
999
1000 /**
1001 * Current error status of the command buffer. Used to track inconsistent
1002 * or incomplete command buffer states that are the consequence of run-time
1003 * errors such as out of memory scenarios. We want to track this in the
1004 * batch because the command buffer object is not visible to some parts
1005 * of the driver.
1006 */
1007 VkResult status;
1008 };
1009
1010 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1011 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1012 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1013 void *location, struct anv_bo *bo, uint32_t offset);
1014 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1015 struct anv_batch *batch);
1016
1017 static inline VkResult
1018 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1019 {
1020 assert(error != VK_SUCCESS);
1021 if (batch->status == VK_SUCCESS)
1022 batch->status = error;
1023 return batch->status;
1024 }
1025
1026 static inline bool
1027 anv_batch_has_error(struct anv_batch *batch)
1028 {
1029 return batch->status != VK_SUCCESS;
1030 }
1031
1032 struct anv_address {
1033 struct anv_bo *bo;
1034 uint32_t offset;
1035 };
1036
1037 static inline uint64_t
1038 _anv_combine_address(struct anv_batch *batch, void *location,
1039 const struct anv_address address, uint32_t delta)
1040 {
1041 if (address.bo == NULL) {
1042 return address.offset + delta;
1043 } else {
1044 assert(batch->start <= location && location < batch->end);
1045
1046 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1047 }
1048 }
1049
1050 #define __gen_address_type struct anv_address
1051 #define __gen_user_data struct anv_batch
1052 #define __gen_combine_address _anv_combine_address
1053
1054 /* Wrapper macros needed to work around preprocessor argument issues. In
1055 * particular, arguments don't get pre-evaluated if they are concatenated.
1056 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1057 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1058 * We can work around this easily enough with these helpers.
1059 */
1060 #define __anv_cmd_length(cmd) cmd ## _length
1061 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1062 #define __anv_cmd_header(cmd) cmd ## _header
1063 #define __anv_cmd_pack(cmd) cmd ## _pack
1064 #define __anv_reg_num(reg) reg ## _num
1065
1066 #define anv_pack_struct(dst, struc, ...) do { \
1067 struct struc __template = { \
1068 __VA_ARGS__ \
1069 }; \
1070 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1071 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1072 } while (0)
1073
1074 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1075 void *__dst = anv_batch_emit_dwords(batch, n); \
1076 if (__dst) { \
1077 struct cmd __template = { \
1078 __anv_cmd_header(cmd), \
1079 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1080 __VA_ARGS__ \
1081 }; \
1082 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1083 } \
1084 __dst; \
1085 })
1086
1087 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1088 do { \
1089 uint32_t *dw; \
1090 \
1091 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1092 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1093 if (!dw) \
1094 break; \
1095 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1096 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1097 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1098 } while (0)
1099
1100 #define anv_batch_emit(batch, cmd, name) \
1101 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1102 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1103 __builtin_expect(_dst != NULL, 1); \
1104 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1105 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1106 _dst = NULL; \
1107 }))
1108
1109 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1110 .GraphicsDataTypeGFDT = 0, \
1111 .LLCCacheabilityControlLLCCC = 0, \
1112 .L3CacheabilityControlL3CC = 1, \
1113 }
1114
1115 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1116 .LLCeLLCCacheabilityControlLLCCC = 0, \
1117 .L3CacheabilityControlL3CC = 1, \
1118 }
1119
1120 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1121 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1122 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1123 .AgeforQUADLRU = 0 \
1124 }
1125
1126 /* Skylake: MOCS is now an index into an array of 62 different caching
1127 * configurations programmed by the kernel.
1128 */
1129
1130 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1131 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1132 .IndextoMOCSTables = 2 \
1133 }
1134
1135 #define GEN9_MOCS_PTE { \
1136 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1137 .IndextoMOCSTables = 1 \
1138 }
1139
1140 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1141 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1142 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1143 .IndextoMOCSTables = 2 \
1144 }
1145
1146 #define GEN10_MOCS_PTE { \
1147 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1148 .IndextoMOCSTables = 1 \
1149 }
1150
1151 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1152 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1153 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1154 .IndextoMOCSTables = 2 \
1155 }
1156
1157 #define GEN11_MOCS_PTE { \
1158 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1159 .IndextoMOCSTables = 1 \
1160 }
1161
1162 struct anv_device_memory {
1163 struct anv_bo * bo;
1164 struct anv_memory_type * type;
1165 VkDeviceSize map_size;
1166 void * map;
1167 };
1168
1169 /**
1170 * Header for Vertex URB Entry (VUE)
1171 */
1172 struct anv_vue_header {
1173 uint32_t Reserved;
1174 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1175 uint32_t ViewportIndex;
1176 float PointWidth;
1177 };
1178
1179 struct anv_descriptor_set_binding_layout {
1180 #ifndef NDEBUG
1181 /* The type of the descriptors in this binding */
1182 VkDescriptorType type;
1183 #endif
1184
1185 /* Number of array elements in this binding */
1186 uint16_t array_size;
1187
1188 /* Index into the flattend descriptor set */
1189 uint16_t descriptor_index;
1190
1191 /* Index into the dynamic state array for a dynamic buffer */
1192 int16_t dynamic_offset_index;
1193
1194 /* Index into the descriptor set buffer views */
1195 int16_t buffer_index;
1196
1197 struct {
1198 /* Index into the binding table for the associated surface */
1199 int16_t surface_index;
1200
1201 /* Index into the sampler table for the associated sampler */
1202 int16_t sampler_index;
1203
1204 /* Index into the image table for the associated image */
1205 int16_t image_index;
1206 } stage[MESA_SHADER_STAGES];
1207
1208 /* Immutable samplers (or NULL if no immutable samplers) */
1209 struct anv_sampler **immutable_samplers;
1210 };
1211
1212 struct anv_descriptor_set_layout {
1213 /* Descriptor set layouts can be destroyed at almost any time */
1214 uint32_t ref_cnt;
1215
1216 /* Number of bindings in this descriptor set */
1217 uint16_t binding_count;
1218
1219 /* Total size of the descriptor set with room for all array entries */
1220 uint16_t size;
1221
1222 /* Shader stages affected by this descriptor set */
1223 uint16_t shader_stages;
1224
1225 /* Number of buffers in this descriptor set */
1226 uint16_t buffer_count;
1227
1228 /* Number of dynamic offsets used by this descriptor set */
1229 uint16_t dynamic_offset_count;
1230
1231 /* Bindings in this descriptor set */
1232 struct anv_descriptor_set_binding_layout binding[0];
1233 };
1234
1235 static inline void
1236 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1237 {
1238 assert(layout && layout->ref_cnt >= 1);
1239 p_atomic_inc(&layout->ref_cnt);
1240 }
1241
1242 static inline void
1243 anv_descriptor_set_layout_unref(struct anv_device *device,
1244 struct anv_descriptor_set_layout *layout)
1245 {
1246 assert(layout && layout->ref_cnt >= 1);
1247 if (p_atomic_dec_zero(&layout->ref_cnt))
1248 vk_free(&device->alloc, layout);
1249 }
1250
1251 struct anv_descriptor {
1252 VkDescriptorType type;
1253
1254 union {
1255 struct {
1256 VkImageLayout layout;
1257 struct anv_image_view *image_view;
1258 struct anv_sampler *sampler;
1259 };
1260
1261 struct {
1262 struct anv_buffer *buffer;
1263 uint64_t offset;
1264 uint64_t range;
1265 };
1266
1267 struct anv_buffer_view *buffer_view;
1268 };
1269 };
1270
1271 struct anv_descriptor_set {
1272 struct anv_descriptor_set_layout *layout;
1273 uint32_t size;
1274 uint32_t buffer_count;
1275 struct anv_buffer_view *buffer_views;
1276 struct anv_descriptor descriptors[0];
1277 };
1278
1279 struct anv_buffer_view {
1280 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1281 struct anv_bo *bo;
1282 uint32_t offset; /**< Offset into bo. */
1283 uint64_t range; /**< VkBufferViewCreateInfo::range */
1284
1285 struct anv_state surface_state;
1286 struct anv_state storage_surface_state;
1287 struct anv_state writeonly_storage_surface_state;
1288
1289 struct brw_image_param storage_image_param;
1290 };
1291
1292 struct anv_push_descriptor_set {
1293 struct anv_descriptor_set set;
1294
1295 /* Put this field right behind anv_descriptor_set so it fills up the
1296 * descriptors[0] field. */
1297 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1298 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1299 };
1300
1301 struct anv_descriptor_pool {
1302 uint32_t size;
1303 uint32_t next;
1304 uint32_t free_list;
1305
1306 struct anv_state_stream surface_state_stream;
1307 void *surface_state_free_list;
1308
1309 char data[0];
1310 };
1311
1312 enum anv_descriptor_template_entry_type {
1313 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1314 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1315 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1316 };
1317
1318 struct anv_descriptor_template_entry {
1319 /* The type of descriptor in this entry */
1320 VkDescriptorType type;
1321
1322 /* Binding in the descriptor set */
1323 uint32_t binding;
1324
1325 /* Offset at which to write into the descriptor set binding */
1326 uint32_t array_element;
1327
1328 /* Number of elements to write into the descriptor set binding */
1329 uint32_t array_count;
1330
1331 /* Offset into the user provided data */
1332 size_t offset;
1333
1334 /* Stride between elements into the user provided data */
1335 size_t stride;
1336 };
1337
1338 struct anv_descriptor_update_template {
1339 VkPipelineBindPoint bind_point;
1340
1341 /* The descriptor set this template corresponds to. This value is only
1342 * valid if the template was created with the templateType
1343 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1344 */
1345 uint8_t set;
1346
1347 /* Number of entries in this template */
1348 uint32_t entry_count;
1349
1350 /* Entries of the template */
1351 struct anv_descriptor_template_entry entries[0];
1352 };
1353
1354 size_t
1355 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1356
1357 size_t
1358 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1359
1360 void
1361 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1362 const struct gen_device_info * const devinfo,
1363 const VkDescriptorImageInfo * const info,
1364 VkDescriptorType type,
1365 uint32_t binding,
1366 uint32_t element);
1367
1368 void
1369 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1370 VkDescriptorType type,
1371 struct anv_buffer_view *buffer_view,
1372 uint32_t binding,
1373 uint32_t element);
1374
1375 void
1376 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1377 struct anv_device *device,
1378 struct anv_state_stream *alloc_stream,
1379 VkDescriptorType type,
1380 struct anv_buffer *buffer,
1381 uint32_t binding,
1382 uint32_t element,
1383 VkDeviceSize offset,
1384 VkDeviceSize range);
1385
1386 void
1387 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1388 struct anv_device *device,
1389 struct anv_state_stream *alloc_stream,
1390 const struct anv_descriptor_update_template *template,
1391 const void *data);
1392
1393 VkResult
1394 anv_descriptor_set_create(struct anv_device *device,
1395 struct anv_descriptor_pool *pool,
1396 struct anv_descriptor_set_layout *layout,
1397 struct anv_descriptor_set **out_set);
1398
1399 void
1400 anv_descriptor_set_destroy(struct anv_device *device,
1401 struct anv_descriptor_pool *pool,
1402 struct anv_descriptor_set *set);
1403
1404 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1405
1406 struct anv_pipeline_binding {
1407 /* The descriptor set this surface corresponds to. The special value of
1408 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1409 * to a color attachment and not a regular descriptor.
1410 */
1411 uint8_t set;
1412
1413 /* Binding in the descriptor set */
1414 uint32_t binding;
1415
1416 /* Index in the binding */
1417 uint32_t index;
1418
1419 /* Plane in the binding index */
1420 uint8_t plane;
1421
1422 /* Input attachment index (relative to the subpass) */
1423 uint8_t input_attachment_index;
1424
1425 /* For a storage image, whether it is write-only */
1426 bool write_only;
1427 };
1428
1429 struct anv_pipeline_layout {
1430 struct {
1431 struct anv_descriptor_set_layout *layout;
1432 uint32_t dynamic_offset_start;
1433 } set[MAX_SETS];
1434
1435 uint32_t num_sets;
1436
1437 struct {
1438 bool has_dynamic_offsets;
1439 } stage[MESA_SHADER_STAGES];
1440
1441 unsigned char sha1[20];
1442 };
1443
1444 struct anv_buffer {
1445 struct anv_device * device;
1446 VkDeviceSize size;
1447
1448 VkBufferUsageFlags usage;
1449
1450 /* Set when bound */
1451 struct anv_bo * bo;
1452 VkDeviceSize offset;
1453 };
1454
1455 static inline uint64_t
1456 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1457 {
1458 assert(offset <= buffer->size);
1459 if (range == VK_WHOLE_SIZE) {
1460 return buffer->size - offset;
1461 } else {
1462 assert(range <= buffer->size);
1463 return range;
1464 }
1465 }
1466
1467 enum anv_cmd_dirty_bits {
1468 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1469 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1470 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1471 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1472 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1473 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1474 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1475 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1476 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1477 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1478 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1479 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1480 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1481 };
1482 typedef uint32_t anv_cmd_dirty_mask_t;
1483
1484 enum anv_pipe_bits {
1485 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1486 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1487 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1488 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1489 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1490 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1491 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1492 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1493 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1494 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1495 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1496
1497 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1498 * a flush has happened but not a CS stall. The next time we do any sort
1499 * of invalidation we need to insert a CS stall at that time. Otherwise,
1500 * we would have to CS stall on every flush which could be bad.
1501 */
1502 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1503 };
1504
1505 #define ANV_PIPE_FLUSH_BITS ( \
1506 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1507 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1508 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1509
1510 #define ANV_PIPE_STALL_BITS ( \
1511 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1512 ANV_PIPE_DEPTH_STALL_BIT | \
1513 ANV_PIPE_CS_STALL_BIT)
1514
1515 #define ANV_PIPE_INVALIDATE_BITS ( \
1516 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1517 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1518 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1519 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1520 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1521 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1522
1523 static inline enum anv_pipe_bits
1524 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1525 {
1526 enum anv_pipe_bits pipe_bits = 0;
1527
1528 unsigned b;
1529 for_each_bit(b, flags) {
1530 switch ((VkAccessFlagBits)(1 << b)) {
1531 case VK_ACCESS_SHADER_WRITE_BIT:
1532 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1533 break;
1534 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1535 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1536 break;
1537 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1538 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1539 break;
1540 case VK_ACCESS_TRANSFER_WRITE_BIT:
1541 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1542 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1543 break;
1544 default:
1545 break; /* Nothing to do */
1546 }
1547 }
1548
1549 return pipe_bits;
1550 }
1551
1552 static inline enum anv_pipe_bits
1553 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1554 {
1555 enum anv_pipe_bits pipe_bits = 0;
1556
1557 unsigned b;
1558 for_each_bit(b, flags) {
1559 switch ((VkAccessFlagBits)(1 << b)) {
1560 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1561 case VK_ACCESS_INDEX_READ_BIT:
1562 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1563 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1564 break;
1565 case VK_ACCESS_UNIFORM_READ_BIT:
1566 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1567 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1568 break;
1569 case VK_ACCESS_SHADER_READ_BIT:
1570 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1571 case VK_ACCESS_TRANSFER_READ_BIT:
1572 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1573 break;
1574 default:
1575 break; /* Nothing to do */
1576 }
1577 }
1578
1579 return pipe_bits;
1580 }
1581
1582 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1583 VK_IMAGE_ASPECT_COLOR_BIT | \
1584 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1585 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1586 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1587 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1588 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1589 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1590 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1591
1592 struct anv_vertex_binding {
1593 struct anv_buffer * buffer;
1594 VkDeviceSize offset;
1595 };
1596
1597 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1598 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1599
1600 struct anv_push_constants {
1601 /* Current allocated size of this push constants data structure.
1602 * Because a decent chunk of it may not be used (images on SKL, for
1603 * instance), we won't actually allocate the entire structure up-front.
1604 */
1605 uint32_t size;
1606
1607 /* Push constant data provided by the client through vkPushConstants */
1608 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1609
1610 /* Image data for image_load_store on pre-SKL */
1611 struct brw_image_param images[MAX_IMAGES];
1612 };
1613
1614 struct anv_dynamic_state {
1615 struct {
1616 uint32_t count;
1617 VkViewport viewports[MAX_VIEWPORTS];
1618 } viewport;
1619
1620 struct {
1621 uint32_t count;
1622 VkRect2D scissors[MAX_SCISSORS];
1623 } scissor;
1624
1625 float line_width;
1626
1627 struct {
1628 float bias;
1629 float clamp;
1630 float slope;
1631 } depth_bias;
1632
1633 float blend_constants[4];
1634
1635 struct {
1636 float min;
1637 float max;
1638 } depth_bounds;
1639
1640 struct {
1641 uint32_t front;
1642 uint32_t back;
1643 } stencil_compare_mask;
1644
1645 struct {
1646 uint32_t front;
1647 uint32_t back;
1648 } stencil_write_mask;
1649
1650 struct {
1651 uint32_t front;
1652 uint32_t back;
1653 } stencil_reference;
1654 };
1655
1656 extern const struct anv_dynamic_state default_dynamic_state;
1657
1658 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1659 const struct anv_dynamic_state *src,
1660 uint32_t copy_mask);
1661
1662 struct anv_surface_state {
1663 struct anv_state state;
1664 /** Address of the surface referred to by this state
1665 *
1666 * This address is relative to the start of the BO.
1667 */
1668 uint64_t address;
1669 /* Address of the aux surface, if any
1670 *
1671 * This field is 0 if and only if no aux surface exists.
1672 *
1673 * This address is relative to the start of the BO. On gen7, the bottom 12
1674 * bits of this address include extra aux information.
1675 */
1676 uint64_t aux_address;
1677 };
1678
1679 /**
1680 * Attachment state when recording a renderpass instance.
1681 *
1682 * The clear value is valid only if there exists a pending clear.
1683 */
1684 struct anv_attachment_state {
1685 enum isl_aux_usage aux_usage;
1686 enum isl_aux_usage input_aux_usage;
1687 struct anv_surface_state color;
1688 struct anv_surface_state input;
1689
1690 VkImageLayout current_layout;
1691 VkImageAspectFlags pending_clear_aspects;
1692 VkImageAspectFlags pending_load_aspects;
1693 bool fast_clear;
1694 VkClearValue clear_value;
1695 bool clear_color_is_zero_one;
1696 bool clear_color_is_zero;
1697 };
1698
1699 /** State tracking for particular pipeline bind point
1700 *
1701 * This struct is the base struct for anv_cmd_graphics_state and
1702 * anv_cmd_compute_state. These are used to track state which is bound to a
1703 * particular type of pipeline. Generic state that applies per-stage such as
1704 * binding table offsets and push constants is tracked generically with a
1705 * per-stage array in anv_cmd_state.
1706 */
1707 struct anv_cmd_pipeline_state {
1708 struct anv_pipeline *pipeline;
1709 struct anv_pipeline_layout *layout;
1710
1711 struct anv_descriptor_set *descriptors[MAX_SETS];
1712 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1713
1714 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
1715 };
1716
1717 /** State tracking for graphics pipeline
1718 *
1719 * This has anv_cmd_pipeline_state as a base struct to track things which get
1720 * bound to a graphics pipeline. Along with general pipeline bind point state
1721 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1722 * state which is graphics-specific.
1723 */
1724 struct anv_cmd_graphics_state {
1725 struct anv_cmd_pipeline_state base;
1726
1727 anv_cmd_dirty_mask_t dirty;
1728 uint32_t vb_dirty;
1729
1730 struct anv_dynamic_state dynamic;
1731
1732 struct {
1733 struct anv_buffer *index_buffer;
1734 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1735 uint32_t index_offset;
1736 } gen7;
1737 };
1738
1739 /** State tracking for compute pipeline
1740 *
1741 * This has anv_cmd_pipeline_state as a base struct to track things which get
1742 * bound to a compute pipeline. Along with general pipeline bind point state
1743 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1744 * state which is compute-specific.
1745 */
1746 struct anv_cmd_compute_state {
1747 struct anv_cmd_pipeline_state base;
1748
1749 bool pipeline_dirty;
1750
1751 struct anv_address num_workgroups;
1752 };
1753
1754 /** State required while building cmd buffer */
1755 struct anv_cmd_state {
1756 /* PIPELINE_SELECT.PipelineSelection */
1757 uint32_t current_pipeline;
1758 const struct gen_l3_config * current_l3_config;
1759
1760 struct anv_cmd_graphics_state gfx;
1761 struct anv_cmd_compute_state compute;
1762
1763 enum anv_pipe_bits pending_pipe_bits;
1764 VkShaderStageFlags descriptors_dirty;
1765 VkShaderStageFlags push_constants_dirty;
1766
1767 struct anv_framebuffer * framebuffer;
1768 struct anv_render_pass * pass;
1769 struct anv_subpass * subpass;
1770 VkRect2D render_area;
1771 uint32_t restart_index;
1772 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1773 VkShaderStageFlags push_constant_stages;
1774 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1775 struct anv_state binding_tables[MESA_SHADER_STAGES];
1776 struct anv_state samplers[MESA_SHADER_STAGES];
1777
1778 /**
1779 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1780 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1781 * and before invoking the secondary in ExecuteCommands.
1782 */
1783 bool pma_fix_enabled;
1784
1785 /**
1786 * Whether or not we know for certain that HiZ is enabled for the current
1787 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1788 * enabled or not, this will be false.
1789 */
1790 bool hiz_enabled;
1791
1792 /**
1793 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1794 * valid only when recording a render pass instance.
1795 */
1796 struct anv_attachment_state * attachments;
1797
1798 /**
1799 * Surface states for color render targets. These are stored in a single
1800 * flat array. For depth-stencil attachments, the surface state is simply
1801 * left blank.
1802 */
1803 struct anv_state render_pass_states;
1804
1805 /**
1806 * A null surface state of the right size to match the framebuffer. This
1807 * is one of the states in render_pass_states.
1808 */
1809 struct anv_state null_surface_state;
1810 };
1811
1812 struct anv_cmd_pool {
1813 VkAllocationCallbacks alloc;
1814 struct list_head cmd_buffers;
1815 };
1816
1817 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1818
1819 enum anv_cmd_buffer_exec_mode {
1820 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1821 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1822 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1823 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1824 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1825 };
1826
1827 struct anv_cmd_buffer {
1828 VK_LOADER_DATA _loader_data;
1829
1830 struct anv_device * device;
1831
1832 struct anv_cmd_pool * pool;
1833 struct list_head pool_link;
1834
1835 struct anv_batch batch;
1836
1837 /* Fields required for the actual chain of anv_batch_bo's.
1838 *
1839 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1840 */
1841 struct list_head batch_bos;
1842 enum anv_cmd_buffer_exec_mode exec_mode;
1843
1844 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1845 * referenced by this command buffer
1846 *
1847 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1848 */
1849 struct u_vector seen_bbos;
1850
1851 /* A vector of int32_t's for every block of binding tables.
1852 *
1853 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1854 */
1855 struct u_vector bt_block_states;
1856 uint32_t bt_next;
1857
1858 struct anv_reloc_list surface_relocs;
1859 /** Last seen surface state block pool center bo offset */
1860 uint32_t last_ss_pool_center;
1861
1862 /* Serial for tracking buffer completion */
1863 uint32_t serial;
1864
1865 /* Stream objects for storing temporary data */
1866 struct anv_state_stream surface_state_stream;
1867 struct anv_state_stream dynamic_state_stream;
1868
1869 VkCommandBufferUsageFlags usage_flags;
1870 VkCommandBufferLevel level;
1871
1872 struct anv_cmd_state state;
1873 };
1874
1875 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1876 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1877 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1878 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1879 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1880 struct anv_cmd_buffer *secondary);
1881 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1882 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1883 struct anv_cmd_buffer *cmd_buffer,
1884 const VkSemaphore *in_semaphores,
1885 uint32_t num_in_semaphores,
1886 const VkSemaphore *out_semaphores,
1887 uint32_t num_out_semaphores,
1888 VkFence fence);
1889
1890 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1891
1892 VkResult
1893 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1894 gl_shader_stage stage, uint32_t size);
1895 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1896 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1897 (offsetof(struct anv_push_constants, field) + \
1898 sizeof(cmd_buffer->state.push_constants[0]->field)))
1899
1900 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1901 const void *data, uint32_t size, uint32_t alignment);
1902 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1903 uint32_t *a, uint32_t *b,
1904 uint32_t dwords, uint32_t alignment);
1905
1906 struct anv_address
1907 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1908 struct anv_state
1909 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1910 uint32_t entries, uint32_t *state_offset);
1911 struct anv_state
1912 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1913 struct anv_state
1914 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1915 uint32_t size, uint32_t alignment);
1916
1917 VkResult
1918 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1919
1920 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1921 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1922 bool depth_clamp_enable);
1923 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1924
1925 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1926 struct anv_render_pass *pass,
1927 struct anv_framebuffer *framebuffer,
1928 const VkClearValue *clear_values);
1929
1930 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1931
1932 struct anv_state
1933 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1934 gl_shader_stage stage);
1935 struct anv_state
1936 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1937
1938 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1939
1940 const struct anv_image_view *
1941 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1942
1943 VkResult
1944 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1945 uint32_t num_entries,
1946 uint32_t *state_offset,
1947 struct anv_state *bt_state);
1948
1949 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1950
1951 enum anv_fence_type {
1952 ANV_FENCE_TYPE_NONE = 0,
1953 ANV_FENCE_TYPE_BO,
1954 ANV_FENCE_TYPE_SYNCOBJ,
1955 };
1956
1957 enum anv_bo_fence_state {
1958 /** Indicates that this is a new (or newly reset fence) */
1959 ANV_BO_FENCE_STATE_RESET,
1960
1961 /** Indicates that this fence has been submitted to the GPU but is still
1962 * (as far as we know) in use by the GPU.
1963 */
1964 ANV_BO_FENCE_STATE_SUBMITTED,
1965
1966 ANV_BO_FENCE_STATE_SIGNALED,
1967 };
1968
1969 struct anv_fence_impl {
1970 enum anv_fence_type type;
1971
1972 union {
1973 /** Fence implementation for BO fences
1974 *
1975 * These fences use a BO and a set of CPU-tracked state flags. The BO
1976 * is added to the object list of the last execbuf call in a QueueSubmit
1977 * and is marked EXEC_WRITE. The state flags track when the BO has been
1978 * submitted to the kernel. We need to do this because Vulkan lets you
1979 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1980 * will say it's idle in this case.
1981 */
1982 struct {
1983 struct anv_bo bo;
1984 enum anv_bo_fence_state state;
1985 } bo;
1986
1987 /** DRM syncobj handle for syncobj-based fences */
1988 uint32_t syncobj;
1989 };
1990 };
1991
1992 struct anv_fence {
1993 /* Permanent fence state. Every fence has some form of permanent state
1994 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1995 * cross-process fences) or it could just be a dummy for use internally.
1996 */
1997 struct anv_fence_impl permanent;
1998
1999 /* Temporary fence state. A fence *may* have temporary state. That state
2000 * is added to the fence by an import operation and is reset back to
2001 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2002 * state cannot be signaled because the fence must already be signaled
2003 * before the temporary state can be exported from the fence in the other
2004 * process and imported here.
2005 */
2006 struct anv_fence_impl temporary;
2007 };
2008
2009 struct anv_event {
2010 uint64_t semaphore;
2011 struct anv_state state;
2012 };
2013
2014 enum anv_semaphore_type {
2015 ANV_SEMAPHORE_TYPE_NONE = 0,
2016 ANV_SEMAPHORE_TYPE_DUMMY,
2017 ANV_SEMAPHORE_TYPE_BO,
2018 ANV_SEMAPHORE_TYPE_SYNC_FILE,
2019 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
2020 };
2021
2022 struct anv_semaphore_impl {
2023 enum anv_semaphore_type type;
2024
2025 union {
2026 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2027 * This BO will be added to the object list on any execbuf2 calls for
2028 * which this semaphore is used as a wait or signal fence. When used as
2029 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2030 */
2031 struct anv_bo *bo;
2032
2033 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2034 * If the semaphore is in the unsignaled state due to either just being
2035 * created or because it has been used for a wait, fd will be -1.
2036 */
2037 int fd;
2038
2039 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2040 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2041 * import so we don't need to bother with a userspace cache.
2042 */
2043 uint32_t syncobj;
2044 };
2045 };
2046
2047 struct anv_semaphore {
2048 /* Permanent semaphore state. Every semaphore has some form of permanent
2049 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2050 * (for cross-process semaphores0 or it could just be a dummy for use
2051 * internally.
2052 */
2053 struct anv_semaphore_impl permanent;
2054
2055 /* Temporary semaphore state. A semaphore *may* have temporary state.
2056 * That state is added to the semaphore by an import operation and is reset
2057 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2058 * semaphore with temporary state cannot be signaled because the semaphore
2059 * must already be signaled before the temporary state can be exported from
2060 * the semaphore in the other process and imported here.
2061 */
2062 struct anv_semaphore_impl temporary;
2063 };
2064
2065 void anv_semaphore_reset_temporary(struct anv_device *device,
2066 struct anv_semaphore *semaphore);
2067
2068 struct anv_shader_module {
2069 unsigned char sha1[20];
2070 uint32_t size;
2071 char data[0];
2072 };
2073
2074 static inline gl_shader_stage
2075 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2076 {
2077 assert(__builtin_popcount(vk_stage) == 1);
2078 return ffs(vk_stage) - 1;
2079 }
2080
2081 static inline VkShaderStageFlagBits
2082 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2083 {
2084 return (1 << mesa_stage);
2085 }
2086
2087 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2088
2089 #define anv_foreach_stage(stage, stage_bits) \
2090 for (gl_shader_stage stage, \
2091 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2092 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2093 __tmp &= ~(1 << (stage)))
2094
2095 struct anv_pipeline_bind_map {
2096 uint32_t surface_count;
2097 uint32_t sampler_count;
2098 uint32_t image_count;
2099
2100 struct anv_pipeline_binding * surface_to_descriptor;
2101 struct anv_pipeline_binding * sampler_to_descriptor;
2102 };
2103
2104 struct anv_shader_bin_key {
2105 uint32_t size;
2106 uint8_t data[0];
2107 };
2108
2109 struct anv_shader_bin {
2110 uint32_t ref_cnt;
2111
2112 const struct anv_shader_bin_key *key;
2113
2114 struct anv_state kernel;
2115 uint32_t kernel_size;
2116
2117 const struct brw_stage_prog_data *prog_data;
2118 uint32_t prog_data_size;
2119
2120 struct anv_pipeline_bind_map bind_map;
2121 };
2122
2123 struct anv_shader_bin *
2124 anv_shader_bin_create(struct anv_device *device,
2125 const void *key, uint32_t key_size,
2126 const void *kernel, uint32_t kernel_size,
2127 const struct brw_stage_prog_data *prog_data,
2128 uint32_t prog_data_size, const void *prog_data_param,
2129 const struct anv_pipeline_bind_map *bind_map);
2130
2131 void
2132 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2133
2134 static inline void
2135 anv_shader_bin_ref(struct anv_shader_bin *shader)
2136 {
2137 assert(shader && shader->ref_cnt >= 1);
2138 p_atomic_inc(&shader->ref_cnt);
2139 }
2140
2141 static inline void
2142 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2143 {
2144 assert(shader && shader->ref_cnt >= 1);
2145 if (p_atomic_dec_zero(&shader->ref_cnt))
2146 anv_shader_bin_destroy(device, shader);
2147 }
2148
2149 struct anv_pipeline {
2150 struct anv_device * device;
2151 struct anv_batch batch;
2152 uint32_t batch_data[512];
2153 struct anv_reloc_list batch_relocs;
2154 uint32_t dynamic_state_mask;
2155 struct anv_dynamic_state dynamic_state;
2156
2157 struct anv_subpass * subpass;
2158
2159 bool needs_data_cache;
2160
2161 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2162
2163 struct {
2164 const struct gen_l3_config * l3_config;
2165 uint32_t total_size;
2166 } urb;
2167
2168 VkShaderStageFlags active_stages;
2169 struct anv_state blend_state;
2170
2171 uint32_t vb_used;
2172 uint32_t binding_stride[MAX_VBS];
2173 bool instancing_enable[MAX_VBS];
2174 bool primitive_restart;
2175 uint32_t topology;
2176
2177 uint32_t cs_right_mask;
2178
2179 bool writes_depth;
2180 bool depth_test_enable;
2181 bool writes_stencil;
2182 bool stencil_test_enable;
2183 bool depth_clamp_enable;
2184 bool sample_shading_enable;
2185 bool kill_pixel;
2186
2187 struct {
2188 uint32_t sf[7];
2189 uint32_t depth_stencil_state[3];
2190 } gen7;
2191
2192 struct {
2193 uint32_t sf[4];
2194 uint32_t raster[5];
2195 uint32_t wm_depth_stencil[3];
2196 } gen8;
2197
2198 struct {
2199 uint32_t wm_depth_stencil[4];
2200 } gen9;
2201
2202 uint32_t interface_descriptor_data[8];
2203 };
2204
2205 static inline bool
2206 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2207 gl_shader_stage stage)
2208 {
2209 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2210 }
2211
2212 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2213 static inline const struct brw_##prefix##_prog_data * \
2214 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2215 { \
2216 if (anv_pipeline_has_stage(pipeline, stage)) { \
2217 return (const struct brw_##prefix##_prog_data *) \
2218 pipeline->shaders[stage]->prog_data; \
2219 } else { \
2220 return NULL; \
2221 } \
2222 }
2223
2224 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2225 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2226 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2227 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2228 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2229 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2230
2231 static inline const struct brw_vue_prog_data *
2232 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2233 {
2234 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2235 return &get_gs_prog_data(pipeline)->base;
2236 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2237 return &get_tes_prog_data(pipeline)->base;
2238 else
2239 return &get_vs_prog_data(pipeline)->base;
2240 }
2241
2242 VkResult
2243 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2244 struct anv_pipeline_cache *cache,
2245 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2246 const VkAllocationCallbacks *alloc);
2247
2248 VkResult
2249 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2250 struct anv_pipeline_cache *cache,
2251 const VkComputePipelineCreateInfo *info,
2252 struct anv_shader_module *module,
2253 const char *entrypoint,
2254 const VkSpecializationInfo *spec_info);
2255
2256 struct anv_format_plane {
2257 enum isl_format isl_format:16;
2258 struct isl_swizzle swizzle;
2259
2260 /* Whether this plane contains chroma channels */
2261 bool has_chroma;
2262
2263 /* For downscaling of YUV planes */
2264 uint8_t denominator_scales[2];
2265
2266 /* How to map sampled ycbcr planes to a single 4 component element. */
2267 struct isl_swizzle ycbcr_swizzle;
2268 };
2269
2270
2271 struct anv_format {
2272 struct anv_format_plane planes[3];
2273 uint8_t n_planes;
2274 bool can_ycbcr;
2275 };
2276
2277 static inline uint32_t
2278 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2279 VkImageAspectFlags aspect_mask)
2280 {
2281 switch (aspect_mask) {
2282 case VK_IMAGE_ASPECT_COLOR_BIT:
2283 case VK_IMAGE_ASPECT_DEPTH_BIT:
2284 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2285 return 0;
2286 case VK_IMAGE_ASPECT_STENCIL_BIT:
2287 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2288 return 0;
2289 /* Fall-through */
2290 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2291 return 1;
2292 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2293 return 2;
2294 default:
2295 /* Purposefully assert with depth/stencil aspects. */
2296 unreachable("invalid image aspect");
2297 }
2298 }
2299
2300 static inline uint32_t
2301 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2302 {
2303 uint32_t planes = 0;
2304
2305 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2306 VK_IMAGE_ASPECT_DEPTH_BIT |
2307 VK_IMAGE_ASPECT_STENCIL_BIT |
2308 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2309 planes++;
2310 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2311 planes++;
2312 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2313 planes++;
2314
2315 return planes;
2316 }
2317
2318 static inline VkImageAspectFlags
2319 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2320 uint32_t plane)
2321 {
2322 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2323 if (_mesa_bitcount(image_aspects) > 1)
2324 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2325 return VK_IMAGE_ASPECT_COLOR_BIT;
2326 }
2327 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2328 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2329 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2330 return VK_IMAGE_ASPECT_STENCIL_BIT;
2331 }
2332
2333 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2334 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2335
2336 const struct anv_format *
2337 anv_get_format(VkFormat format);
2338
2339 static inline uint32_t
2340 anv_get_format_planes(VkFormat vk_format)
2341 {
2342 const struct anv_format *format = anv_get_format(vk_format);
2343
2344 return format != NULL ? format->n_planes : 0;
2345 }
2346
2347 struct anv_format_plane
2348 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2349 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2350
2351 static inline enum isl_format
2352 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2353 VkImageAspectFlags aspect, VkImageTiling tiling)
2354 {
2355 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2356 }
2357
2358 static inline struct isl_swizzle
2359 anv_swizzle_for_render(struct isl_swizzle swizzle)
2360 {
2361 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2362 * RGB as RGBA for texturing
2363 */
2364 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2365 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2366
2367 /* But it doesn't matter what we render to that channel */
2368 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2369
2370 return swizzle;
2371 }
2372
2373 void
2374 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2375
2376 /**
2377 * Subsurface of an anv_image.
2378 */
2379 struct anv_surface {
2380 /** Valid only if isl_surf::size > 0. */
2381 struct isl_surf isl;
2382
2383 /**
2384 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2385 */
2386 uint32_t offset;
2387 };
2388
2389 struct anv_image {
2390 VkImageType type;
2391 /* The original VkFormat provided by the client. This may not match any
2392 * of the actual surface formats.
2393 */
2394 VkFormat vk_format;
2395 const struct anv_format *format;
2396
2397 VkImageAspectFlags aspects;
2398 VkExtent3D extent;
2399 uint32_t levels;
2400 uint32_t array_size;
2401 uint32_t samples; /**< VkImageCreateInfo::samples */
2402 uint32_t n_planes;
2403 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2404 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2405
2406 /** True if this is needs to be bound to an appropriately tiled BO.
2407 *
2408 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2409 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2410 * we require a dedicated allocation so that we can know to allocate a
2411 * tiled buffer.
2412 */
2413 bool needs_set_tiling;
2414
2415 VkDeviceSize size;
2416 uint32_t alignment;
2417
2418 /* Whether the image is made of several underlying buffer objects rather a
2419 * single one with different offsets.
2420 */
2421 bool disjoint;
2422
2423 /**
2424 * Image subsurfaces
2425 *
2426 * For each foo, anv_image::planes[x].surface is valid if and only if
2427 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2428 * to figure the number associated with a given aspect.
2429 *
2430 * The hardware requires that the depth buffer and stencil buffer be
2431 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2432 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2433 * allocate the depth and stencil buffers as separate surfaces in the same
2434 * bo.
2435 *
2436 * Memory layout :
2437 *
2438 * -----------------------
2439 * | surface0 | /|\
2440 * ----------------------- |
2441 * | shadow surface0 | |
2442 * ----------------------- | Plane 0
2443 * | aux surface0 | |
2444 * ----------------------- |
2445 * | fast clear colors0 | \|/
2446 * -----------------------
2447 * | surface1 | /|\
2448 * ----------------------- |
2449 * | shadow surface1 | |
2450 * ----------------------- | Plane 1
2451 * | aux surface1 | |
2452 * ----------------------- |
2453 * | fast clear colors1 | \|/
2454 * -----------------------
2455 * | ... |
2456 * | |
2457 * -----------------------
2458 */
2459 struct {
2460 /**
2461 * Offset of the entire plane (whenever the image is disjoint this is
2462 * set to 0).
2463 */
2464 uint32_t offset;
2465
2466 VkDeviceSize size;
2467 uint32_t alignment;
2468
2469 struct anv_surface surface;
2470
2471 /**
2472 * A surface which shadows the main surface and may have different
2473 * tiling. This is used for sampling using a tiling that isn't supported
2474 * for other operations.
2475 */
2476 struct anv_surface shadow_surface;
2477
2478 /**
2479 * For color images, this is the aux usage for this image when not used
2480 * as a color attachment.
2481 *
2482 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2483 * image has a HiZ buffer.
2484 */
2485 enum isl_aux_usage aux_usage;
2486
2487 struct anv_surface aux_surface;
2488
2489 /**
2490 * Offset of the fast clear state (used to compute the
2491 * fast_clear_state_offset of the following planes).
2492 */
2493 uint32_t fast_clear_state_offset;
2494
2495 /**
2496 * BO associated with this plane, set when bound.
2497 */
2498 struct anv_bo *bo;
2499 VkDeviceSize bo_offset;
2500
2501 /**
2502 * When destroying the image, also free the bo.
2503 * */
2504 bool bo_is_owned;
2505 } planes[3];
2506 };
2507
2508 /* The ordering of this enum is important */
2509 enum anv_fast_clear_type {
2510 /** Image does not have/support any fast-clear blocks */
2511 ANV_FAST_CLEAR_NONE = 0,
2512 /** Image has/supports fast-clear but only to the default value */
2513 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
2514 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2515 ANV_FAST_CLEAR_ANY = 2,
2516 };
2517
2518 /* Returns the number of auxiliary buffer levels attached to an image. */
2519 static inline uint8_t
2520 anv_image_aux_levels(const struct anv_image * const image,
2521 VkImageAspectFlagBits aspect)
2522 {
2523 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2524 return image->planes[plane].aux_surface.isl.size > 0 ?
2525 image->planes[plane].aux_surface.isl.levels : 0;
2526 }
2527
2528 /* Returns the number of auxiliary buffer layers attached to an image. */
2529 static inline uint32_t
2530 anv_image_aux_layers(const struct anv_image * const image,
2531 VkImageAspectFlagBits aspect,
2532 const uint8_t miplevel)
2533 {
2534 assert(image);
2535
2536 /* The miplevel must exist in the main buffer. */
2537 assert(miplevel < image->levels);
2538
2539 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2540 /* There are no layers with auxiliary data because the miplevel has no
2541 * auxiliary data.
2542 */
2543 return 0;
2544 } else {
2545 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2546 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2547 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2548 }
2549 }
2550
2551 static inline struct anv_address
2552 anv_image_get_clear_color_addr(const struct anv_device *device,
2553 const struct anv_image *image,
2554 VkImageAspectFlagBits aspect)
2555 {
2556 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
2557
2558 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2559 return (struct anv_address) {
2560 .bo = image->planes[plane].bo,
2561 .offset = image->planes[plane].bo_offset +
2562 image->planes[plane].fast_clear_state_offset,
2563 };
2564 }
2565
2566 static inline struct anv_address
2567 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
2568 const struct anv_image *image,
2569 VkImageAspectFlagBits aspect)
2570 {
2571 struct anv_address addr =
2572 anv_image_get_clear_color_addr(device, image, aspect);
2573 addr.offset += device->isl_dev.ss.clear_value_size;
2574 return addr;
2575 }
2576
2577 static inline struct anv_address
2578 anv_image_get_compression_state_addr(const struct anv_device *device,
2579 const struct anv_image *image,
2580 VkImageAspectFlagBits aspect,
2581 uint32_t level, uint32_t array_layer)
2582 {
2583 assert(level < anv_image_aux_levels(image, aspect));
2584 assert(array_layer < anv_image_aux_layers(image, aspect, level));
2585 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2586 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
2587
2588 struct anv_address addr =
2589 anv_image_get_fast_clear_type_addr(device, image, aspect);
2590 addr.offset += 4; /* Go past the fast clear type */
2591
2592 if (image->type == VK_IMAGE_TYPE_3D) {
2593 for (uint32_t l = 0; l < level; l++)
2594 addr.offset += anv_minify(image->extent.depth, l) * 4;
2595 } else {
2596 addr.offset += level * image->array_size * 4;
2597 }
2598 addr.offset += array_layer * 4;
2599
2600 return addr;
2601 }
2602
2603 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2604 static inline bool
2605 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2606 const struct anv_image *image)
2607 {
2608 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2609 return false;
2610
2611 if (devinfo->gen < 8)
2612 return false;
2613
2614 return image->samples == 1;
2615 }
2616
2617 void
2618 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
2619 const struct anv_image *image,
2620 VkImageAspectFlagBits aspect,
2621 enum isl_aux_usage aux_usage,
2622 uint32_t level,
2623 uint32_t base_layer,
2624 uint32_t layer_count);
2625
2626 void
2627 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
2628 const struct anv_image *image,
2629 VkImageAspectFlagBits aspect,
2630 enum isl_aux_usage aux_usage,
2631 enum isl_format format, struct isl_swizzle swizzle,
2632 uint32_t level, uint32_t base_layer, uint32_t layer_count,
2633 VkRect2D area, union isl_color_value clear_color);
2634 void
2635 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
2636 const struct anv_image *image,
2637 VkImageAspectFlags aspects,
2638 enum isl_aux_usage depth_aux_usage,
2639 uint32_t level,
2640 uint32_t base_layer, uint32_t layer_count,
2641 VkRect2D area,
2642 float depth_value, uint8_t stencil_value);
2643 void
2644 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
2645 const struct anv_image *image,
2646 VkImageAspectFlagBits aspect, uint32_t level,
2647 uint32_t base_layer, uint32_t layer_count,
2648 enum isl_aux_op hiz_op);
2649 void
2650 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
2651 const struct anv_image *image,
2652 VkImageAspectFlags aspects,
2653 uint32_t level,
2654 uint32_t base_layer, uint32_t layer_count,
2655 VkRect2D area, uint8_t stencil_value);
2656 void
2657 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
2658 const struct anv_image *image,
2659 VkImageAspectFlagBits aspect,
2660 uint32_t base_layer, uint32_t layer_count,
2661 enum isl_aux_op mcs_op, bool predicate);
2662 void
2663 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
2664 const struct anv_image *image,
2665 VkImageAspectFlagBits aspect, uint32_t level,
2666 uint32_t base_layer, uint32_t layer_count,
2667 enum isl_aux_op ccs_op, bool predicate);
2668
2669 void
2670 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2671 const struct anv_image *image,
2672 uint32_t base_level, uint32_t level_count,
2673 uint32_t base_layer, uint32_t layer_count);
2674
2675 enum isl_aux_usage
2676 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2677 const struct anv_image *image,
2678 const VkImageAspectFlagBits aspect,
2679 const VkImageLayout layout);
2680
2681 enum anv_fast_clear_type
2682 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
2683 const struct anv_image * const image,
2684 const VkImageAspectFlagBits aspect,
2685 const VkImageLayout layout);
2686
2687 /* This is defined as a macro so that it works for both
2688 * VkImageSubresourceRange and VkImageSubresourceLayers
2689 */
2690 #define anv_get_layerCount(_image, _range) \
2691 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2692 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2693
2694 static inline uint32_t
2695 anv_get_levelCount(const struct anv_image *image,
2696 const VkImageSubresourceRange *range)
2697 {
2698 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2699 image->levels - range->baseMipLevel : range->levelCount;
2700 }
2701
2702 static inline VkImageAspectFlags
2703 anv_image_expand_aspects(const struct anv_image *image,
2704 VkImageAspectFlags aspects)
2705 {
2706 /* If the underlying image has color plane aspects and
2707 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2708 * the underlying image. */
2709 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2710 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2711 return image->aspects;
2712
2713 return aspects;
2714 }
2715
2716 static inline bool
2717 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2718 VkImageAspectFlags aspects2)
2719 {
2720 if (aspects1 == aspects2)
2721 return true;
2722
2723 /* Only 1 color aspects are compatibles. */
2724 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2725 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2726 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2727 return true;
2728
2729 return false;
2730 }
2731
2732 struct anv_image_view {
2733 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2734
2735 VkImageAspectFlags aspect_mask;
2736 VkFormat vk_format;
2737 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2738
2739 unsigned n_planes;
2740 struct {
2741 uint32_t image_plane;
2742
2743 struct isl_view isl;
2744
2745 /**
2746 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2747 * image layout of SHADER_READ_ONLY_OPTIMAL or
2748 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2749 */
2750 struct anv_surface_state optimal_sampler_surface_state;
2751
2752 /**
2753 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2754 * image layout of GENERAL.
2755 */
2756 struct anv_surface_state general_sampler_surface_state;
2757
2758 /**
2759 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2760 * states for write-only and readable, using the real format for
2761 * write-only and the lowered format for readable.
2762 */
2763 struct anv_surface_state storage_surface_state;
2764 struct anv_surface_state writeonly_storage_surface_state;
2765
2766 struct brw_image_param storage_image_param;
2767 } planes[3];
2768 };
2769
2770 enum anv_image_view_state_flags {
2771 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2772 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2773 };
2774
2775 void anv_image_fill_surface_state(struct anv_device *device,
2776 const struct anv_image *image,
2777 VkImageAspectFlagBits aspect,
2778 const struct isl_view *view,
2779 isl_surf_usage_flags_t view_usage,
2780 enum isl_aux_usage aux_usage,
2781 const union isl_color_value *clear_color,
2782 enum anv_image_view_state_flags flags,
2783 struct anv_surface_state *state_inout,
2784 struct brw_image_param *image_param_out);
2785
2786 struct anv_image_create_info {
2787 const VkImageCreateInfo *vk_info;
2788
2789 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2790 isl_tiling_flags_t isl_tiling_flags;
2791
2792 /** These flags will be added to any derived from VkImageCreateInfo. */
2793 isl_surf_usage_flags_t isl_extra_usage_flags;
2794
2795 uint32_t stride;
2796 };
2797
2798 VkResult anv_image_create(VkDevice _device,
2799 const struct anv_image_create_info *info,
2800 const VkAllocationCallbacks* alloc,
2801 VkImage *pImage);
2802
2803 #ifdef ANDROID
2804 VkResult anv_image_from_gralloc(VkDevice device_h,
2805 const VkImageCreateInfo *base_info,
2806 const VkNativeBufferANDROID *gralloc_info,
2807 const VkAllocationCallbacks *alloc,
2808 VkImage *pImage);
2809 #endif
2810
2811 const struct anv_surface *
2812 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2813 VkImageAspectFlags aspect_mask);
2814
2815 enum isl_format
2816 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2817
2818 static inline struct VkExtent3D
2819 anv_sanitize_image_extent(const VkImageType imageType,
2820 const struct VkExtent3D imageExtent)
2821 {
2822 switch (imageType) {
2823 case VK_IMAGE_TYPE_1D:
2824 return (VkExtent3D) { imageExtent.width, 1, 1 };
2825 case VK_IMAGE_TYPE_2D:
2826 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2827 case VK_IMAGE_TYPE_3D:
2828 return imageExtent;
2829 default:
2830 unreachable("invalid image type");
2831 }
2832 }
2833
2834 static inline struct VkOffset3D
2835 anv_sanitize_image_offset(const VkImageType imageType,
2836 const struct VkOffset3D imageOffset)
2837 {
2838 switch (imageType) {
2839 case VK_IMAGE_TYPE_1D:
2840 return (VkOffset3D) { imageOffset.x, 0, 0 };
2841 case VK_IMAGE_TYPE_2D:
2842 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2843 case VK_IMAGE_TYPE_3D:
2844 return imageOffset;
2845 default:
2846 unreachable("invalid image type");
2847 }
2848 }
2849
2850
2851 void anv_fill_buffer_surface_state(struct anv_device *device,
2852 struct anv_state state,
2853 enum isl_format format,
2854 uint32_t offset, uint32_t range,
2855 uint32_t stride);
2856
2857
2858 struct anv_ycbcr_conversion {
2859 const struct anv_format * format;
2860 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2861 VkSamplerYcbcrRangeKHR ycbcr_range;
2862 VkComponentSwizzle mapping[4];
2863 VkChromaLocationKHR chroma_offsets[2];
2864 VkFilter chroma_filter;
2865 bool chroma_reconstruction;
2866 };
2867
2868 struct anv_sampler {
2869 uint32_t state[3][4];
2870 uint32_t n_planes;
2871 struct anv_ycbcr_conversion *conversion;
2872 };
2873
2874 struct anv_framebuffer {
2875 uint32_t width;
2876 uint32_t height;
2877 uint32_t layers;
2878
2879 uint32_t attachment_count;
2880 struct anv_image_view * attachments[0];
2881 };
2882
2883 struct anv_subpass_attachment {
2884 VkImageUsageFlagBits usage;
2885 uint32_t attachment;
2886 VkImageLayout layout;
2887 };
2888
2889 struct anv_subpass {
2890 uint32_t attachment_count;
2891
2892 /**
2893 * A pointer to all attachment references used in this subpass.
2894 * Only valid if ::attachment_count > 0.
2895 */
2896 struct anv_subpass_attachment * attachments;
2897 uint32_t input_count;
2898 struct anv_subpass_attachment * input_attachments;
2899 uint32_t color_count;
2900 struct anv_subpass_attachment * color_attachments;
2901 struct anv_subpass_attachment * resolve_attachments;
2902
2903 struct anv_subpass_attachment depth_stencil_attachment;
2904
2905 uint32_t view_mask;
2906
2907 /** Subpass has a depth/stencil self-dependency */
2908 bool has_ds_self_dep;
2909
2910 /** Subpass has at least one resolve attachment */
2911 bool has_resolve;
2912 };
2913
2914 static inline unsigned
2915 anv_subpass_view_count(const struct anv_subpass *subpass)
2916 {
2917 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2918 }
2919
2920 struct anv_render_pass_attachment {
2921 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2922 * its members individually.
2923 */
2924 VkFormat format;
2925 uint32_t samples;
2926 VkImageUsageFlags usage;
2927 VkAttachmentLoadOp load_op;
2928 VkAttachmentStoreOp store_op;
2929 VkAttachmentLoadOp stencil_load_op;
2930 VkImageLayout initial_layout;
2931 VkImageLayout final_layout;
2932 VkImageLayout first_subpass_layout;
2933
2934 /* The subpass id in which the attachment will be used last. */
2935 uint32_t last_subpass_idx;
2936 };
2937
2938 struct anv_render_pass {
2939 uint32_t attachment_count;
2940 uint32_t subpass_count;
2941 /* An array of subpass_count+1 flushes, one per subpass boundary */
2942 enum anv_pipe_bits * subpass_flushes;
2943 struct anv_render_pass_attachment * attachments;
2944 struct anv_subpass subpasses[0];
2945 };
2946
2947 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2948
2949 struct anv_query_pool {
2950 VkQueryType type;
2951 VkQueryPipelineStatisticFlags pipeline_statistics;
2952 /** Stride between slots, in bytes */
2953 uint32_t stride;
2954 /** Number of slots in this query pool */
2955 uint32_t slots;
2956 struct anv_bo bo;
2957 };
2958
2959 int anv_get_entrypoint_index(const char *name);
2960
2961 bool
2962 anv_entrypoint_is_enabled(int index, uint32_t core_version,
2963 const struct anv_instance_extension_table *instance,
2964 const struct anv_device_extension_table *device);
2965
2966 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2967 const char *name);
2968
2969 void anv_dump_image_to_ppm(struct anv_device *device,
2970 struct anv_image *image, unsigned miplevel,
2971 unsigned array_layer, VkImageAspectFlagBits aspect,
2972 const char *filename);
2973
2974 enum anv_dump_action {
2975 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2976 };
2977
2978 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2979 void anv_dump_finish(void);
2980
2981 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2982 struct anv_framebuffer *fb);
2983
2984 static inline uint32_t
2985 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2986 {
2987 /* This function must be called from within a subpass. */
2988 assert(cmd_state->pass && cmd_state->subpass);
2989
2990 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2991
2992 /* The id of this subpass shouldn't exceed the number of subpasses in this
2993 * render pass minus 1.
2994 */
2995 assert(subpass_id < cmd_state->pass->subpass_count);
2996 return subpass_id;
2997 }
2998
2999 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3000 \
3001 static inline struct __anv_type * \
3002 __anv_type ## _from_handle(__VkType _handle) \
3003 { \
3004 return (struct __anv_type *) _handle; \
3005 } \
3006 \
3007 static inline __VkType \
3008 __anv_type ## _to_handle(struct __anv_type *_obj) \
3009 { \
3010 return (__VkType) _obj; \
3011 }
3012
3013 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3014 \
3015 static inline struct __anv_type * \
3016 __anv_type ## _from_handle(__VkType _handle) \
3017 { \
3018 return (struct __anv_type *)(uintptr_t) _handle; \
3019 } \
3020 \
3021 static inline __VkType \
3022 __anv_type ## _to_handle(struct __anv_type *_obj) \
3023 { \
3024 return (__VkType)(uintptr_t) _obj; \
3025 }
3026
3027 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3028 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3029
3030 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
3031 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
3032 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
3033 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
3034 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
3035
3036 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
3037 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
3038 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
3039 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
3040 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
3041 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
3042 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
3043 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
3044 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
3045 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
3046 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
3047 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
3048 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
3049 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
3050 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
3051 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
3052 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
3053 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
3054 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
3055 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
3056 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
3057 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
3058 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
3059
3060 /* Gen-specific function declarations */
3061 #ifdef genX
3062 # include "anv_genX.h"
3063 #else
3064 # define genX(x) gen7_##x
3065 # include "anv_genX.h"
3066 # undef genX
3067 # define genX(x) gen75_##x
3068 # include "anv_genX.h"
3069 # undef genX
3070 # define genX(x) gen8_##x
3071 # include "anv_genX.h"
3072 # undef genX
3073 # define genX(x) gen9_##x
3074 # include "anv_genX.h"
3075 # undef genX
3076 # define genX(x) gen10_##x
3077 # include "anv_genX.h"
3078 # undef genX
3079 # define genX(x) gen11_##x
3080 # include "anv_genX.h"
3081 # undef genX
3082 #endif
3083
3084 #endif /* ANV_PRIVATE_H */