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anv/pipeline_cache: Rework to use multialloc and blob
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53
54 /* Pre-declarations needed for WSI entrypoints */
55 struct wl_surface;
56 struct wl_display;
57 typedef struct xcb_connection_t xcb_connection_t;
58 typedef uint32_t xcb_visualid_t;
59 typedef uint32_t xcb_window_t;
60
61 struct anv_buffer;
62 struct anv_buffer_view;
63 struct anv_image_view;
64 struct anv_instance;
65 struct anv_debug_report_callback;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "anv_entrypoints.h"
74 #include "isl/isl.h"
75
76 #include "common/gen_debug.h"
77 #include "wsi_common.h"
78
79 /* Allowing different clear colors requires us to perform a depth resolve at
80 * the end of certain render passes. This is because while slow clears store
81 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
82 * See the PRMs for examples describing when additional resolves would be
83 * necessary. To enable fast clears without requiring extra resolves, we set
84 * the clear value to a globally-defined one. We could allow different values
85 * if the user doesn't expect coherent data during or after a render passes
86 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
87 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
88 * 1.0f seems to be the only value used. The only application that doesn't set
89 * this value does so through the usage of an seemingly uninitialized clear
90 * value.
91 */
92 #define ANV_HZ_FC_VAL 1.0f
93
94 #define MAX_VBS 28
95 #define MAX_SETS 8
96 #define MAX_RTS 8
97 #define MAX_VIEWPORTS 16
98 #define MAX_SCISSORS 16
99 #define MAX_PUSH_CONSTANTS_SIZE 128
100 #define MAX_DYNAMIC_BUFFERS 16
101 #define MAX_IMAGES 8
102 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
103
104 #define ANV_SVGS_VB_INDEX MAX_VBS
105 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
106
107 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
108
109 static inline uint32_t
110 align_down_npot_u32(uint32_t v, uint32_t a)
111 {
112 return v - (v % a);
113 }
114
115 static inline uint32_t
116 align_u32(uint32_t v, uint32_t a)
117 {
118 assert(a != 0 && a == (a & -a));
119 return (v + a - 1) & ~(a - 1);
120 }
121
122 static inline uint64_t
123 align_u64(uint64_t v, uint64_t a)
124 {
125 assert(a != 0 && a == (a & -a));
126 return (v + a - 1) & ~(a - 1);
127 }
128
129 static inline int32_t
130 align_i32(int32_t v, int32_t a)
131 {
132 assert(a != 0 && a == (a & -a));
133 return (v + a - 1) & ~(a - 1);
134 }
135
136 /** Alignment must be a power of 2. */
137 static inline bool
138 anv_is_aligned(uintmax_t n, uintmax_t a)
139 {
140 assert(a == (a & -a));
141 return (n & (a - 1)) == 0;
142 }
143
144 static inline uint32_t
145 anv_minify(uint32_t n, uint32_t levels)
146 {
147 if (unlikely(n == 0))
148 return 0;
149 else
150 return MAX2(n >> levels, 1);
151 }
152
153 static inline float
154 anv_clamp_f(float f, float min, float max)
155 {
156 assert(min < max);
157
158 if (f > max)
159 return max;
160 else if (f < min)
161 return min;
162 else
163 return f;
164 }
165
166 static inline bool
167 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
168 {
169 if (*inout_mask & clear_mask) {
170 *inout_mask &= ~clear_mask;
171 return true;
172 } else {
173 return false;
174 }
175 }
176
177 static inline union isl_color_value
178 vk_to_isl_color(VkClearColorValue color)
179 {
180 return (union isl_color_value) {
181 .u32 = {
182 color.uint32[0],
183 color.uint32[1],
184 color.uint32[2],
185 color.uint32[3],
186 },
187 };
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
201 * to be added here in order to utilize mapping in debug/error/perf macros.
202 */
203 #define REPORT_OBJECT_TYPE(o) \
204 __builtin_choose_expr ( \
205 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
206 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
207 __builtin_choose_expr ( \
208 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
209 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
210 __builtin_choose_expr ( \
211 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
212 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
213 __builtin_choose_expr ( \
214 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
215 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
216 __builtin_choose_expr ( \
217 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
218 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
219 __builtin_choose_expr ( \
220 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
221 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
222 __builtin_choose_expr ( \
223 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
224 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
225 __builtin_choose_expr ( \
226 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
227 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
228 __builtin_choose_expr ( \
229 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
230 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
231 __builtin_choose_expr ( \
232 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
233 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
234 __builtin_choose_expr ( \
235 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
236 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
237 __builtin_choose_expr ( \
238 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
239 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
240 __builtin_choose_expr ( \
241 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
242 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
243 __builtin_choose_expr ( \
244 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
245 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
246 __builtin_choose_expr ( \
247 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
248 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
249 __builtin_choose_expr ( \
250 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
251 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
252 __builtin_choose_expr ( \
253 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
254 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
255 __builtin_choose_expr ( \
256 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
257 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
258 __builtin_choose_expr ( \
259 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
260 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
261 __builtin_choose_expr ( \
262 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
263 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
264 __builtin_choose_expr ( \
265 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
266 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
267 __builtin_choose_expr ( \
268 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
269 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
270 __builtin_choose_expr ( \
271 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
272 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
273 __builtin_choose_expr ( \
274 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
275 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
276 __builtin_choose_expr ( \
277 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
278 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct anv_debug_callback*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), void*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
297 /* The void expression results in a compile-time error \
298 when assigning the result to something. */ \
299 (void)0)))))))))))))))))))))))))))))))
300
301 /* Whenever we generate an error, pass it through this function. Useful for
302 * debugging, where we can break on it. Only call at error site, not when
303 * propagating errors. Might be useful to plug in a stack trace here.
304 */
305
306 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
307 VkDebugReportObjectTypeEXT type, VkResult error,
308 const char *file, int line, const char *format, ...);
309
310 #ifdef DEBUG
311 #define vk_error(error) __vk_errorf(NULL, NULL,\
312 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
313 error, __FILE__, __LINE__, NULL);
314 #define vk_errorf(instance, obj, error, format, ...)\
315 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
316 __FILE__, __LINE__, format, ## __VA_ARGS__);
317 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
318 #else
319 #define vk_error(error) error
320 #define vk_errorf(instance, obj, error, format, ...) error
321 #define anv_debug(format, ...)
322 #endif
323
324 /**
325 * Warn on ignored extension structs.
326 *
327 * The Vulkan spec requires us to ignore unsupported or unknown structs in
328 * a pNext chain. In debug mode, emitting warnings for ignored structs may
329 * help us discover structs that we should not have ignored.
330 *
331 *
332 * From the Vulkan 1.0.38 spec:
333 *
334 * Any component of the implementation (the loader, any enabled layers,
335 * and drivers) must skip over, without processing (other than reading the
336 * sType and pNext members) any chained structures with sType values not
337 * defined by extensions supported by that component.
338 */
339 #define anv_debug_ignored_stype(sType) \
340 anv_debug("%s: ignored VkStructureType %u\n", __func__, (sType))
341
342 void __anv_finishme(const char *file, int line, const char *format, ...)
343 anv_printflike(3, 4);
344 void __anv_perf_warn(struct anv_instance *instance, const void *object,
345 VkDebugReportObjectTypeEXT type, const char *file,
346 int line, const char *format, ...)
347 anv_printflike(6, 7);
348 void anv_loge(const char *format, ...) anv_printflike(1, 2);
349 void anv_loge_v(const char *format, va_list va);
350
351 void anv_debug_report(struct anv_instance *instance,
352 VkDebugReportFlagsEXT flags,
353 VkDebugReportObjectTypeEXT object_type,
354 uint64_t handle,
355 size_t location,
356 int32_t messageCode,
357 const char* pLayerPrefix,
358 const char *pMessage);
359
360 /**
361 * Print a FINISHME message, including its source location.
362 */
363 #define anv_finishme(format, ...) \
364 do { \
365 static bool reported = false; \
366 if (!reported) { \
367 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
368 reported = true; \
369 } \
370 } while (0)
371
372 /**
373 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
374 */
375 #define anv_perf_warn(instance, obj, format, ...) \
376 do { \
377 static bool reported = false; \
378 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
379 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
380 format, ##__VA_ARGS__); \
381 reported = true; \
382 } \
383 } while (0)
384
385 /* A non-fatal assert. Useful for debugging. */
386 #ifdef DEBUG
387 #define anv_assert(x) ({ \
388 if (unlikely(!(x))) \
389 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
390 })
391 #else
392 #define anv_assert(x)
393 #endif
394
395 /* A multi-pointer allocator
396 *
397 * When copying data structures from the user (such as a render pass), it's
398 * common to need to allocate data for a bunch of different things. Instead
399 * of doing several allocations and having to handle all of the error checking
400 * that entails, it can be easier to do a single allocation. This struct
401 * helps facilitate that. The intended usage looks like this:
402 *
403 * ANV_MULTIALLOC(ma)
404 * anv_multialloc_add(&ma, &main_ptr, 1);
405 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
406 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
407 *
408 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
409 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
410 */
411 struct anv_multialloc {
412 size_t size;
413 size_t align;
414
415 uint32_t ptr_count;
416 void **ptrs[8];
417 };
418
419 #define ANV_MULTIALLOC_INIT \
420 ((struct anv_multialloc) { 0, })
421
422 #define ANV_MULTIALLOC(_name) \
423 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
424
425 __attribute__((always_inline))
426 static inline void
427 _anv_multialloc_add(struct anv_multialloc *ma,
428 void **ptr, size_t size, size_t align)
429 {
430 size_t offset = align_u64(ma->size, align);
431 ma->size = offset + size;
432 ma->align = MAX2(ma->align, align);
433
434 /* Store the offset in the pointer. */
435 *ptr = (void *)(uintptr_t)offset;
436
437 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
438 ma->ptrs[ma->ptr_count++] = ptr;
439 }
440
441 #define anv_multialloc_add_size(_ma, _ptr, _size) \
442 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
443
444 #define anv_multialloc_add(_ma, _ptr, _count) \
445 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
446
447 __attribute__((always_inline))
448 static inline void *
449 anv_multialloc_alloc(struct anv_multialloc *ma,
450 const VkAllocationCallbacks *alloc,
451 VkSystemAllocationScope scope)
452 {
453 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
454 if (!ptr)
455 return NULL;
456
457 /* Fill out each of the pointers with their final value.
458 *
459 * for (uint32_t i = 0; i < ma->ptr_count; i++)
460 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
461 *
462 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
463 * constant, GCC is incapable of figuring this out and unrolling the loop
464 * so we have to give it a little help.
465 */
466 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
467 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
468 if ((_i) < ma->ptr_count) \
469 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
470 _ANV_MULTIALLOC_UPDATE_POINTER(0);
471 _ANV_MULTIALLOC_UPDATE_POINTER(1);
472 _ANV_MULTIALLOC_UPDATE_POINTER(2);
473 _ANV_MULTIALLOC_UPDATE_POINTER(3);
474 _ANV_MULTIALLOC_UPDATE_POINTER(4);
475 _ANV_MULTIALLOC_UPDATE_POINTER(5);
476 _ANV_MULTIALLOC_UPDATE_POINTER(6);
477 _ANV_MULTIALLOC_UPDATE_POINTER(7);
478 #undef _ANV_MULTIALLOC_UPDATE_POINTER
479
480 return ptr;
481 }
482
483 __attribute__((always_inline))
484 static inline void *
485 anv_multialloc_alloc2(struct anv_multialloc *ma,
486 const VkAllocationCallbacks *parent_alloc,
487 const VkAllocationCallbacks *alloc,
488 VkSystemAllocationScope scope)
489 {
490 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
491 }
492
493 struct anv_bo {
494 uint32_t gem_handle;
495
496 /* Index into the current validation list. This is used by the
497 * validation list building alrogithm to track which buffers are already
498 * in the validation list so that we can ensure uniqueness.
499 */
500 uint32_t index;
501
502 /* Last known offset. This value is provided by the kernel when we
503 * execbuf and is used as the presumed offset for the next bunch of
504 * relocations.
505 */
506 uint64_t offset;
507
508 uint64_t size;
509 void *map;
510
511 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
512 uint32_t flags;
513 };
514
515 static inline void
516 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
517 {
518 bo->gem_handle = gem_handle;
519 bo->index = 0;
520 bo->offset = -1;
521 bo->size = size;
522 bo->map = NULL;
523 bo->flags = 0;
524 }
525
526 /* Represents a lock-free linked list of "free" things. This is used by
527 * both the block pool and the state pools. Unfortunately, in order to
528 * solve the ABA problem, we can't use a single uint32_t head.
529 */
530 union anv_free_list {
531 struct {
532 int32_t offset;
533
534 /* A simple count that is incremented every time the head changes. */
535 uint32_t count;
536 };
537 uint64_t u64;
538 };
539
540 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
541
542 struct anv_block_state {
543 union {
544 struct {
545 uint32_t next;
546 uint32_t end;
547 };
548 uint64_t u64;
549 };
550 };
551
552 struct anv_block_pool {
553 struct anv_device *device;
554
555 struct anv_bo bo;
556
557 /* The offset from the start of the bo to the "center" of the block
558 * pool. Pointers to allocated blocks are given by
559 * bo.map + center_bo_offset + offsets.
560 */
561 uint32_t center_bo_offset;
562
563 /* Current memory map of the block pool. This pointer may or may not
564 * point to the actual beginning of the block pool memory. If
565 * anv_block_pool_alloc_back has ever been called, then this pointer
566 * will point to the "center" position of the buffer and all offsets
567 * (negative or positive) given out by the block pool alloc functions
568 * will be valid relative to this pointer.
569 *
570 * In particular, map == bo.map + center_offset
571 */
572 void *map;
573 int fd;
574
575 /**
576 * Array of mmaps and gem handles owned by the block pool, reclaimed when
577 * the block pool is destroyed.
578 */
579 struct u_vector mmap_cleanups;
580
581 struct anv_block_state state;
582
583 struct anv_block_state back_state;
584 };
585
586 /* Block pools are backed by a fixed-size 1GB memfd */
587 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
588
589 /* The center of the block pool is also the middle of the memfd. This may
590 * change in the future if we decide differently for some reason.
591 */
592 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
593
594 static inline uint32_t
595 anv_block_pool_size(struct anv_block_pool *pool)
596 {
597 return pool->state.end + pool->back_state.end;
598 }
599
600 struct anv_state {
601 int32_t offset;
602 uint32_t alloc_size;
603 void *map;
604 };
605
606 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
607
608 struct anv_fixed_size_state_pool {
609 union anv_free_list free_list;
610 struct anv_block_state block;
611 };
612
613 #define ANV_MIN_STATE_SIZE_LOG2 6
614 #define ANV_MAX_STATE_SIZE_LOG2 20
615
616 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
617
618 struct anv_state_pool {
619 struct anv_block_pool block_pool;
620
621 /* The size of blocks which will be allocated from the block pool */
622 uint32_t block_size;
623
624 /** Free list for "back" allocations */
625 union anv_free_list back_alloc_free_list;
626
627 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
628 };
629
630 struct anv_state_stream_block;
631
632 struct anv_state_stream {
633 struct anv_state_pool *state_pool;
634
635 /* The size of blocks to allocate from the state pool */
636 uint32_t block_size;
637
638 /* Current block we're allocating from */
639 struct anv_state block;
640
641 /* Offset into the current block at which to allocate the next state */
642 uint32_t next;
643
644 /* List of all blocks allocated from this pool */
645 struct anv_state_stream_block *block_list;
646 };
647
648 /* The block_pool functions exported for testing only. The block pool should
649 * only be used via a state pool (see below).
650 */
651 VkResult anv_block_pool_init(struct anv_block_pool *pool,
652 struct anv_device *device,
653 uint32_t initial_size);
654 void anv_block_pool_finish(struct anv_block_pool *pool);
655 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
656 uint32_t block_size);
657 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
658 uint32_t block_size);
659
660 VkResult anv_state_pool_init(struct anv_state_pool *pool,
661 struct anv_device *device,
662 uint32_t block_size);
663 void anv_state_pool_finish(struct anv_state_pool *pool);
664 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
665 uint32_t state_size, uint32_t alignment);
666 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
667 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
668 void anv_state_stream_init(struct anv_state_stream *stream,
669 struct anv_state_pool *state_pool,
670 uint32_t block_size);
671 void anv_state_stream_finish(struct anv_state_stream *stream);
672 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
673 uint32_t size, uint32_t alignment);
674
675 /**
676 * Implements a pool of re-usable BOs. The interface is identical to that
677 * of block_pool except that each block is its own BO.
678 */
679 struct anv_bo_pool {
680 struct anv_device *device;
681
682 void *free_list[16];
683 };
684
685 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
686 void anv_bo_pool_finish(struct anv_bo_pool *pool);
687 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
688 uint32_t size);
689 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
690
691 struct anv_scratch_bo {
692 bool exists;
693 struct anv_bo bo;
694 };
695
696 struct anv_scratch_pool {
697 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
698 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
699 };
700
701 void anv_scratch_pool_init(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 void anv_scratch_pool_finish(struct anv_device *device,
704 struct anv_scratch_pool *pool);
705 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
706 struct anv_scratch_pool *pool,
707 gl_shader_stage stage,
708 unsigned per_thread_scratch);
709
710 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
711 struct anv_bo_cache {
712 struct hash_table *bo_map;
713 pthread_mutex_t mutex;
714 };
715
716 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
717 void anv_bo_cache_finish(struct anv_bo_cache *cache);
718 VkResult anv_bo_cache_alloc(struct anv_device *device,
719 struct anv_bo_cache *cache,
720 uint64_t size, struct anv_bo **bo);
721 VkResult anv_bo_cache_import(struct anv_device *device,
722 struct anv_bo_cache *cache,
723 int fd, uint64_t size, struct anv_bo **bo);
724 VkResult anv_bo_cache_export(struct anv_device *device,
725 struct anv_bo_cache *cache,
726 struct anv_bo *bo_in, int *fd_out);
727 void anv_bo_cache_release(struct anv_device *device,
728 struct anv_bo_cache *cache,
729 struct anv_bo *bo);
730
731 struct anv_memory_type {
732 /* Standard bits passed on to the client */
733 VkMemoryPropertyFlags propertyFlags;
734 uint32_t heapIndex;
735
736 /* Driver-internal book-keeping */
737 VkBufferUsageFlags valid_buffer_usage;
738 };
739
740 struct anv_memory_heap {
741 /* Standard bits passed on to the client */
742 VkDeviceSize size;
743 VkMemoryHeapFlags flags;
744
745 /* Driver-internal book-keeping */
746 bool supports_48bit_addresses;
747 };
748
749 struct anv_physical_device {
750 VK_LOADER_DATA _loader_data;
751
752 struct anv_instance * instance;
753 uint32_t chipset_id;
754 char path[20];
755 const char * name;
756 struct gen_device_info info;
757 /** Amount of "GPU memory" we want to advertise
758 *
759 * Clearly, this value is bogus since Intel is a UMA architecture. On
760 * gen7 platforms, we are limited by GTT size unless we want to implement
761 * fine-grained tracking and GTT splitting. On Broadwell and above we are
762 * practically unlimited. However, we will never report more than 3/4 of
763 * the total system ram to try and avoid running out of RAM.
764 */
765 bool supports_48bit_addresses;
766 struct brw_compiler * compiler;
767 struct isl_device isl_dev;
768 int cmd_parser_version;
769 bool has_exec_async;
770 bool has_exec_fence;
771 bool has_syncobj;
772 bool has_syncobj_wait;
773
774 uint32_t eu_total;
775 uint32_t subslice_total;
776
777 struct {
778 uint32_t type_count;
779 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
780 uint32_t heap_count;
781 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
782 } memory;
783
784 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
785 uint8_t driver_uuid[VK_UUID_SIZE];
786 uint8_t device_uuid[VK_UUID_SIZE];
787
788 struct wsi_device wsi_device;
789 int local_fd;
790 };
791
792 struct anv_debug_report_callback {
793 /* Link in the 'callbacks' list in anv_instance struct. */
794 struct list_head link;
795 VkDebugReportFlagsEXT flags;
796 PFN_vkDebugReportCallbackEXT callback;
797 void * data;
798 };
799
800 struct anv_instance {
801 VK_LOADER_DATA _loader_data;
802
803 VkAllocationCallbacks alloc;
804
805 uint32_t apiVersion;
806 int physicalDeviceCount;
807 struct anv_physical_device physicalDevice;
808
809 /* VK_EXT_debug_report debug callbacks */
810 pthread_mutex_t callbacks_mutex;
811 struct list_head callbacks;
812 struct anv_debug_report_callback destroy_debug_cb;
813 };
814
815 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
816 void anv_finish_wsi(struct anv_physical_device *physical_device);
817
818 bool anv_instance_extension_supported(const char *name);
819 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
820 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
821 const char *name);
822
823 struct anv_queue {
824 VK_LOADER_DATA _loader_data;
825
826 struct anv_device * device;
827
828 struct anv_state_pool * pool;
829 };
830
831 struct anv_pipeline_cache {
832 struct anv_device * device;
833 pthread_mutex_t mutex;
834
835 struct hash_table * cache;
836 };
837
838 struct anv_pipeline_bind_map;
839
840 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
841 struct anv_device *device,
842 bool cache_enabled);
843 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
844
845 struct anv_shader_bin *
846 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
847 const void *key, uint32_t key_size);
848 struct anv_shader_bin *
849 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
850 const void *key_data, uint32_t key_size,
851 const void *kernel_data, uint32_t kernel_size,
852 const struct brw_stage_prog_data *prog_data,
853 uint32_t prog_data_size,
854 const struct anv_pipeline_bind_map *bind_map);
855
856 struct anv_device {
857 VK_LOADER_DATA _loader_data;
858
859 VkAllocationCallbacks alloc;
860
861 struct anv_instance * instance;
862 uint32_t chipset_id;
863 struct gen_device_info info;
864 struct isl_device isl_dev;
865 int context_id;
866 int fd;
867 bool can_chain_batches;
868 bool robust_buffer_access;
869
870 struct anv_bo_pool batch_bo_pool;
871
872 struct anv_bo_cache bo_cache;
873
874 struct anv_state_pool dynamic_state_pool;
875 struct anv_state_pool instruction_state_pool;
876 struct anv_state_pool surface_state_pool;
877
878 struct anv_bo workaround_bo;
879 struct anv_bo trivial_batch_bo;
880
881 struct anv_pipeline_cache blorp_shader_cache;
882 struct blorp_context blorp;
883
884 struct anv_state border_colors;
885
886 struct anv_queue queue;
887
888 struct anv_scratch_pool scratch_pool;
889
890 uint32_t default_mocs;
891
892 pthread_mutex_t mutex;
893 pthread_cond_t queue_submit;
894 bool lost;
895 };
896
897 static void inline
898 anv_state_flush(struct anv_device *device, struct anv_state state)
899 {
900 if (device->info.has_llc)
901 return;
902
903 gen_flush_range(state.map, state.alloc_size);
904 }
905
906 void anv_device_init_blorp(struct anv_device *device);
907 void anv_device_finish_blorp(struct anv_device *device);
908
909 VkResult anv_device_execbuf(struct anv_device *device,
910 struct drm_i915_gem_execbuffer2 *execbuf,
911 struct anv_bo **execbuf_bos);
912 VkResult anv_device_query_status(struct anv_device *device);
913 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
914 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
915 int64_t timeout);
916
917 void* anv_gem_mmap(struct anv_device *device,
918 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
919 void anv_gem_munmap(void *p, uint64_t size);
920 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
921 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
922 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
923 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
924 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
925 int anv_gem_execbuffer(struct anv_device *device,
926 struct drm_i915_gem_execbuffer2 *execbuf);
927 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
928 uint32_t stride, uint32_t tiling);
929 int anv_gem_create_context(struct anv_device *device);
930 int anv_gem_destroy_context(struct anv_device *device, int context);
931 int anv_gem_get_context_param(int fd, int context, uint32_t param,
932 uint64_t *value);
933 int anv_gem_get_param(int fd, uint32_t param);
934 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
935 int anv_gem_get_aperture(int fd, uint64_t *size);
936 bool anv_gem_supports_48b_addresses(int fd);
937 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
938 uint32_t *active, uint32_t *pending);
939 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
940 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
941 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
942 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
943 uint32_t read_domains, uint32_t write_domain);
944 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
945 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
946 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
947 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
948 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
949 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
950 uint32_t handle);
951 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
952 uint32_t handle, int fd);
953 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
954 bool anv_gem_supports_syncobj_wait(int fd);
955 int anv_gem_syncobj_wait(struct anv_device *device,
956 uint32_t *handles, uint32_t num_handles,
957 int64_t abs_timeout_ns, bool wait_all);
958
959 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
960
961 struct anv_reloc_list {
962 uint32_t num_relocs;
963 uint32_t array_length;
964 struct drm_i915_gem_relocation_entry * relocs;
965 struct anv_bo ** reloc_bos;
966 };
967
968 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
969 const VkAllocationCallbacks *alloc);
970 void anv_reloc_list_finish(struct anv_reloc_list *list,
971 const VkAllocationCallbacks *alloc);
972
973 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
974 const VkAllocationCallbacks *alloc,
975 uint32_t offset, struct anv_bo *target_bo,
976 uint32_t delta);
977
978 struct anv_batch_bo {
979 /* Link in the anv_cmd_buffer.owned_batch_bos list */
980 struct list_head link;
981
982 struct anv_bo bo;
983
984 /* Bytes actually consumed in this batch BO */
985 uint32_t length;
986
987 struct anv_reloc_list relocs;
988 };
989
990 struct anv_batch {
991 const VkAllocationCallbacks * alloc;
992
993 void * start;
994 void * end;
995 void * next;
996
997 struct anv_reloc_list * relocs;
998
999 /* This callback is called (with the associated user data) in the event
1000 * that the batch runs out of space.
1001 */
1002 VkResult (*extend_cb)(struct anv_batch *, void *);
1003 void * user_data;
1004
1005 /**
1006 * Current error status of the command buffer. Used to track inconsistent
1007 * or incomplete command buffer states that are the consequence of run-time
1008 * errors such as out of memory scenarios. We want to track this in the
1009 * batch because the command buffer object is not visible to some parts
1010 * of the driver.
1011 */
1012 VkResult status;
1013 };
1014
1015 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1016 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1017 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1018 void *location, struct anv_bo *bo, uint32_t offset);
1019 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1020 struct anv_batch *batch);
1021
1022 static inline VkResult
1023 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1024 {
1025 assert(error != VK_SUCCESS);
1026 if (batch->status == VK_SUCCESS)
1027 batch->status = error;
1028 return batch->status;
1029 }
1030
1031 static inline bool
1032 anv_batch_has_error(struct anv_batch *batch)
1033 {
1034 return batch->status != VK_SUCCESS;
1035 }
1036
1037 struct anv_address {
1038 struct anv_bo *bo;
1039 uint32_t offset;
1040 };
1041
1042 static inline uint64_t
1043 _anv_combine_address(struct anv_batch *batch, void *location,
1044 const struct anv_address address, uint32_t delta)
1045 {
1046 if (address.bo == NULL) {
1047 return address.offset + delta;
1048 } else {
1049 assert(batch->start <= location && location < batch->end);
1050
1051 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1052 }
1053 }
1054
1055 #define __gen_address_type struct anv_address
1056 #define __gen_user_data struct anv_batch
1057 #define __gen_combine_address _anv_combine_address
1058
1059 /* Wrapper macros needed to work around preprocessor argument issues. In
1060 * particular, arguments don't get pre-evaluated if they are concatenated.
1061 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1062 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1063 * We can work around this easily enough with these helpers.
1064 */
1065 #define __anv_cmd_length(cmd) cmd ## _length
1066 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1067 #define __anv_cmd_header(cmd) cmd ## _header
1068 #define __anv_cmd_pack(cmd) cmd ## _pack
1069 #define __anv_reg_num(reg) reg ## _num
1070
1071 #define anv_pack_struct(dst, struc, ...) do { \
1072 struct struc __template = { \
1073 __VA_ARGS__ \
1074 }; \
1075 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1076 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1077 } while (0)
1078
1079 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1080 void *__dst = anv_batch_emit_dwords(batch, n); \
1081 if (__dst) { \
1082 struct cmd __template = { \
1083 __anv_cmd_header(cmd), \
1084 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1085 __VA_ARGS__ \
1086 }; \
1087 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1088 } \
1089 __dst; \
1090 })
1091
1092 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1093 do { \
1094 uint32_t *dw; \
1095 \
1096 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1097 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1098 if (!dw) \
1099 break; \
1100 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1101 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1102 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1103 } while (0)
1104
1105 #define anv_batch_emit(batch, cmd, name) \
1106 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1107 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1108 __builtin_expect(_dst != NULL, 1); \
1109 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1110 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1111 _dst = NULL; \
1112 }))
1113
1114 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1115 .GraphicsDataTypeGFDT = 0, \
1116 .LLCCacheabilityControlLLCCC = 0, \
1117 .L3CacheabilityControlL3CC = 1, \
1118 }
1119
1120 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1121 .LLCeLLCCacheabilityControlLLCCC = 0, \
1122 .L3CacheabilityControlL3CC = 1, \
1123 }
1124
1125 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1126 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1127 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1128 .AgeforQUADLRU = 0 \
1129 }
1130
1131 /* Skylake: MOCS is now an index into an array of 62 different caching
1132 * configurations programmed by the kernel.
1133 */
1134
1135 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1136 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1137 .IndextoMOCSTables = 2 \
1138 }
1139
1140 #define GEN9_MOCS_PTE { \
1141 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1142 .IndextoMOCSTables = 1 \
1143 }
1144
1145 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1146 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1147 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1148 .IndextoMOCSTables = 2 \
1149 }
1150
1151 #define GEN10_MOCS_PTE { \
1152 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1153 .IndextoMOCSTables = 1 \
1154 }
1155
1156 struct anv_device_memory {
1157 struct anv_bo * bo;
1158 struct anv_memory_type * type;
1159 VkDeviceSize map_size;
1160 void * map;
1161 };
1162
1163 /**
1164 * Header for Vertex URB Entry (VUE)
1165 */
1166 struct anv_vue_header {
1167 uint32_t Reserved;
1168 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1169 uint32_t ViewportIndex;
1170 float PointWidth;
1171 };
1172
1173 struct anv_descriptor_set_binding_layout {
1174 #ifndef NDEBUG
1175 /* The type of the descriptors in this binding */
1176 VkDescriptorType type;
1177 #endif
1178
1179 /* Number of array elements in this binding */
1180 uint16_t array_size;
1181
1182 /* Index into the flattend descriptor set */
1183 uint16_t descriptor_index;
1184
1185 /* Index into the dynamic state array for a dynamic buffer */
1186 int16_t dynamic_offset_index;
1187
1188 /* Index into the descriptor set buffer views */
1189 int16_t buffer_index;
1190
1191 struct {
1192 /* Index into the binding table for the associated surface */
1193 int16_t surface_index;
1194
1195 /* Index into the sampler table for the associated sampler */
1196 int16_t sampler_index;
1197
1198 /* Index into the image table for the associated image */
1199 int16_t image_index;
1200 } stage[MESA_SHADER_STAGES];
1201
1202 /* Immutable samplers (or NULL if no immutable samplers) */
1203 struct anv_sampler **immutable_samplers;
1204 };
1205
1206 struct anv_descriptor_set_layout {
1207 /* Number of bindings in this descriptor set */
1208 uint16_t binding_count;
1209
1210 /* Total size of the descriptor set with room for all array entries */
1211 uint16_t size;
1212
1213 /* Shader stages affected by this descriptor set */
1214 uint16_t shader_stages;
1215
1216 /* Number of buffers in this descriptor set */
1217 uint16_t buffer_count;
1218
1219 /* Number of dynamic offsets used by this descriptor set */
1220 uint16_t dynamic_offset_count;
1221
1222 /* Bindings in this descriptor set */
1223 struct anv_descriptor_set_binding_layout binding[0];
1224 };
1225
1226 struct anv_descriptor {
1227 VkDescriptorType type;
1228
1229 union {
1230 struct {
1231 VkImageLayout layout;
1232 struct anv_image_view *image_view;
1233 struct anv_sampler *sampler;
1234 };
1235
1236 struct {
1237 struct anv_buffer *buffer;
1238 uint64_t offset;
1239 uint64_t range;
1240 };
1241
1242 struct anv_buffer_view *buffer_view;
1243 };
1244 };
1245
1246 struct anv_descriptor_set {
1247 const struct anv_descriptor_set_layout *layout;
1248 uint32_t size;
1249 uint32_t buffer_count;
1250 struct anv_buffer_view *buffer_views;
1251 struct anv_descriptor descriptors[0];
1252 };
1253
1254 struct anv_buffer_view {
1255 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1256 struct anv_bo *bo;
1257 uint32_t offset; /**< Offset into bo. */
1258 uint64_t range; /**< VkBufferViewCreateInfo::range */
1259
1260 struct anv_state surface_state;
1261 struct anv_state storage_surface_state;
1262 struct anv_state writeonly_storage_surface_state;
1263
1264 struct brw_image_param storage_image_param;
1265 };
1266
1267 struct anv_push_descriptor_set {
1268 struct anv_descriptor_set set;
1269
1270 /* Put this field right behind anv_descriptor_set so it fills up the
1271 * descriptors[0] field. */
1272 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1273 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1274 };
1275
1276 struct anv_descriptor_pool {
1277 uint32_t size;
1278 uint32_t next;
1279 uint32_t free_list;
1280
1281 struct anv_state_stream surface_state_stream;
1282 void *surface_state_free_list;
1283
1284 char data[0];
1285 };
1286
1287 enum anv_descriptor_template_entry_type {
1288 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1289 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1290 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1291 };
1292
1293 struct anv_descriptor_template_entry {
1294 /* The type of descriptor in this entry */
1295 VkDescriptorType type;
1296
1297 /* Binding in the descriptor set */
1298 uint32_t binding;
1299
1300 /* Offset at which to write into the descriptor set binding */
1301 uint32_t array_element;
1302
1303 /* Number of elements to write into the descriptor set binding */
1304 uint32_t array_count;
1305
1306 /* Offset into the user provided data */
1307 size_t offset;
1308
1309 /* Stride between elements into the user provided data */
1310 size_t stride;
1311 };
1312
1313 struct anv_descriptor_update_template {
1314 /* The descriptor set this template corresponds to. This value is only
1315 * valid if the template was created with the templateType
1316 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1317 */
1318 uint8_t set;
1319
1320 /* Number of entries in this template */
1321 uint32_t entry_count;
1322
1323 /* Entries of the template */
1324 struct anv_descriptor_template_entry entries[0];
1325 };
1326
1327 size_t
1328 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1329
1330 size_t
1331 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1332
1333 void
1334 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1335 const struct gen_device_info * const devinfo,
1336 const VkDescriptorImageInfo * const info,
1337 VkDescriptorType type,
1338 uint32_t binding,
1339 uint32_t element);
1340
1341 void
1342 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1343 VkDescriptorType type,
1344 struct anv_buffer_view *buffer_view,
1345 uint32_t binding,
1346 uint32_t element);
1347
1348 void
1349 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1350 struct anv_device *device,
1351 struct anv_state_stream *alloc_stream,
1352 VkDescriptorType type,
1353 struct anv_buffer *buffer,
1354 uint32_t binding,
1355 uint32_t element,
1356 VkDeviceSize offset,
1357 VkDeviceSize range);
1358
1359 void
1360 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1361 struct anv_device *device,
1362 struct anv_state_stream *alloc_stream,
1363 const struct anv_descriptor_update_template *template,
1364 const void *data);
1365
1366 VkResult
1367 anv_descriptor_set_create(struct anv_device *device,
1368 struct anv_descriptor_pool *pool,
1369 const struct anv_descriptor_set_layout *layout,
1370 struct anv_descriptor_set **out_set);
1371
1372 void
1373 anv_descriptor_set_destroy(struct anv_device *device,
1374 struct anv_descriptor_pool *pool,
1375 struct anv_descriptor_set *set);
1376
1377 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1378
1379 struct anv_pipeline_binding {
1380 /* The descriptor set this surface corresponds to. The special value of
1381 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1382 * to a color attachment and not a regular descriptor.
1383 */
1384 uint8_t set;
1385
1386 /* Binding in the descriptor set */
1387 uint32_t binding;
1388
1389 /* Index in the binding */
1390 uint32_t index;
1391
1392 /* Plane in the binding index */
1393 uint8_t plane;
1394
1395 /* Input attachment index (relative to the subpass) */
1396 uint8_t input_attachment_index;
1397
1398 /* For a storage image, whether it is write-only */
1399 bool write_only;
1400 };
1401
1402 struct anv_pipeline_layout {
1403 struct {
1404 struct anv_descriptor_set_layout *layout;
1405 uint32_t dynamic_offset_start;
1406 } set[MAX_SETS];
1407
1408 uint32_t num_sets;
1409
1410 struct {
1411 bool has_dynamic_offsets;
1412 } stage[MESA_SHADER_STAGES];
1413
1414 unsigned char sha1[20];
1415 };
1416
1417 struct anv_buffer {
1418 struct anv_device * device;
1419 VkDeviceSize size;
1420
1421 VkBufferUsageFlags usage;
1422
1423 /* Set when bound */
1424 struct anv_bo * bo;
1425 VkDeviceSize offset;
1426 };
1427
1428 static inline uint64_t
1429 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1430 {
1431 assert(offset <= buffer->size);
1432 if (range == VK_WHOLE_SIZE) {
1433 return buffer->size - offset;
1434 } else {
1435 assert(range <= buffer->size);
1436 return range;
1437 }
1438 }
1439
1440 enum anv_cmd_dirty_bits {
1441 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1442 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1443 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1444 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1445 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1446 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1447 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1448 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1449 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1450 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1451 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1452 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1453 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1454 };
1455 typedef uint32_t anv_cmd_dirty_mask_t;
1456
1457 enum anv_pipe_bits {
1458 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1459 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1460 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1461 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1462 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1463 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1464 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1465 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1466 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1467 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1468 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1469
1470 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1471 * a flush has happened but not a CS stall. The next time we do any sort
1472 * of invalidation we need to insert a CS stall at that time. Otherwise,
1473 * we would have to CS stall on every flush which could be bad.
1474 */
1475 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1476 };
1477
1478 #define ANV_PIPE_FLUSH_BITS ( \
1479 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1480 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1481 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1482
1483 #define ANV_PIPE_STALL_BITS ( \
1484 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1485 ANV_PIPE_DEPTH_STALL_BIT | \
1486 ANV_PIPE_CS_STALL_BIT)
1487
1488 #define ANV_PIPE_INVALIDATE_BITS ( \
1489 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1490 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1491 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1492 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1493 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1494 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1495
1496 static inline enum anv_pipe_bits
1497 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1498 {
1499 enum anv_pipe_bits pipe_bits = 0;
1500
1501 unsigned b;
1502 for_each_bit(b, flags) {
1503 switch ((VkAccessFlagBits)(1 << b)) {
1504 case VK_ACCESS_SHADER_WRITE_BIT:
1505 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1506 break;
1507 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1508 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1509 break;
1510 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1511 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1512 break;
1513 case VK_ACCESS_TRANSFER_WRITE_BIT:
1514 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1515 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1516 break;
1517 default:
1518 break; /* Nothing to do */
1519 }
1520 }
1521
1522 return pipe_bits;
1523 }
1524
1525 static inline enum anv_pipe_bits
1526 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1527 {
1528 enum anv_pipe_bits pipe_bits = 0;
1529
1530 unsigned b;
1531 for_each_bit(b, flags) {
1532 switch ((VkAccessFlagBits)(1 << b)) {
1533 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1534 case VK_ACCESS_INDEX_READ_BIT:
1535 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1536 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1537 break;
1538 case VK_ACCESS_UNIFORM_READ_BIT:
1539 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1540 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1541 break;
1542 case VK_ACCESS_SHADER_READ_BIT:
1543 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1544 case VK_ACCESS_TRANSFER_READ_BIT:
1545 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1546 break;
1547 default:
1548 break; /* Nothing to do */
1549 }
1550 }
1551
1552 return pipe_bits;
1553 }
1554
1555 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT ( \
1556 VK_IMAGE_ASPECT_COLOR_BIT | \
1557 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1558 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1559 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1560 #define VK_IMAGE_ASPECT_PLANES_BITS ( \
1561 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1562 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1563 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1564
1565 struct anv_vertex_binding {
1566 struct anv_buffer * buffer;
1567 VkDeviceSize offset;
1568 };
1569
1570 struct anv_push_constants {
1571 /* Current allocated size of this push constants data structure.
1572 * Because a decent chunk of it may not be used (images on SKL, for
1573 * instance), we won't actually allocate the entire structure up-front.
1574 */
1575 uint32_t size;
1576
1577 /* Push constant data provided by the client through vkPushConstants */
1578 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1579
1580 /* Image data for image_load_store on pre-SKL */
1581 struct brw_image_param images[MAX_IMAGES];
1582 };
1583
1584 struct anv_dynamic_state {
1585 struct {
1586 uint32_t count;
1587 VkViewport viewports[MAX_VIEWPORTS];
1588 } viewport;
1589
1590 struct {
1591 uint32_t count;
1592 VkRect2D scissors[MAX_SCISSORS];
1593 } scissor;
1594
1595 float line_width;
1596
1597 struct {
1598 float bias;
1599 float clamp;
1600 float slope;
1601 } depth_bias;
1602
1603 float blend_constants[4];
1604
1605 struct {
1606 float min;
1607 float max;
1608 } depth_bounds;
1609
1610 struct {
1611 uint32_t front;
1612 uint32_t back;
1613 } stencil_compare_mask;
1614
1615 struct {
1616 uint32_t front;
1617 uint32_t back;
1618 } stencil_write_mask;
1619
1620 struct {
1621 uint32_t front;
1622 uint32_t back;
1623 } stencil_reference;
1624 };
1625
1626 extern const struct anv_dynamic_state default_dynamic_state;
1627
1628 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1629 const struct anv_dynamic_state *src,
1630 uint32_t copy_mask);
1631
1632 struct anv_surface_state {
1633 struct anv_state state;
1634 /** Address of the surface referred to by this state
1635 *
1636 * This address is relative to the start of the BO.
1637 */
1638 uint64_t address;
1639 /* Address of the aux surface, if any
1640 *
1641 * This field is 0 if and only if no aux surface exists.
1642 *
1643 * This address is relative to the start of the BO. On gen7, the bottom 12
1644 * bits of this address include extra aux information.
1645 */
1646 uint64_t aux_address;
1647 };
1648
1649 /**
1650 * Attachment state when recording a renderpass instance.
1651 *
1652 * The clear value is valid only if there exists a pending clear.
1653 */
1654 struct anv_attachment_state {
1655 enum isl_aux_usage aux_usage;
1656 enum isl_aux_usage input_aux_usage;
1657 struct anv_surface_state color;
1658 struct anv_surface_state input;
1659
1660 VkImageLayout current_layout;
1661 VkImageAspectFlags pending_clear_aspects;
1662 bool fast_clear;
1663 VkClearValue clear_value;
1664 bool clear_color_is_zero_one;
1665 bool clear_color_is_zero;
1666 };
1667
1668 /** State required while building cmd buffer */
1669 struct anv_cmd_state {
1670 /* PIPELINE_SELECT.PipelineSelection */
1671 uint32_t current_pipeline;
1672 const struct gen_l3_config * current_l3_config;
1673 uint32_t vb_dirty;
1674 anv_cmd_dirty_mask_t dirty;
1675 anv_cmd_dirty_mask_t compute_dirty;
1676 enum anv_pipe_bits pending_pipe_bits;
1677 uint32_t num_workgroups_offset;
1678 struct anv_bo *num_workgroups_bo;
1679 VkShaderStageFlags descriptors_dirty;
1680 VkShaderStageFlags push_constants_dirty;
1681 uint32_t scratch_size;
1682 struct anv_pipeline * pipeline;
1683 struct anv_pipeline * compute_pipeline;
1684 struct anv_framebuffer * framebuffer;
1685 struct anv_render_pass * pass;
1686 struct anv_subpass * subpass;
1687 VkRect2D render_area;
1688 uint32_t restart_index;
1689 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1690 struct anv_descriptor_set * descriptors[MAX_SETS];
1691 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1692 VkShaderStageFlags push_constant_stages;
1693 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1694 struct anv_state binding_tables[MESA_SHADER_STAGES];
1695 struct anv_state samplers[MESA_SHADER_STAGES];
1696 struct anv_dynamic_state dynamic;
1697 bool need_query_wa;
1698
1699 struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
1700
1701 /**
1702 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1703 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1704 * and before invoking the secondary in ExecuteCommands.
1705 */
1706 bool pma_fix_enabled;
1707
1708 /**
1709 * Whether or not we know for certain that HiZ is enabled for the current
1710 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1711 * enabled or not, this will be false.
1712 */
1713 bool hiz_enabled;
1714
1715 /**
1716 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1717 * valid only when recording a render pass instance.
1718 */
1719 struct anv_attachment_state * attachments;
1720
1721 /**
1722 * Surface states for color render targets. These are stored in a single
1723 * flat array. For depth-stencil attachments, the surface state is simply
1724 * left blank.
1725 */
1726 struct anv_state render_pass_states;
1727
1728 /**
1729 * A null surface state of the right size to match the framebuffer. This
1730 * is one of the states in render_pass_states.
1731 */
1732 struct anv_state null_surface_state;
1733
1734 struct {
1735 struct anv_buffer * index_buffer;
1736 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1737 uint32_t index_offset;
1738 } gen7;
1739 };
1740
1741 struct anv_cmd_pool {
1742 VkAllocationCallbacks alloc;
1743 struct list_head cmd_buffers;
1744 };
1745
1746 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1747
1748 enum anv_cmd_buffer_exec_mode {
1749 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1750 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1751 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1752 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1753 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1754 };
1755
1756 struct anv_cmd_buffer {
1757 VK_LOADER_DATA _loader_data;
1758
1759 struct anv_device * device;
1760
1761 struct anv_cmd_pool * pool;
1762 struct list_head pool_link;
1763
1764 struct anv_batch batch;
1765
1766 /* Fields required for the actual chain of anv_batch_bo's.
1767 *
1768 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1769 */
1770 struct list_head batch_bos;
1771 enum anv_cmd_buffer_exec_mode exec_mode;
1772
1773 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1774 * referenced by this command buffer
1775 *
1776 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1777 */
1778 struct u_vector seen_bbos;
1779
1780 /* A vector of int32_t's for every block of binding tables.
1781 *
1782 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1783 */
1784 struct u_vector bt_block_states;
1785 uint32_t bt_next;
1786
1787 struct anv_reloc_list surface_relocs;
1788 /** Last seen surface state block pool center bo offset */
1789 uint32_t last_ss_pool_center;
1790
1791 /* Serial for tracking buffer completion */
1792 uint32_t serial;
1793
1794 /* Stream objects for storing temporary data */
1795 struct anv_state_stream surface_state_stream;
1796 struct anv_state_stream dynamic_state_stream;
1797
1798 VkCommandBufferUsageFlags usage_flags;
1799 VkCommandBufferLevel level;
1800
1801 struct anv_cmd_state state;
1802 };
1803
1804 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1805 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1806 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1807 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1808 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1809 struct anv_cmd_buffer *secondary);
1810 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1811 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1812 struct anv_cmd_buffer *cmd_buffer,
1813 const VkSemaphore *in_semaphores,
1814 uint32_t num_in_semaphores,
1815 const VkSemaphore *out_semaphores,
1816 uint32_t num_out_semaphores,
1817 VkFence fence);
1818
1819 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1820
1821 VkResult
1822 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1823 gl_shader_stage stage, uint32_t size);
1824 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1825 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1826 (offsetof(struct anv_push_constants, field) + \
1827 sizeof(cmd_buffer->state.push_constants[0]->field)))
1828
1829 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1830 const void *data, uint32_t size, uint32_t alignment);
1831 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1832 uint32_t *a, uint32_t *b,
1833 uint32_t dwords, uint32_t alignment);
1834
1835 struct anv_address
1836 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1837 struct anv_state
1838 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1839 uint32_t entries, uint32_t *state_offset);
1840 struct anv_state
1841 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1842 struct anv_state
1843 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1844 uint32_t size, uint32_t alignment);
1845
1846 VkResult
1847 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1848
1849 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1850 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1851 bool depth_clamp_enable);
1852 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1853
1854 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1855 struct anv_render_pass *pass,
1856 struct anv_framebuffer *framebuffer,
1857 const VkClearValue *clear_values);
1858
1859 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1860
1861 struct anv_state
1862 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1863 gl_shader_stage stage);
1864 struct anv_state
1865 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1866
1867 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1868 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1869
1870 const struct anv_image_view *
1871 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1872
1873 VkResult
1874 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1875 uint32_t num_entries,
1876 uint32_t *state_offset,
1877 struct anv_state *bt_state);
1878
1879 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1880
1881 enum anv_fence_type {
1882 ANV_FENCE_TYPE_NONE = 0,
1883 ANV_FENCE_TYPE_BO,
1884 ANV_FENCE_TYPE_SYNCOBJ,
1885 };
1886
1887 enum anv_bo_fence_state {
1888 /** Indicates that this is a new (or newly reset fence) */
1889 ANV_BO_FENCE_STATE_RESET,
1890
1891 /** Indicates that this fence has been submitted to the GPU but is still
1892 * (as far as we know) in use by the GPU.
1893 */
1894 ANV_BO_FENCE_STATE_SUBMITTED,
1895
1896 ANV_BO_FENCE_STATE_SIGNALED,
1897 };
1898
1899 struct anv_fence_impl {
1900 enum anv_fence_type type;
1901
1902 union {
1903 /** Fence implementation for BO fences
1904 *
1905 * These fences use a BO and a set of CPU-tracked state flags. The BO
1906 * is added to the object list of the last execbuf call in a QueueSubmit
1907 * and is marked EXEC_WRITE. The state flags track when the BO has been
1908 * submitted to the kernel. We need to do this because Vulkan lets you
1909 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1910 * will say it's idle in this case.
1911 */
1912 struct {
1913 struct anv_bo bo;
1914 enum anv_bo_fence_state state;
1915 } bo;
1916
1917 /** DRM syncobj handle for syncobj-based fences */
1918 uint32_t syncobj;
1919 };
1920 };
1921
1922 struct anv_fence {
1923 /* Permanent fence state. Every fence has some form of permanent state
1924 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1925 * cross-process fences) or it could just be a dummy for use internally.
1926 */
1927 struct anv_fence_impl permanent;
1928
1929 /* Temporary fence state. A fence *may* have temporary state. That state
1930 * is added to the fence by an import operation and is reset back to
1931 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1932 * state cannot be signaled because the fence must already be signaled
1933 * before the temporary state can be exported from the fence in the other
1934 * process and imported here.
1935 */
1936 struct anv_fence_impl temporary;
1937 };
1938
1939 struct anv_event {
1940 uint64_t semaphore;
1941 struct anv_state state;
1942 };
1943
1944 enum anv_semaphore_type {
1945 ANV_SEMAPHORE_TYPE_NONE = 0,
1946 ANV_SEMAPHORE_TYPE_DUMMY,
1947 ANV_SEMAPHORE_TYPE_BO,
1948 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1949 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1950 };
1951
1952 struct anv_semaphore_impl {
1953 enum anv_semaphore_type type;
1954
1955 union {
1956 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1957 * This BO will be added to the object list on any execbuf2 calls for
1958 * which this semaphore is used as a wait or signal fence. When used as
1959 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1960 */
1961 struct anv_bo *bo;
1962
1963 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
1964 * If the semaphore is in the unsignaled state due to either just being
1965 * created or because it has been used for a wait, fd will be -1.
1966 */
1967 int fd;
1968
1969 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1970 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1971 * import so we don't need to bother with a userspace cache.
1972 */
1973 uint32_t syncobj;
1974 };
1975 };
1976
1977 struct anv_semaphore {
1978 /* Permanent semaphore state. Every semaphore has some form of permanent
1979 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1980 * (for cross-process semaphores0 or it could just be a dummy for use
1981 * internally.
1982 */
1983 struct anv_semaphore_impl permanent;
1984
1985 /* Temporary semaphore state. A semaphore *may* have temporary state.
1986 * That state is added to the semaphore by an import operation and is reset
1987 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1988 * semaphore with temporary state cannot be signaled because the semaphore
1989 * must already be signaled before the temporary state can be exported from
1990 * the semaphore in the other process and imported here.
1991 */
1992 struct anv_semaphore_impl temporary;
1993 };
1994
1995 void anv_semaphore_reset_temporary(struct anv_device *device,
1996 struct anv_semaphore *semaphore);
1997
1998 struct anv_shader_module {
1999 unsigned char sha1[20];
2000 uint32_t size;
2001 char data[0];
2002 };
2003
2004 static inline gl_shader_stage
2005 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2006 {
2007 assert(__builtin_popcount(vk_stage) == 1);
2008 return ffs(vk_stage) - 1;
2009 }
2010
2011 static inline VkShaderStageFlagBits
2012 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2013 {
2014 return (1 << mesa_stage);
2015 }
2016
2017 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2018
2019 #define anv_foreach_stage(stage, stage_bits) \
2020 for (gl_shader_stage stage, \
2021 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2022 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2023 __tmp &= ~(1 << (stage)))
2024
2025 struct anv_pipeline_bind_map {
2026 uint32_t surface_count;
2027 uint32_t sampler_count;
2028 uint32_t image_count;
2029
2030 struct anv_pipeline_binding * surface_to_descriptor;
2031 struct anv_pipeline_binding * sampler_to_descriptor;
2032 };
2033
2034 struct anv_shader_bin_key {
2035 uint32_t size;
2036 uint8_t data[0];
2037 };
2038
2039 struct anv_shader_bin {
2040 uint32_t ref_cnt;
2041
2042 const struct anv_shader_bin_key *key;
2043
2044 struct anv_state kernel;
2045 uint32_t kernel_size;
2046
2047 const struct brw_stage_prog_data *prog_data;
2048 uint32_t prog_data_size;
2049
2050 struct anv_pipeline_bind_map bind_map;
2051 };
2052
2053 struct anv_shader_bin *
2054 anv_shader_bin_create(struct anv_device *device,
2055 const void *key, uint32_t key_size,
2056 const void *kernel, uint32_t kernel_size,
2057 const struct brw_stage_prog_data *prog_data,
2058 uint32_t prog_data_size, const void *prog_data_param,
2059 const struct anv_pipeline_bind_map *bind_map);
2060
2061 void
2062 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2063
2064 static inline void
2065 anv_shader_bin_ref(struct anv_shader_bin *shader)
2066 {
2067 assert(shader && shader->ref_cnt >= 1);
2068 p_atomic_inc(&shader->ref_cnt);
2069 }
2070
2071 static inline void
2072 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2073 {
2074 assert(shader && shader->ref_cnt >= 1);
2075 if (p_atomic_dec_zero(&shader->ref_cnt))
2076 anv_shader_bin_destroy(device, shader);
2077 }
2078
2079 struct anv_pipeline {
2080 struct anv_device * device;
2081 struct anv_batch batch;
2082 uint32_t batch_data[512];
2083 struct anv_reloc_list batch_relocs;
2084 uint32_t dynamic_state_mask;
2085 struct anv_dynamic_state dynamic_state;
2086
2087 struct anv_subpass * subpass;
2088 struct anv_pipeline_layout * layout;
2089
2090 bool needs_data_cache;
2091
2092 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2093
2094 struct {
2095 const struct gen_l3_config * l3_config;
2096 uint32_t total_size;
2097 } urb;
2098
2099 VkShaderStageFlags active_stages;
2100 struct anv_state blend_state;
2101
2102 uint32_t vb_used;
2103 uint32_t binding_stride[MAX_VBS];
2104 bool instancing_enable[MAX_VBS];
2105 bool primitive_restart;
2106 uint32_t topology;
2107
2108 uint32_t cs_right_mask;
2109
2110 bool writes_depth;
2111 bool depth_test_enable;
2112 bool writes_stencil;
2113 bool stencil_test_enable;
2114 bool depth_clamp_enable;
2115 bool sample_shading_enable;
2116 bool kill_pixel;
2117
2118 struct {
2119 uint32_t sf[7];
2120 uint32_t depth_stencil_state[3];
2121 } gen7;
2122
2123 struct {
2124 uint32_t sf[4];
2125 uint32_t raster[5];
2126 uint32_t wm_depth_stencil[3];
2127 } gen8;
2128
2129 struct {
2130 uint32_t wm_depth_stencil[4];
2131 } gen9;
2132
2133 uint32_t interface_descriptor_data[8];
2134 };
2135
2136 static inline bool
2137 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2138 gl_shader_stage stage)
2139 {
2140 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2141 }
2142
2143 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2144 static inline const struct brw_##prefix##_prog_data * \
2145 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2146 { \
2147 if (anv_pipeline_has_stage(pipeline, stage)) { \
2148 return (const struct brw_##prefix##_prog_data *) \
2149 pipeline->shaders[stage]->prog_data; \
2150 } else { \
2151 return NULL; \
2152 } \
2153 }
2154
2155 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2156 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2157 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2158 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2159 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2160 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2161
2162 static inline const struct brw_vue_prog_data *
2163 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2164 {
2165 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2166 return &get_gs_prog_data(pipeline)->base;
2167 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2168 return &get_tes_prog_data(pipeline)->base;
2169 else
2170 return &get_vs_prog_data(pipeline)->base;
2171 }
2172
2173 VkResult
2174 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2175 struct anv_pipeline_cache *cache,
2176 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2177 const VkAllocationCallbacks *alloc);
2178
2179 VkResult
2180 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2181 struct anv_pipeline_cache *cache,
2182 const VkComputePipelineCreateInfo *info,
2183 struct anv_shader_module *module,
2184 const char *entrypoint,
2185 const VkSpecializationInfo *spec_info);
2186
2187 struct anv_format_plane {
2188 enum isl_format isl_format:16;
2189 struct isl_swizzle swizzle;
2190
2191 /* Whether this plane contains chroma channels */
2192 bool has_chroma;
2193
2194 /* For downscaling of YUV planes */
2195 uint8_t denominator_scales[2];
2196
2197 /* How to map sampled ycbcr planes to a single 4 component element. */
2198 struct isl_swizzle ycbcr_swizzle;
2199 };
2200
2201
2202 struct anv_format {
2203 struct anv_format_plane planes[3];
2204 uint8_t n_planes;
2205 bool can_ycbcr;
2206 };
2207
2208 static inline uint32_t
2209 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2210 VkImageAspectFlags aspect_mask)
2211 {
2212 switch (aspect_mask) {
2213 case VK_IMAGE_ASPECT_COLOR_BIT:
2214 case VK_IMAGE_ASPECT_DEPTH_BIT:
2215 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2216 return 0;
2217 case VK_IMAGE_ASPECT_STENCIL_BIT:
2218 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2219 return 0;
2220 /* Fall-through */
2221 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2222 return 1;
2223 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2224 return 2;
2225 default:
2226 /* Purposefully assert with depth/stencil aspects. */
2227 unreachable("invalid image aspect");
2228 }
2229 }
2230
2231 static inline uint32_t
2232 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2233 {
2234 uint32_t planes = 0;
2235
2236 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2237 VK_IMAGE_ASPECT_DEPTH_BIT |
2238 VK_IMAGE_ASPECT_STENCIL_BIT |
2239 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2240 planes++;
2241 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2242 planes++;
2243 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2244 planes++;
2245
2246 return planes;
2247 }
2248
2249 static inline VkImageAspectFlags
2250 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2251 uint32_t plane)
2252 {
2253 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT) {
2254 if (_mesa_bitcount(image_aspects) > 1)
2255 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2256 return VK_IMAGE_ASPECT_COLOR_BIT;
2257 }
2258 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2259 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2260 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2261 return VK_IMAGE_ASPECT_STENCIL_BIT;
2262 }
2263
2264 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2265 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2266
2267 const struct anv_format *
2268 anv_get_format(VkFormat format);
2269
2270 static inline uint32_t
2271 anv_get_format_planes(VkFormat vk_format)
2272 {
2273 const struct anv_format *format = anv_get_format(vk_format);
2274
2275 return format != NULL ? format->n_planes : 0;
2276 }
2277
2278 struct anv_format_plane
2279 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2280 VkImageAspectFlags aspect, VkImageTiling tiling);
2281
2282 static inline enum isl_format
2283 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2284 VkImageAspectFlags aspect, VkImageTiling tiling)
2285 {
2286 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2287 }
2288
2289 static inline struct isl_swizzle
2290 anv_swizzle_for_render(struct isl_swizzle swizzle)
2291 {
2292 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2293 * RGB as RGBA for texturing
2294 */
2295 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2296 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2297
2298 /* But it doesn't matter what we render to that channel */
2299 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2300
2301 return swizzle;
2302 }
2303
2304 void
2305 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2306
2307 /**
2308 * Subsurface of an anv_image.
2309 */
2310 struct anv_surface {
2311 /** Valid only if isl_surf::size > 0. */
2312 struct isl_surf isl;
2313
2314 /**
2315 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2316 */
2317 uint32_t offset;
2318 };
2319
2320 struct anv_image {
2321 VkImageType type;
2322 /* The original VkFormat provided by the client. This may not match any
2323 * of the actual surface formats.
2324 */
2325 VkFormat vk_format;
2326 const struct anv_format *format;
2327
2328 VkImageAspectFlags aspects;
2329 VkExtent3D extent;
2330 uint32_t levels;
2331 uint32_t array_size;
2332 uint32_t samples; /**< VkImageCreateInfo::samples */
2333 uint32_t n_planes;
2334 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2335 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2336
2337 VkDeviceSize size;
2338 uint32_t alignment;
2339
2340 /* Whether the image is made of several underlying buffer objects rather a
2341 * single one with different offsets.
2342 */
2343 bool disjoint;
2344
2345 /**
2346 * Image subsurfaces
2347 *
2348 * For each foo, anv_image::planes[x].surface is valid if and only if
2349 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2350 * to figure the number associated with a given aspect.
2351 *
2352 * The hardware requires that the depth buffer and stencil buffer be
2353 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2354 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2355 * allocate the depth and stencil buffers as separate surfaces in the same
2356 * bo.
2357 *
2358 * Memory layout :
2359 *
2360 * -----------------------
2361 * | surface0 | /|\
2362 * ----------------------- |
2363 * | shadow surface0 | |
2364 * ----------------------- | Plane 0
2365 * | aux surface0 | |
2366 * ----------------------- |
2367 * | fast clear colors0 | \|/
2368 * -----------------------
2369 * | surface1 | /|\
2370 * ----------------------- |
2371 * | shadow surface1 | |
2372 * ----------------------- | Plane 1
2373 * | aux surface1 | |
2374 * ----------------------- |
2375 * | fast clear colors1 | \|/
2376 * -----------------------
2377 * | ... |
2378 * | |
2379 * -----------------------
2380 */
2381 struct {
2382 /**
2383 * Offset of the entire plane (whenever the image is disjoint this is
2384 * set to 0).
2385 */
2386 uint32_t offset;
2387
2388 VkDeviceSize size;
2389 uint32_t alignment;
2390
2391 struct anv_surface surface;
2392
2393 /**
2394 * A surface which shadows the main surface and may have different
2395 * tiling. This is used for sampling using a tiling that isn't supported
2396 * for other operations.
2397 */
2398 struct anv_surface shadow_surface;
2399
2400 /**
2401 * For color images, this is the aux usage for this image when not used
2402 * as a color attachment.
2403 *
2404 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2405 * image has a HiZ buffer.
2406 */
2407 enum isl_aux_usage aux_usage;
2408
2409 struct anv_surface aux_surface;
2410
2411 /**
2412 * Offset of the fast clear state (used to compute the
2413 * fast_clear_state_offset of the following planes).
2414 */
2415 uint32_t fast_clear_state_offset;
2416
2417 /**
2418 * BO associated with this plane, set when bound.
2419 */
2420 struct anv_bo *bo;
2421 VkDeviceSize bo_offset;
2422 } planes[3];
2423 };
2424
2425 /* Returns the number of auxiliary buffer levels attached to an image. */
2426 static inline uint8_t
2427 anv_image_aux_levels(const struct anv_image * const image,
2428 VkImageAspectFlagBits aspect)
2429 {
2430 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2431 return image->planes[plane].aux_surface.isl.size > 0 ?
2432 image->planes[plane].aux_surface.isl.levels : 0;
2433 }
2434
2435 /* Returns the number of auxiliary buffer layers attached to an image. */
2436 static inline uint32_t
2437 anv_image_aux_layers(const struct anv_image * const image,
2438 VkImageAspectFlagBits aspect,
2439 const uint8_t miplevel)
2440 {
2441 assert(image);
2442
2443 /* The miplevel must exist in the main buffer. */
2444 assert(miplevel < image->levels);
2445
2446 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2447 /* There are no layers with auxiliary data because the miplevel has no
2448 * auxiliary data.
2449 */
2450 return 0;
2451 } else {
2452 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2453 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2454 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2455 }
2456 }
2457
2458 static inline unsigned
2459 anv_fast_clear_state_entry_size(const struct anv_device *device)
2460 {
2461 assert(device);
2462 /* Entry contents:
2463 * +--------------------------------------------+
2464 * | clear value dword(s) | needs resolve dword |
2465 * +--------------------------------------------+
2466 */
2467
2468 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2469 * GPU memcpy operations.
2470 */
2471 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2472 return device->isl_dev.ss.clear_value_size + 4;
2473 }
2474
2475 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2476 static inline bool
2477 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2478 const struct anv_image *image)
2479 {
2480 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2481 return false;
2482
2483 if (devinfo->gen < 8)
2484 return false;
2485
2486 return image->samples == 1;
2487 }
2488
2489 void
2490 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2491 const struct anv_image *image,
2492 enum blorp_hiz_op op);
2493 void
2494 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2495 const struct anv_state surface_state,
2496 const struct anv_image * const image,
2497 VkImageAspectFlagBits aspect,
2498 const uint8_t level, const uint32_t layer_count,
2499 const enum blorp_fast_clear_op op);
2500
2501 void
2502 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2503 const struct anv_image *image,
2504 VkImageAspectFlagBits aspect,
2505 const uint32_t base_level, const uint32_t level_count,
2506 const uint32_t base_layer, uint32_t layer_count);
2507
2508 void
2509 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2510 const struct anv_image *image,
2511 uint32_t base_level, uint32_t level_count,
2512 uint32_t base_layer, uint32_t layer_count);
2513
2514 enum isl_aux_usage
2515 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2516 const struct anv_image *image,
2517 const VkImageAspectFlagBits aspect,
2518 const VkImageLayout layout);
2519
2520 /* This is defined as a macro so that it works for both
2521 * VkImageSubresourceRange and VkImageSubresourceLayers
2522 */
2523 #define anv_get_layerCount(_image, _range) \
2524 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2525 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2526
2527 static inline uint32_t
2528 anv_get_levelCount(const struct anv_image *image,
2529 const VkImageSubresourceRange *range)
2530 {
2531 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2532 image->levels - range->baseMipLevel : range->levelCount;
2533 }
2534
2535 static inline VkImageAspectFlags
2536 anv_image_expand_aspects(const struct anv_image *image,
2537 VkImageAspectFlags aspects)
2538 {
2539 /* If the underlying image has color plane aspects and
2540 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2541 * the underlying image. */
2542 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS) != 0 &&
2543 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2544 return image->aspects;
2545
2546 return aspects;
2547 }
2548
2549 static inline bool
2550 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2551 VkImageAspectFlags aspects2)
2552 {
2553 if (aspects1 == aspects2)
2554 return true;
2555
2556 /* Only 1 color aspects are compatibles. */
2557 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT) != 0 &&
2558 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT) != 0 &&
2559 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2560 return true;
2561
2562 return false;
2563 }
2564
2565 struct anv_image_view {
2566 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2567
2568 VkImageAspectFlags aspect_mask;
2569 VkFormat vk_format;
2570 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2571
2572 unsigned n_planes;
2573 struct {
2574 uint32_t image_plane;
2575
2576 struct isl_view isl;
2577
2578 /**
2579 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2580 * image layout of SHADER_READ_ONLY_OPTIMAL or
2581 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2582 */
2583 struct anv_surface_state optimal_sampler_surface_state;
2584
2585 /**
2586 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2587 * image layout of GENERAL.
2588 */
2589 struct anv_surface_state general_sampler_surface_state;
2590
2591 /**
2592 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2593 * states for write-only and readable, using the real format for
2594 * write-only and the lowered format for readable.
2595 */
2596 struct anv_surface_state storage_surface_state;
2597 struct anv_surface_state writeonly_storage_surface_state;
2598
2599 struct brw_image_param storage_image_param;
2600 } planes[3];
2601 };
2602
2603 enum anv_image_view_state_flags {
2604 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2605 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2606 };
2607
2608 void anv_image_fill_surface_state(struct anv_device *device,
2609 const struct anv_image *image,
2610 VkImageAspectFlagBits aspect,
2611 const struct isl_view *view,
2612 isl_surf_usage_flags_t view_usage,
2613 enum isl_aux_usage aux_usage,
2614 const union isl_color_value *clear_color,
2615 enum anv_image_view_state_flags flags,
2616 struct anv_surface_state *state_inout,
2617 struct brw_image_param *image_param_out);
2618
2619 struct anv_image_create_info {
2620 const VkImageCreateInfo *vk_info;
2621
2622 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2623 isl_tiling_flags_t isl_tiling_flags;
2624
2625 uint32_t stride;
2626 };
2627
2628 VkResult anv_image_create(VkDevice _device,
2629 const struct anv_image_create_info *info,
2630 const VkAllocationCallbacks* alloc,
2631 VkImage *pImage);
2632
2633 const struct anv_surface *
2634 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2635 VkImageAspectFlags aspect_mask);
2636
2637 enum isl_format
2638 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2639
2640 static inline struct VkExtent3D
2641 anv_sanitize_image_extent(const VkImageType imageType,
2642 const struct VkExtent3D imageExtent)
2643 {
2644 switch (imageType) {
2645 case VK_IMAGE_TYPE_1D:
2646 return (VkExtent3D) { imageExtent.width, 1, 1 };
2647 case VK_IMAGE_TYPE_2D:
2648 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2649 case VK_IMAGE_TYPE_3D:
2650 return imageExtent;
2651 default:
2652 unreachable("invalid image type");
2653 }
2654 }
2655
2656 static inline struct VkOffset3D
2657 anv_sanitize_image_offset(const VkImageType imageType,
2658 const struct VkOffset3D imageOffset)
2659 {
2660 switch (imageType) {
2661 case VK_IMAGE_TYPE_1D:
2662 return (VkOffset3D) { imageOffset.x, 0, 0 };
2663 case VK_IMAGE_TYPE_2D:
2664 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2665 case VK_IMAGE_TYPE_3D:
2666 return imageOffset;
2667 default:
2668 unreachable("invalid image type");
2669 }
2670 }
2671
2672
2673 void anv_fill_buffer_surface_state(struct anv_device *device,
2674 struct anv_state state,
2675 enum isl_format format,
2676 uint32_t offset, uint32_t range,
2677 uint32_t stride);
2678
2679
2680 struct anv_ycbcr_conversion {
2681 const struct anv_format * format;
2682 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2683 VkSamplerYcbcrRangeKHR ycbcr_range;
2684 VkComponentSwizzle mapping[4];
2685 VkChromaLocationKHR chroma_offsets[2];
2686 VkFilter chroma_filter;
2687 bool chroma_reconstruction;
2688 };
2689
2690 struct anv_sampler {
2691 uint32_t state[3][4];
2692 uint32_t n_planes;
2693 struct anv_ycbcr_conversion *conversion;
2694 };
2695
2696 struct anv_framebuffer {
2697 uint32_t width;
2698 uint32_t height;
2699 uint32_t layers;
2700
2701 uint32_t attachment_count;
2702 struct anv_image_view * attachments[0];
2703 };
2704
2705 struct anv_subpass {
2706 uint32_t attachment_count;
2707
2708 /**
2709 * A pointer to all attachment references used in this subpass.
2710 * Only valid if ::attachment_count > 0.
2711 */
2712 VkAttachmentReference * attachments;
2713 uint32_t input_count;
2714 VkAttachmentReference * input_attachments;
2715 uint32_t color_count;
2716 VkAttachmentReference * color_attachments;
2717 VkAttachmentReference * resolve_attachments;
2718
2719 VkAttachmentReference depth_stencil_attachment;
2720
2721 uint32_t view_mask;
2722
2723 /** Subpass has a depth/stencil self-dependency */
2724 bool has_ds_self_dep;
2725
2726 /** Subpass has at least one resolve attachment */
2727 bool has_resolve;
2728 };
2729
2730 static inline unsigned
2731 anv_subpass_view_count(const struct anv_subpass *subpass)
2732 {
2733 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2734 }
2735
2736 struct anv_render_pass_attachment {
2737 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2738 * its members individually.
2739 */
2740 VkFormat format;
2741 uint32_t samples;
2742 VkImageUsageFlags usage;
2743 VkAttachmentLoadOp load_op;
2744 VkAttachmentStoreOp store_op;
2745 VkAttachmentLoadOp stencil_load_op;
2746 VkImageLayout initial_layout;
2747 VkImageLayout final_layout;
2748 VkImageLayout first_subpass_layout;
2749
2750 /* The subpass id in which the attachment will be used last. */
2751 uint32_t last_subpass_idx;
2752 };
2753
2754 struct anv_render_pass {
2755 uint32_t attachment_count;
2756 uint32_t subpass_count;
2757 /* An array of subpass_count+1 flushes, one per subpass boundary */
2758 enum anv_pipe_bits * subpass_flushes;
2759 struct anv_render_pass_attachment * attachments;
2760 struct anv_subpass subpasses[0];
2761 };
2762
2763 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2764
2765 struct anv_query_pool {
2766 VkQueryType type;
2767 VkQueryPipelineStatisticFlags pipeline_statistics;
2768 /** Stride between slots, in bytes */
2769 uint32_t stride;
2770 /** Number of slots in this query pool */
2771 uint32_t slots;
2772 struct anv_bo bo;
2773 };
2774
2775 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2776 const char *name);
2777
2778 void anv_dump_image_to_ppm(struct anv_device *device,
2779 struct anv_image *image, unsigned miplevel,
2780 unsigned array_layer, VkImageAspectFlagBits aspect,
2781 const char *filename);
2782
2783 enum anv_dump_action {
2784 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2785 };
2786
2787 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2788 void anv_dump_finish(void);
2789
2790 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2791 struct anv_framebuffer *fb);
2792
2793 static inline uint32_t
2794 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2795 {
2796 /* This function must be called from within a subpass. */
2797 assert(cmd_state->pass && cmd_state->subpass);
2798
2799 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2800
2801 /* The id of this subpass shouldn't exceed the number of subpasses in this
2802 * render pass minus 1.
2803 */
2804 assert(subpass_id < cmd_state->pass->subpass_count);
2805 return subpass_id;
2806 }
2807
2808 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2809 \
2810 static inline struct __anv_type * \
2811 __anv_type ## _from_handle(__VkType _handle) \
2812 { \
2813 return (struct __anv_type *) _handle; \
2814 } \
2815 \
2816 static inline __VkType \
2817 __anv_type ## _to_handle(struct __anv_type *_obj) \
2818 { \
2819 return (__VkType) _obj; \
2820 }
2821
2822 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2823 \
2824 static inline struct __anv_type * \
2825 __anv_type ## _from_handle(__VkType _handle) \
2826 { \
2827 return (struct __anv_type *)(uintptr_t) _handle; \
2828 } \
2829 \
2830 static inline __VkType \
2831 __anv_type ## _to_handle(struct __anv_type *_obj) \
2832 { \
2833 return (__VkType)(uintptr_t) _obj; \
2834 }
2835
2836 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2837 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2838
2839 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2840 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2841 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2842 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2843 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2844
2845 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2846 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2847 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2848 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2849 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2850 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2851 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2852 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2853 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2854 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2855 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2856 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2857 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2858 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2859 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2860 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2861 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2862 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2863 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2864 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2865 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2866 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_debug_report_callback, VkDebugReportCallbackEXT)
2867 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
2868
2869 /* Gen-specific function declarations */
2870 #ifdef genX
2871 # include "anv_genX.h"
2872 #else
2873 # define genX(x) gen7_##x
2874 # include "anv_genX.h"
2875 # undef genX
2876 # define genX(x) gen75_##x
2877 # include "anv_genX.h"
2878 # undef genX
2879 # define genX(x) gen8_##x
2880 # include "anv_genX.h"
2881 # undef genX
2882 # define genX(x) gen9_##x
2883 # include "anv_genX.h"
2884 # undef genX
2885 # define genX(x) gen10_##x
2886 # include "anv_genX.h"
2887 # undef genX
2888 #endif
2889
2890 #endif /* ANV_PRIVATE_H */