2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
54 /* Pre-declarations needed for WSI entrypoints */
57 typedef struct xcb_connection_t xcb_connection_t
;
58 typedef uint32_t xcb_visualid_t
;
59 typedef uint32_t xcb_window_t
;
62 struct anv_buffer_view
;
63 struct anv_image_view
;
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
71 #include "anv_entrypoints.h"
74 #include "common/gen_debug.h"
75 #include "wsi_common.h"
77 /* Allowing different clear colors requires us to perform a depth resolve at
78 * the end of certain render passes. This is because while slow clears store
79 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
80 * See the PRMs for examples describing when additional resolves would be
81 * necessary. To enable fast clears without requiring extra resolves, we set
82 * the clear value to a globally-defined one. We could allow different values
83 * if the user doesn't expect coherent data during or after a render passes
84 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
85 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
86 * 1.0f seems to be the only value used. The only application that doesn't set
87 * this value does so through the usage of an seemingly uninitialized clear
90 #define ANV_HZ_FC_VAL 1.0f
95 #define MAX_VIEWPORTS 16
96 #define MAX_SCISSORS 16
97 #define MAX_PUSH_CONSTANTS_SIZE 128
98 #define MAX_DYNAMIC_BUFFERS 16
100 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
102 #define ANV_SVGS_VB_INDEX MAX_VBS
103 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
105 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
107 static inline uint32_t
108 align_down_npot_u32(uint32_t v
, uint32_t a
)
113 static inline uint32_t
114 align_u32(uint32_t v
, uint32_t a
)
116 assert(a
!= 0 && a
== (a
& -a
));
117 return (v
+ a
- 1) & ~(a
- 1);
120 static inline uint64_t
121 align_u64(uint64_t v
, uint64_t a
)
123 assert(a
!= 0 && a
== (a
& -a
));
124 return (v
+ a
- 1) & ~(a
- 1);
127 static inline int32_t
128 align_i32(int32_t v
, int32_t a
)
130 assert(a
!= 0 && a
== (a
& -a
));
131 return (v
+ a
- 1) & ~(a
- 1);
134 /** Alignment must be a power of 2. */
136 anv_is_aligned(uintmax_t n
, uintmax_t a
)
138 assert(a
== (a
& -a
));
139 return (n
& (a
- 1)) == 0;
142 static inline uint32_t
143 anv_minify(uint32_t n
, uint32_t levels
)
145 if (unlikely(n
== 0))
148 return MAX2(n
>> levels
, 1);
152 anv_clamp_f(float f
, float min
, float max
)
165 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
167 if (*inout_mask
& clear_mask
) {
168 *inout_mask
&= ~clear_mask
;
175 static inline union isl_color_value
176 vk_to_isl_color(VkClearColorValue color
)
178 return (union isl_color_value
) {
188 #define for_each_bit(b, dword) \
189 for (uint32_t __dword = (dword); \
190 (b) = __builtin_ffs(__dword) - 1, __dword; \
191 __dword &= ~(1 << (b)))
193 #define typed_memcpy(dest, src, count) ({ \
194 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
195 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 /* Whenever we generate an error, pass it through this function. Useful for
199 * debugging, where we can break on it. Only call at error site, not when
200 * propagating errors. Might be useful to plug in a stack trace here.
203 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
206 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
207 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
210 #define vk_error(error) error
211 #define vk_errorf(error, format, ...) error
212 #define anv_debug(format, ...)
216 * Warn on ignored extension structs.
218 * The Vulkan spec requires us to ignore unsupported or unknown structs in
219 * a pNext chain. In debug mode, emitting warnings for ignored structs may
220 * help us discover structs that we should not have ignored.
223 * From the Vulkan 1.0.38 spec:
225 * Any component of the implementation (the loader, any enabled layers,
226 * and drivers) must skip over, without processing (other than reading the
227 * sType and pNext members) any chained structures with sType values not
228 * defined by extensions supported by that component.
230 #define anv_debug_ignored_stype(sType) \
231 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
233 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
234 anv_printflike(3, 4);
235 void __anv_perf_warn(const char *file
, int line
, const char *format
, ...)
236 anv_printflike(3, 4);
237 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
238 void anv_loge_v(const char *format
, va_list va
);
241 * Print a FINISHME message, including its source location.
243 #define anv_finishme(format, ...) \
245 static bool reported = false; \
247 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
253 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
255 #define anv_perf_warn(format, ...) \
257 static bool reported = false; \
258 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
259 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
264 /* A non-fatal assert. Useful for debugging. */
266 #define anv_assert(x) ({ \
267 if (unlikely(!(x))) \
268 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 #define anv_assert(x)
274 /* A multi-pointer allocator
276 * When copying data structures from the user (such as a render pass), it's
277 * common to need to allocate data for a bunch of different things. Instead
278 * of doing several allocations and having to handle all of the error checking
279 * that entails, it can be easier to do a single allocation. This struct
280 * helps facilitate that. The intended usage looks like this:
283 * anv_multialloc_add(&ma, &main_ptr, 1);
284 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
285 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
287 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
288 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
290 struct anv_multialloc
{
298 #define ANV_MULTIALLOC_INIT \
299 ((struct anv_multialloc) { 0, })
301 #define ANV_MULTIALLOC(_name) \
302 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
304 __attribute__((always_inline
))
306 _anv_multialloc_add(struct anv_multialloc
*ma
,
307 void **ptr
, size_t size
, size_t align
)
309 size_t offset
= align_u64(ma
->size
, align
);
310 ma
->size
= offset
+ size
;
311 ma
->align
= MAX2(ma
->align
, align
);
313 /* Store the offset in the pointer. */
314 *ptr
= (void *)(uintptr_t)offset
;
316 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
317 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
320 #define anv_multialloc_add(_ma, _ptr, _count) \
321 _anv_multialloc_add((_ma), (void **)(_ptr), \
322 (_count) * sizeof(**(_ptr)), __alignof__(**(_ptr)))
324 __attribute__((always_inline
))
326 anv_multialloc_alloc(struct anv_multialloc
*ma
,
327 const VkAllocationCallbacks
*alloc
,
328 VkSystemAllocationScope scope
)
330 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
334 /* Fill out each of the pointers with their final value.
336 * for (uint32_t i = 0; i < ma->ptr_count; i++)
337 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
339 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
340 * constant, GCC is incapable of figuring this out and unrolling the loop
341 * so we have to give it a little help.
343 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
344 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
345 if ((_i) < ma->ptr_count) \
346 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
347 _ANV_MULTIALLOC_UPDATE_POINTER(0);
348 _ANV_MULTIALLOC_UPDATE_POINTER(1);
349 _ANV_MULTIALLOC_UPDATE_POINTER(2);
350 _ANV_MULTIALLOC_UPDATE_POINTER(3);
351 _ANV_MULTIALLOC_UPDATE_POINTER(4);
352 _ANV_MULTIALLOC_UPDATE_POINTER(5);
353 _ANV_MULTIALLOC_UPDATE_POINTER(6);
354 _ANV_MULTIALLOC_UPDATE_POINTER(7);
355 #undef _ANV_MULTIALLOC_UPDATE_POINTER
360 __attribute__((always_inline
))
362 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
363 const VkAllocationCallbacks
*parent_alloc
,
364 const VkAllocationCallbacks
*alloc
,
365 VkSystemAllocationScope scope
)
367 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
373 /* Index into the current validation list. This is used by the
374 * validation list building alrogithm to track which buffers are already
375 * in the validation list so that we can ensure uniqueness.
379 /* Last known offset. This value is provided by the kernel when we
380 * execbuf and is used as the presumed offset for the next bunch of
388 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
393 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
395 bo
->gem_handle
= gem_handle
;
403 /* Represents a lock-free linked list of "free" things. This is used by
404 * both the block pool and the state pools. Unfortunately, in order to
405 * solve the ABA problem, we can't use a single uint32_t head.
407 union anv_free_list
{
411 /* A simple count that is incremented every time the head changes. */
417 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
419 struct anv_block_state
{
429 struct anv_block_pool
{
430 struct anv_device
*device
;
434 /* The offset from the start of the bo to the "center" of the block
435 * pool. Pointers to allocated blocks are given by
436 * bo.map + center_bo_offset + offsets.
438 uint32_t center_bo_offset
;
440 /* Current memory map of the block pool. This pointer may or may not
441 * point to the actual beginning of the block pool memory. If
442 * anv_block_pool_alloc_back has ever been called, then this pointer
443 * will point to the "center" position of the buffer and all offsets
444 * (negative or positive) given out by the block pool alloc functions
445 * will be valid relative to this pointer.
447 * In particular, map == bo.map + center_offset
453 * Array of mmaps and gem handles owned by the block pool, reclaimed when
454 * the block pool is destroyed.
456 struct u_vector mmap_cleanups
;
458 struct anv_block_state state
;
460 struct anv_block_state back_state
;
463 /* Block pools are backed by a fixed-size 1GB memfd */
464 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
466 /* The center of the block pool is also the middle of the memfd. This may
467 * change in the future if we decide differently for some reason.
469 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
471 static inline uint32_t
472 anv_block_pool_size(struct anv_block_pool
*pool
)
474 return pool
->state
.end
+ pool
->back_state
.end
;
483 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
485 struct anv_fixed_size_state_pool
{
486 union anv_free_list free_list
;
487 struct anv_block_state block
;
490 #define ANV_MIN_STATE_SIZE_LOG2 6
491 #define ANV_MAX_STATE_SIZE_LOG2 20
493 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
495 struct anv_state_pool
{
496 struct anv_block_pool block_pool
;
498 /* The size of blocks which will be allocated from the block pool */
501 /** Free list for "back" allocations */
502 union anv_free_list back_alloc_free_list
;
504 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
507 struct anv_state_stream_block
;
509 struct anv_state_stream
{
510 struct anv_state_pool
*state_pool
;
512 /* The size of blocks to allocate from the state pool */
515 /* Current block we're allocating from */
516 struct anv_state block
;
518 /* Offset into the current block at which to allocate the next state */
521 /* List of all blocks allocated from this pool */
522 struct anv_state_stream_block
*block_list
;
525 /* The block_pool functions exported for testing only. The block pool should
526 * only be used via a state pool (see below).
528 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
529 struct anv_device
*device
,
530 uint32_t initial_size
);
531 void anv_block_pool_finish(struct anv_block_pool
*pool
);
532 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
533 uint32_t block_size
);
534 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
535 uint32_t block_size
);
537 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
538 struct anv_device
*device
,
539 uint32_t block_size
);
540 void anv_state_pool_finish(struct anv_state_pool
*pool
);
541 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
542 uint32_t state_size
, uint32_t alignment
);
543 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
544 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
545 void anv_state_stream_init(struct anv_state_stream
*stream
,
546 struct anv_state_pool
*state_pool
,
547 uint32_t block_size
);
548 void anv_state_stream_finish(struct anv_state_stream
*stream
);
549 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
550 uint32_t size
, uint32_t alignment
);
553 * Implements a pool of re-usable BOs. The interface is identical to that
554 * of block_pool except that each block is its own BO.
557 struct anv_device
*device
;
562 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
563 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
564 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
566 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
568 struct anv_scratch_bo
{
573 struct anv_scratch_pool
{
574 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
575 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
578 void anv_scratch_pool_init(struct anv_device
*device
,
579 struct anv_scratch_pool
*pool
);
580 void anv_scratch_pool_finish(struct anv_device
*device
,
581 struct anv_scratch_pool
*pool
);
582 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
583 struct anv_scratch_pool
*pool
,
584 gl_shader_stage stage
,
585 unsigned per_thread_scratch
);
587 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
588 struct anv_bo_cache
{
589 struct hash_table
*bo_map
;
590 pthread_mutex_t mutex
;
593 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
594 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
595 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
596 struct anv_bo_cache
*cache
,
597 uint64_t size
, struct anv_bo
**bo
);
598 VkResult
anv_bo_cache_import(struct anv_device
*device
,
599 struct anv_bo_cache
*cache
,
600 int fd
, uint64_t size
, struct anv_bo
**bo
);
601 VkResult
anv_bo_cache_export(struct anv_device
*device
,
602 struct anv_bo_cache
*cache
,
603 struct anv_bo
*bo_in
, int *fd_out
);
604 void anv_bo_cache_release(struct anv_device
*device
,
605 struct anv_bo_cache
*cache
,
608 struct anv_memory_type
{
609 /* Standard bits passed on to the client */
610 VkMemoryPropertyFlags propertyFlags
;
613 /* Driver-internal book-keeping */
614 VkBufferUsageFlags valid_buffer_usage
;
617 struct anv_memory_heap
{
618 /* Standard bits passed on to the client */
620 VkMemoryHeapFlags flags
;
622 /* Driver-internal book-keeping */
623 bool supports_48bit_addresses
;
626 struct anv_physical_device
{
627 VK_LOADER_DATA _loader_data
;
629 struct anv_instance
* instance
;
633 struct gen_device_info info
;
634 /** Amount of "GPU memory" we want to advertise
636 * Clearly, this value is bogus since Intel is a UMA architecture. On
637 * gen7 platforms, we are limited by GTT size unless we want to implement
638 * fine-grained tracking and GTT splitting. On Broadwell and above we are
639 * practically unlimited. However, we will never report more than 3/4 of
640 * the total system ram to try and avoid running out of RAM.
642 bool supports_48bit_addresses
;
643 struct brw_compiler
* compiler
;
644 struct isl_device isl_dev
;
645 int cmd_parser_version
;
651 uint32_t subslice_total
;
655 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
657 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
660 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
661 uint8_t driver_uuid
[VK_UUID_SIZE
];
662 uint8_t device_uuid
[VK_UUID_SIZE
];
664 struct wsi_device wsi_device
;
668 struct anv_instance
{
669 VK_LOADER_DATA _loader_data
;
671 VkAllocationCallbacks alloc
;
674 int physicalDeviceCount
;
675 struct anv_physical_device physicalDevice
;
678 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
679 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
681 bool anv_instance_extension_supported(const char *name
);
682 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
683 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
687 VK_LOADER_DATA _loader_data
;
689 struct anv_device
* device
;
691 struct anv_state_pool
* pool
;
694 struct anv_pipeline_cache
{
695 struct anv_device
* device
;
696 pthread_mutex_t mutex
;
698 struct hash_table
* cache
;
701 struct anv_pipeline_bind_map
;
703 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
704 struct anv_device
*device
,
706 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
708 struct anv_shader_bin
*
709 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
710 const void *key
, uint32_t key_size
);
711 struct anv_shader_bin
*
712 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
713 const void *key_data
, uint32_t key_size
,
714 const void *kernel_data
, uint32_t kernel_size
,
715 const struct brw_stage_prog_data
*prog_data
,
716 uint32_t prog_data_size
,
717 const struct anv_pipeline_bind_map
*bind_map
);
720 VK_LOADER_DATA _loader_data
;
722 VkAllocationCallbacks alloc
;
724 struct anv_instance
* instance
;
726 struct gen_device_info info
;
727 struct isl_device isl_dev
;
730 bool can_chain_batches
;
731 bool robust_buffer_access
;
733 struct anv_bo_pool batch_bo_pool
;
735 struct anv_bo_cache bo_cache
;
737 struct anv_state_pool dynamic_state_pool
;
738 struct anv_state_pool instruction_state_pool
;
739 struct anv_state_pool surface_state_pool
;
741 struct anv_bo workaround_bo
;
742 struct anv_bo trivial_batch_bo
;
744 struct anv_pipeline_cache blorp_shader_cache
;
745 struct blorp_context blorp
;
747 struct anv_state border_colors
;
749 struct anv_queue queue
;
751 struct anv_scratch_pool scratch_pool
;
753 uint32_t default_mocs
;
755 pthread_mutex_t mutex
;
756 pthread_cond_t queue_submit
;
761 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
763 if (device
->info
.has_llc
)
766 gen_flush_range(state
.map
, state
.alloc_size
);
769 void anv_device_init_blorp(struct anv_device
*device
);
770 void anv_device_finish_blorp(struct anv_device
*device
);
772 VkResult
anv_device_execbuf(struct anv_device
*device
,
773 struct drm_i915_gem_execbuffer2
*execbuf
,
774 struct anv_bo
**execbuf_bos
);
775 VkResult
anv_device_query_status(struct anv_device
*device
);
776 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
777 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
780 void* anv_gem_mmap(struct anv_device
*device
,
781 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
782 void anv_gem_munmap(void *p
, uint64_t size
);
783 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
784 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
785 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
786 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
787 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
788 int anv_gem_execbuffer(struct anv_device
*device
,
789 struct drm_i915_gem_execbuffer2
*execbuf
);
790 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
791 uint32_t stride
, uint32_t tiling
);
792 int anv_gem_create_context(struct anv_device
*device
);
793 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
794 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
796 int anv_gem_get_param(int fd
, uint32_t param
);
797 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
798 int anv_gem_get_aperture(int fd
, uint64_t *size
);
799 bool anv_gem_supports_48b_addresses(int fd
);
800 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
801 uint32_t *active
, uint32_t *pending
);
802 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
803 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
804 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
805 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
806 uint32_t read_domains
, uint32_t write_domain
);
807 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
808 uint32_t anv_gem_syncobj_create(struct anv_device
*device
);
809 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
810 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
811 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
813 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
815 struct anv_reloc_list
{
817 uint32_t array_length
;
818 struct drm_i915_gem_relocation_entry
* relocs
;
819 struct anv_bo
** reloc_bos
;
822 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
823 const VkAllocationCallbacks
*alloc
);
824 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
825 const VkAllocationCallbacks
*alloc
);
827 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
828 const VkAllocationCallbacks
*alloc
,
829 uint32_t offset
, struct anv_bo
*target_bo
,
832 struct anv_batch_bo
{
833 /* Link in the anv_cmd_buffer.owned_batch_bos list */
834 struct list_head link
;
838 /* Bytes actually consumed in this batch BO */
841 struct anv_reloc_list relocs
;
845 const VkAllocationCallbacks
* alloc
;
851 struct anv_reloc_list
* relocs
;
853 /* This callback is called (with the associated user data) in the event
854 * that the batch runs out of space.
856 VkResult (*extend_cb
)(struct anv_batch
*, void *);
860 * Current error status of the command buffer. Used to track inconsistent
861 * or incomplete command buffer states that are the consequence of run-time
862 * errors such as out of memory scenarios. We want to track this in the
863 * batch because the command buffer object is not visible to some parts
869 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
870 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
871 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
872 void *location
, struct anv_bo
*bo
, uint32_t offset
);
873 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
874 struct anv_batch
*batch
);
876 static inline VkResult
877 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
879 assert(error
!= VK_SUCCESS
);
880 if (batch
->status
== VK_SUCCESS
)
881 batch
->status
= error
;
882 return batch
->status
;
886 anv_batch_has_error(struct anv_batch
*batch
)
888 return batch
->status
!= VK_SUCCESS
;
896 static inline uint64_t
897 _anv_combine_address(struct anv_batch
*batch
, void *location
,
898 const struct anv_address address
, uint32_t delta
)
900 if (address
.bo
== NULL
) {
901 return address
.offset
+ delta
;
903 assert(batch
->start
<= location
&& location
< batch
->end
);
905 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
909 #define __gen_address_type struct anv_address
910 #define __gen_user_data struct anv_batch
911 #define __gen_combine_address _anv_combine_address
913 /* Wrapper macros needed to work around preprocessor argument issues. In
914 * particular, arguments don't get pre-evaluated if they are concatenated.
915 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
916 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
917 * We can work around this easily enough with these helpers.
919 #define __anv_cmd_length(cmd) cmd ## _length
920 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
921 #define __anv_cmd_header(cmd) cmd ## _header
922 #define __anv_cmd_pack(cmd) cmd ## _pack
923 #define __anv_reg_num(reg) reg ## _num
925 #define anv_pack_struct(dst, struc, ...) do { \
926 struct struc __template = { \
929 __anv_cmd_pack(struc)(NULL, dst, &__template); \
930 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
933 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
934 void *__dst = anv_batch_emit_dwords(batch, n); \
936 struct cmd __template = { \
937 __anv_cmd_header(cmd), \
938 .DWordLength = n - __anv_cmd_length_bias(cmd), \
941 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
946 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
950 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
951 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
954 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
955 dw[i] = (dwords0)[i] | (dwords1)[i]; \
956 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
959 #define anv_batch_emit(batch, cmd, name) \
960 for (struct cmd name = { __anv_cmd_header(cmd) }, \
961 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
962 __builtin_expect(_dst != NULL, 1); \
963 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
964 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
968 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
969 .GraphicsDataTypeGFDT = 0, \
970 .LLCCacheabilityControlLLCCC = 0, \
971 .L3CacheabilityControlL3CC = 1, \
974 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
975 .LLCeLLCCacheabilityControlLLCCC = 0, \
976 .L3CacheabilityControlL3CC = 1, \
979 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
980 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
981 .TargetCache = L3DefertoPATforLLCeLLCselection, \
985 /* Skylake: MOCS is now an index into an array of 62 different caching
986 * configurations programmed by the kernel.
989 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
990 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
991 .IndextoMOCSTables = 2 \
994 #define GEN9_MOCS_PTE { \
995 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
996 .IndextoMOCSTables = 1 \
999 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1000 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1001 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1002 .IndextoMOCSTables = 2 \
1005 #define GEN10_MOCS_PTE { \
1006 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1007 .IndextoMOCSTables = 1 \
1010 struct anv_device_memory
{
1012 struct anv_memory_type
* type
;
1013 VkDeviceSize map_size
;
1018 * Header for Vertex URB Entry (VUE)
1020 struct anv_vue_header
{
1022 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1023 uint32_t ViewportIndex
;
1027 struct anv_descriptor_set_binding_layout
{
1029 /* The type of the descriptors in this binding */
1030 VkDescriptorType type
;
1033 /* Number of array elements in this binding */
1034 uint16_t array_size
;
1036 /* Index into the flattend descriptor set */
1037 uint16_t descriptor_index
;
1039 /* Index into the dynamic state array for a dynamic buffer */
1040 int16_t dynamic_offset_index
;
1042 /* Index into the descriptor set buffer views */
1043 int16_t buffer_index
;
1046 /* Index into the binding table for the associated surface */
1047 int16_t surface_index
;
1049 /* Index into the sampler table for the associated sampler */
1050 int16_t sampler_index
;
1052 /* Index into the image table for the associated image */
1053 int16_t image_index
;
1054 } stage
[MESA_SHADER_STAGES
];
1056 /* Immutable samplers (or NULL if no immutable samplers) */
1057 struct anv_sampler
**immutable_samplers
;
1060 struct anv_descriptor_set_layout
{
1061 /* Number of bindings in this descriptor set */
1062 uint16_t binding_count
;
1064 /* Total size of the descriptor set with room for all array entries */
1067 /* Shader stages affected by this descriptor set */
1068 uint16_t shader_stages
;
1070 /* Number of buffers in this descriptor set */
1071 uint16_t buffer_count
;
1073 /* Number of dynamic offsets used by this descriptor set */
1074 uint16_t dynamic_offset_count
;
1076 /* Bindings in this descriptor set */
1077 struct anv_descriptor_set_binding_layout binding
[0];
1080 struct anv_descriptor
{
1081 VkDescriptorType type
;
1085 VkImageLayout layout
;
1086 struct anv_image_view
*image_view
;
1087 struct anv_sampler
*sampler
;
1091 struct anv_buffer
*buffer
;
1096 struct anv_buffer_view
*buffer_view
;
1100 struct anv_descriptor_set
{
1101 const struct anv_descriptor_set_layout
*layout
;
1103 uint32_t buffer_count
;
1104 struct anv_buffer_view
*buffer_views
;
1105 struct anv_descriptor descriptors
[0];
1108 struct anv_buffer_view
{
1109 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1111 uint32_t offset
; /**< Offset into bo. */
1112 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1114 struct anv_state surface_state
;
1115 struct anv_state storage_surface_state
;
1116 struct anv_state writeonly_storage_surface_state
;
1118 struct brw_image_param storage_image_param
;
1121 struct anv_push_descriptor_set
{
1122 struct anv_descriptor_set set
;
1124 /* Put this field right behind anv_descriptor_set so it fills up the
1125 * descriptors[0] field. */
1126 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1128 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1131 struct anv_descriptor_pool
{
1136 struct anv_state_stream surface_state_stream
;
1137 void *surface_state_free_list
;
1142 enum anv_descriptor_template_entry_type
{
1143 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1144 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1145 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1148 struct anv_descriptor_template_entry
{
1149 /* The type of descriptor in this entry */
1150 VkDescriptorType type
;
1152 /* Binding in the descriptor set */
1155 /* Offset at which to write into the descriptor set binding */
1156 uint32_t array_element
;
1158 /* Number of elements to write into the descriptor set binding */
1159 uint32_t array_count
;
1161 /* Offset into the user provided data */
1164 /* Stride between elements into the user provided data */
1168 struct anv_descriptor_update_template
{
1169 /* The descriptor set this template corresponds to. This value is only
1170 * valid if the template was created with the templateType
1171 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1175 /* Number of entries in this template */
1176 uint32_t entry_count
;
1178 /* Entries of the template */
1179 struct anv_descriptor_template_entry entries
[0];
1183 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1186 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1187 const struct gen_device_info
* const devinfo
,
1188 const VkDescriptorImageInfo
* const info
,
1189 VkDescriptorType type
,
1194 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1195 VkDescriptorType type
,
1196 struct anv_buffer_view
*buffer_view
,
1201 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1202 struct anv_device
*device
,
1203 struct anv_state_stream
*alloc_stream
,
1204 VkDescriptorType type
,
1205 struct anv_buffer
*buffer
,
1208 VkDeviceSize offset
,
1209 VkDeviceSize range
);
1212 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1213 struct anv_device
*device
,
1214 struct anv_state_stream
*alloc_stream
,
1215 const struct anv_descriptor_update_template
*template,
1219 anv_descriptor_set_create(struct anv_device
*device
,
1220 struct anv_descriptor_pool
*pool
,
1221 const struct anv_descriptor_set_layout
*layout
,
1222 struct anv_descriptor_set
**out_set
);
1225 anv_descriptor_set_destroy(struct anv_device
*device
,
1226 struct anv_descriptor_pool
*pool
,
1227 struct anv_descriptor_set
*set
);
1229 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1231 struct anv_pipeline_binding
{
1232 /* The descriptor set this surface corresponds to. The special value of
1233 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1234 * to a color attachment and not a regular descriptor.
1238 /* Binding in the descriptor set */
1241 /* Index in the binding */
1244 /* Input attachment index (relative to the subpass) */
1245 uint8_t input_attachment_index
;
1247 /* For a storage image, whether it is write-only */
1251 struct anv_pipeline_layout
{
1253 struct anv_descriptor_set_layout
*layout
;
1254 uint32_t dynamic_offset_start
;
1260 bool has_dynamic_offsets
;
1261 } stage
[MESA_SHADER_STAGES
];
1263 unsigned char sha1
[20];
1267 struct anv_device
* device
;
1270 VkBufferUsageFlags usage
;
1272 /* Set when bound */
1274 VkDeviceSize offset
;
1277 static inline uint64_t
1278 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1280 assert(offset
<= buffer
->size
);
1281 if (range
== VK_WHOLE_SIZE
) {
1282 return buffer
->size
- offset
;
1284 assert(range
<= buffer
->size
);
1289 enum anv_cmd_dirty_bits
{
1290 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1291 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1292 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1293 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1294 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1295 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1296 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1297 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1298 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1299 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1300 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1301 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1302 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1304 typedef uint32_t anv_cmd_dirty_mask_t
;
1306 enum anv_pipe_bits
{
1307 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1308 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1309 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1310 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1311 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1312 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1313 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1314 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1315 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1316 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1317 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1319 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1320 * a flush has happened but not a CS stall. The next time we do any sort
1321 * of invalidation we need to insert a CS stall at that time. Otherwise,
1322 * we would have to CS stall on every flush which could be bad.
1324 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1327 #define ANV_PIPE_FLUSH_BITS ( \
1328 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1329 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1330 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1332 #define ANV_PIPE_STALL_BITS ( \
1333 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1334 ANV_PIPE_DEPTH_STALL_BIT | \
1335 ANV_PIPE_CS_STALL_BIT)
1337 #define ANV_PIPE_INVALIDATE_BITS ( \
1338 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1339 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1340 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1341 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1342 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1343 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1345 static inline enum anv_pipe_bits
1346 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1348 enum anv_pipe_bits pipe_bits
= 0;
1351 for_each_bit(b
, flags
) {
1352 switch ((VkAccessFlagBits
)(1 << b
)) {
1353 case VK_ACCESS_SHADER_WRITE_BIT
:
1354 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1356 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1357 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1359 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1360 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1362 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1363 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1364 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1367 break; /* Nothing to do */
1374 static inline enum anv_pipe_bits
1375 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1377 enum anv_pipe_bits pipe_bits
= 0;
1380 for_each_bit(b
, flags
) {
1381 switch ((VkAccessFlagBits
)(1 << b
)) {
1382 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1383 case VK_ACCESS_INDEX_READ_BIT
:
1384 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1385 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1387 case VK_ACCESS_UNIFORM_READ_BIT
:
1388 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1389 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1391 case VK_ACCESS_SHADER_READ_BIT
:
1392 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1393 case VK_ACCESS_TRANSFER_READ_BIT
:
1394 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1397 break; /* Nothing to do */
1404 struct anv_vertex_binding
{
1405 struct anv_buffer
* buffer
;
1406 VkDeviceSize offset
;
1409 struct anv_push_constants
{
1410 /* Current allocated size of this push constants data structure.
1411 * Because a decent chunk of it may not be used (images on SKL, for
1412 * instance), we won't actually allocate the entire structure up-front.
1416 /* Push constant data provided by the client through vkPushConstants */
1417 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1419 /* Our hardware only provides zero-based vertex and instance id so, in
1420 * order to satisfy the vulkan requirements, we may have to push one or
1421 * both of these into the shader.
1423 uint32_t base_vertex
;
1424 uint32_t base_instance
;
1426 /* Image data for image_load_store on pre-SKL */
1427 struct brw_image_param images
[MAX_IMAGES
];
1430 struct anv_dynamic_state
{
1433 VkViewport viewports
[MAX_VIEWPORTS
];
1438 VkRect2D scissors
[MAX_SCISSORS
];
1449 float blend_constants
[4];
1459 } stencil_compare_mask
;
1464 } stencil_write_mask
;
1469 } stencil_reference
;
1472 extern const struct anv_dynamic_state default_dynamic_state
;
1474 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1475 const struct anv_dynamic_state
*src
,
1476 uint32_t copy_mask
);
1479 * Attachment state when recording a renderpass instance.
1481 * The clear value is valid only if there exists a pending clear.
1483 struct anv_attachment_state
{
1484 enum isl_aux_usage aux_usage
;
1485 enum isl_aux_usage input_aux_usage
;
1486 struct anv_state color_rt_state
;
1487 struct anv_state input_att_state
;
1489 VkImageLayout current_layout
;
1490 VkImageAspectFlags pending_clear_aspects
;
1492 VkClearValue clear_value
;
1493 bool clear_color_is_zero_one
;
1494 bool clear_color_is_zero
;
1497 /** State required while building cmd buffer */
1498 struct anv_cmd_state
{
1499 /* PIPELINE_SELECT.PipelineSelection */
1500 uint32_t current_pipeline
;
1501 const struct gen_l3_config
* current_l3_config
;
1503 anv_cmd_dirty_mask_t dirty
;
1504 anv_cmd_dirty_mask_t compute_dirty
;
1505 enum anv_pipe_bits pending_pipe_bits
;
1506 uint32_t num_workgroups_offset
;
1507 struct anv_bo
*num_workgroups_bo
;
1508 VkShaderStageFlags descriptors_dirty
;
1509 VkShaderStageFlags push_constants_dirty
;
1510 uint32_t scratch_size
;
1511 struct anv_pipeline
* pipeline
;
1512 struct anv_pipeline
* compute_pipeline
;
1513 struct anv_framebuffer
* framebuffer
;
1514 struct anv_render_pass
* pass
;
1515 struct anv_subpass
* subpass
;
1516 VkRect2D render_area
;
1517 uint32_t restart_index
;
1518 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1519 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1520 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1521 VkShaderStageFlags push_constant_stages
;
1522 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1523 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1524 struct anv_state samplers
[MESA_SHADER_STAGES
];
1525 struct anv_dynamic_state dynamic
;
1528 struct anv_push_descriptor_set push_descriptor
;
1531 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1532 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1533 * and before invoking the secondary in ExecuteCommands.
1535 bool pma_fix_enabled
;
1538 * Whether or not we know for certain that HiZ is enabled for the current
1539 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1540 * enabled or not, this will be false.
1545 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1546 * valid only when recording a render pass instance.
1548 struct anv_attachment_state
* attachments
;
1551 * Surface states for color render targets. These are stored in a single
1552 * flat array. For depth-stencil attachments, the surface state is simply
1555 struct anv_state render_pass_states
;
1558 * A null surface state of the right size to match the framebuffer. This
1559 * is one of the states in render_pass_states.
1561 struct anv_state null_surface_state
;
1564 struct anv_buffer
* index_buffer
;
1565 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1566 uint32_t index_offset
;
1570 struct anv_cmd_pool
{
1571 VkAllocationCallbacks alloc
;
1572 struct list_head cmd_buffers
;
1575 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1577 enum anv_cmd_buffer_exec_mode
{
1578 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1579 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1580 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1581 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1582 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1585 struct anv_cmd_buffer
{
1586 VK_LOADER_DATA _loader_data
;
1588 struct anv_device
* device
;
1590 struct anv_cmd_pool
* pool
;
1591 struct list_head pool_link
;
1593 struct anv_batch batch
;
1595 /* Fields required for the actual chain of anv_batch_bo's.
1597 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1599 struct list_head batch_bos
;
1600 enum anv_cmd_buffer_exec_mode exec_mode
;
1602 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1603 * referenced by this command buffer
1605 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1607 struct u_vector seen_bbos
;
1609 /* A vector of int32_t's for every block of binding tables.
1611 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1613 struct u_vector bt_block_states
;
1616 struct anv_reloc_list surface_relocs
;
1617 /** Last seen surface state block pool center bo offset */
1618 uint32_t last_ss_pool_center
;
1620 /* Serial for tracking buffer completion */
1623 /* Stream objects for storing temporary data */
1624 struct anv_state_stream surface_state_stream
;
1625 struct anv_state_stream dynamic_state_stream
;
1627 VkCommandBufferUsageFlags usage_flags
;
1628 VkCommandBufferLevel level
;
1630 struct anv_cmd_state state
;
1633 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1634 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1635 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1636 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1637 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1638 struct anv_cmd_buffer
*secondary
);
1639 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1640 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1641 struct anv_cmd_buffer
*cmd_buffer
,
1642 const VkSemaphore
*in_semaphores
,
1643 uint32_t num_in_semaphores
,
1644 const VkSemaphore
*out_semaphores
,
1645 uint32_t num_out_semaphores
,
1648 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1651 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1652 gl_shader_stage stage
, uint32_t size
);
1653 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1654 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1655 (offsetof(struct anv_push_constants, field) + \
1656 sizeof(cmd_buffer->state.push_constants[0]->field)))
1658 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1659 const void *data
, uint32_t size
, uint32_t alignment
);
1660 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1661 uint32_t *a
, uint32_t *b
,
1662 uint32_t dwords
, uint32_t alignment
);
1665 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1667 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1668 uint32_t entries
, uint32_t *state_offset
);
1670 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1672 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1673 uint32_t size
, uint32_t alignment
);
1676 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1678 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1679 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1680 bool depth_clamp_enable
);
1681 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1683 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1684 struct anv_render_pass
*pass
,
1685 struct anv_framebuffer
*framebuffer
,
1686 const VkClearValue
*clear_values
);
1688 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1691 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1692 gl_shader_stage stage
);
1694 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1696 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1697 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1699 const struct anv_image_view
*
1700 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1703 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1704 uint32_t num_entries
,
1705 uint32_t *state_offset
,
1706 struct anv_state
*bt_state
);
1708 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1710 enum anv_fence_type
{
1711 ANV_FENCE_TYPE_NONE
= 0,
1713 ANV_FENCE_TYPE_SYNCOBJ
,
1716 enum anv_bo_fence_state
{
1717 /** Indicates that this is a new (or newly reset fence) */
1718 ANV_BO_FENCE_STATE_RESET
,
1720 /** Indicates that this fence has been submitted to the GPU but is still
1721 * (as far as we know) in use by the GPU.
1723 ANV_BO_FENCE_STATE_SUBMITTED
,
1725 ANV_BO_FENCE_STATE_SIGNALED
,
1728 struct anv_fence_impl
{
1729 enum anv_fence_type type
;
1732 /** Fence implementation for BO fences
1734 * These fences use a BO and a set of CPU-tracked state flags. The BO
1735 * is added to the object list of the last execbuf call in a QueueSubmit
1736 * and is marked EXEC_WRITE. The state flags track when the BO has been
1737 * submitted to the kernel. We need to do this because Vulkan lets you
1738 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1739 * will say it's idle in this case.
1743 enum anv_bo_fence_state state
;
1749 /* Permanent fence state. Every fence has some form of permanent state
1750 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1751 * cross-process fences0 or it could just be a dummy for use internally.
1753 struct anv_fence_impl permanent
;
1755 /* Temporary fence state. A fence *may* have temporary state. That state
1756 * is added to the fence by an import operation and is reset back to
1757 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1758 * state cannot be signaled because the fence must already be signaled
1759 * before the temporary state can be exported from the fence in the other
1760 * process and imported here.
1762 struct anv_fence_impl temporary
;
1767 struct anv_state state
;
1770 enum anv_semaphore_type
{
1771 ANV_SEMAPHORE_TYPE_NONE
= 0,
1772 ANV_SEMAPHORE_TYPE_DUMMY
,
1773 ANV_SEMAPHORE_TYPE_BO
,
1774 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
1775 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
1778 struct anv_semaphore_impl
{
1779 enum anv_semaphore_type type
;
1782 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1783 * This BO will be added to the object list on any execbuf2 calls for
1784 * which this semaphore is used as a wait or signal fence. When used as
1785 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1789 /* The sync file descriptor when type == AKV_SEMAPHORE_TYPE_SYNC_FILE.
1790 * If the semaphore is in the unsignaled state due to either just being
1791 * created or because it has been used for a wait, fd will be -1.
1795 /* Sync object handle when type == AKV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1796 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1797 * import so we don't need to bother with a userspace cache.
1803 struct anv_semaphore
{
1804 /* Permanent semaphore state. Every semaphore has some form of permanent
1805 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1806 * (for cross-process semaphores0 or it could just be a dummy for use
1809 struct anv_semaphore_impl permanent
;
1811 /* Temporary semaphore state. A semaphore *may* have temporary state.
1812 * That state is added to the semaphore by an import operation and is reset
1813 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1814 * semaphore with temporary state cannot be signaled because the semaphore
1815 * must already be signaled before the temporary state can be exported from
1816 * the semaphore in the other process and imported here.
1818 struct anv_semaphore_impl temporary
;
1821 void anv_semaphore_reset_temporary(struct anv_device
*device
,
1822 struct anv_semaphore
*semaphore
);
1824 struct anv_shader_module
{
1825 unsigned char sha1
[20];
1830 static inline gl_shader_stage
1831 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1833 assert(__builtin_popcount(vk_stage
) == 1);
1834 return ffs(vk_stage
) - 1;
1837 static inline VkShaderStageFlagBits
1838 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1840 return (1 << mesa_stage
);
1843 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1845 #define anv_foreach_stage(stage, stage_bits) \
1846 for (gl_shader_stage stage, \
1847 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1848 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1849 __tmp &= ~(1 << (stage)))
1851 struct anv_pipeline_bind_map
{
1852 uint32_t surface_count
;
1853 uint32_t sampler_count
;
1854 uint32_t image_count
;
1856 struct anv_pipeline_binding
* surface_to_descriptor
;
1857 struct anv_pipeline_binding
* sampler_to_descriptor
;
1860 struct anv_shader_bin_key
{
1865 struct anv_shader_bin
{
1868 const struct anv_shader_bin_key
*key
;
1870 struct anv_state kernel
;
1871 uint32_t kernel_size
;
1873 const struct brw_stage_prog_data
*prog_data
;
1874 uint32_t prog_data_size
;
1876 struct anv_pipeline_bind_map bind_map
;
1878 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1881 struct anv_shader_bin
*
1882 anv_shader_bin_create(struct anv_device
*device
,
1883 const void *key
, uint32_t key_size
,
1884 const void *kernel
, uint32_t kernel_size
,
1885 const struct brw_stage_prog_data
*prog_data
,
1886 uint32_t prog_data_size
, const void *prog_data_param
,
1887 const struct anv_pipeline_bind_map
*bind_map
);
1890 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1893 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1895 assert(shader
&& shader
->ref_cnt
>= 1);
1896 p_atomic_inc(&shader
->ref_cnt
);
1900 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1902 assert(shader
&& shader
->ref_cnt
>= 1);
1903 if (p_atomic_dec_zero(&shader
->ref_cnt
))
1904 anv_shader_bin_destroy(device
, shader
);
1907 struct anv_pipeline
{
1908 struct anv_device
* device
;
1909 struct anv_batch batch
;
1910 uint32_t batch_data
[512];
1911 struct anv_reloc_list batch_relocs
;
1912 uint32_t dynamic_state_mask
;
1913 struct anv_dynamic_state dynamic_state
;
1915 struct anv_subpass
* subpass
;
1916 struct anv_pipeline_layout
* layout
;
1918 bool needs_data_cache
;
1920 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1923 const struct gen_l3_config
* l3_config
;
1924 uint32_t total_size
;
1927 VkShaderStageFlags active_stages
;
1928 struct anv_state blend_state
;
1931 uint32_t binding_stride
[MAX_VBS
];
1932 bool instancing_enable
[MAX_VBS
];
1933 bool primitive_restart
;
1936 uint32_t cs_right_mask
;
1939 bool depth_test_enable
;
1940 bool writes_stencil
;
1941 bool stencil_test_enable
;
1942 bool depth_clamp_enable
;
1943 bool sample_shading_enable
;
1948 uint32_t depth_stencil_state
[3];
1954 uint32_t wm_depth_stencil
[3];
1958 uint32_t wm_depth_stencil
[4];
1961 uint32_t interface_descriptor_data
[8];
1965 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1966 gl_shader_stage stage
)
1968 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1971 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1972 static inline const struct brw_##prefix##_prog_data * \
1973 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1975 if (anv_pipeline_has_stage(pipeline, stage)) { \
1976 return (const struct brw_##prefix##_prog_data *) \
1977 pipeline->shaders[stage]->prog_data; \
1983 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1984 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1985 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1986 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1987 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1988 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1990 static inline const struct brw_vue_prog_data
*
1991 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1993 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1994 return &get_gs_prog_data(pipeline
)->base
;
1995 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1996 return &get_tes_prog_data(pipeline
)->base
;
1998 return &get_vs_prog_data(pipeline
)->base
;
2002 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2003 struct anv_pipeline_cache
*cache
,
2004 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2005 const VkAllocationCallbacks
*alloc
);
2008 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2009 struct anv_pipeline_cache
*cache
,
2010 const VkComputePipelineCreateInfo
*info
,
2011 struct anv_shader_module
*module
,
2012 const char *entrypoint
,
2013 const VkSpecializationInfo
*spec_info
);
2016 enum isl_format isl_format
:16;
2017 struct isl_swizzle swizzle
;
2021 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
2022 VkImageAspectFlags aspect
, VkImageTiling tiling
);
2024 static inline enum isl_format
2025 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2026 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2028 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2031 static inline struct isl_swizzle
2032 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2034 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2035 * RGB as RGBA for texturing
2037 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2038 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2040 /* But it doesn't matter what we render to that channel */
2041 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2047 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2050 * Subsurface of an anv_image.
2052 struct anv_surface
{
2053 /** Valid only if isl_surf::size > 0. */
2054 struct isl_surf isl
;
2057 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2064 /* The original VkFormat provided by the client. This may not match any
2065 * of the actual surface formats.
2068 VkImageAspectFlags aspects
;
2071 uint32_t array_size
;
2072 uint32_t samples
; /**< VkImageCreateInfo::samples */
2073 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2074 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2079 /* Set when bound */
2081 VkDeviceSize offset
;
2086 * For each foo, anv_image::foo_surface is valid if and only if
2087 * anv_image::aspects has a foo aspect.
2089 * The hardware requires that the depth buffer and stencil buffer be
2090 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2091 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2092 * allocate the depth and stencil buffers as separate surfaces in the same
2096 struct anv_surface color_surface
;
2099 struct anv_surface depth_surface
;
2100 struct anv_surface stencil_surface
;
2105 * For color images, this is the aux usage for this image when not used as a
2108 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
2111 enum isl_aux_usage aux_usage
;
2113 struct anv_surface aux_surface
;
2116 /* Returns the number of auxiliary buffer levels attached to an image. */
2117 static inline uint8_t
2118 anv_image_aux_levels(const struct anv_image
* const image
)
2121 return image
->aux_surface
.isl
.size
> 0 ? image
->aux_surface
.isl
.levels
: 0;
2124 /* Returns the number of auxiliary buffer layers attached to an image. */
2125 static inline uint32_t
2126 anv_image_aux_layers(const struct anv_image
* const image
,
2127 const uint8_t miplevel
)
2131 /* The miplevel must exist in the main buffer. */
2132 assert(miplevel
< image
->levels
);
2134 if (miplevel
>= anv_image_aux_levels(image
)) {
2135 /* There are no layers with auxiliary data because the miplevel has no
2140 return MAX2(image
->aux_surface
.isl
.logical_level0_px
.array_len
,
2141 image
->aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2145 static inline unsigned
2146 anv_fast_clear_state_entry_size(const struct anv_device
*device
)
2150 * +--------------------------------------------+
2151 * | clear value dword(s) | needs resolve dword |
2152 * +--------------------------------------------+
2155 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2156 * GPU memcpy operations.
2158 assert(device
->isl_dev
.ss
.clear_value_size
% 4 == 0);
2159 return device
->isl_dev
.ss
.clear_value_size
+ 4;
2162 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2164 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2165 const VkImageAspectFlags aspect_mask
,
2166 const uint32_t samples
)
2168 /* Validate the inputs. */
2169 assert(devinfo
&& aspect_mask
&& samples
);
2170 return devinfo
->gen
>= 8 && (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2175 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
2176 const struct anv_image
*image
,
2177 enum blorp_hiz_op op
);
2179 anv_ccs_resolve(struct anv_cmd_buffer
* const cmd_buffer
,
2180 const struct anv_state surface_state
,
2181 const struct anv_image
* const image
,
2182 const uint8_t level
, const uint32_t layer_count
,
2183 const enum blorp_fast_clear_op op
);
2186 anv_image_fast_clear(struct anv_cmd_buffer
*cmd_buffer
,
2187 const struct anv_image
*image
,
2188 const uint32_t base_level
, const uint32_t level_count
,
2189 const uint32_t base_layer
, uint32_t layer_count
);
2192 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2193 const struct anv_image
*image
,
2194 const VkImageAspectFlags aspects
,
2195 const VkImageLayout layout
);
2197 /* This is defined as a macro so that it works for both
2198 * VkImageSubresourceRange and VkImageSubresourceLayers
2200 #define anv_get_layerCount(_image, _range) \
2201 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2202 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2204 static inline uint32_t
2205 anv_get_levelCount(const struct anv_image
*image
,
2206 const VkImageSubresourceRange
*range
)
2208 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2209 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2213 struct anv_image_view
{
2214 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2216 uint32_t offset
; /**< Offset into bo. */
2218 struct isl_view isl
;
2220 VkImageAspectFlags aspect_mask
;
2222 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2225 * RENDER_SURFACE_STATE when using image as a sampler surface with an image
2226 * layout of SHADER_READ_ONLY_OPTIMAL or DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2228 enum isl_aux_usage optimal_sampler_aux_usage
;
2229 struct anv_state optimal_sampler_surface_state
;
2232 * RENDER_SURFACE_STATE when using image as a sampler surface with an image
2233 * layout of GENERAL.
2235 enum isl_aux_usage general_sampler_aux_usage
;
2236 struct anv_state general_sampler_surface_state
;
2239 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
2240 * for write-only and readable, using the real format for write-only and the
2241 * lowered format for readable.
2243 struct anv_state storage_surface_state
;
2244 struct anv_state writeonly_storage_surface_state
;
2246 struct brw_image_param storage_image_param
;
2249 struct anv_image_create_info
{
2250 const VkImageCreateInfo
*vk_info
;
2252 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2253 isl_tiling_flags_t isl_tiling_flags
;
2258 VkResult
anv_image_create(VkDevice _device
,
2259 const struct anv_image_create_info
*info
,
2260 const VkAllocationCallbacks
* alloc
,
2263 const struct anv_surface
*
2264 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2265 VkImageAspectFlags aspect_mask
);
2268 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
2270 static inline struct VkExtent3D
2271 anv_sanitize_image_extent(const VkImageType imageType
,
2272 const struct VkExtent3D imageExtent
)
2274 switch (imageType
) {
2275 case VK_IMAGE_TYPE_1D
:
2276 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2277 case VK_IMAGE_TYPE_2D
:
2278 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2279 case VK_IMAGE_TYPE_3D
:
2282 unreachable("invalid image type");
2286 static inline struct VkOffset3D
2287 anv_sanitize_image_offset(const VkImageType imageType
,
2288 const struct VkOffset3D imageOffset
)
2290 switch (imageType
) {
2291 case VK_IMAGE_TYPE_1D
:
2292 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2293 case VK_IMAGE_TYPE_2D
:
2294 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2295 case VK_IMAGE_TYPE_3D
:
2298 unreachable("invalid image type");
2303 void anv_fill_buffer_surface_state(struct anv_device
*device
,
2304 struct anv_state state
,
2305 enum isl_format format
,
2306 uint32_t offset
, uint32_t range
,
2309 struct anv_sampler
{
2313 struct anv_framebuffer
{
2318 uint32_t attachment_count
;
2319 struct anv_image_view
* attachments
[0];
2322 struct anv_subpass
{
2323 uint32_t attachment_count
;
2326 * A pointer to all attachment references used in this subpass.
2327 * Only valid if ::attachment_count > 0.
2329 VkAttachmentReference
* attachments
;
2330 uint32_t input_count
;
2331 VkAttachmentReference
* input_attachments
;
2332 uint32_t color_count
;
2333 VkAttachmentReference
* color_attachments
;
2334 VkAttachmentReference
* resolve_attachments
;
2336 VkAttachmentReference depth_stencil_attachment
;
2340 /** Subpass has a depth/stencil self-dependency */
2341 bool has_ds_self_dep
;
2343 /** Subpass has at least one resolve attachment */
2347 static inline unsigned
2348 anv_subpass_view_count(const struct anv_subpass
*subpass
)
2350 return MAX2(1, _mesa_bitcount(subpass
->view_mask
));
2353 struct anv_render_pass_attachment
{
2354 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2355 * its members individually.
2359 VkImageUsageFlags usage
;
2360 VkAttachmentLoadOp load_op
;
2361 VkAttachmentStoreOp store_op
;
2362 VkAttachmentLoadOp stencil_load_op
;
2363 VkImageLayout initial_layout
;
2364 VkImageLayout final_layout
;
2365 VkImageLayout first_subpass_layout
;
2367 /* The subpass id in which the attachment will be used last. */
2368 uint32_t last_subpass_idx
;
2371 struct anv_render_pass
{
2372 uint32_t attachment_count
;
2373 uint32_t subpass_count
;
2374 /* An array of subpass_count+1 flushes, one per subpass boundary */
2375 enum anv_pipe_bits
* subpass_flushes
;
2376 struct anv_render_pass_attachment
* attachments
;
2377 struct anv_subpass subpasses
[0];
2380 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2382 struct anv_query_pool
{
2384 VkQueryPipelineStatisticFlags pipeline_statistics
;
2385 /** Stride between slots, in bytes */
2387 /** Number of slots in this query pool */
2392 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
2395 void anv_dump_image_to_ppm(struct anv_device
*device
,
2396 struct anv_image
*image
, unsigned miplevel
,
2397 unsigned array_layer
, VkImageAspectFlagBits aspect
,
2398 const char *filename
);
2400 enum anv_dump_action
{
2401 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
2404 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
2405 void anv_dump_finish(void);
2407 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
2408 struct anv_framebuffer
*fb
);
2410 static inline uint32_t
2411 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
2413 /* This function must be called from within a subpass. */
2414 assert(cmd_state
->pass
&& cmd_state
->subpass
);
2416 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
2418 /* The id of this subpass shouldn't exceed the number of subpasses in this
2419 * render pass minus 1.
2421 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
2425 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2427 static inline struct __anv_type * \
2428 __anv_type ## _from_handle(__VkType _handle) \
2430 return (struct __anv_type *) _handle; \
2433 static inline __VkType \
2434 __anv_type ## _to_handle(struct __anv_type *_obj) \
2436 return (__VkType) _obj; \
2439 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2441 static inline struct __anv_type * \
2442 __anv_type ## _from_handle(__VkType _handle) \
2444 return (struct __anv_type *)(uintptr_t) _handle; \
2447 static inline __VkType \
2448 __anv_type ## _to_handle(struct __anv_type *_obj) \
2450 return (__VkType)(uintptr_t) _obj; \
2453 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2454 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2456 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
2457 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
2458 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
2459 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
2460 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
2462 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
2463 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
2464 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
2465 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
2466 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
2467 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
2468 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
2469 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
2470 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
2471 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
2472 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
2473 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
2474 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
2475 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
2476 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
2477 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
2478 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
2479 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
2480 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
2481 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
2482 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
2484 /* Gen-specific function declarations */
2486 # include "anv_genX.h"
2488 # define genX(x) gen7_##x
2489 # include "anv_genX.h"
2491 # define genX(x) gen75_##x
2492 # include "anv_genX.h"
2494 # define genX(x) gen8_##x
2495 # include "anv_genX.h"
2497 # define genX(x) gen9_##x
2498 # include "anv_genX.h"
2500 # define genX(x) gen10_##x
2501 # include "anv_genX.h"
2505 #endif /* ANV_PRIVATE_H */