2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
60 #include "util/xmlconfig.h"
62 #include "vk_debug_report.h"
64 /* Pre-declarations needed for WSI entrypoints */
67 typedef struct xcb_connection_t xcb_connection_t
;
68 typedef uint32_t xcb_visualid_t
;
69 typedef uint32_t xcb_window_t
;
72 struct anv_buffer_view
;
73 struct anv_image_view
;
76 struct gen_aux_map_context
;
78 struct gen_perf_config
;
80 #include <vulkan/vulkan.h>
81 #include <vulkan/vulkan_intel.h>
82 #include <vulkan/vk_icd.h>
84 #include "anv_android.h"
85 #include "anv_entrypoints.h"
86 #include "anv_extensions.h"
89 #include "dev/gen_debug.h"
90 #include "common/intel_log.h"
91 #include "wsi_common.h"
93 /* anv Virtual Memory Layout
94 * =========================
96 * When the anv driver is determining the virtual graphics addresses of memory
97 * objects itself using the softpin mechanism, the following memory ranges
100 * Three special considerations to notice:
102 * (1) the dynamic state pool is located within the same 4 GiB as the low
103 * heap. This is to work around a VF cache issue described in a comment in
104 * anv_physical_device_init_heaps.
106 * (2) the binding table pool is located at lower addresses than the surface
107 * state pool, within a 4 GiB range. This allows surface state base addresses
108 * to cover both binding tables (16 bit offsets) and surface states (32 bit
111 * (3) the last 4 GiB of the address space is withheld from the high
112 * heap. Various hardware units will read past the end of an object for
113 * various reasons. This healthy margin prevents reads from wrapping around
116 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
117 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
118 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
119 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
120 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
121 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
122 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
123 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
124 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
125 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
126 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
128 #define LOW_HEAP_SIZE \
129 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
130 #define DYNAMIC_STATE_POOL_SIZE \
131 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
132 #define BINDING_TABLE_POOL_SIZE \
133 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
134 #define SURFACE_STATE_POOL_SIZE \
135 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
136 #define INSTRUCTION_STATE_POOL_SIZE \
137 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
139 /* Allowing different clear colors requires us to perform a depth resolve at
140 * the end of certain render passes. This is because while slow clears store
141 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
142 * See the PRMs for examples describing when additional resolves would be
143 * necessary. To enable fast clears without requiring extra resolves, we set
144 * the clear value to a globally-defined one. We could allow different values
145 * if the user doesn't expect coherent data during or after a render passes
146 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
147 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
148 * 1.0f seems to be the only value used. The only application that doesn't set
149 * this value does so through the usage of an seemingly uninitialized clear
152 #define ANV_HZ_FC_VAL 1.0f
155 #define MAX_XFB_BUFFERS 4
156 #define MAX_XFB_STREAMS 4
159 #define MAX_VIEWPORTS 16
160 #define MAX_SCISSORS 16
161 #define MAX_PUSH_CONSTANTS_SIZE 128
162 #define MAX_DYNAMIC_BUFFERS 16
163 #define MAX_IMAGES 64
164 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
165 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
166 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
168 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
170 * "The surface state model is used when a Binding Table Index (specified
171 * in the message descriptor) of less than 240 is specified. In this model,
172 * the Binding Table Index is used to index into the binding table, and the
173 * binding table entry contains a pointer to the SURFACE_STATE."
175 * Binding table values above 240 are used for various things in the hardware
176 * such as stateless, stateless with incoherent cache, SLM, and bindless.
178 #define MAX_BINDING_TABLE_SIZE 240
180 /* The kernel relocation API has a limitation of a 32-bit delta value
181 * applied to the address before it is written which, in spite of it being
182 * unsigned, is treated as signed . Because of the way that this maps to
183 * the Vulkan API, we cannot handle an offset into a buffer that does not
184 * fit into a signed 32 bits. The only mechanism we have for dealing with
185 * this at the moment is to limit all VkDeviceMemory objects to a maximum
186 * of 2GB each. The Vulkan spec allows us to do this:
188 * "Some platforms may have a limit on the maximum size of a single
189 * allocation. For example, certain systems may fail to create
190 * allocations with a size greater than or equal to 4GB. Such a limit is
191 * implementation-dependent, and if such a failure occurs then the error
192 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
194 * We don't use vk_error here because it's not an error so much as an
195 * indication to the application that the allocation is too large.
197 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
199 #define ANV_SVGS_VB_INDEX MAX_VBS
200 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
202 /* We reserve this MI ALU register for the purpose of handling predication.
203 * Other code which uses the MI ALU should leave it alone.
205 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
207 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
209 static inline uint32_t
210 align_down_npot_u32(uint32_t v
, uint32_t a
)
215 static inline uint32_t
216 align_u32(uint32_t v
, uint32_t a
)
218 assert(a
!= 0 && a
== (a
& -a
));
219 return (v
+ a
- 1) & ~(a
- 1);
222 static inline uint64_t
223 align_u64(uint64_t v
, uint64_t a
)
225 assert(a
!= 0 && a
== (a
& -a
));
226 return (v
+ a
- 1) & ~(a
- 1);
229 static inline int32_t
230 align_i32(int32_t v
, int32_t a
)
232 assert(a
!= 0 && a
== (a
& -a
));
233 return (v
+ a
- 1) & ~(a
- 1);
236 /** Alignment must be a power of 2. */
238 anv_is_aligned(uintmax_t n
, uintmax_t a
)
240 assert(a
== (a
& -a
));
241 return (n
& (a
- 1)) == 0;
244 static inline uint32_t
245 anv_minify(uint32_t n
, uint32_t levels
)
247 if (unlikely(n
== 0))
250 return MAX2(n
>> levels
, 1);
254 anv_clamp_f(float f
, float min
, float max
)
267 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
269 if (*inout_mask
& clear_mask
) {
270 *inout_mask
&= ~clear_mask
;
277 static inline union isl_color_value
278 vk_to_isl_color(VkClearColorValue color
)
280 return (union isl_color_value
) {
290 #define for_each_bit(b, dword) \
291 for (uint32_t __dword = (dword); \
292 (b) = __builtin_ffs(__dword) - 1, __dword; \
293 __dword &= ~(1 << (b)))
295 #define typed_memcpy(dest, src, count) ({ \
296 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
297 memcpy((dest), (src), (count) * sizeof(*(src))); \
300 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
301 * to be added here in order to utilize mapping in debug/error/perf macros.
303 #define REPORT_OBJECT_TYPE(o) \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
376 __builtin_choose_expr ( \
377 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
378 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
379 __builtin_choose_expr ( \
380 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
381 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
382 __builtin_choose_expr ( \
383 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
384 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
385 __builtin_choose_expr ( \
386 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
387 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
388 __builtin_choose_expr ( \
389 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
390 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
391 __builtin_choose_expr ( \
392 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
393 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
394 __builtin_choose_expr ( \
395 __builtin_types_compatible_p (__typeof (o), void*), \
396 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
397 /* The void expression results in a compile-time error \
398 when assigning the result to something. */ \
399 (void)0)))))))))))))))))))))))))))))))
401 /* Whenever we generate an error, pass it through this function. Useful for
402 * debugging, where we can break on it. Only call at error site, not when
403 * propagating errors. Might be useful to plug in a stack trace here.
406 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
407 VkDebugReportObjectTypeEXT type
, VkResult error
,
408 const char *file
, int line
, const char *format
,
411 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
412 VkDebugReportObjectTypeEXT type
, VkResult error
,
413 const char *file
, int line
, const char *format
, ...);
416 #define vk_error(error) __vk_errorf(NULL, NULL,\
417 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
418 error, __FILE__, __LINE__, NULL)
419 #define vk_errorv(instance, obj, error, format, args)\
420 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
421 __FILE__, __LINE__, format, args)
422 #define vk_errorf(instance, obj, error, format, ...)\
423 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
424 __FILE__, __LINE__, format, ## __VA_ARGS__)
426 #define vk_error(error) error
427 #define vk_errorf(instance, obj, error, format, ...) error
431 * Warn on ignored extension structs.
433 * The Vulkan spec requires us to ignore unsupported or unknown structs in
434 * a pNext chain. In debug mode, emitting warnings for ignored structs may
435 * help us discover structs that we should not have ignored.
438 * From the Vulkan 1.0.38 spec:
440 * Any component of the implementation (the loader, any enabled layers,
441 * and drivers) must skip over, without processing (other than reading the
442 * sType and pNext members) any chained structures with sType values not
443 * defined by extensions supported by that component.
445 #define anv_debug_ignored_stype(sType) \
446 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
448 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
449 VkDebugReportObjectTypeEXT type
, const char *file
,
450 int line
, const char *format
, ...)
451 anv_printflike(6, 7);
452 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
453 void anv_loge_v(const char *format
, va_list va
);
456 * Print a FINISHME message, including its source location.
458 #define anv_finishme(format, ...) \
460 static bool reported = false; \
462 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
469 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
471 #define anv_perf_warn(instance, obj, format, ...) \
473 static bool reported = false; \
474 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
475 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
476 format, ##__VA_ARGS__); \
481 /* A non-fatal assert. Useful for debugging. */
483 #define anv_assert(x) ({ \
484 if (unlikely(!(x))) \
485 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
488 #define anv_assert(x)
491 /* A multi-pointer allocator
493 * When copying data structures from the user (such as a render pass), it's
494 * common to need to allocate data for a bunch of different things. Instead
495 * of doing several allocations and having to handle all of the error checking
496 * that entails, it can be easier to do a single allocation. This struct
497 * helps facilitate that. The intended usage looks like this:
500 * anv_multialloc_add(&ma, &main_ptr, 1);
501 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
502 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
504 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
505 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
507 struct anv_multialloc
{
515 #define ANV_MULTIALLOC_INIT \
516 ((struct anv_multialloc) { 0, })
518 #define ANV_MULTIALLOC(_name) \
519 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
521 __attribute__((always_inline
))
523 _anv_multialloc_add(struct anv_multialloc
*ma
,
524 void **ptr
, size_t size
, size_t align
)
526 size_t offset
= align_u64(ma
->size
, align
);
527 ma
->size
= offset
+ size
;
528 ma
->align
= MAX2(ma
->align
, align
);
530 /* Store the offset in the pointer. */
531 *ptr
= (void *)(uintptr_t)offset
;
533 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
534 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
537 #define anv_multialloc_add_size(_ma, _ptr, _size) \
538 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
540 #define anv_multialloc_add(_ma, _ptr, _count) \
541 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
543 __attribute__((always_inline
))
545 anv_multialloc_alloc(struct anv_multialloc
*ma
,
546 const VkAllocationCallbacks
*alloc
,
547 VkSystemAllocationScope scope
)
549 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
553 /* Fill out each of the pointers with their final value.
555 * for (uint32_t i = 0; i < ma->ptr_count; i++)
556 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
558 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
559 * constant, GCC is incapable of figuring this out and unrolling the loop
560 * so we have to give it a little help.
562 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
563 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
564 if ((_i) < ma->ptr_count) \
565 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
566 _ANV_MULTIALLOC_UPDATE_POINTER(0);
567 _ANV_MULTIALLOC_UPDATE_POINTER(1);
568 _ANV_MULTIALLOC_UPDATE_POINTER(2);
569 _ANV_MULTIALLOC_UPDATE_POINTER(3);
570 _ANV_MULTIALLOC_UPDATE_POINTER(4);
571 _ANV_MULTIALLOC_UPDATE_POINTER(5);
572 _ANV_MULTIALLOC_UPDATE_POINTER(6);
573 _ANV_MULTIALLOC_UPDATE_POINTER(7);
574 #undef _ANV_MULTIALLOC_UPDATE_POINTER
579 __attribute__((always_inline
))
581 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
582 const VkAllocationCallbacks
*parent_alloc
,
583 const VkAllocationCallbacks
*alloc
,
584 VkSystemAllocationScope scope
)
586 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
589 /* Extra ANV-defined BO flags which won't be passed to the kernel */
590 #define ANV_BO_EXTERNAL (1ull << 31)
591 #define ANV_BO_FLAG_MASK (1ull << 31)
596 /* Index into the current validation list. This is used by the
597 * validation list building alrogithm to track which buffers are already
598 * in the validation list so that we can ensure uniqueness.
602 /* Last known offset. This value is provided by the kernel when we
603 * execbuf and is used as the presumed offset for the next bunch of
611 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
616 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
618 bo
->gem_handle
= gem_handle
;
626 /* Represents a lock-free linked list of "free" things. This is used by
627 * both the block pool and the state pools. Unfortunately, in order to
628 * solve the ABA problem, we can't use a single uint32_t head.
630 union anv_free_list
{
634 /* A simple count that is incremented every time the head changes. */
637 /* Make sure it's aligned to 64 bits. This will make atomic operations
638 * faster on 32 bit platforms.
640 uint64_t u64
__attribute__ ((aligned (8)));
643 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
645 struct anv_block_state
{
651 /* Make sure it's aligned to 64 bits. This will make atomic operations
652 * faster on 32 bit platforms.
654 uint64_t u64
__attribute__ ((aligned (8)));
658 #define anv_block_pool_foreach_bo(bo, pool) \
659 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
661 #define ANV_MAX_BLOCK_POOL_BOS 20
663 struct anv_block_pool
{
664 struct anv_device
*device
;
668 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
674 /* The address where the start of the pool is pinned. The various bos that
675 * are created as the pool grows will have addresses in the range
676 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
678 uint64_t start_address
;
680 /* The offset from the start of the bo to the "center" of the block
681 * pool. Pointers to allocated blocks are given by
682 * bo.map + center_bo_offset + offsets.
684 uint32_t center_bo_offset
;
686 /* Current memory map of the block pool. This pointer may or may not
687 * point to the actual beginning of the block pool memory. If
688 * anv_block_pool_alloc_back has ever been called, then this pointer
689 * will point to the "center" position of the buffer and all offsets
690 * (negative or positive) given out by the block pool alloc functions
691 * will be valid relative to this pointer.
693 * In particular, map == bo.map + center_offset
695 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
696 * since it will handle the softpin case as well, where this points to NULL.
702 * Array of mmaps and gem handles owned by the block pool, reclaimed when
703 * the block pool is destroyed.
705 struct u_vector mmap_cleanups
;
707 struct anv_block_state state
;
709 struct anv_block_state back_state
;
712 /* Block pools are backed by a fixed-size 1GB memfd */
713 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
715 /* The center of the block pool is also the middle of the memfd. This may
716 * change in the future if we decide differently for some reason.
718 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
720 static inline uint32_t
721 anv_block_pool_size(struct anv_block_pool
*pool
)
723 return pool
->state
.end
+ pool
->back_state
.end
;
733 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
735 struct anv_fixed_size_state_pool
{
736 union anv_free_list free_list
;
737 struct anv_block_state block
;
740 #define ANV_MIN_STATE_SIZE_LOG2 6
741 #define ANV_MAX_STATE_SIZE_LOG2 21
743 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
745 struct anv_free_entry
{
747 struct anv_state state
;
750 struct anv_state_table
{
751 struct anv_device
*device
;
753 struct anv_free_entry
*map
;
755 struct anv_block_state state
;
756 struct u_vector cleanups
;
759 struct anv_state_pool
{
760 struct anv_block_pool block_pool
;
762 struct anv_state_table table
;
764 /* The size of blocks which will be allocated from the block pool */
767 /** Free list for "back" allocations */
768 union anv_free_list back_alloc_free_list
;
770 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
773 struct anv_state_stream_block
;
775 struct anv_state_stream
{
776 struct anv_state_pool
*state_pool
;
778 /* The size of blocks to allocate from the state pool */
781 /* Current block we're allocating from */
782 struct anv_state block
;
784 /* Offset into the current block at which to allocate the next state */
787 /* List of all blocks allocated from this pool */
788 struct anv_state_stream_block
*block_list
;
791 /* The block_pool functions exported for testing only. The block pool should
792 * only be used via a state pool (see below).
794 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
795 struct anv_device
*device
,
796 uint64_t start_address
,
797 uint32_t initial_size
,
799 void anv_block_pool_finish(struct anv_block_pool
*pool
);
800 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
801 uint32_t block_size
, uint32_t *padding
);
802 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
803 uint32_t block_size
);
804 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
806 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
807 struct anv_device
*device
,
808 uint64_t start_address
,
811 void anv_state_pool_finish(struct anv_state_pool
*pool
);
812 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
813 uint32_t state_size
, uint32_t alignment
);
814 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
815 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
816 void anv_state_stream_init(struct anv_state_stream
*stream
,
817 struct anv_state_pool
*state_pool
,
818 uint32_t block_size
);
819 void anv_state_stream_finish(struct anv_state_stream
*stream
);
820 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
821 uint32_t size
, uint32_t alignment
);
823 VkResult
anv_state_table_init(struct anv_state_table
*table
,
824 struct anv_device
*device
,
825 uint32_t initial_entries
);
826 void anv_state_table_finish(struct anv_state_table
*table
);
827 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
829 void anv_free_list_push(union anv_free_list
*list
,
830 struct anv_state_table
*table
,
831 uint32_t idx
, uint32_t count
);
832 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
833 struct anv_state_table
*table
);
836 static inline struct anv_state
*
837 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
839 return &table
->map
[idx
].state
;
842 * Implements a pool of re-usable BOs. The interface is identical to that
843 * of block_pool except that each block is its own BO.
846 struct anv_device
*device
;
853 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
855 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
856 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
858 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
860 struct anv_scratch_bo
{
865 struct anv_scratch_pool
{
866 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
867 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
870 void anv_scratch_pool_init(struct anv_device
*device
,
871 struct anv_scratch_pool
*pool
);
872 void anv_scratch_pool_finish(struct anv_device
*device
,
873 struct anv_scratch_pool
*pool
);
874 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
875 struct anv_scratch_pool
*pool
,
876 gl_shader_stage stage
,
877 unsigned per_thread_scratch
);
879 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
880 struct anv_bo_cache
{
881 struct hash_table
*bo_map
;
882 pthread_mutex_t mutex
;
885 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
886 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
887 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
888 struct anv_bo_cache
*cache
,
889 uint64_t size
, uint64_t bo_flags
,
891 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
892 struct anv_bo_cache
*cache
,
893 void *host_ptr
, uint32_t size
,
894 uint64_t bo_flags
, struct anv_bo
**bo_out
);
895 VkResult
anv_bo_cache_import(struct anv_device
*device
,
896 struct anv_bo_cache
*cache
,
897 int fd
, uint64_t bo_flags
,
899 VkResult
anv_bo_cache_export(struct anv_device
*device
,
900 struct anv_bo_cache
*cache
,
901 struct anv_bo
*bo_in
, int *fd_out
);
902 void anv_bo_cache_release(struct anv_device
*device
,
903 struct anv_bo_cache
*cache
,
906 struct anv_memory_type
{
907 /* Standard bits passed on to the client */
908 VkMemoryPropertyFlags propertyFlags
;
911 /* Driver-internal book-keeping */
912 VkBufferUsageFlags valid_buffer_usage
;
915 struct anv_memory_heap
{
916 /* Standard bits passed on to the client */
918 VkMemoryHeapFlags flags
;
920 /* Driver-internal book-keeping */
923 bool supports_48bit_addresses
;
927 struct anv_physical_device
{
928 VK_LOADER_DATA _loader_data
;
930 struct anv_instance
* instance
;
941 struct gen_device_info info
;
942 /** Amount of "GPU memory" we want to advertise
944 * Clearly, this value is bogus since Intel is a UMA architecture. On
945 * gen7 platforms, we are limited by GTT size unless we want to implement
946 * fine-grained tracking and GTT splitting. On Broadwell and above we are
947 * practically unlimited. However, we will never report more than 3/4 of
948 * the total system ram to try and avoid running out of RAM.
950 bool supports_48bit_addresses
;
951 struct brw_compiler
* compiler
;
952 struct isl_device isl_dev
;
953 struct gen_perf_config
* perf
;
954 int cmd_parser_version
;
956 bool has_exec_capture
;
959 bool has_syncobj_wait
;
960 bool has_context_priority
;
962 bool has_context_isolation
;
963 bool has_mem_available
;
964 bool always_use_bindless
;
966 /** True if we can access buffers using A64 messages */
967 bool has_a64_buffer_access
;
968 /** True if we can use bindless access for images */
969 bool has_bindless_images
;
970 /** True if we can use bindless access for samplers */
971 bool has_bindless_samplers
;
973 struct anv_device_extension_table supported_extensions
;
974 struct anv_physical_device_dispatch_table dispatch
;
977 uint32_t subslice_total
;
981 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
983 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
986 uint8_t driver_build_sha1
[20];
987 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
988 uint8_t driver_uuid
[VK_UUID_SIZE
];
989 uint8_t device_uuid
[VK_UUID_SIZE
];
991 struct disk_cache
* disk_cache
;
993 struct wsi_device wsi_device
;
998 struct anv_app_info
{
999 const char* app_name
;
1000 uint32_t app_version
;
1001 const char* engine_name
;
1002 uint32_t engine_version
;
1003 uint32_t api_version
;
1006 struct anv_instance
{
1007 VK_LOADER_DATA _loader_data
;
1009 VkAllocationCallbacks alloc
;
1011 struct anv_app_info app_info
;
1013 struct anv_instance_extension_table enabled_extensions
;
1014 struct anv_instance_dispatch_table dispatch
;
1015 struct anv_device_dispatch_table device_dispatch
;
1017 int physicalDeviceCount
;
1018 struct anv_physical_device physicalDevice
;
1020 bool pipeline_cache_enabled
;
1022 struct vk_debug_report_instance debug_report_callbacks
;
1024 struct driOptionCache dri_options
;
1025 struct driOptionCache available_dri_options
;
1028 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1029 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1031 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1032 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1036 VK_LOADER_DATA _loader_data
;
1038 struct anv_device
* device
;
1040 VkDeviceQueueCreateFlags flags
;
1043 struct anv_pipeline_cache
{
1044 struct anv_device
* device
;
1045 pthread_mutex_t mutex
;
1047 struct hash_table
* nir_cache
;
1049 struct hash_table
* cache
;
1052 struct nir_xfb_info
;
1053 struct anv_pipeline_bind_map
;
1055 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1056 struct anv_device
*device
,
1057 bool cache_enabled
);
1058 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1060 struct anv_shader_bin
*
1061 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1062 const void *key
, uint32_t key_size
);
1063 struct anv_shader_bin
*
1064 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1065 const void *key_data
, uint32_t key_size
,
1066 const void *kernel_data
, uint32_t kernel_size
,
1067 const void *constant_data
,
1068 uint32_t constant_data_size
,
1069 const struct brw_stage_prog_data
*prog_data
,
1070 uint32_t prog_data_size
,
1071 const struct brw_compile_stats
*stats
,
1073 const struct nir_xfb_info
*xfb_info
,
1074 const struct anv_pipeline_bind_map
*bind_map
);
1076 struct anv_shader_bin
*
1077 anv_device_search_for_kernel(struct anv_device
*device
,
1078 struct anv_pipeline_cache
*cache
,
1079 const void *key_data
, uint32_t key_size
,
1080 bool *user_cache_bit
);
1082 struct anv_shader_bin
*
1083 anv_device_upload_kernel(struct anv_device
*device
,
1084 struct anv_pipeline_cache
*cache
,
1085 const void *key_data
, uint32_t key_size
,
1086 const void *kernel_data
, uint32_t kernel_size
,
1087 const void *constant_data
,
1088 uint32_t constant_data_size
,
1089 const struct brw_stage_prog_data
*prog_data
,
1090 uint32_t prog_data_size
,
1091 const struct brw_compile_stats
*stats
,
1093 const struct nir_xfb_info
*xfb_info
,
1094 const struct anv_pipeline_bind_map
*bind_map
);
1097 struct nir_shader_compiler_options
;
1100 anv_device_search_for_nir(struct anv_device
*device
,
1101 struct anv_pipeline_cache
*cache
,
1102 const struct nir_shader_compiler_options
*nir_options
,
1103 unsigned char sha1_key
[20],
1107 anv_device_upload_nir(struct anv_device
*device
,
1108 struct anv_pipeline_cache
*cache
,
1109 const struct nir_shader
*nir
,
1110 unsigned char sha1_key
[20]);
1113 VK_LOADER_DATA _loader_data
;
1115 VkAllocationCallbacks alloc
;
1117 struct anv_instance
* instance
;
1118 uint32_t chipset_id
;
1120 struct gen_device_info info
;
1121 struct isl_device isl_dev
;
1124 bool can_chain_batches
;
1125 bool robust_buffer_access
;
1126 struct anv_device_extension_table enabled_extensions
;
1127 struct anv_device_dispatch_table dispatch
;
1129 pthread_mutex_t vma_mutex
;
1130 struct util_vma_heap vma_lo
;
1131 struct util_vma_heap vma_hi
;
1132 uint64_t vma_lo_available
;
1133 uint64_t vma_hi_available
;
1135 /** List of all anv_device_memory objects */
1136 struct list_head memory_objects
;
1138 struct anv_bo_pool batch_bo_pool
;
1140 struct anv_bo_cache bo_cache
;
1142 struct anv_state_pool dynamic_state_pool
;
1143 struct anv_state_pool instruction_state_pool
;
1144 struct anv_state_pool binding_table_pool
;
1145 struct anv_state_pool surface_state_pool
;
1147 struct anv_bo workaround_bo
;
1148 struct anv_bo trivial_batch_bo
;
1149 struct anv_bo hiz_clear_bo
;
1151 struct anv_pipeline_cache default_pipeline_cache
;
1152 struct blorp_context blorp
;
1154 struct anv_state border_colors
;
1156 struct anv_state slice_hash
;
1158 struct anv_queue queue
;
1160 struct anv_scratch_pool scratch_pool
;
1162 uint32_t default_mocs
;
1163 uint32_t external_mocs
;
1165 pthread_mutex_t mutex
;
1166 pthread_cond_t queue_submit
;
1169 struct gen_batch_decode_ctx decoder_ctx
;
1171 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1172 * the cmd_buffer's list.
1174 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1176 int perf_fd
; /* -1 if no opened */
1177 uint64_t perf_metric
; /* 0 if unset */
1179 struct gen_aux_map_context
*aux_map_ctx
;
1182 static inline struct anv_state_pool
*
1183 anv_binding_table_pool(struct anv_device
*device
)
1185 if (device
->instance
->physicalDevice
.use_softpin
)
1186 return &device
->binding_table_pool
;
1188 return &device
->surface_state_pool
;
1191 static inline struct anv_state
1192 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1193 if (device
->instance
->physicalDevice
.use_softpin
)
1194 return anv_state_pool_alloc(&device
->binding_table_pool
,
1195 device
->binding_table_pool
.block_size
, 0);
1197 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1201 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1202 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1205 static inline uint32_t
1206 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1208 if (bo
->flags
& ANV_BO_EXTERNAL
)
1209 return device
->external_mocs
;
1211 return device
->default_mocs
;
1214 void anv_device_init_blorp(struct anv_device
*device
);
1215 void anv_device_finish_blorp(struct anv_device
*device
);
1217 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1218 const char *file
, int line
,
1219 const char *msg
, ...);
1220 #define anv_device_set_lost(dev, ...) \
1221 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1224 anv_device_is_lost(struct anv_device
*device
)
1226 return unlikely(device
->_lost
);
1229 VkResult
anv_device_execbuf(struct anv_device
*device
,
1230 struct drm_i915_gem_execbuffer2
*execbuf
,
1231 struct anv_bo
**execbuf_bos
);
1232 VkResult
anv_device_query_status(struct anv_device
*device
);
1233 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1234 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1237 void* anv_gem_mmap(struct anv_device
*device
,
1238 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1239 void anv_gem_munmap(void *p
, uint64_t size
);
1240 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1241 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1242 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1243 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1244 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1245 int anv_gem_execbuffer(struct anv_device
*device
,
1246 struct drm_i915_gem_execbuffer2
*execbuf
);
1247 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1248 uint32_t stride
, uint32_t tiling
);
1249 int anv_gem_create_context(struct anv_device
*device
);
1250 bool anv_gem_has_context_priority(int fd
);
1251 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1252 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1254 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1256 int anv_gem_get_param(int fd
, uint32_t param
);
1257 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1258 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1259 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1260 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1261 uint32_t *active
, uint32_t *pending
);
1262 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1263 int anv_gem_reg_read(struct anv_device
*device
,
1264 uint32_t offset
, uint64_t *result
);
1265 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1266 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1267 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1268 uint32_t read_domains
, uint32_t write_domain
);
1269 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1270 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1271 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1272 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1273 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1274 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1276 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1277 uint32_t handle
, int fd
);
1278 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1279 bool anv_gem_supports_syncobj_wait(int fd
);
1280 int anv_gem_syncobj_wait(struct anv_device
*device
,
1281 uint32_t *handles
, uint32_t num_handles
,
1282 int64_t abs_timeout_ns
, bool wait_all
);
1284 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1285 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1287 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1289 struct anv_reloc_list
{
1290 uint32_t num_relocs
;
1291 uint32_t array_length
;
1292 struct drm_i915_gem_relocation_entry
* relocs
;
1293 struct anv_bo
** reloc_bos
;
1297 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1298 const VkAllocationCallbacks
*alloc
);
1299 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1300 const VkAllocationCallbacks
*alloc
);
1302 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1303 const VkAllocationCallbacks
*alloc
,
1304 uint32_t offset
, struct anv_bo
*target_bo
,
1307 struct anv_batch_bo
{
1308 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1309 struct list_head link
;
1313 /* Bytes actually consumed in this batch BO */
1316 struct anv_reloc_list relocs
;
1320 const VkAllocationCallbacks
* alloc
;
1326 struct anv_reloc_list
* relocs
;
1328 /* This callback is called (with the associated user data) in the event
1329 * that the batch runs out of space.
1331 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1335 * Current error status of the command buffer. Used to track inconsistent
1336 * or incomplete command buffer states that are the consequence of run-time
1337 * errors such as out of memory scenarios. We want to track this in the
1338 * batch because the command buffer object is not visible to some parts
1344 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1345 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1346 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1347 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1348 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1349 struct anv_batch
*batch
);
1351 static inline VkResult
1352 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1354 assert(error
!= VK_SUCCESS
);
1355 if (batch
->status
== VK_SUCCESS
)
1356 batch
->status
= error
;
1357 return batch
->status
;
1361 anv_batch_has_error(struct anv_batch
*batch
)
1363 return batch
->status
!= VK_SUCCESS
;
1366 struct anv_address
{
1371 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1374 anv_address_is_null(struct anv_address addr
)
1376 return addr
.bo
== NULL
&& addr
.offset
== 0;
1379 static inline uint64_t
1380 anv_address_physical(struct anv_address addr
)
1382 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1383 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1385 return gen_canonical_address(addr
.offset
);
1388 static inline struct anv_address
1389 anv_address_add(struct anv_address addr
, uint64_t offset
)
1391 addr
.offset
+= offset
;
1396 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1398 unsigned reloc_size
= 0;
1399 if (device
->info
.gen
>= 8) {
1400 reloc_size
= sizeof(uint64_t);
1401 *(uint64_t *)p
= gen_canonical_address(v
);
1403 reloc_size
= sizeof(uint32_t);
1407 if (flush
&& !device
->info
.has_llc
)
1408 gen_flush_range(p
, reloc_size
);
1411 static inline uint64_t
1412 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1413 const struct anv_address address
, uint32_t delta
)
1415 if (address
.bo
== NULL
) {
1416 return address
.offset
+ delta
;
1418 assert(batch
->start
<= location
&& location
< batch
->end
);
1420 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1424 #define __gen_address_type struct anv_address
1425 #define __gen_user_data struct anv_batch
1426 #define __gen_combine_address _anv_combine_address
1428 /* Wrapper macros needed to work around preprocessor argument issues. In
1429 * particular, arguments don't get pre-evaluated if they are concatenated.
1430 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1431 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1432 * We can work around this easily enough with these helpers.
1434 #define __anv_cmd_length(cmd) cmd ## _length
1435 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1436 #define __anv_cmd_header(cmd) cmd ## _header
1437 #define __anv_cmd_pack(cmd) cmd ## _pack
1438 #define __anv_reg_num(reg) reg ## _num
1440 #define anv_pack_struct(dst, struc, ...) do { \
1441 struct struc __template = { \
1444 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1445 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1448 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1449 void *__dst = anv_batch_emit_dwords(batch, n); \
1451 struct cmd __template = { \
1452 __anv_cmd_header(cmd), \
1453 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1456 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1461 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1465 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1466 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1469 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1470 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1471 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1474 #define anv_batch_emit(batch, cmd, name) \
1475 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1476 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1477 __builtin_expect(_dst != NULL, 1); \
1478 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1479 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1483 /* MEMORY_OBJECT_CONTROL_STATE:
1484 * .GraphicsDataTypeGFDT = 0,
1485 * .LLCCacheabilityControlLLCCC = 0,
1486 * .L3CacheabilityControlL3CC = 1,
1490 /* MEMORY_OBJECT_CONTROL_STATE:
1491 * .LLCeLLCCacheabilityControlLLCCC = 0,
1492 * .L3CacheabilityControlL3CC = 1,
1494 #define GEN75_MOCS 1
1496 /* MEMORY_OBJECT_CONTROL_STATE:
1497 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1498 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1499 * .AgeforQUADLRU = 0
1501 #define GEN8_MOCS 0x78
1503 /* MEMORY_OBJECT_CONTROL_STATE:
1504 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1505 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1506 * .AgeforQUADLRU = 0
1508 #define GEN8_EXTERNAL_MOCS 0x18
1510 /* Skylake: MOCS is now an index into an array of 62 different caching
1511 * configurations programmed by the kernel.
1514 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1515 #define GEN9_MOCS (2 << 1)
1517 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1518 #define GEN9_EXTERNAL_MOCS (1 << 1)
1520 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1521 #define GEN10_MOCS GEN9_MOCS
1522 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1524 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1525 #define GEN11_MOCS GEN9_MOCS
1526 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1528 /* TigerLake MOCS */
1529 #define GEN12_MOCS GEN9_MOCS
1530 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1531 #define GEN12_EXTERNAL_MOCS (3 << 1)
1533 struct anv_device_memory
{
1534 struct list_head link
;
1537 struct anv_memory_type
* type
;
1538 VkDeviceSize map_size
;
1541 /* If set, we are holding reference to AHardwareBuffer
1542 * which we must release when memory is freed.
1544 struct AHardwareBuffer
* ahw
;
1546 /* If set, this memory comes from a host pointer. */
1551 * Header for Vertex URB Entry (VUE)
1553 struct anv_vue_header
{
1555 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1556 uint32_t ViewportIndex
;
1560 /** Struct representing a sampled image descriptor
1562 * This descriptor layout is used for sampled images, bare sampler, and
1563 * combined image/sampler descriptors.
1565 struct anv_sampled_image_descriptor
{
1566 /** Bindless image handle
1568 * This is expected to already be shifted such that the 20-bit
1569 * SURFACE_STATE table index is in the top 20 bits.
1573 /** Bindless sampler handle
1575 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1576 * to the dynamic state base address.
1581 struct anv_texture_swizzle_descriptor
{
1584 * See also nir_intrinsic_channel_select_intel
1588 /** Unused padding to ensure the struct is a multiple of 64 bits */
1592 /** Struct representing a storage image descriptor */
1593 struct anv_storage_image_descriptor
{
1594 /** Bindless image handles
1596 * These are expected to already be shifted such that the 20-bit
1597 * SURFACE_STATE table index is in the top 20 bits.
1599 uint32_t read_write
;
1600 uint32_t write_only
;
1603 /** Struct representing a address/range descriptor
1605 * The fields of this struct correspond directly to the data layout of
1606 * nir_address_format_64bit_bounded_global addresses. The last field is the
1607 * offset in the NIR address so it must be zero so that when you load the
1608 * descriptor you get a pointer to the start of the range.
1610 struct anv_address_range_descriptor
{
1616 enum anv_descriptor_data
{
1617 /** The descriptor contains a BTI reference to a surface state */
1618 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1619 /** The descriptor contains a BTI reference to a sampler state */
1620 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1621 /** The descriptor contains an actual buffer view */
1622 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1623 /** The descriptor contains auxiliary image layout data */
1624 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1625 /** The descriptor contains auxiliary image layout data */
1626 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1627 /** anv_address_range_descriptor with a buffer address and range */
1628 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1629 /** Bindless surface handle */
1630 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1631 /** Storage image handles */
1632 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1633 /** Storage image handles */
1634 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1637 struct anv_descriptor_set_binding_layout
{
1639 /* The type of the descriptors in this binding */
1640 VkDescriptorType type
;
1643 /* Flags provided when this binding was created */
1644 VkDescriptorBindingFlagsEXT flags
;
1646 /* Bitfield representing the type of data this descriptor contains */
1647 enum anv_descriptor_data data
;
1649 /* Maximum number of YCbCr texture/sampler planes */
1650 uint8_t max_plane_count
;
1652 /* Number of array elements in this binding (or size in bytes for inline
1655 uint16_t array_size
;
1657 /* Index into the flattend descriptor set */
1658 uint16_t descriptor_index
;
1660 /* Index into the dynamic state array for a dynamic buffer */
1661 int16_t dynamic_offset_index
;
1663 /* Index into the descriptor set buffer views */
1664 int16_t buffer_view_index
;
1666 /* Offset into the descriptor buffer where this descriptor lives */
1667 uint32_t descriptor_offset
;
1669 /* Immutable samplers (or NULL if no immutable samplers) */
1670 struct anv_sampler
**immutable_samplers
;
1673 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1675 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1676 VkDescriptorType type
);
1678 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1679 const struct anv_descriptor_set_binding_layout
*binding
,
1682 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1683 const struct anv_descriptor_set_binding_layout
*binding
,
1686 struct anv_descriptor_set_layout
{
1687 /* Descriptor set layouts can be destroyed at almost any time */
1690 /* Number of bindings in this descriptor set */
1691 uint16_t binding_count
;
1693 /* Total size of the descriptor set with room for all array entries */
1696 /* Shader stages affected by this descriptor set */
1697 uint16_t shader_stages
;
1699 /* Number of buffer views in this descriptor set */
1700 uint16_t buffer_view_count
;
1702 /* Number of dynamic offsets used by this descriptor set */
1703 uint16_t dynamic_offset_count
;
1705 /* Size of the descriptor buffer for this descriptor set */
1706 uint32_t descriptor_buffer_size
;
1708 /* Bindings in this descriptor set */
1709 struct anv_descriptor_set_binding_layout binding
[0];
1713 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1715 assert(layout
&& layout
->ref_cnt
>= 1);
1716 p_atomic_inc(&layout
->ref_cnt
);
1720 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1721 struct anv_descriptor_set_layout
*layout
)
1723 assert(layout
&& layout
->ref_cnt
>= 1);
1724 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1725 vk_free(&device
->alloc
, layout
);
1728 struct anv_descriptor
{
1729 VkDescriptorType type
;
1733 VkImageLayout layout
;
1734 struct anv_image_view
*image_view
;
1735 struct anv_sampler
*sampler
;
1739 struct anv_buffer
*buffer
;
1744 struct anv_buffer_view
*buffer_view
;
1748 struct anv_descriptor_set
{
1749 struct anv_descriptor_pool
*pool
;
1750 struct anv_descriptor_set_layout
*layout
;
1753 /* State relative to anv_descriptor_pool::bo */
1754 struct anv_state desc_mem
;
1755 /* Surface state for the descriptor buffer */
1756 struct anv_state desc_surface_state
;
1758 uint32_t buffer_view_count
;
1759 struct anv_buffer_view
*buffer_views
;
1761 /* Link to descriptor pool's desc_sets list . */
1762 struct list_head pool_link
;
1764 struct anv_descriptor descriptors
[0];
1767 struct anv_buffer_view
{
1768 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1769 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1771 struct anv_address address
;
1773 struct anv_state surface_state
;
1774 struct anv_state storage_surface_state
;
1775 struct anv_state writeonly_storage_surface_state
;
1777 struct brw_image_param storage_image_param
;
1780 struct anv_push_descriptor_set
{
1781 struct anv_descriptor_set set
;
1783 /* Put this field right behind anv_descriptor_set so it fills up the
1784 * descriptors[0] field. */
1785 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1787 /** True if the descriptor set buffer has been referenced by a draw or
1790 bool set_used_on_gpu
;
1792 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1795 struct anv_descriptor_pool
{
1801 struct util_vma_heap bo_heap
;
1803 struct anv_state_stream surface_state_stream
;
1804 void *surface_state_free_list
;
1806 struct list_head desc_sets
;
1811 enum anv_descriptor_template_entry_type
{
1812 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1813 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1814 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1817 struct anv_descriptor_template_entry
{
1818 /* The type of descriptor in this entry */
1819 VkDescriptorType type
;
1821 /* Binding in the descriptor set */
1824 /* Offset at which to write into the descriptor set binding */
1825 uint32_t array_element
;
1827 /* Number of elements to write into the descriptor set binding */
1828 uint32_t array_count
;
1830 /* Offset into the user provided data */
1833 /* Stride between elements into the user provided data */
1837 struct anv_descriptor_update_template
{
1838 VkPipelineBindPoint bind_point
;
1840 /* The descriptor set this template corresponds to. This value is only
1841 * valid if the template was created with the templateType
1842 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1846 /* Number of entries in this template */
1847 uint32_t entry_count
;
1849 /* Entries of the template */
1850 struct anv_descriptor_template_entry entries
[0];
1854 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1857 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1858 struct anv_descriptor_set
*set
,
1859 const VkDescriptorImageInfo
* const info
,
1860 VkDescriptorType type
,
1865 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1866 struct anv_descriptor_set
*set
,
1867 VkDescriptorType type
,
1868 struct anv_buffer_view
*buffer_view
,
1873 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1874 struct anv_descriptor_set
*set
,
1875 struct anv_state_stream
*alloc_stream
,
1876 VkDescriptorType type
,
1877 struct anv_buffer
*buffer
,
1880 VkDeviceSize offset
,
1881 VkDeviceSize range
);
1883 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1884 struct anv_descriptor_set
*set
,
1891 anv_descriptor_set_write_template(struct anv_device
*device
,
1892 struct anv_descriptor_set
*set
,
1893 struct anv_state_stream
*alloc_stream
,
1894 const struct anv_descriptor_update_template
*template,
1898 anv_descriptor_set_create(struct anv_device
*device
,
1899 struct anv_descriptor_pool
*pool
,
1900 struct anv_descriptor_set_layout
*layout
,
1901 struct anv_descriptor_set
**out_set
);
1904 anv_descriptor_set_destroy(struct anv_device
*device
,
1905 struct anv_descriptor_pool
*pool
,
1906 struct anv_descriptor_set
*set
);
1908 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1909 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1910 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1911 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1913 struct anv_pipeline_binding
{
1914 /* The descriptor set this surface corresponds to. The special value of
1915 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1916 * to a color attachment and not a regular descriptor.
1920 /* Binding in the descriptor set */
1923 /* Index in the binding */
1926 /* Plane in the binding index */
1929 /* Input attachment index (relative to the subpass) */
1930 uint8_t input_attachment_index
;
1932 /* For a storage image, whether it is write-only */
1936 struct anv_pipeline_layout
{
1938 struct anv_descriptor_set_layout
*layout
;
1939 uint32_t dynamic_offset_start
;
1944 unsigned char sha1
[20];
1948 struct anv_device
* device
;
1951 VkBufferUsageFlags usage
;
1953 /* Set when bound */
1954 struct anv_address address
;
1957 static inline uint64_t
1958 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1960 assert(offset
<= buffer
->size
);
1961 if (range
== VK_WHOLE_SIZE
) {
1962 return buffer
->size
- offset
;
1964 assert(range
+ offset
>= range
);
1965 assert(range
+ offset
<= buffer
->size
);
1970 enum anv_cmd_dirty_bits
{
1971 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1972 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1973 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1974 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1975 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1976 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1977 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1978 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1979 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1980 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1981 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1982 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1983 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1984 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
1986 typedef uint32_t anv_cmd_dirty_mask_t
;
1988 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
1989 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
1990 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
1991 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
1992 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
1993 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
1994 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
1995 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
1996 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
1997 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
1998 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2000 static inline enum anv_cmd_dirty_bits
2001 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2004 case VK_DYNAMIC_STATE_VIEWPORT
:
2005 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2006 case VK_DYNAMIC_STATE_SCISSOR
:
2007 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2008 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2009 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2010 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2011 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2012 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2013 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2014 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2015 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2016 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2017 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2018 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2019 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2020 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2021 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2022 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2023 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2025 assert(!"Unsupported dynamic state");
2031 enum anv_pipe_bits
{
2032 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2033 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2034 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2035 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2036 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2037 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2038 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2039 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2040 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2041 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2042 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2044 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2045 * a flush has happened but not a CS stall. The next time we do any sort
2046 * of invalidation we need to insert a CS stall at that time. Otherwise,
2047 * we would have to CS stall on every flush which could be bad.
2049 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2051 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2052 * target operations related to transfer commands with VkBuffer as
2053 * destination are ongoing. Some operations like copies on the command
2054 * streamer might need to be aware of this to trigger the appropriate stall
2055 * before they can proceed with the copy.
2057 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2060 #define ANV_PIPE_FLUSH_BITS ( \
2061 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2062 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2063 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
2065 #define ANV_PIPE_STALL_BITS ( \
2066 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2067 ANV_PIPE_DEPTH_STALL_BIT | \
2068 ANV_PIPE_CS_STALL_BIT)
2070 #define ANV_PIPE_INVALIDATE_BITS ( \
2071 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2072 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2073 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2074 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2075 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2076 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2078 static inline enum anv_pipe_bits
2079 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2081 enum anv_pipe_bits pipe_bits
= 0;
2084 for_each_bit(b
, flags
) {
2085 switch ((VkAccessFlagBits
)(1 << b
)) {
2086 case VK_ACCESS_SHADER_WRITE_BIT
:
2087 /* We're transitioning a buffer that was previously used as write
2088 * destination through the data port. To make its content available
2089 * to future operations, flush the data cache.
2091 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2093 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2094 /* We're transitioning a buffer that was previously used as render
2095 * target. To make its content available to future operations, flush
2096 * the render target cache.
2098 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2100 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2101 /* We're transitioning a buffer that was previously used as depth
2102 * buffer. To make its content available to future operations, flush
2105 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2107 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2108 /* We're transitioning a buffer that was previously used as a
2109 * transfer write destination. Generic write operations include color
2110 * & depth operations as well as buffer operations like :
2111 * - vkCmdClearColorImage()
2112 * - vkCmdClearDepthStencilImage()
2113 * - vkCmdBlitImage()
2114 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2116 * Most of these operations are implemented using Blorp which writes
2117 * through the render target, so flush that cache to make it visible
2118 * to future operations. And for depth related operations we also
2119 * need to flush the depth cache.
2121 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2122 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2124 case VK_ACCESS_MEMORY_WRITE_BIT
:
2125 /* We're transitioning a buffer for generic write operations. Flush
2128 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2131 break; /* Nothing to do */
2138 static inline enum anv_pipe_bits
2139 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2141 enum anv_pipe_bits pipe_bits
= 0;
2144 for_each_bit(b
, flags
) {
2145 switch ((VkAccessFlagBits
)(1 << b
)) {
2146 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2147 /* Indirect draw commands take a buffer as input that we're going to
2148 * read from the command streamer to load some of the HW registers
2149 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2150 * command streamer stall so that all the cache flushes have
2151 * completed before the command streamer loads from memory.
2153 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2154 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2155 * through a vertex buffer, so invalidate that cache.
2157 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2158 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2159 * UBO from the buffer, so we need to invalidate constant cache.
2161 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2163 case VK_ACCESS_INDEX_READ_BIT
:
2164 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2165 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2166 * commands, so we invalidate the VF cache to make sure there is no
2167 * stale data when we start rendering.
2169 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2171 case VK_ACCESS_UNIFORM_READ_BIT
:
2172 /* We transitioning a buffer to be used as uniform data. Because
2173 * uniform is accessed through the data port & sampler, we need to
2174 * invalidate the texture cache (sampler) & constant cache (data
2175 * port) to avoid stale data.
2177 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2178 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2180 case VK_ACCESS_SHADER_READ_BIT
:
2181 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2182 case VK_ACCESS_TRANSFER_READ_BIT
:
2183 /* Transitioning a buffer to be read through the sampler, so
2184 * invalidate the texture cache, we don't want any stale data.
2186 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2188 case VK_ACCESS_MEMORY_READ_BIT
:
2189 /* Transitioning a buffer for generic read, invalidate all the
2192 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2194 case VK_ACCESS_MEMORY_WRITE_BIT
:
2195 /* Generic write, make sure all previously written things land in
2198 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2200 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2201 /* Transitioning a buffer for conditional rendering. We'll load the
2202 * content of this buffer into HW registers using the command
2203 * streamer, so we need to stall the command streamer to make sure
2204 * any in-flight flush operations have completed.
2206 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2209 break; /* Nothing to do */
2216 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2217 VK_IMAGE_ASPECT_COLOR_BIT | \
2218 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2219 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2220 VK_IMAGE_ASPECT_PLANE_2_BIT)
2221 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2222 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2223 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2224 VK_IMAGE_ASPECT_PLANE_2_BIT)
2226 struct anv_vertex_binding
{
2227 struct anv_buffer
* buffer
;
2228 VkDeviceSize offset
;
2231 struct anv_xfb_binding
{
2232 struct anv_buffer
* buffer
;
2233 VkDeviceSize offset
;
2237 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2238 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2239 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2241 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2242 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2243 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2245 struct anv_push_constants
{
2246 /* Push constant data provided by the client through vkPushConstants */
2247 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2249 /* Used for vkCmdDispatchBase */
2250 uint32_t base_work_group_id
[3];
2253 struct anv_dynamic_state
{
2256 VkViewport viewports
[MAX_VIEWPORTS
];
2261 VkRect2D scissors
[MAX_SCISSORS
];
2272 float blend_constants
[4];
2282 } stencil_compare_mask
;
2287 } stencil_write_mask
;
2292 } stencil_reference
;
2300 extern const struct anv_dynamic_state default_dynamic_state
;
2302 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2303 const struct anv_dynamic_state
*src
,
2304 uint32_t copy_mask
);
2306 struct anv_surface_state
{
2307 struct anv_state state
;
2308 /** Address of the surface referred to by this state
2310 * This address is relative to the start of the BO.
2312 struct anv_address address
;
2313 /* Address of the aux surface, if any
2315 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2317 * With the exception of gen8, the bottom 12 bits of this address' offset
2318 * include extra aux information.
2320 struct anv_address aux_address
;
2321 /* Address of the clear color, if any
2323 * This address is relative to the start of the BO.
2325 struct anv_address clear_address
;
2329 * Attachment state when recording a renderpass instance.
2331 * The clear value is valid only if there exists a pending clear.
2333 struct anv_attachment_state
{
2334 enum isl_aux_usage aux_usage
;
2335 enum isl_aux_usage input_aux_usage
;
2336 struct anv_surface_state color
;
2337 struct anv_surface_state input
;
2339 VkImageLayout current_layout
;
2340 VkImageAspectFlags pending_clear_aspects
;
2341 VkImageAspectFlags pending_load_aspects
;
2343 VkClearValue clear_value
;
2344 bool clear_color_is_zero_one
;
2345 bool clear_color_is_zero
;
2347 /* When multiview is active, attachments with a renderpass clear
2348 * operation have their respective layers cleared on the first
2349 * subpass that uses them, and only in that subpass. We keep track
2350 * of this using a bitfield to indicate which layers of an attachment
2351 * have not been cleared yet when multiview is active.
2353 uint32_t pending_clear_views
;
2354 struct anv_image_view
* image_view
;
2357 /** State tracking for particular pipeline bind point
2359 * This struct is the base struct for anv_cmd_graphics_state and
2360 * anv_cmd_compute_state. These are used to track state which is bound to a
2361 * particular type of pipeline. Generic state that applies per-stage such as
2362 * binding table offsets and push constants is tracked generically with a
2363 * per-stage array in anv_cmd_state.
2365 struct anv_cmd_pipeline_state
{
2366 struct anv_pipeline
*pipeline
;
2367 struct anv_pipeline_layout
*layout
;
2369 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2370 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2372 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2375 /** State tracking for graphics pipeline
2377 * This has anv_cmd_pipeline_state as a base struct to track things which get
2378 * bound to a graphics pipeline. Along with general pipeline bind point state
2379 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2380 * state which is graphics-specific.
2382 struct anv_cmd_graphics_state
{
2383 struct anv_cmd_pipeline_state base
;
2385 anv_cmd_dirty_mask_t dirty
;
2388 struct anv_dynamic_state dynamic
;
2391 struct anv_buffer
*index_buffer
;
2392 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2393 uint32_t index_offset
;
2397 /** State tracking for compute pipeline
2399 * This has anv_cmd_pipeline_state as a base struct to track things which get
2400 * bound to a compute pipeline. Along with general pipeline bind point state
2401 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2402 * state which is compute-specific.
2404 struct anv_cmd_compute_state
{
2405 struct anv_cmd_pipeline_state base
;
2407 bool pipeline_dirty
;
2409 struct anv_address num_workgroups
;
2412 /** State required while building cmd buffer */
2413 struct anv_cmd_state
{
2414 /* PIPELINE_SELECT.PipelineSelection */
2415 uint32_t current_pipeline
;
2416 const struct gen_l3_config
* current_l3_config
;
2417 uint32_t last_aux_map_state
;
2419 struct anv_cmd_graphics_state gfx
;
2420 struct anv_cmd_compute_state compute
;
2422 enum anv_pipe_bits pending_pipe_bits
;
2423 VkShaderStageFlags descriptors_dirty
;
2424 VkShaderStageFlags push_constants_dirty
;
2426 struct anv_framebuffer
* framebuffer
;
2427 struct anv_render_pass
* pass
;
2428 struct anv_subpass
* subpass
;
2429 VkRect2D render_area
;
2430 uint32_t restart_index
;
2431 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2433 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2434 VkShaderStageFlags push_constant_stages
;
2435 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2436 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2437 struct anv_state samplers
[MESA_SHADER_STAGES
];
2440 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2441 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2442 * and before invoking the secondary in ExecuteCommands.
2444 bool pma_fix_enabled
;
2447 * Whether or not we know for certain that HiZ is enabled for the current
2448 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2449 * enabled or not, this will be false.
2453 bool conditional_render_enabled
;
2456 * Last rendering scale argument provided to
2457 * genX(cmd_buffer_emit_hashing_mode)().
2459 unsigned current_hash_scale
;
2462 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2463 * valid only when recording a render pass instance.
2465 struct anv_attachment_state
* attachments
;
2468 * Surface states for color render targets. These are stored in a single
2469 * flat array. For depth-stencil attachments, the surface state is simply
2472 struct anv_state render_pass_states
;
2475 * A null surface state of the right size to match the framebuffer. This
2476 * is one of the states in render_pass_states.
2478 struct anv_state null_surface_state
;
2481 struct anv_cmd_pool
{
2482 VkAllocationCallbacks alloc
;
2483 struct list_head cmd_buffers
;
2486 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2488 enum anv_cmd_buffer_exec_mode
{
2489 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2490 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2491 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2492 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2493 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2496 struct anv_cmd_buffer
{
2497 VK_LOADER_DATA _loader_data
;
2499 struct anv_device
* device
;
2501 struct anv_cmd_pool
* pool
;
2502 struct list_head pool_link
;
2504 struct anv_batch batch
;
2506 /* Fields required for the actual chain of anv_batch_bo's.
2508 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2510 struct list_head batch_bos
;
2511 enum anv_cmd_buffer_exec_mode exec_mode
;
2513 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2514 * referenced by this command buffer
2516 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2518 struct u_vector seen_bbos
;
2520 /* A vector of int32_t's for every block of binding tables.
2522 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2524 struct u_vector bt_block_states
;
2527 struct anv_reloc_list surface_relocs
;
2528 /** Last seen surface state block pool center bo offset */
2529 uint32_t last_ss_pool_center
;
2531 /* Serial for tracking buffer completion */
2534 /* Stream objects for storing temporary data */
2535 struct anv_state_stream surface_state_stream
;
2536 struct anv_state_stream dynamic_state_stream
;
2538 VkCommandBufferUsageFlags usage_flags
;
2539 VkCommandBufferLevel level
;
2541 struct anv_cmd_state state
;
2543 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2544 uint64_t intel_perf_marker
;
2547 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2548 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2549 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2550 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2551 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2552 struct anv_cmd_buffer
*secondary
);
2553 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2554 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2555 struct anv_cmd_buffer
*cmd_buffer
,
2556 const VkSemaphore
*in_semaphores
,
2557 uint32_t num_in_semaphores
,
2558 const VkSemaphore
*out_semaphores
,
2559 uint32_t num_out_semaphores
,
2562 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2564 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2565 const void *data
, uint32_t size
, uint32_t alignment
);
2566 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2567 uint32_t *a
, uint32_t *b
,
2568 uint32_t dwords
, uint32_t alignment
);
2571 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2573 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2574 uint32_t entries
, uint32_t *state_offset
);
2576 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2578 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2579 uint32_t size
, uint32_t alignment
);
2582 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2584 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2585 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2586 bool depth_clamp_enable
);
2587 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2589 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2590 struct anv_render_pass
*pass
,
2591 struct anv_framebuffer
*framebuffer
,
2592 const VkClearValue
*clear_values
);
2594 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2597 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2598 gl_shader_stage stage
);
2600 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2602 const struct anv_image_view
*
2603 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2606 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2607 uint32_t num_entries
,
2608 uint32_t *state_offset
,
2609 struct anv_state
*bt_state
);
2611 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2613 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2615 enum anv_fence_type
{
2616 ANV_FENCE_TYPE_NONE
= 0,
2618 ANV_FENCE_TYPE_SYNCOBJ
,
2622 enum anv_bo_fence_state
{
2623 /** Indicates that this is a new (or newly reset fence) */
2624 ANV_BO_FENCE_STATE_RESET
,
2626 /** Indicates that this fence has been submitted to the GPU but is still
2627 * (as far as we know) in use by the GPU.
2629 ANV_BO_FENCE_STATE_SUBMITTED
,
2631 ANV_BO_FENCE_STATE_SIGNALED
,
2634 struct anv_fence_impl
{
2635 enum anv_fence_type type
;
2638 /** Fence implementation for BO fences
2640 * These fences use a BO and a set of CPU-tracked state flags. The BO
2641 * is added to the object list of the last execbuf call in a QueueSubmit
2642 * and is marked EXEC_WRITE. The state flags track when the BO has been
2643 * submitted to the kernel. We need to do this because Vulkan lets you
2644 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2645 * will say it's idle in this case.
2649 enum anv_bo_fence_state state
;
2652 /** DRM syncobj handle for syncobj-based fences */
2656 struct wsi_fence
*fence_wsi
;
2661 /* Permanent fence state. Every fence has some form of permanent state
2662 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2663 * cross-process fences) or it could just be a dummy for use internally.
2665 struct anv_fence_impl permanent
;
2667 /* Temporary fence state. A fence *may* have temporary state. That state
2668 * is added to the fence by an import operation and is reset back to
2669 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2670 * state cannot be signaled because the fence must already be signaled
2671 * before the temporary state can be exported from the fence in the other
2672 * process and imported here.
2674 struct anv_fence_impl temporary
;
2679 struct anv_state state
;
2682 enum anv_semaphore_type
{
2683 ANV_SEMAPHORE_TYPE_NONE
= 0,
2684 ANV_SEMAPHORE_TYPE_DUMMY
,
2685 ANV_SEMAPHORE_TYPE_BO
,
2686 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2687 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2690 struct anv_semaphore_impl
{
2691 enum anv_semaphore_type type
;
2694 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2695 * This BO will be added to the object list on any execbuf2 calls for
2696 * which this semaphore is used as a wait or signal fence. When used as
2697 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2701 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2702 * If the semaphore is in the unsignaled state due to either just being
2703 * created or because it has been used for a wait, fd will be -1.
2707 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2708 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2709 * import so we don't need to bother with a userspace cache.
2715 struct anv_semaphore
{
2716 /* Permanent semaphore state. Every semaphore has some form of permanent
2717 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2718 * (for cross-process semaphores0 or it could just be a dummy for use
2721 struct anv_semaphore_impl permanent
;
2723 /* Temporary semaphore state. A semaphore *may* have temporary state.
2724 * That state is added to the semaphore by an import operation and is reset
2725 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2726 * semaphore with temporary state cannot be signaled because the semaphore
2727 * must already be signaled before the temporary state can be exported from
2728 * the semaphore in the other process and imported here.
2730 struct anv_semaphore_impl temporary
;
2733 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2734 struct anv_semaphore
*semaphore
);
2736 struct anv_shader_module
{
2737 unsigned char sha1
[20];
2742 static inline gl_shader_stage
2743 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2745 assert(__builtin_popcount(vk_stage
) == 1);
2746 return ffs(vk_stage
) - 1;
2749 static inline VkShaderStageFlagBits
2750 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2752 return (1 << mesa_stage
);
2755 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2757 #define anv_foreach_stage(stage, stage_bits) \
2758 for (gl_shader_stage stage, \
2759 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2760 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2761 __tmp &= ~(1 << (stage)))
2763 struct anv_pipeline_bind_map
{
2764 uint32_t surface_count
;
2765 uint32_t sampler_count
;
2767 struct anv_pipeline_binding
* surface_to_descriptor
;
2768 struct anv_pipeline_binding
* sampler_to_descriptor
;
2771 struct anv_shader_bin_key
{
2776 struct anv_shader_bin
{
2779 const struct anv_shader_bin_key
*key
;
2781 struct anv_state kernel
;
2782 uint32_t kernel_size
;
2784 struct anv_state constant_data
;
2785 uint32_t constant_data_size
;
2787 const struct brw_stage_prog_data
*prog_data
;
2788 uint32_t prog_data_size
;
2790 struct brw_compile_stats stats
[3];
2793 struct nir_xfb_info
*xfb_info
;
2795 struct anv_pipeline_bind_map bind_map
;
2798 struct anv_shader_bin
*
2799 anv_shader_bin_create(struct anv_device
*device
,
2800 const void *key
, uint32_t key_size
,
2801 const void *kernel
, uint32_t kernel_size
,
2802 const void *constant_data
, uint32_t constant_data_size
,
2803 const struct brw_stage_prog_data
*prog_data
,
2804 uint32_t prog_data_size
, const void *prog_data_param
,
2805 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2806 const struct nir_xfb_info
*xfb_info
,
2807 const struct anv_pipeline_bind_map
*bind_map
);
2810 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2813 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2815 assert(shader
&& shader
->ref_cnt
>= 1);
2816 p_atomic_inc(&shader
->ref_cnt
);
2820 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2822 assert(shader
&& shader
->ref_cnt
>= 1);
2823 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2824 anv_shader_bin_destroy(device
, shader
);
2827 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2828 #define MAX_PIPELINE_EXECUTABLES 7
2830 struct anv_pipeline_executable
{
2831 gl_shader_stage stage
;
2833 struct brw_compile_stats stats
;
2839 struct anv_pipeline
{
2840 struct anv_device
* device
;
2841 struct anv_batch batch
;
2842 uint32_t batch_data
[512];
2843 struct anv_reloc_list batch_relocs
;
2844 anv_cmd_dirty_mask_t dynamic_state_mask
;
2845 struct anv_dynamic_state dynamic_state
;
2849 VkPipelineCreateFlags flags
;
2850 struct anv_subpass
* subpass
;
2852 bool needs_data_cache
;
2854 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2856 uint32_t num_executables
;
2857 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2860 const struct gen_l3_config
* l3_config
;
2861 uint32_t total_size
;
2864 VkShaderStageFlags active_stages
;
2865 struct anv_state blend_state
;
2868 struct anv_pipeline_vertex_binding
{
2871 uint32_t instance_divisor
;
2876 bool primitive_restart
;
2879 uint32_t cs_right_mask
;
2882 bool depth_test_enable
;
2883 bool writes_stencil
;
2884 bool stencil_test_enable
;
2885 bool depth_clamp_enable
;
2886 bool depth_clip_enable
;
2887 bool sample_shading_enable
;
2889 bool depth_bounds_test_enable
;
2893 uint32_t depth_stencil_state
[3];
2899 uint32_t wm_depth_stencil
[3];
2903 uint32_t wm_depth_stencil
[4];
2906 uint32_t interface_descriptor_data
[8];
2910 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2911 gl_shader_stage stage
)
2913 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2916 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2917 static inline const struct brw_##prefix##_prog_data * \
2918 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2920 if (anv_pipeline_has_stage(pipeline, stage)) { \
2921 return (const struct brw_##prefix##_prog_data *) \
2922 pipeline->shaders[stage]->prog_data; \
2928 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2929 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2930 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2931 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2932 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2933 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2935 static inline const struct brw_vue_prog_data
*
2936 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2938 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2939 return &get_gs_prog_data(pipeline
)->base
;
2940 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2941 return &get_tes_prog_data(pipeline
)->base
;
2943 return &get_vs_prog_data(pipeline
)->base
;
2947 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2948 struct anv_pipeline_cache
*cache
,
2949 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2950 const VkAllocationCallbacks
*alloc
);
2953 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2954 struct anv_pipeline_cache
*cache
,
2955 const VkComputePipelineCreateInfo
*info
,
2956 const struct anv_shader_module
*module
,
2957 const char *entrypoint
,
2958 const VkSpecializationInfo
*spec_info
);
2960 struct anv_format_plane
{
2961 enum isl_format isl_format
:16;
2962 struct isl_swizzle swizzle
;
2964 /* Whether this plane contains chroma channels */
2967 /* For downscaling of YUV planes */
2968 uint8_t denominator_scales
[2];
2970 /* How to map sampled ycbcr planes to a single 4 component element. */
2971 struct isl_swizzle ycbcr_swizzle
;
2973 /* What aspect is associated to this plane */
2974 VkImageAspectFlags aspect
;
2979 struct anv_format_plane planes
[3];
2985 static inline uint32_t
2986 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2987 VkImageAspectFlags aspect_mask
)
2989 switch (aspect_mask
) {
2990 case VK_IMAGE_ASPECT_COLOR_BIT
:
2991 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2992 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2994 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2995 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2998 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3000 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3003 /* Purposefully assert with depth/stencil aspects. */
3004 unreachable("invalid image aspect");
3008 static inline VkImageAspectFlags
3009 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3012 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3013 if (util_bitcount(image_aspects
) > 1)
3014 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3015 return VK_IMAGE_ASPECT_COLOR_BIT
;
3017 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3018 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3019 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3020 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3023 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3024 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3026 const struct anv_format
*
3027 anv_get_format(VkFormat format
);
3029 static inline uint32_t
3030 anv_get_format_planes(VkFormat vk_format
)
3032 const struct anv_format
*format
= anv_get_format(vk_format
);
3034 return format
!= NULL
? format
->n_planes
: 0;
3037 struct anv_format_plane
3038 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3039 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3041 static inline enum isl_format
3042 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3043 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3045 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3048 static inline struct isl_swizzle
3049 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3051 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3052 * RGB as RGBA for texturing
3054 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3055 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3057 /* But it doesn't matter what we render to that channel */
3058 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3064 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3067 * Subsurface of an anv_image.
3069 struct anv_surface
{
3070 /** Valid only if isl_surf::size_B > 0. */
3071 struct isl_surf isl
;
3074 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3080 VkImageType type
; /**< VkImageCreateInfo::imageType */
3081 /* The original VkFormat provided by the client. This may not match any
3082 * of the actual surface formats.
3085 const struct anv_format
*format
;
3087 VkImageAspectFlags aspects
;
3090 uint32_t array_size
;
3091 uint32_t samples
; /**< VkImageCreateInfo::samples */
3093 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3094 VkImageUsageFlags stencil_usage
;
3095 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3096 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3098 /** True if this is needs to be bound to an appropriately tiled BO.
3100 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3101 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3102 * we require a dedicated allocation so that we can know to allocate a
3105 bool needs_set_tiling
;
3108 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3109 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3111 uint64_t drm_format_mod
;
3116 /* Whether the image is made of several underlying buffer objects rather a
3117 * single one with different offsets.
3121 /* All the formats that can be used when creating views of this image
3122 * are CCS_E compatible.
3124 bool ccs_e_compatible
;
3126 /* Image was created with external format. */
3127 bool external_format
;
3132 * For each foo, anv_image::planes[x].surface is valid if and only if
3133 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3134 * to figure the number associated with a given aspect.
3136 * The hardware requires that the depth buffer and stencil buffer be
3137 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3138 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3139 * allocate the depth and stencil buffers as separate surfaces in the same
3144 * -----------------------
3146 * ----------------------- |
3147 * | shadow surface0 | |
3148 * ----------------------- | Plane 0
3149 * | aux surface0 | |
3150 * ----------------------- |
3151 * | fast clear colors0 | \|/
3152 * -----------------------
3154 * ----------------------- |
3155 * | shadow surface1 | |
3156 * ----------------------- | Plane 1
3157 * | aux surface1 | |
3158 * ----------------------- |
3159 * | fast clear colors1 | \|/
3160 * -----------------------
3163 * -----------------------
3167 * Offset of the entire plane (whenever the image is disjoint this is
3175 struct anv_surface surface
;
3178 * A surface which shadows the main surface and may have different
3179 * tiling. This is used for sampling using a tiling that isn't supported
3180 * for other operations.
3182 struct anv_surface shadow_surface
;
3185 * For color images, this is the aux usage for this image when not used
3186 * as a color attachment.
3188 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3189 * image has a HiZ buffer.
3191 enum isl_aux_usage aux_usage
;
3193 struct anv_surface aux_surface
;
3196 * Offset of the fast clear state (used to compute the
3197 * fast_clear_state_offset of the following planes).
3199 uint32_t fast_clear_state_offset
;
3202 * BO associated with this plane, set when bound.
3204 struct anv_address address
;
3207 * Address of the main surface used to fill the aux map table. This is
3208 * used at destruction of the image since the Vulkan spec does not
3209 * guarantee that the address.bo field we still be valid at destruction.
3211 uint64_t aux_map_surface_address
;
3214 * When destroying the image, also free the bo.
3220 /* The ordering of this enum is important */
3221 enum anv_fast_clear_type
{
3222 /** Image does not have/support any fast-clear blocks */
3223 ANV_FAST_CLEAR_NONE
= 0,
3224 /** Image has/supports fast-clear but only to the default value */
3225 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3226 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3227 ANV_FAST_CLEAR_ANY
= 2,
3230 /* Returns the number of auxiliary buffer levels attached to an image. */
3231 static inline uint8_t
3232 anv_image_aux_levels(const struct anv_image
* const image
,
3233 VkImageAspectFlagBits aspect
)
3235 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3236 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3237 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
3240 /* Returns the number of auxiliary buffer layers attached to an image. */
3241 static inline uint32_t
3242 anv_image_aux_layers(const struct anv_image
* const image
,
3243 VkImageAspectFlagBits aspect
,
3244 const uint8_t miplevel
)
3248 /* The miplevel must exist in the main buffer. */
3249 assert(miplevel
< image
->levels
);
3251 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3252 /* There are no layers with auxiliary data because the miplevel has no
3257 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3258 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
3259 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
3263 static inline struct anv_address
3264 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3265 const struct anv_image
*image
,
3266 VkImageAspectFlagBits aspect
)
3268 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3270 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3271 return anv_address_add(image
->planes
[plane
].address
,
3272 image
->planes
[plane
].fast_clear_state_offset
);
3275 static inline struct anv_address
3276 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3277 const struct anv_image
*image
,
3278 VkImageAspectFlagBits aspect
)
3280 struct anv_address addr
=
3281 anv_image_get_clear_color_addr(device
, image
, aspect
);
3283 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3284 device
->isl_dev
.ss
.clear_color_state_size
:
3285 device
->isl_dev
.ss
.clear_value_size
;
3286 return anv_address_add(addr
, clear_color_state_size
);
3289 static inline struct anv_address
3290 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3291 const struct anv_image
*image
,
3292 VkImageAspectFlagBits aspect
,
3293 uint32_t level
, uint32_t array_layer
)
3295 assert(level
< anv_image_aux_levels(image
, aspect
));
3296 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3297 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3298 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3300 struct anv_address addr
=
3301 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3302 addr
.offset
+= 4; /* Go past the fast clear type */
3304 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3305 for (uint32_t l
= 0; l
< level
; l
++)
3306 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3308 addr
.offset
+= level
* image
->array_size
* 4;
3310 addr
.offset
+= array_layer
* 4;
3312 assert(addr
.offset
<
3313 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3317 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3319 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3320 const struct anv_image
*image
)
3322 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3325 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3326 * struct. There's documentation which suggests that this feature actually
3327 * reduces performance on BDW, but it has only been observed to help so
3328 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3329 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3331 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3334 return image
->samples
== 1;
3338 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3339 const struct anv_image
*image
,
3342 return device
->info
.has_aux_map
&&
3343 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3347 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3348 const struct anv_image
*image
,
3349 VkImageAspectFlagBits aspect
,
3350 enum isl_aux_usage aux_usage
,
3352 uint32_t base_layer
,
3353 uint32_t layer_count
);
3356 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3357 const struct anv_image
*image
,
3358 VkImageAspectFlagBits aspect
,
3359 enum isl_aux_usage aux_usage
,
3360 enum isl_format format
, struct isl_swizzle swizzle
,
3361 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3362 VkRect2D area
, union isl_color_value clear_color
);
3364 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3365 const struct anv_image
*image
,
3366 VkImageAspectFlags aspects
,
3367 enum isl_aux_usage depth_aux_usage
,
3369 uint32_t base_layer
, uint32_t layer_count
,
3371 float depth_value
, uint8_t stencil_value
);
3373 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3374 const struct anv_image
*src_image
,
3375 enum isl_aux_usage src_aux_usage
,
3376 uint32_t src_level
, uint32_t src_base_layer
,
3377 const struct anv_image
*dst_image
,
3378 enum isl_aux_usage dst_aux_usage
,
3379 uint32_t dst_level
, uint32_t dst_base_layer
,
3380 VkImageAspectFlagBits aspect
,
3381 uint32_t src_x
, uint32_t src_y
,
3382 uint32_t dst_x
, uint32_t dst_y
,
3383 uint32_t width
, uint32_t height
,
3384 uint32_t layer_count
,
3385 enum blorp_filter filter
);
3387 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3388 const struct anv_image
*image
,
3389 VkImageAspectFlagBits aspect
, uint32_t level
,
3390 uint32_t base_layer
, uint32_t layer_count
,
3391 enum isl_aux_op hiz_op
);
3393 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3394 const struct anv_image
*image
,
3395 VkImageAspectFlags aspects
,
3397 uint32_t base_layer
, uint32_t layer_count
,
3398 VkRect2D area
, uint8_t stencil_value
);
3400 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3401 const struct anv_image
*image
,
3402 enum isl_format format
,
3403 VkImageAspectFlagBits aspect
,
3404 uint32_t base_layer
, uint32_t layer_count
,
3405 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3408 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3409 const struct anv_image
*image
,
3410 enum isl_format format
,
3411 VkImageAspectFlagBits aspect
, uint32_t level
,
3412 uint32_t base_layer
, uint32_t layer_count
,
3413 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3417 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3418 const struct anv_image
*image
,
3419 VkImageAspectFlagBits aspect
,
3420 uint32_t base_level
, uint32_t level_count
,
3421 uint32_t base_layer
, uint32_t layer_count
);
3424 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3425 const struct anv_image
*image
,
3426 const VkImageAspectFlagBits aspect
,
3427 const VkImageLayout layout
);
3429 enum anv_fast_clear_type
3430 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3431 const struct anv_image
* const image
,
3432 const VkImageAspectFlagBits aspect
,
3433 const VkImageLayout layout
);
3435 /* This is defined as a macro so that it works for both
3436 * VkImageSubresourceRange and VkImageSubresourceLayers
3438 #define anv_get_layerCount(_image, _range) \
3439 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3440 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3442 static inline uint32_t
3443 anv_get_levelCount(const struct anv_image
*image
,
3444 const VkImageSubresourceRange
*range
)
3446 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3447 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3450 static inline VkImageAspectFlags
3451 anv_image_expand_aspects(const struct anv_image
*image
,
3452 VkImageAspectFlags aspects
)
3454 /* If the underlying image has color plane aspects and
3455 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3456 * the underlying image. */
3457 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3458 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3459 return image
->aspects
;
3465 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3466 VkImageAspectFlags aspects2
)
3468 if (aspects1
== aspects2
)
3471 /* Only 1 color aspects are compatibles. */
3472 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3473 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3474 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3480 struct anv_image_view
{
3481 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3483 VkImageAspectFlags aspect_mask
;
3485 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3489 uint32_t image_plane
;
3491 struct isl_view isl
;
3494 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3495 * image layout of SHADER_READ_ONLY_OPTIMAL or
3496 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3498 struct anv_surface_state optimal_sampler_surface_state
;
3501 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3502 * image layout of GENERAL.
3504 struct anv_surface_state general_sampler_surface_state
;
3507 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3508 * states for write-only and readable, using the real format for
3509 * write-only and the lowered format for readable.
3511 struct anv_surface_state storage_surface_state
;
3512 struct anv_surface_state writeonly_storage_surface_state
;
3514 struct brw_image_param storage_image_param
;
3518 enum anv_image_view_state_flags
{
3519 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3520 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3523 void anv_image_fill_surface_state(struct anv_device
*device
,
3524 const struct anv_image
*image
,
3525 VkImageAspectFlagBits aspect
,
3526 const struct isl_view
*view
,
3527 isl_surf_usage_flags_t view_usage
,
3528 enum isl_aux_usage aux_usage
,
3529 const union isl_color_value
*clear_color
,
3530 enum anv_image_view_state_flags flags
,
3531 struct anv_surface_state
*state_inout
,
3532 struct brw_image_param
*image_param_out
);
3534 struct anv_image_create_info
{
3535 const VkImageCreateInfo
*vk_info
;
3537 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3538 isl_tiling_flags_t isl_tiling_flags
;
3540 /** These flags will be added to any derived from VkImageCreateInfo. */
3541 isl_surf_usage_flags_t isl_extra_usage_flags
;
3544 bool external_format
;
3547 VkResult
anv_image_create(VkDevice _device
,
3548 const struct anv_image_create_info
*info
,
3549 const VkAllocationCallbacks
* alloc
,
3552 const struct anv_surface
*
3553 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3554 VkImageAspectFlags aspect_mask
);
3557 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3559 static inline struct VkExtent3D
3560 anv_sanitize_image_extent(const VkImageType imageType
,
3561 const struct VkExtent3D imageExtent
)
3563 switch (imageType
) {
3564 case VK_IMAGE_TYPE_1D
:
3565 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3566 case VK_IMAGE_TYPE_2D
:
3567 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3568 case VK_IMAGE_TYPE_3D
:
3571 unreachable("invalid image type");
3575 static inline struct VkOffset3D
3576 anv_sanitize_image_offset(const VkImageType imageType
,
3577 const struct VkOffset3D imageOffset
)
3579 switch (imageType
) {
3580 case VK_IMAGE_TYPE_1D
:
3581 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3582 case VK_IMAGE_TYPE_2D
:
3583 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3584 case VK_IMAGE_TYPE_3D
:
3587 unreachable("invalid image type");
3591 VkFormatFeatureFlags
3592 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3594 const struct anv_format
*anv_format
,
3595 VkImageTiling vk_tiling
);
3597 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3598 struct anv_state state
,
3599 enum isl_format format
,
3600 struct anv_address address
,
3601 uint32_t range
, uint32_t stride
);
3604 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3605 const struct anv_attachment_state
*att_state
,
3606 const struct anv_image_view
*iview
)
3608 const struct isl_format_layout
*view_fmtl
=
3609 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3611 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3612 if (view_fmtl->channels.c.bits) \
3613 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3615 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3616 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3617 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3618 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3620 #undef COPY_CLEAR_COLOR_CHANNEL
3624 struct anv_ycbcr_conversion
{
3625 const struct anv_format
* format
;
3626 VkSamplerYcbcrModelConversion ycbcr_model
;
3627 VkSamplerYcbcrRange ycbcr_range
;
3628 VkComponentSwizzle mapping
[4];
3629 VkChromaLocation chroma_offsets
[2];
3630 VkFilter chroma_filter
;
3631 bool chroma_reconstruction
;
3634 struct anv_sampler
{
3635 uint32_t state
[3][4];
3637 struct anv_ycbcr_conversion
*conversion
;
3639 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3640 * and with a 32-byte stride for use as bindless samplers.
3642 struct anv_state bindless_state
;
3645 struct anv_framebuffer
{
3650 uint32_t attachment_count
;
3651 struct anv_image_view
* attachments
[0];
3654 struct anv_subpass_attachment
{
3655 VkImageUsageFlagBits usage
;
3656 uint32_t attachment
;
3657 VkImageLayout layout
;
3660 struct anv_subpass
{
3661 uint32_t attachment_count
;
3664 * A pointer to all attachment references used in this subpass.
3665 * Only valid if ::attachment_count > 0.
3667 struct anv_subpass_attachment
* attachments
;
3668 uint32_t input_count
;
3669 struct anv_subpass_attachment
* input_attachments
;
3670 uint32_t color_count
;
3671 struct anv_subpass_attachment
* color_attachments
;
3672 struct anv_subpass_attachment
* resolve_attachments
;
3674 struct anv_subpass_attachment
* depth_stencil_attachment
;
3675 struct anv_subpass_attachment
* ds_resolve_attachment
;
3676 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3677 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3681 /** Subpass has a depth/stencil self-dependency */
3682 bool has_ds_self_dep
;
3684 /** Subpass has at least one color resolve attachment */
3685 bool has_color_resolve
;
3688 static inline unsigned
3689 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3691 return MAX2(1, util_bitcount(subpass
->view_mask
));
3694 struct anv_render_pass_attachment
{
3695 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3696 * its members individually.
3700 VkImageUsageFlags usage
;
3701 VkAttachmentLoadOp load_op
;
3702 VkAttachmentStoreOp store_op
;
3703 VkAttachmentLoadOp stencil_load_op
;
3704 VkImageLayout initial_layout
;
3705 VkImageLayout final_layout
;
3706 VkImageLayout first_subpass_layout
;
3708 /* The subpass id in which the attachment will be used last. */
3709 uint32_t last_subpass_idx
;
3712 struct anv_render_pass
{
3713 uint32_t attachment_count
;
3714 uint32_t subpass_count
;
3715 /* An array of subpass_count+1 flushes, one per subpass boundary */
3716 enum anv_pipe_bits
* subpass_flushes
;
3717 struct anv_render_pass_attachment
* attachments
;
3718 struct anv_subpass subpasses
[0];
3721 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3723 struct anv_query_pool
{
3725 VkQueryPipelineStatisticFlags pipeline_statistics
;
3726 /** Stride between slots, in bytes */
3728 /** Number of slots in this query pool */
3733 int anv_get_instance_entrypoint_index(const char *name
);
3734 int anv_get_device_entrypoint_index(const char *name
);
3735 int anv_get_physical_device_entrypoint_index(const char *name
);
3737 const char *anv_get_instance_entry_name(int index
);
3738 const char *anv_get_physical_device_entry_name(int index
);
3739 const char *anv_get_device_entry_name(int index
);
3742 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3743 const struct anv_instance_extension_table
*instance
);
3745 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3746 const struct anv_instance_extension_table
*instance
);
3748 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3749 const struct anv_instance_extension_table
*instance
,
3750 const struct anv_device_extension_table
*device
);
3752 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3755 void anv_dump_image_to_ppm(struct anv_device
*device
,
3756 struct anv_image
*image
, unsigned miplevel
,
3757 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3758 const char *filename
);
3760 enum anv_dump_action
{
3761 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3764 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3765 void anv_dump_finish(void);
3767 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3769 static inline uint32_t
3770 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3772 /* This function must be called from within a subpass. */
3773 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3775 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3777 /* The id of this subpass shouldn't exceed the number of subpasses in this
3778 * render pass minus 1.
3780 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3784 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
3785 void anv_device_perf_init(struct anv_device
*device
);
3787 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3789 static inline struct __anv_type * \
3790 __anv_type ## _from_handle(__VkType _handle) \
3792 return (struct __anv_type *) _handle; \
3795 static inline __VkType \
3796 __anv_type ## _to_handle(struct __anv_type *_obj) \
3798 return (__VkType) _obj; \
3801 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3803 static inline struct __anv_type * \
3804 __anv_type ## _from_handle(__VkType _handle) \
3806 return (struct __anv_type *)(uintptr_t) _handle; \
3809 static inline __VkType \
3810 __anv_type ## _to_handle(struct __anv_type *_obj) \
3812 return (__VkType)(uintptr_t) _obj; \
3815 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3816 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3818 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3819 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3820 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3821 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3822 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3824 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3825 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3826 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3827 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3828 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3829 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3830 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3831 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3832 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3833 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3834 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3835 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3836 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3837 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3838 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3839 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3840 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3841 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3842 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3843 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3844 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3845 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3846 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3848 /* Gen-specific function declarations */
3850 # include "anv_genX.h"
3852 # define genX(x) gen7_##x
3853 # include "anv_genX.h"
3855 # define genX(x) gen75_##x
3856 # include "anv_genX.h"
3858 # define genX(x) gen8_##x
3859 # include "anv_genX.h"
3861 # define genX(x) gen9_##x
3862 # include "anv_genX.h"
3864 # define genX(x) gen10_##x
3865 # include "anv_genX.h"
3867 # define genX(x) gen11_##x
3868 # include "anv_genX.h"
3870 # define genX(x) gen12_##x
3871 # include "anv_genX.h"
3875 #endif /* ANV_PRIVATE_H */