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vulkan: move anv VK_EXT_debug_report implementation to common code.
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 /* Pre-declarations needed for WSI entrypoints */
56 struct wl_surface;
57 struct wl_display;
58 typedef struct xcb_connection_t xcb_connection_t;
59 typedef uint32_t xcb_visualid_t;
60 typedef uint32_t xcb_window_t;
61
62 struct anv_buffer;
63 struct anv_buffer_view;
64 struct anv_image_view;
65 struct anv_instance;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "isl/isl.h"
76
77 #include "common/gen_debug.h"
78 #include "common/intel_log.h"
79 #include "wsi_common.h"
80
81 /* Allowing different clear colors requires us to perform a depth resolve at
82 * the end of certain render passes. This is because while slow clears store
83 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
84 * See the PRMs for examples describing when additional resolves would be
85 * necessary. To enable fast clears without requiring extra resolves, we set
86 * the clear value to a globally-defined one. We could allow different values
87 * if the user doesn't expect coherent data during or after a render passes
88 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
89 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
90 * 1.0f seems to be the only value used. The only application that doesn't set
91 * this value does so through the usage of an seemingly uninitialized clear
92 * value.
93 */
94 #define ANV_HZ_FC_VAL 1.0f
95
96 #define MAX_VBS 28
97 #define MAX_SETS 8
98 #define MAX_RTS 8
99 #define MAX_VIEWPORTS 16
100 #define MAX_SCISSORS 16
101 #define MAX_PUSH_CONSTANTS_SIZE 128
102 #define MAX_DYNAMIC_BUFFERS 16
103 #define MAX_IMAGES 8
104 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
105
106 #define ANV_SVGS_VB_INDEX MAX_VBS
107 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
108
109 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_down_npot_u32(uint32_t v, uint32_t a)
113 {
114 return v - (v % a);
115 }
116
117 static inline uint32_t
118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 anv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 anv_minify(uint32_t n, uint32_t levels)
148 {
149 if (unlikely(n == 0))
150 return 0;
151 else
152 return MAX2(n >> levels, 1);
153 }
154
155 static inline float
156 anv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 static inline union isl_color_value
180 vk_to_isl_color(VkClearColorValue color)
181 {
182 return (union isl_color_value) {
183 .u32 = {
184 color.uint32[0],
185 color.uint32[1],
186 color.uint32[2],
187 color.uint32[3],
188 },
189 };
190 }
191
192 #define for_each_bit(b, dword) \
193 for (uint32_t __dword = (dword); \
194 (b) = __builtin_ffs(__dword) - 1, __dword; \
195 __dword &= ~(1 << (b)))
196
197 #define typed_memcpy(dest, src, count) ({ \
198 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
199 memcpy((dest), (src), (count) * sizeof(*(src))); \
200 })
201
202 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
203 * to be added here in order to utilize mapping in debug/error/perf macros.
204 */
205 #define REPORT_OBJECT_TYPE(o) \
206 __builtin_choose_expr ( \
207 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
208 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
209 __builtin_choose_expr ( \
210 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
211 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
212 __builtin_choose_expr ( \
213 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
214 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
215 __builtin_choose_expr ( \
216 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
217 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
218 __builtin_choose_expr ( \
219 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
220 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
221 __builtin_choose_expr ( \
222 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
223 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
224 __builtin_choose_expr ( \
225 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
226 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
227 __builtin_choose_expr ( \
228 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
229 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
230 __builtin_choose_expr ( \
231 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
232 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
233 __builtin_choose_expr ( \
234 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
235 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
236 __builtin_choose_expr ( \
237 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
238 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
239 __builtin_choose_expr ( \
240 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
241 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
242 __builtin_choose_expr ( \
243 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
244 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
245 __builtin_choose_expr ( \
246 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
247 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
248 __builtin_choose_expr ( \
249 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
250 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
251 __builtin_choose_expr ( \
252 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
253 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
254 __builtin_choose_expr ( \
255 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
256 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
257 __builtin_choose_expr ( \
258 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
259 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
260 __builtin_choose_expr ( \
261 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
262 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
263 __builtin_choose_expr ( \
264 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
265 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
266 __builtin_choose_expr ( \
267 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
268 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
269 __builtin_choose_expr ( \
270 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
271 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
272 __builtin_choose_expr ( \
273 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
274 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
275 __builtin_choose_expr ( \
276 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
277 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
278 __builtin_choose_expr ( \
279 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
280 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
281 __builtin_choose_expr ( \
282 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
283 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
284 __builtin_choose_expr ( \
285 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
286 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
287 __builtin_choose_expr ( \
288 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
289 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
290 __builtin_choose_expr ( \
291 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
292 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
293 __builtin_choose_expr ( \
294 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
295 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
296 __builtin_choose_expr ( \
297 __builtin_types_compatible_p (__typeof (o), void*), \
298 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
299 /* The void expression results in a compile-time error \
300 when assigning the result to something. */ \
301 (void)0)))))))))))))))))))))))))))))))
302
303 /* Whenever we generate an error, pass it through this function. Useful for
304 * debugging, where we can break on it. Only call at error site, not when
305 * propagating errors. Might be useful to plug in a stack trace here.
306 */
307
308 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
309 VkDebugReportObjectTypeEXT type, VkResult error,
310 const char *file, int line, const char *format, ...);
311
312 #ifdef DEBUG
313 #define vk_error(error) __vk_errorf(NULL, NULL,\
314 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
315 error, __FILE__, __LINE__, NULL);
316 #define vk_errorf(instance, obj, error, format, ...)\
317 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
318 __FILE__, __LINE__, format, ## __VA_ARGS__);
319 #else
320 #define vk_error(error) error
321 #define vk_errorf(instance, obj, error, format, ...) error
322 #endif
323
324 /**
325 * Warn on ignored extension structs.
326 *
327 * The Vulkan spec requires us to ignore unsupported or unknown structs in
328 * a pNext chain. In debug mode, emitting warnings for ignored structs may
329 * help us discover structs that we should not have ignored.
330 *
331 *
332 * From the Vulkan 1.0.38 spec:
333 *
334 * Any component of the implementation (the loader, any enabled layers,
335 * and drivers) must skip over, without processing (other than reading the
336 * sType and pNext members) any chained structures with sType values not
337 * defined by extensions supported by that component.
338 */
339 #define anv_debug_ignored_stype(sType) \
340 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
341
342 void __anv_perf_warn(struct anv_instance *instance, const void *object,
343 VkDebugReportObjectTypeEXT type, const char *file,
344 int line, const char *format, ...)
345 anv_printflike(6, 7);
346 void anv_loge(const char *format, ...) anv_printflike(1, 2);
347 void anv_loge_v(const char *format, va_list va);
348
349 /**
350 * Print a FINISHME message, including its source location.
351 */
352 #define anv_finishme(format, ...) \
353 do { \
354 static bool reported = false; \
355 if (!reported) { \
356 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
357 ##__VA_ARGS__); \
358 reported = true; \
359 } \
360 } while (0)
361
362 /**
363 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
364 */
365 #define anv_perf_warn(instance, obj, format, ...) \
366 do { \
367 static bool reported = false; \
368 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
369 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
370 format, ##__VA_ARGS__); \
371 reported = true; \
372 } \
373 } while (0)
374
375 /* A non-fatal assert. Useful for debugging. */
376 #ifdef DEBUG
377 #define anv_assert(x) ({ \
378 if (unlikely(!(x))) \
379 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
380 })
381 #else
382 #define anv_assert(x)
383 #endif
384
385 /* A multi-pointer allocator
386 *
387 * When copying data structures from the user (such as a render pass), it's
388 * common to need to allocate data for a bunch of different things. Instead
389 * of doing several allocations and having to handle all of the error checking
390 * that entails, it can be easier to do a single allocation. This struct
391 * helps facilitate that. The intended usage looks like this:
392 *
393 * ANV_MULTIALLOC(ma)
394 * anv_multialloc_add(&ma, &main_ptr, 1);
395 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
396 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
397 *
398 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
399 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
400 */
401 struct anv_multialloc {
402 size_t size;
403 size_t align;
404
405 uint32_t ptr_count;
406 void **ptrs[8];
407 };
408
409 #define ANV_MULTIALLOC_INIT \
410 ((struct anv_multialloc) { 0, })
411
412 #define ANV_MULTIALLOC(_name) \
413 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
414
415 __attribute__((always_inline))
416 static inline void
417 _anv_multialloc_add(struct anv_multialloc *ma,
418 void **ptr, size_t size, size_t align)
419 {
420 size_t offset = align_u64(ma->size, align);
421 ma->size = offset + size;
422 ma->align = MAX2(ma->align, align);
423
424 /* Store the offset in the pointer. */
425 *ptr = (void *)(uintptr_t)offset;
426
427 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
428 ma->ptrs[ma->ptr_count++] = ptr;
429 }
430
431 #define anv_multialloc_add_size(_ma, _ptr, _size) \
432 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
433
434 #define anv_multialloc_add(_ma, _ptr, _count) \
435 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
436
437 __attribute__((always_inline))
438 static inline void *
439 anv_multialloc_alloc(struct anv_multialloc *ma,
440 const VkAllocationCallbacks *alloc,
441 VkSystemAllocationScope scope)
442 {
443 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
444 if (!ptr)
445 return NULL;
446
447 /* Fill out each of the pointers with their final value.
448 *
449 * for (uint32_t i = 0; i < ma->ptr_count; i++)
450 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
451 *
452 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
453 * constant, GCC is incapable of figuring this out and unrolling the loop
454 * so we have to give it a little help.
455 */
456 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
457 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
458 if ((_i) < ma->ptr_count) \
459 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
460 _ANV_MULTIALLOC_UPDATE_POINTER(0);
461 _ANV_MULTIALLOC_UPDATE_POINTER(1);
462 _ANV_MULTIALLOC_UPDATE_POINTER(2);
463 _ANV_MULTIALLOC_UPDATE_POINTER(3);
464 _ANV_MULTIALLOC_UPDATE_POINTER(4);
465 _ANV_MULTIALLOC_UPDATE_POINTER(5);
466 _ANV_MULTIALLOC_UPDATE_POINTER(6);
467 _ANV_MULTIALLOC_UPDATE_POINTER(7);
468 #undef _ANV_MULTIALLOC_UPDATE_POINTER
469
470 return ptr;
471 }
472
473 __attribute__((always_inline))
474 static inline void *
475 anv_multialloc_alloc2(struct anv_multialloc *ma,
476 const VkAllocationCallbacks *parent_alloc,
477 const VkAllocationCallbacks *alloc,
478 VkSystemAllocationScope scope)
479 {
480 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
481 }
482
483 struct anv_bo {
484 uint32_t gem_handle;
485
486 /* Index into the current validation list. This is used by the
487 * validation list building alrogithm to track which buffers are already
488 * in the validation list so that we can ensure uniqueness.
489 */
490 uint32_t index;
491
492 /* Last known offset. This value is provided by the kernel when we
493 * execbuf and is used as the presumed offset for the next bunch of
494 * relocations.
495 */
496 uint64_t offset;
497
498 uint64_t size;
499 void *map;
500
501 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
502 uint32_t flags;
503 };
504
505 static inline void
506 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
507 {
508 bo->gem_handle = gem_handle;
509 bo->index = 0;
510 bo->offset = -1;
511 bo->size = size;
512 bo->map = NULL;
513 bo->flags = 0;
514 }
515
516 /* Represents a lock-free linked list of "free" things. This is used by
517 * both the block pool and the state pools. Unfortunately, in order to
518 * solve the ABA problem, we can't use a single uint32_t head.
519 */
520 union anv_free_list {
521 struct {
522 int32_t offset;
523
524 /* A simple count that is incremented every time the head changes. */
525 uint32_t count;
526 };
527 uint64_t u64;
528 };
529
530 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
531
532 struct anv_block_state {
533 union {
534 struct {
535 uint32_t next;
536 uint32_t end;
537 };
538 uint64_t u64;
539 };
540 };
541
542 struct anv_block_pool {
543 struct anv_device *device;
544
545 uint64_t bo_flags;
546
547 struct anv_bo bo;
548
549 /* The offset from the start of the bo to the "center" of the block
550 * pool. Pointers to allocated blocks are given by
551 * bo.map + center_bo_offset + offsets.
552 */
553 uint32_t center_bo_offset;
554
555 /* Current memory map of the block pool. This pointer may or may not
556 * point to the actual beginning of the block pool memory. If
557 * anv_block_pool_alloc_back has ever been called, then this pointer
558 * will point to the "center" position of the buffer and all offsets
559 * (negative or positive) given out by the block pool alloc functions
560 * will be valid relative to this pointer.
561 *
562 * In particular, map == bo.map + center_offset
563 */
564 void *map;
565 int fd;
566
567 /**
568 * Array of mmaps and gem handles owned by the block pool, reclaimed when
569 * the block pool is destroyed.
570 */
571 struct u_vector mmap_cleanups;
572
573 struct anv_block_state state;
574
575 struct anv_block_state back_state;
576 };
577
578 /* Block pools are backed by a fixed-size 1GB memfd */
579 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
580
581 /* The center of the block pool is also the middle of the memfd. This may
582 * change in the future if we decide differently for some reason.
583 */
584 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
585
586 static inline uint32_t
587 anv_block_pool_size(struct anv_block_pool *pool)
588 {
589 return pool->state.end + pool->back_state.end;
590 }
591
592 struct anv_state {
593 int32_t offset;
594 uint32_t alloc_size;
595 void *map;
596 };
597
598 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
599
600 struct anv_fixed_size_state_pool {
601 union anv_free_list free_list;
602 struct anv_block_state block;
603 };
604
605 #define ANV_MIN_STATE_SIZE_LOG2 6
606 #define ANV_MAX_STATE_SIZE_LOG2 20
607
608 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
609
610 struct anv_state_pool {
611 struct anv_block_pool block_pool;
612
613 /* The size of blocks which will be allocated from the block pool */
614 uint32_t block_size;
615
616 /** Free list for "back" allocations */
617 union anv_free_list back_alloc_free_list;
618
619 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
620 };
621
622 struct anv_state_stream_block;
623
624 struct anv_state_stream {
625 struct anv_state_pool *state_pool;
626
627 /* The size of blocks to allocate from the state pool */
628 uint32_t block_size;
629
630 /* Current block we're allocating from */
631 struct anv_state block;
632
633 /* Offset into the current block at which to allocate the next state */
634 uint32_t next;
635
636 /* List of all blocks allocated from this pool */
637 struct anv_state_stream_block *block_list;
638 };
639
640 /* The block_pool functions exported for testing only. The block pool should
641 * only be used via a state pool (see below).
642 */
643 VkResult anv_block_pool_init(struct anv_block_pool *pool,
644 struct anv_device *device,
645 uint32_t initial_size,
646 uint64_t bo_flags);
647 void anv_block_pool_finish(struct anv_block_pool *pool);
648 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
649 uint32_t block_size);
650 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
651 uint32_t block_size);
652
653 VkResult anv_state_pool_init(struct anv_state_pool *pool,
654 struct anv_device *device,
655 uint32_t block_size,
656 uint64_t bo_flags);
657 void anv_state_pool_finish(struct anv_state_pool *pool);
658 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
659 uint32_t state_size, uint32_t alignment);
660 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
661 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
662 void anv_state_stream_init(struct anv_state_stream *stream,
663 struct anv_state_pool *state_pool,
664 uint32_t block_size);
665 void anv_state_stream_finish(struct anv_state_stream *stream);
666 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
667 uint32_t size, uint32_t alignment);
668
669 /**
670 * Implements a pool of re-usable BOs. The interface is identical to that
671 * of block_pool except that each block is its own BO.
672 */
673 struct anv_bo_pool {
674 struct anv_device *device;
675
676 uint64_t bo_flags;
677
678 void *free_list[16];
679 };
680
681 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
682 uint64_t bo_flags);
683 void anv_bo_pool_finish(struct anv_bo_pool *pool);
684 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
685 uint32_t size);
686 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
687
688 struct anv_scratch_bo {
689 bool exists;
690 struct anv_bo bo;
691 };
692
693 struct anv_scratch_pool {
694 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
695 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
696 };
697
698 void anv_scratch_pool_init(struct anv_device *device,
699 struct anv_scratch_pool *pool);
700 void anv_scratch_pool_finish(struct anv_device *device,
701 struct anv_scratch_pool *pool);
702 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
703 struct anv_scratch_pool *pool,
704 gl_shader_stage stage,
705 unsigned per_thread_scratch);
706
707 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
708 struct anv_bo_cache {
709 struct hash_table *bo_map;
710 pthread_mutex_t mutex;
711 };
712
713 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
714 void anv_bo_cache_finish(struct anv_bo_cache *cache);
715 VkResult anv_bo_cache_alloc(struct anv_device *device,
716 struct anv_bo_cache *cache,
717 uint64_t size, struct anv_bo **bo);
718 VkResult anv_bo_cache_import(struct anv_device *device,
719 struct anv_bo_cache *cache,
720 int fd, struct anv_bo **bo);
721 VkResult anv_bo_cache_export(struct anv_device *device,
722 struct anv_bo_cache *cache,
723 struct anv_bo *bo_in, int *fd_out);
724 void anv_bo_cache_release(struct anv_device *device,
725 struct anv_bo_cache *cache,
726 struct anv_bo *bo);
727
728 struct anv_memory_type {
729 /* Standard bits passed on to the client */
730 VkMemoryPropertyFlags propertyFlags;
731 uint32_t heapIndex;
732
733 /* Driver-internal book-keeping */
734 VkBufferUsageFlags valid_buffer_usage;
735 };
736
737 struct anv_memory_heap {
738 /* Standard bits passed on to the client */
739 VkDeviceSize size;
740 VkMemoryHeapFlags flags;
741
742 /* Driver-internal book-keeping */
743 bool supports_48bit_addresses;
744 };
745
746 struct anv_physical_device {
747 VK_LOADER_DATA _loader_data;
748
749 struct anv_instance * instance;
750 uint32_t chipset_id;
751 char path[20];
752 const char * name;
753 struct gen_device_info info;
754 /** Amount of "GPU memory" we want to advertise
755 *
756 * Clearly, this value is bogus since Intel is a UMA architecture. On
757 * gen7 platforms, we are limited by GTT size unless we want to implement
758 * fine-grained tracking and GTT splitting. On Broadwell and above we are
759 * practically unlimited. However, we will never report more than 3/4 of
760 * the total system ram to try and avoid running out of RAM.
761 */
762 bool supports_48bit_addresses;
763 struct brw_compiler * compiler;
764 struct isl_device isl_dev;
765 int cmd_parser_version;
766 bool has_exec_async;
767 bool has_exec_capture;
768 bool has_exec_fence;
769 bool has_syncobj;
770 bool has_syncobj_wait;
771
772 uint32_t eu_total;
773 uint32_t subslice_total;
774
775 struct {
776 uint32_t type_count;
777 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
778 uint32_t heap_count;
779 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
780 } memory;
781
782 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
783 uint8_t driver_uuid[VK_UUID_SIZE];
784 uint8_t device_uuid[VK_UUID_SIZE];
785
786 struct wsi_device wsi_device;
787 int local_fd;
788 };
789
790 struct anv_instance {
791 VK_LOADER_DATA _loader_data;
792
793 VkAllocationCallbacks alloc;
794
795 uint32_t apiVersion;
796 int physicalDeviceCount;
797 struct anv_physical_device physicalDevice;
798
799 struct vk_debug_report_instance debug_report_callbacks;
800 };
801
802 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
803 void anv_finish_wsi(struct anv_physical_device *physical_device);
804
805 bool anv_instance_extension_supported(const char *name);
806 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
807 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
808 const char *name);
809
810 struct anv_queue {
811 VK_LOADER_DATA _loader_data;
812
813 struct anv_device * device;
814
815 struct anv_state_pool * pool;
816 };
817
818 struct anv_pipeline_cache {
819 struct anv_device * device;
820 pthread_mutex_t mutex;
821
822 struct hash_table * cache;
823 };
824
825 struct anv_pipeline_bind_map;
826
827 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
828 struct anv_device *device,
829 bool cache_enabled);
830 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
831
832 struct anv_shader_bin *
833 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
834 const void *key, uint32_t key_size);
835 struct anv_shader_bin *
836 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
837 const void *key_data, uint32_t key_size,
838 const void *kernel_data, uint32_t kernel_size,
839 const struct brw_stage_prog_data *prog_data,
840 uint32_t prog_data_size,
841 const struct anv_pipeline_bind_map *bind_map);
842
843 struct anv_device {
844 VK_LOADER_DATA _loader_data;
845
846 VkAllocationCallbacks alloc;
847
848 struct anv_instance * instance;
849 uint32_t chipset_id;
850 struct gen_device_info info;
851 struct isl_device isl_dev;
852 int context_id;
853 int fd;
854 bool can_chain_batches;
855 bool robust_buffer_access;
856
857 struct anv_bo_pool batch_bo_pool;
858
859 struct anv_bo_cache bo_cache;
860
861 struct anv_state_pool dynamic_state_pool;
862 struct anv_state_pool instruction_state_pool;
863 struct anv_state_pool surface_state_pool;
864
865 struct anv_bo workaround_bo;
866 struct anv_bo trivial_batch_bo;
867
868 struct anv_pipeline_cache blorp_shader_cache;
869 struct blorp_context blorp;
870
871 struct anv_state border_colors;
872
873 struct anv_queue queue;
874
875 struct anv_scratch_pool scratch_pool;
876
877 uint32_t default_mocs;
878
879 pthread_mutex_t mutex;
880 pthread_cond_t queue_submit;
881 bool lost;
882 };
883
884 static void inline
885 anv_state_flush(struct anv_device *device, struct anv_state state)
886 {
887 if (device->info.has_llc)
888 return;
889
890 gen_flush_range(state.map, state.alloc_size);
891 }
892
893 void anv_device_init_blorp(struct anv_device *device);
894 void anv_device_finish_blorp(struct anv_device *device);
895
896 VkResult anv_device_execbuf(struct anv_device *device,
897 struct drm_i915_gem_execbuffer2 *execbuf,
898 struct anv_bo **execbuf_bos);
899 VkResult anv_device_query_status(struct anv_device *device);
900 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
901 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
902 int64_t timeout);
903
904 void* anv_gem_mmap(struct anv_device *device,
905 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
906 void anv_gem_munmap(void *p, uint64_t size);
907 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
908 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
909 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
910 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
911 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
912 int anv_gem_execbuffer(struct anv_device *device,
913 struct drm_i915_gem_execbuffer2 *execbuf);
914 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
915 uint32_t stride, uint32_t tiling);
916 int anv_gem_create_context(struct anv_device *device);
917 int anv_gem_destroy_context(struct anv_device *device, int context);
918 int anv_gem_get_context_param(int fd, int context, uint32_t param,
919 uint64_t *value);
920 int anv_gem_get_param(int fd, uint32_t param);
921 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
922 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
923 int anv_gem_get_aperture(int fd, uint64_t *size);
924 bool anv_gem_supports_48b_addresses(int fd);
925 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
926 uint32_t *active, uint32_t *pending);
927 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
928 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
929 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
930 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
931 uint32_t read_domains, uint32_t write_domain);
932 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
933 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
934 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
935 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
936 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
937 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
938 uint32_t handle);
939 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
940 uint32_t handle, int fd);
941 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
942 bool anv_gem_supports_syncobj_wait(int fd);
943 int anv_gem_syncobj_wait(struct anv_device *device,
944 uint32_t *handles, uint32_t num_handles,
945 int64_t abs_timeout_ns, bool wait_all);
946
947 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
948
949 struct anv_reloc_list {
950 uint32_t num_relocs;
951 uint32_t array_length;
952 struct drm_i915_gem_relocation_entry * relocs;
953 struct anv_bo ** reloc_bos;
954 };
955
956 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
957 const VkAllocationCallbacks *alloc);
958 void anv_reloc_list_finish(struct anv_reloc_list *list,
959 const VkAllocationCallbacks *alloc);
960
961 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
962 const VkAllocationCallbacks *alloc,
963 uint32_t offset, struct anv_bo *target_bo,
964 uint32_t delta);
965
966 struct anv_batch_bo {
967 /* Link in the anv_cmd_buffer.owned_batch_bos list */
968 struct list_head link;
969
970 struct anv_bo bo;
971
972 /* Bytes actually consumed in this batch BO */
973 uint32_t length;
974
975 struct anv_reloc_list relocs;
976 };
977
978 struct anv_batch {
979 const VkAllocationCallbacks * alloc;
980
981 void * start;
982 void * end;
983 void * next;
984
985 struct anv_reloc_list * relocs;
986
987 /* This callback is called (with the associated user data) in the event
988 * that the batch runs out of space.
989 */
990 VkResult (*extend_cb)(struct anv_batch *, void *);
991 void * user_data;
992
993 /**
994 * Current error status of the command buffer. Used to track inconsistent
995 * or incomplete command buffer states that are the consequence of run-time
996 * errors such as out of memory scenarios. We want to track this in the
997 * batch because the command buffer object is not visible to some parts
998 * of the driver.
999 */
1000 VkResult status;
1001 };
1002
1003 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1004 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1005 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1006 void *location, struct anv_bo *bo, uint32_t offset);
1007 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1008 struct anv_batch *batch);
1009
1010 static inline VkResult
1011 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1012 {
1013 assert(error != VK_SUCCESS);
1014 if (batch->status == VK_SUCCESS)
1015 batch->status = error;
1016 return batch->status;
1017 }
1018
1019 static inline bool
1020 anv_batch_has_error(struct anv_batch *batch)
1021 {
1022 return batch->status != VK_SUCCESS;
1023 }
1024
1025 struct anv_address {
1026 struct anv_bo *bo;
1027 uint32_t offset;
1028 };
1029
1030 static inline uint64_t
1031 _anv_combine_address(struct anv_batch *batch, void *location,
1032 const struct anv_address address, uint32_t delta)
1033 {
1034 if (address.bo == NULL) {
1035 return address.offset + delta;
1036 } else {
1037 assert(batch->start <= location && location < batch->end);
1038
1039 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1040 }
1041 }
1042
1043 #define __gen_address_type struct anv_address
1044 #define __gen_user_data struct anv_batch
1045 #define __gen_combine_address _anv_combine_address
1046
1047 /* Wrapper macros needed to work around preprocessor argument issues. In
1048 * particular, arguments don't get pre-evaluated if they are concatenated.
1049 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1050 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1051 * We can work around this easily enough with these helpers.
1052 */
1053 #define __anv_cmd_length(cmd) cmd ## _length
1054 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1055 #define __anv_cmd_header(cmd) cmd ## _header
1056 #define __anv_cmd_pack(cmd) cmd ## _pack
1057 #define __anv_reg_num(reg) reg ## _num
1058
1059 #define anv_pack_struct(dst, struc, ...) do { \
1060 struct struc __template = { \
1061 __VA_ARGS__ \
1062 }; \
1063 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1064 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1065 } while (0)
1066
1067 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1068 void *__dst = anv_batch_emit_dwords(batch, n); \
1069 if (__dst) { \
1070 struct cmd __template = { \
1071 __anv_cmd_header(cmd), \
1072 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1073 __VA_ARGS__ \
1074 }; \
1075 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1076 } \
1077 __dst; \
1078 })
1079
1080 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1081 do { \
1082 uint32_t *dw; \
1083 \
1084 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1085 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1086 if (!dw) \
1087 break; \
1088 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1089 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1090 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1091 } while (0)
1092
1093 #define anv_batch_emit(batch, cmd, name) \
1094 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1095 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1096 __builtin_expect(_dst != NULL, 1); \
1097 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1098 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1099 _dst = NULL; \
1100 }))
1101
1102 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1103 .GraphicsDataTypeGFDT = 0, \
1104 .LLCCacheabilityControlLLCCC = 0, \
1105 .L3CacheabilityControlL3CC = 1, \
1106 }
1107
1108 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1109 .LLCeLLCCacheabilityControlLLCCC = 0, \
1110 .L3CacheabilityControlL3CC = 1, \
1111 }
1112
1113 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1114 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1115 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1116 .AgeforQUADLRU = 0 \
1117 }
1118
1119 /* Skylake: MOCS is now an index into an array of 62 different caching
1120 * configurations programmed by the kernel.
1121 */
1122
1123 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1124 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1125 .IndextoMOCSTables = 2 \
1126 }
1127
1128 #define GEN9_MOCS_PTE { \
1129 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1130 .IndextoMOCSTables = 1 \
1131 }
1132
1133 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1134 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1135 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1136 .IndextoMOCSTables = 2 \
1137 }
1138
1139 #define GEN10_MOCS_PTE { \
1140 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1141 .IndextoMOCSTables = 1 \
1142 }
1143
1144 struct anv_device_memory {
1145 struct anv_bo * bo;
1146 struct anv_memory_type * type;
1147 VkDeviceSize map_size;
1148 void * map;
1149 };
1150
1151 /**
1152 * Header for Vertex URB Entry (VUE)
1153 */
1154 struct anv_vue_header {
1155 uint32_t Reserved;
1156 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1157 uint32_t ViewportIndex;
1158 float PointWidth;
1159 };
1160
1161 struct anv_descriptor_set_binding_layout {
1162 #ifndef NDEBUG
1163 /* The type of the descriptors in this binding */
1164 VkDescriptorType type;
1165 #endif
1166
1167 /* Number of array elements in this binding */
1168 uint16_t array_size;
1169
1170 /* Index into the flattend descriptor set */
1171 uint16_t descriptor_index;
1172
1173 /* Index into the dynamic state array for a dynamic buffer */
1174 int16_t dynamic_offset_index;
1175
1176 /* Index into the descriptor set buffer views */
1177 int16_t buffer_index;
1178
1179 struct {
1180 /* Index into the binding table for the associated surface */
1181 int16_t surface_index;
1182
1183 /* Index into the sampler table for the associated sampler */
1184 int16_t sampler_index;
1185
1186 /* Index into the image table for the associated image */
1187 int16_t image_index;
1188 } stage[MESA_SHADER_STAGES];
1189
1190 /* Immutable samplers (or NULL if no immutable samplers) */
1191 struct anv_sampler **immutable_samplers;
1192 };
1193
1194 struct anv_descriptor_set_layout {
1195 /* Number of bindings in this descriptor set */
1196 uint16_t binding_count;
1197
1198 /* Total size of the descriptor set with room for all array entries */
1199 uint16_t size;
1200
1201 /* Shader stages affected by this descriptor set */
1202 uint16_t shader_stages;
1203
1204 /* Number of buffers in this descriptor set */
1205 uint16_t buffer_count;
1206
1207 /* Number of dynamic offsets used by this descriptor set */
1208 uint16_t dynamic_offset_count;
1209
1210 /* Bindings in this descriptor set */
1211 struct anv_descriptor_set_binding_layout binding[0];
1212 };
1213
1214 struct anv_descriptor {
1215 VkDescriptorType type;
1216
1217 union {
1218 struct {
1219 VkImageLayout layout;
1220 struct anv_image_view *image_view;
1221 struct anv_sampler *sampler;
1222 };
1223
1224 struct {
1225 struct anv_buffer *buffer;
1226 uint64_t offset;
1227 uint64_t range;
1228 };
1229
1230 struct anv_buffer_view *buffer_view;
1231 };
1232 };
1233
1234 struct anv_descriptor_set {
1235 const struct anv_descriptor_set_layout *layout;
1236 uint32_t size;
1237 uint32_t buffer_count;
1238 struct anv_buffer_view *buffer_views;
1239 struct anv_descriptor descriptors[0];
1240 };
1241
1242 struct anv_buffer_view {
1243 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1244 struct anv_bo *bo;
1245 uint32_t offset; /**< Offset into bo. */
1246 uint64_t range; /**< VkBufferViewCreateInfo::range */
1247
1248 struct anv_state surface_state;
1249 struct anv_state storage_surface_state;
1250 struct anv_state writeonly_storage_surface_state;
1251
1252 struct brw_image_param storage_image_param;
1253 };
1254
1255 struct anv_push_descriptor_set {
1256 struct anv_descriptor_set set;
1257
1258 /* Put this field right behind anv_descriptor_set so it fills up the
1259 * descriptors[0] field. */
1260 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1261 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1262 };
1263
1264 struct anv_descriptor_pool {
1265 uint32_t size;
1266 uint32_t next;
1267 uint32_t free_list;
1268
1269 struct anv_state_stream surface_state_stream;
1270 void *surface_state_free_list;
1271
1272 char data[0];
1273 };
1274
1275 enum anv_descriptor_template_entry_type {
1276 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1277 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1278 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1279 };
1280
1281 struct anv_descriptor_template_entry {
1282 /* The type of descriptor in this entry */
1283 VkDescriptorType type;
1284
1285 /* Binding in the descriptor set */
1286 uint32_t binding;
1287
1288 /* Offset at which to write into the descriptor set binding */
1289 uint32_t array_element;
1290
1291 /* Number of elements to write into the descriptor set binding */
1292 uint32_t array_count;
1293
1294 /* Offset into the user provided data */
1295 size_t offset;
1296
1297 /* Stride between elements into the user provided data */
1298 size_t stride;
1299 };
1300
1301 struct anv_descriptor_update_template {
1302 /* The descriptor set this template corresponds to. This value is only
1303 * valid if the template was created with the templateType
1304 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1305 */
1306 uint8_t set;
1307
1308 /* Number of entries in this template */
1309 uint32_t entry_count;
1310
1311 /* Entries of the template */
1312 struct anv_descriptor_template_entry entries[0];
1313 };
1314
1315 size_t
1316 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1317
1318 size_t
1319 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1320
1321 void
1322 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1323 const struct gen_device_info * const devinfo,
1324 const VkDescriptorImageInfo * const info,
1325 VkDescriptorType type,
1326 uint32_t binding,
1327 uint32_t element);
1328
1329 void
1330 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1331 VkDescriptorType type,
1332 struct anv_buffer_view *buffer_view,
1333 uint32_t binding,
1334 uint32_t element);
1335
1336 void
1337 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1338 struct anv_device *device,
1339 struct anv_state_stream *alloc_stream,
1340 VkDescriptorType type,
1341 struct anv_buffer *buffer,
1342 uint32_t binding,
1343 uint32_t element,
1344 VkDeviceSize offset,
1345 VkDeviceSize range);
1346
1347 void
1348 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1349 struct anv_device *device,
1350 struct anv_state_stream *alloc_stream,
1351 const struct anv_descriptor_update_template *template,
1352 const void *data);
1353
1354 VkResult
1355 anv_descriptor_set_create(struct anv_device *device,
1356 struct anv_descriptor_pool *pool,
1357 const struct anv_descriptor_set_layout *layout,
1358 struct anv_descriptor_set **out_set);
1359
1360 void
1361 anv_descriptor_set_destroy(struct anv_device *device,
1362 struct anv_descriptor_pool *pool,
1363 struct anv_descriptor_set *set);
1364
1365 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1366
1367 struct anv_pipeline_binding {
1368 /* The descriptor set this surface corresponds to. The special value of
1369 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1370 * to a color attachment and not a regular descriptor.
1371 */
1372 uint8_t set;
1373
1374 /* Binding in the descriptor set */
1375 uint32_t binding;
1376
1377 /* Index in the binding */
1378 uint32_t index;
1379
1380 /* Plane in the binding index */
1381 uint8_t plane;
1382
1383 /* Input attachment index (relative to the subpass) */
1384 uint8_t input_attachment_index;
1385
1386 /* For a storage image, whether it is write-only */
1387 bool write_only;
1388 };
1389
1390 struct anv_pipeline_layout {
1391 struct {
1392 struct anv_descriptor_set_layout *layout;
1393 uint32_t dynamic_offset_start;
1394 } set[MAX_SETS];
1395
1396 uint32_t num_sets;
1397
1398 struct {
1399 bool has_dynamic_offsets;
1400 } stage[MESA_SHADER_STAGES];
1401
1402 unsigned char sha1[20];
1403 };
1404
1405 struct anv_buffer {
1406 struct anv_device * device;
1407 VkDeviceSize size;
1408
1409 VkBufferUsageFlags usage;
1410
1411 /* Set when bound */
1412 struct anv_bo * bo;
1413 VkDeviceSize offset;
1414 };
1415
1416 static inline uint64_t
1417 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1418 {
1419 assert(offset <= buffer->size);
1420 if (range == VK_WHOLE_SIZE) {
1421 return buffer->size - offset;
1422 } else {
1423 assert(range <= buffer->size);
1424 return range;
1425 }
1426 }
1427
1428 enum anv_cmd_dirty_bits {
1429 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1430 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1431 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1432 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1433 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1434 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1435 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1436 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1437 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1438 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1439 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1440 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1441 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1442 };
1443 typedef uint32_t anv_cmd_dirty_mask_t;
1444
1445 enum anv_pipe_bits {
1446 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1447 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1448 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1449 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1450 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1451 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1452 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1453 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1454 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1455 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1456 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1457
1458 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1459 * a flush has happened but not a CS stall. The next time we do any sort
1460 * of invalidation we need to insert a CS stall at that time. Otherwise,
1461 * we would have to CS stall on every flush which could be bad.
1462 */
1463 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1464 };
1465
1466 #define ANV_PIPE_FLUSH_BITS ( \
1467 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1468 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1469 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1470
1471 #define ANV_PIPE_STALL_BITS ( \
1472 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1473 ANV_PIPE_DEPTH_STALL_BIT | \
1474 ANV_PIPE_CS_STALL_BIT)
1475
1476 #define ANV_PIPE_INVALIDATE_BITS ( \
1477 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1478 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1479 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1480 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1481 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1482 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1483
1484 static inline enum anv_pipe_bits
1485 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1486 {
1487 enum anv_pipe_bits pipe_bits = 0;
1488
1489 unsigned b;
1490 for_each_bit(b, flags) {
1491 switch ((VkAccessFlagBits)(1 << b)) {
1492 case VK_ACCESS_SHADER_WRITE_BIT:
1493 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1494 break;
1495 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1496 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1497 break;
1498 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1499 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1500 break;
1501 case VK_ACCESS_TRANSFER_WRITE_BIT:
1502 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1503 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1504 break;
1505 default:
1506 break; /* Nothing to do */
1507 }
1508 }
1509
1510 return pipe_bits;
1511 }
1512
1513 static inline enum anv_pipe_bits
1514 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1515 {
1516 enum anv_pipe_bits pipe_bits = 0;
1517
1518 unsigned b;
1519 for_each_bit(b, flags) {
1520 switch ((VkAccessFlagBits)(1 << b)) {
1521 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1522 case VK_ACCESS_INDEX_READ_BIT:
1523 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1524 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1525 break;
1526 case VK_ACCESS_UNIFORM_READ_BIT:
1527 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1528 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1529 break;
1530 case VK_ACCESS_SHADER_READ_BIT:
1531 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1532 case VK_ACCESS_TRANSFER_READ_BIT:
1533 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1534 break;
1535 default:
1536 break; /* Nothing to do */
1537 }
1538 }
1539
1540 return pipe_bits;
1541 }
1542
1543 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1544 VK_IMAGE_ASPECT_COLOR_BIT | \
1545 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1546 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1547 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1548 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1549 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1550 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1551 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1552
1553 struct anv_vertex_binding {
1554 struct anv_buffer * buffer;
1555 VkDeviceSize offset;
1556 };
1557
1558 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1559 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1560
1561 struct anv_push_constants {
1562 /* Current allocated size of this push constants data structure.
1563 * Because a decent chunk of it may not be used (images on SKL, for
1564 * instance), we won't actually allocate the entire structure up-front.
1565 */
1566 uint32_t size;
1567
1568 /* Push constant data provided by the client through vkPushConstants */
1569 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1570
1571 /* Image data for image_load_store on pre-SKL */
1572 struct brw_image_param images[MAX_IMAGES];
1573 };
1574
1575 struct anv_dynamic_state {
1576 struct {
1577 uint32_t count;
1578 VkViewport viewports[MAX_VIEWPORTS];
1579 } viewport;
1580
1581 struct {
1582 uint32_t count;
1583 VkRect2D scissors[MAX_SCISSORS];
1584 } scissor;
1585
1586 float line_width;
1587
1588 struct {
1589 float bias;
1590 float clamp;
1591 float slope;
1592 } depth_bias;
1593
1594 float blend_constants[4];
1595
1596 struct {
1597 float min;
1598 float max;
1599 } depth_bounds;
1600
1601 struct {
1602 uint32_t front;
1603 uint32_t back;
1604 } stencil_compare_mask;
1605
1606 struct {
1607 uint32_t front;
1608 uint32_t back;
1609 } stencil_write_mask;
1610
1611 struct {
1612 uint32_t front;
1613 uint32_t back;
1614 } stencil_reference;
1615 };
1616
1617 extern const struct anv_dynamic_state default_dynamic_state;
1618
1619 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1620 const struct anv_dynamic_state *src,
1621 uint32_t copy_mask);
1622
1623 struct anv_surface_state {
1624 struct anv_state state;
1625 /** Address of the surface referred to by this state
1626 *
1627 * This address is relative to the start of the BO.
1628 */
1629 uint64_t address;
1630 /* Address of the aux surface, if any
1631 *
1632 * This field is 0 if and only if no aux surface exists.
1633 *
1634 * This address is relative to the start of the BO. On gen7, the bottom 12
1635 * bits of this address include extra aux information.
1636 */
1637 uint64_t aux_address;
1638 };
1639
1640 /**
1641 * Attachment state when recording a renderpass instance.
1642 *
1643 * The clear value is valid only if there exists a pending clear.
1644 */
1645 struct anv_attachment_state {
1646 enum isl_aux_usage aux_usage;
1647 enum isl_aux_usage input_aux_usage;
1648 struct anv_surface_state color;
1649 struct anv_surface_state input;
1650
1651 VkImageLayout current_layout;
1652 VkImageAspectFlags pending_clear_aspects;
1653 bool fast_clear;
1654 VkClearValue clear_value;
1655 bool clear_color_is_zero_one;
1656 bool clear_color_is_zero;
1657 };
1658
1659 /** State required while building cmd buffer */
1660 struct anv_cmd_state {
1661 /* PIPELINE_SELECT.PipelineSelection */
1662 uint32_t current_pipeline;
1663 const struct gen_l3_config * current_l3_config;
1664 uint32_t vb_dirty;
1665 anv_cmd_dirty_mask_t dirty;
1666 anv_cmd_dirty_mask_t compute_dirty;
1667 enum anv_pipe_bits pending_pipe_bits;
1668 uint32_t num_workgroups_offset;
1669 struct anv_bo *num_workgroups_bo;
1670 VkShaderStageFlags descriptors_dirty;
1671 VkShaderStageFlags push_constants_dirty;
1672 uint32_t scratch_size;
1673 struct anv_pipeline * pipeline;
1674 struct anv_pipeline * compute_pipeline;
1675 struct anv_framebuffer * framebuffer;
1676 struct anv_render_pass * pass;
1677 struct anv_subpass * subpass;
1678 VkRect2D render_area;
1679 uint32_t restart_index;
1680 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1681 struct anv_descriptor_set * descriptors[MAX_SETS];
1682 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1683 VkShaderStageFlags push_constant_stages;
1684 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1685 struct anv_state binding_tables[MESA_SHADER_STAGES];
1686 struct anv_state samplers[MESA_SHADER_STAGES];
1687 struct anv_dynamic_state dynamic;
1688 bool need_query_wa;
1689
1690 struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
1691
1692 /**
1693 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1694 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1695 * and before invoking the secondary in ExecuteCommands.
1696 */
1697 bool pma_fix_enabled;
1698
1699 /**
1700 * Whether or not we know for certain that HiZ is enabled for the current
1701 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1702 * enabled or not, this will be false.
1703 */
1704 bool hiz_enabled;
1705
1706 /**
1707 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1708 * valid only when recording a render pass instance.
1709 */
1710 struct anv_attachment_state * attachments;
1711
1712 /**
1713 * Surface states for color render targets. These are stored in a single
1714 * flat array. For depth-stencil attachments, the surface state is simply
1715 * left blank.
1716 */
1717 struct anv_state render_pass_states;
1718
1719 /**
1720 * A null surface state of the right size to match the framebuffer. This
1721 * is one of the states in render_pass_states.
1722 */
1723 struct anv_state null_surface_state;
1724
1725 struct {
1726 struct anv_buffer * index_buffer;
1727 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1728 uint32_t index_offset;
1729 } gen7;
1730 };
1731
1732 struct anv_cmd_pool {
1733 VkAllocationCallbacks alloc;
1734 struct list_head cmd_buffers;
1735 };
1736
1737 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1738
1739 enum anv_cmd_buffer_exec_mode {
1740 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1741 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1742 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1743 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1744 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1745 };
1746
1747 struct anv_cmd_buffer {
1748 VK_LOADER_DATA _loader_data;
1749
1750 struct anv_device * device;
1751
1752 struct anv_cmd_pool * pool;
1753 struct list_head pool_link;
1754
1755 struct anv_batch batch;
1756
1757 /* Fields required for the actual chain of anv_batch_bo's.
1758 *
1759 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1760 */
1761 struct list_head batch_bos;
1762 enum anv_cmd_buffer_exec_mode exec_mode;
1763
1764 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1765 * referenced by this command buffer
1766 *
1767 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1768 */
1769 struct u_vector seen_bbos;
1770
1771 /* A vector of int32_t's for every block of binding tables.
1772 *
1773 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1774 */
1775 struct u_vector bt_block_states;
1776 uint32_t bt_next;
1777
1778 struct anv_reloc_list surface_relocs;
1779 /** Last seen surface state block pool center bo offset */
1780 uint32_t last_ss_pool_center;
1781
1782 /* Serial for tracking buffer completion */
1783 uint32_t serial;
1784
1785 /* Stream objects for storing temporary data */
1786 struct anv_state_stream surface_state_stream;
1787 struct anv_state_stream dynamic_state_stream;
1788
1789 VkCommandBufferUsageFlags usage_flags;
1790 VkCommandBufferLevel level;
1791
1792 struct anv_cmd_state state;
1793 };
1794
1795 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1796 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1797 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1798 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1799 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1800 struct anv_cmd_buffer *secondary);
1801 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1802 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1803 struct anv_cmd_buffer *cmd_buffer,
1804 const VkSemaphore *in_semaphores,
1805 uint32_t num_in_semaphores,
1806 const VkSemaphore *out_semaphores,
1807 uint32_t num_out_semaphores,
1808 VkFence fence);
1809
1810 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1811
1812 VkResult
1813 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1814 gl_shader_stage stage, uint32_t size);
1815 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1816 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1817 (offsetof(struct anv_push_constants, field) + \
1818 sizeof(cmd_buffer->state.push_constants[0]->field)))
1819
1820 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1821 const void *data, uint32_t size, uint32_t alignment);
1822 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1823 uint32_t *a, uint32_t *b,
1824 uint32_t dwords, uint32_t alignment);
1825
1826 struct anv_address
1827 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1828 struct anv_state
1829 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1830 uint32_t entries, uint32_t *state_offset);
1831 struct anv_state
1832 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1833 struct anv_state
1834 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1835 uint32_t size, uint32_t alignment);
1836
1837 VkResult
1838 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1839
1840 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1841 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1842 bool depth_clamp_enable);
1843 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1844
1845 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1846 struct anv_render_pass *pass,
1847 struct anv_framebuffer *framebuffer,
1848 const VkClearValue *clear_values);
1849
1850 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1851
1852 struct anv_state
1853 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1854 gl_shader_stage stage);
1855 struct anv_state
1856 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1857
1858 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1859 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1860
1861 const struct anv_image_view *
1862 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1863
1864 VkResult
1865 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1866 uint32_t num_entries,
1867 uint32_t *state_offset,
1868 struct anv_state *bt_state);
1869
1870 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1871
1872 enum anv_fence_type {
1873 ANV_FENCE_TYPE_NONE = 0,
1874 ANV_FENCE_TYPE_BO,
1875 ANV_FENCE_TYPE_SYNCOBJ,
1876 };
1877
1878 enum anv_bo_fence_state {
1879 /** Indicates that this is a new (or newly reset fence) */
1880 ANV_BO_FENCE_STATE_RESET,
1881
1882 /** Indicates that this fence has been submitted to the GPU but is still
1883 * (as far as we know) in use by the GPU.
1884 */
1885 ANV_BO_FENCE_STATE_SUBMITTED,
1886
1887 ANV_BO_FENCE_STATE_SIGNALED,
1888 };
1889
1890 struct anv_fence_impl {
1891 enum anv_fence_type type;
1892
1893 union {
1894 /** Fence implementation for BO fences
1895 *
1896 * These fences use a BO and a set of CPU-tracked state flags. The BO
1897 * is added to the object list of the last execbuf call in a QueueSubmit
1898 * and is marked EXEC_WRITE. The state flags track when the BO has been
1899 * submitted to the kernel. We need to do this because Vulkan lets you
1900 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1901 * will say it's idle in this case.
1902 */
1903 struct {
1904 struct anv_bo bo;
1905 enum anv_bo_fence_state state;
1906 } bo;
1907
1908 /** DRM syncobj handle for syncobj-based fences */
1909 uint32_t syncobj;
1910 };
1911 };
1912
1913 struct anv_fence {
1914 /* Permanent fence state. Every fence has some form of permanent state
1915 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1916 * cross-process fences) or it could just be a dummy for use internally.
1917 */
1918 struct anv_fence_impl permanent;
1919
1920 /* Temporary fence state. A fence *may* have temporary state. That state
1921 * is added to the fence by an import operation and is reset back to
1922 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1923 * state cannot be signaled because the fence must already be signaled
1924 * before the temporary state can be exported from the fence in the other
1925 * process and imported here.
1926 */
1927 struct anv_fence_impl temporary;
1928 };
1929
1930 struct anv_event {
1931 uint64_t semaphore;
1932 struct anv_state state;
1933 };
1934
1935 enum anv_semaphore_type {
1936 ANV_SEMAPHORE_TYPE_NONE = 0,
1937 ANV_SEMAPHORE_TYPE_DUMMY,
1938 ANV_SEMAPHORE_TYPE_BO,
1939 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1940 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1941 };
1942
1943 struct anv_semaphore_impl {
1944 enum anv_semaphore_type type;
1945
1946 union {
1947 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1948 * This BO will be added to the object list on any execbuf2 calls for
1949 * which this semaphore is used as a wait or signal fence. When used as
1950 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1951 */
1952 struct anv_bo *bo;
1953
1954 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
1955 * If the semaphore is in the unsignaled state due to either just being
1956 * created or because it has been used for a wait, fd will be -1.
1957 */
1958 int fd;
1959
1960 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1961 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1962 * import so we don't need to bother with a userspace cache.
1963 */
1964 uint32_t syncobj;
1965 };
1966 };
1967
1968 struct anv_semaphore {
1969 /* Permanent semaphore state. Every semaphore has some form of permanent
1970 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1971 * (for cross-process semaphores0 or it could just be a dummy for use
1972 * internally.
1973 */
1974 struct anv_semaphore_impl permanent;
1975
1976 /* Temporary semaphore state. A semaphore *may* have temporary state.
1977 * That state is added to the semaphore by an import operation and is reset
1978 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1979 * semaphore with temporary state cannot be signaled because the semaphore
1980 * must already be signaled before the temporary state can be exported from
1981 * the semaphore in the other process and imported here.
1982 */
1983 struct anv_semaphore_impl temporary;
1984 };
1985
1986 void anv_semaphore_reset_temporary(struct anv_device *device,
1987 struct anv_semaphore *semaphore);
1988
1989 struct anv_shader_module {
1990 unsigned char sha1[20];
1991 uint32_t size;
1992 char data[0];
1993 };
1994
1995 static inline gl_shader_stage
1996 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1997 {
1998 assert(__builtin_popcount(vk_stage) == 1);
1999 return ffs(vk_stage) - 1;
2000 }
2001
2002 static inline VkShaderStageFlagBits
2003 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2004 {
2005 return (1 << mesa_stage);
2006 }
2007
2008 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2009
2010 #define anv_foreach_stage(stage, stage_bits) \
2011 for (gl_shader_stage stage, \
2012 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2013 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2014 __tmp &= ~(1 << (stage)))
2015
2016 struct anv_pipeline_bind_map {
2017 uint32_t surface_count;
2018 uint32_t sampler_count;
2019 uint32_t image_count;
2020
2021 struct anv_pipeline_binding * surface_to_descriptor;
2022 struct anv_pipeline_binding * sampler_to_descriptor;
2023 };
2024
2025 struct anv_shader_bin_key {
2026 uint32_t size;
2027 uint8_t data[0];
2028 };
2029
2030 struct anv_shader_bin {
2031 uint32_t ref_cnt;
2032
2033 const struct anv_shader_bin_key *key;
2034
2035 struct anv_state kernel;
2036 uint32_t kernel_size;
2037
2038 const struct brw_stage_prog_data *prog_data;
2039 uint32_t prog_data_size;
2040
2041 struct anv_pipeline_bind_map bind_map;
2042 };
2043
2044 struct anv_shader_bin *
2045 anv_shader_bin_create(struct anv_device *device,
2046 const void *key, uint32_t key_size,
2047 const void *kernel, uint32_t kernel_size,
2048 const struct brw_stage_prog_data *prog_data,
2049 uint32_t prog_data_size, const void *prog_data_param,
2050 const struct anv_pipeline_bind_map *bind_map);
2051
2052 void
2053 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2054
2055 static inline void
2056 anv_shader_bin_ref(struct anv_shader_bin *shader)
2057 {
2058 assert(shader && shader->ref_cnt >= 1);
2059 p_atomic_inc(&shader->ref_cnt);
2060 }
2061
2062 static inline void
2063 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2064 {
2065 assert(shader && shader->ref_cnt >= 1);
2066 if (p_atomic_dec_zero(&shader->ref_cnt))
2067 anv_shader_bin_destroy(device, shader);
2068 }
2069
2070 struct anv_pipeline {
2071 struct anv_device * device;
2072 struct anv_batch batch;
2073 uint32_t batch_data[512];
2074 struct anv_reloc_list batch_relocs;
2075 uint32_t dynamic_state_mask;
2076 struct anv_dynamic_state dynamic_state;
2077
2078 struct anv_subpass * subpass;
2079 struct anv_pipeline_layout * layout;
2080
2081 bool needs_data_cache;
2082
2083 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2084
2085 struct {
2086 const struct gen_l3_config * l3_config;
2087 uint32_t total_size;
2088 } urb;
2089
2090 VkShaderStageFlags active_stages;
2091 struct anv_state blend_state;
2092
2093 uint32_t vb_used;
2094 uint32_t binding_stride[MAX_VBS];
2095 bool instancing_enable[MAX_VBS];
2096 bool primitive_restart;
2097 uint32_t topology;
2098
2099 uint32_t cs_right_mask;
2100
2101 bool writes_depth;
2102 bool depth_test_enable;
2103 bool writes_stencil;
2104 bool stencil_test_enable;
2105 bool depth_clamp_enable;
2106 bool sample_shading_enable;
2107 bool kill_pixel;
2108
2109 struct {
2110 uint32_t sf[7];
2111 uint32_t depth_stencil_state[3];
2112 } gen7;
2113
2114 struct {
2115 uint32_t sf[4];
2116 uint32_t raster[5];
2117 uint32_t wm_depth_stencil[3];
2118 } gen8;
2119
2120 struct {
2121 uint32_t wm_depth_stencil[4];
2122 } gen9;
2123
2124 uint32_t interface_descriptor_data[8];
2125 };
2126
2127 static inline bool
2128 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2129 gl_shader_stage stage)
2130 {
2131 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2132 }
2133
2134 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2135 static inline const struct brw_##prefix##_prog_data * \
2136 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2137 { \
2138 if (anv_pipeline_has_stage(pipeline, stage)) { \
2139 return (const struct brw_##prefix##_prog_data *) \
2140 pipeline->shaders[stage]->prog_data; \
2141 } else { \
2142 return NULL; \
2143 } \
2144 }
2145
2146 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2147 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2148 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2149 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2150 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2151 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2152
2153 static inline const struct brw_vue_prog_data *
2154 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2155 {
2156 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2157 return &get_gs_prog_data(pipeline)->base;
2158 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2159 return &get_tes_prog_data(pipeline)->base;
2160 else
2161 return &get_vs_prog_data(pipeline)->base;
2162 }
2163
2164 VkResult
2165 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2166 struct anv_pipeline_cache *cache,
2167 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2168 const VkAllocationCallbacks *alloc);
2169
2170 VkResult
2171 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2172 struct anv_pipeline_cache *cache,
2173 const VkComputePipelineCreateInfo *info,
2174 struct anv_shader_module *module,
2175 const char *entrypoint,
2176 const VkSpecializationInfo *spec_info);
2177
2178 struct anv_format_plane {
2179 enum isl_format isl_format:16;
2180 struct isl_swizzle swizzle;
2181
2182 /* Whether this plane contains chroma channels */
2183 bool has_chroma;
2184
2185 /* For downscaling of YUV planes */
2186 uint8_t denominator_scales[2];
2187
2188 /* How to map sampled ycbcr planes to a single 4 component element. */
2189 struct isl_swizzle ycbcr_swizzle;
2190 };
2191
2192
2193 struct anv_format {
2194 struct anv_format_plane planes[3];
2195 uint8_t n_planes;
2196 bool can_ycbcr;
2197 };
2198
2199 static inline uint32_t
2200 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2201 VkImageAspectFlags aspect_mask)
2202 {
2203 switch (aspect_mask) {
2204 case VK_IMAGE_ASPECT_COLOR_BIT:
2205 case VK_IMAGE_ASPECT_DEPTH_BIT:
2206 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2207 return 0;
2208 case VK_IMAGE_ASPECT_STENCIL_BIT:
2209 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2210 return 0;
2211 /* Fall-through */
2212 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2213 return 1;
2214 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2215 return 2;
2216 default:
2217 /* Purposefully assert with depth/stencil aspects. */
2218 unreachable("invalid image aspect");
2219 }
2220 }
2221
2222 static inline uint32_t
2223 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2224 {
2225 uint32_t planes = 0;
2226
2227 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2228 VK_IMAGE_ASPECT_DEPTH_BIT |
2229 VK_IMAGE_ASPECT_STENCIL_BIT |
2230 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2231 planes++;
2232 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2233 planes++;
2234 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2235 planes++;
2236
2237 return planes;
2238 }
2239
2240 static inline VkImageAspectFlags
2241 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2242 uint32_t plane)
2243 {
2244 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2245 if (_mesa_bitcount(image_aspects) > 1)
2246 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2247 return VK_IMAGE_ASPECT_COLOR_BIT;
2248 }
2249 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2250 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2251 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2252 return VK_IMAGE_ASPECT_STENCIL_BIT;
2253 }
2254
2255 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2256 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2257
2258 const struct anv_format *
2259 anv_get_format(VkFormat format);
2260
2261 static inline uint32_t
2262 anv_get_format_planes(VkFormat vk_format)
2263 {
2264 const struct anv_format *format = anv_get_format(vk_format);
2265
2266 return format != NULL ? format->n_planes : 0;
2267 }
2268
2269 struct anv_format_plane
2270 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2271 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2272
2273 static inline enum isl_format
2274 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2275 VkImageAspectFlags aspect, VkImageTiling tiling)
2276 {
2277 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2278 }
2279
2280 static inline struct isl_swizzle
2281 anv_swizzle_for_render(struct isl_swizzle swizzle)
2282 {
2283 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2284 * RGB as RGBA for texturing
2285 */
2286 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2287 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2288
2289 /* But it doesn't matter what we render to that channel */
2290 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2291
2292 return swizzle;
2293 }
2294
2295 void
2296 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2297
2298 /**
2299 * Subsurface of an anv_image.
2300 */
2301 struct anv_surface {
2302 /** Valid only if isl_surf::size > 0. */
2303 struct isl_surf isl;
2304
2305 /**
2306 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2307 */
2308 uint32_t offset;
2309 };
2310
2311 struct anv_image {
2312 VkImageType type;
2313 /* The original VkFormat provided by the client. This may not match any
2314 * of the actual surface formats.
2315 */
2316 VkFormat vk_format;
2317 const struct anv_format *format;
2318
2319 VkImageAspectFlags aspects;
2320 VkExtent3D extent;
2321 uint32_t levels;
2322 uint32_t array_size;
2323 uint32_t samples; /**< VkImageCreateInfo::samples */
2324 uint32_t n_planes;
2325 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2326 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2327
2328 /**
2329 * DRM format modifier for this image or DRM_FORMAT_MOD_INVALID.
2330 */
2331 uint64_t drm_format_mod;
2332
2333 VkDeviceSize size;
2334 uint32_t alignment;
2335
2336 /* Whether the image is made of several underlying buffer objects rather a
2337 * single one with different offsets.
2338 */
2339 bool disjoint;
2340
2341 /**
2342 * Image subsurfaces
2343 *
2344 * For each foo, anv_image::planes[x].surface is valid if and only if
2345 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2346 * to figure the number associated with a given aspect.
2347 *
2348 * The hardware requires that the depth buffer and stencil buffer be
2349 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2350 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2351 * allocate the depth and stencil buffers as separate surfaces in the same
2352 * bo.
2353 *
2354 * Memory layout :
2355 *
2356 * -----------------------
2357 * | surface0 | /|\
2358 * ----------------------- |
2359 * | shadow surface0 | |
2360 * ----------------------- | Plane 0
2361 * | aux surface0 | |
2362 * ----------------------- |
2363 * | fast clear colors0 | \|/
2364 * -----------------------
2365 * | surface1 | /|\
2366 * ----------------------- |
2367 * | shadow surface1 | |
2368 * ----------------------- | Plane 1
2369 * | aux surface1 | |
2370 * ----------------------- |
2371 * | fast clear colors1 | \|/
2372 * -----------------------
2373 * | ... |
2374 * | |
2375 * -----------------------
2376 */
2377 struct {
2378 /**
2379 * Offset of the entire plane (whenever the image is disjoint this is
2380 * set to 0).
2381 */
2382 uint32_t offset;
2383
2384 VkDeviceSize size;
2385 uint32_t alignment;
2386
2387 struct anv_surface surface;
2388
2389 /**
2390 * A surface which shadows the main surface and may have different
2391 * tiling. This is used for sampling using a tiling that isn't supported
2392 * for other operations.
2393 */
2394 struct anv_surface shadow_surface;
2395
2396 /**
2397 * For color images, this is the aux usage for this image when not used
2398 * as a color attachment.
2399 *
2400 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2401 * image has a HiZ buffer.
2402 */
2403 enum isl_aux_usage aux_usage;
2404
2405 struct anv_surface aux_surface;
2406
2407 /**
2408 * Offset of the fast clear state (used to compute the
2409 * fast_clear_state_offset of the following planes).
2410 */
2411 uint32_t fast_clear_state_offset;
2412
2413 /**
2414 * BO associated with this plane, set when bound.
2415 */
2416 struct anv_bo *bo;
2417 VkDeviceSize bo_offset;
2418
2419 /**
2420 * When destroying the image, also free the bo.
2421 * */
2422 bool bo_is_owned;
2423 } planes[3];
2424 };
2425
2426 /* Returns the number of auxiliary buffer levels attached to an image. */
2427 static inline uint8_t
2428 anv_image_aux_levels(const struct anv_image * const image,
2429 VkImageAspectFlagBits aspect)
2430 {
2431 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2432 return image->planes[plane].aux_surface.isl.size > 0 ?
2433 image->planes[plane].aux_surface.isl.levels : 0;
2434 }
2435
2436 /* Returns the number of auxiliary buffer layers attached to an image. */
2437 static inline uint32_t
2438 anv_image_aux_layers(const struct anv_image * const image,
2439 VkImageAspectFlagBits aspect,
2440 const uint8_t miplevel)
2441 {
2442 assert(image);
2443
2444 /* The miplevel must exist in the main buffer. */
2445 assert(miplevel < image->levels);
2446
2447 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2448 /* There are no layers with auxiliary data because the miplevel has no
2449 * auxiliary data.
2450 */
2451 return 0;
2452 } else {
2453 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2454 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2455 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2456 }
2457 }
2458
2459 static inline unsigned
2460 anv_fast_clear_state_entry_size(const struct anv_device *device)
2461 {
2462 assert(device);
2463 /* Entry contents:
2464 * +--------------------------------------------+
2465 * | clear value dword(s) | needs resolve dword |
2466 * +--------------------------------------------+
2467 */
2468
2469 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2470 * GPU memcpy operations.
2471 */
2472 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2473 return device->isl_dev.ss.clear_value_size + 4;
2474 }
2475
2476 static inline struct anv_address
2477 anv_image_get_clear_color_addr(const struct anv_device *device,
2478 const struct anv_image *image,
2479 VkImageAspectFlagBits aspect,
2480 unsigned level)
2481 {
2482 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2483 return (struct anv_address) {
2484 .bo = image->planes[plane].bo,
2485 .offset = image->planes[plane].bo_offset +
2486 image->planes[plane].fast_clear_state_offset +
2487 anv_fast_clear_state_entry_size(device) * level,
2488 };
2489 }
2490
2491 static inline struct anv_address
2492 anv_image_get_needs_resolve_addr(const struct anv_device *device,
2493 const struct anv_image *image,
2494 VkImageAspectFlagBits aspect,
2495 unsigned level)
2496 {
2497 struct anv_address addr =
2498 anv_image_get_clear_color_addr(device, image, aspect, level);
2499 addr.offset += device->isl_dev.ss.clear_value_size;
2500 return addr;
2501 }
2502
2503 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2504 static inline bool
2505 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2506 const struct anv_image *image)
2507 {
2508 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2509 return false;
2510
2511 if (devinfo->gen < 8)
2512 return false;
2513
2514 return image->samples == 1;
2515 }
2516
2517 void
2518 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2519 const struct anv_image *image,
2520 enum blorp_hiz_op op);
2521 void
2522 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2523 const struct anv_image * const image,
2524 VkImageAspectFlagBits aspect,
2525 const uint8_t level,
2526 const uint32_t start_layer, const uint32_t layer_count,
2527 const enum blorp_fast_clear_op op);
2528
2529 void
2530 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2531 const struct anv_image *image,
2532 VkImageAspectFlagBits aspect,
2533 const uint32_t base_level, const uint32_t level_count,
2534 const uint32_t base_layer, uint32_t layer_count);
2535
2536 void
2537 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2538 const struct anv_image *image,
2539 uint32_t base_level, uint32_t level_count,
2540 uint32_t base_layer, uint32_t layer_count);
2541
2542 enum isl_aux_usage
2543 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2544 const struct anv_image *image,
2545 const VkImageAspectFlagBits aspect,
2546 const VkImageLayout layout);
2547
2548 /* This is defined as a macro so that it works for both
2549 * VkImageSubresourceRange and VkImageSubresourceLayers
2550 */
2551 #define anv_get_layerCount(_image, _range) \
2552 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2553 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2554
2555 static inline uint32_t
2556 anv_get_levelCount(const struct anv_image *image,
2557 const VkImageSubresourceRange *range)
2558 {
2559 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2560 image->levels - range->baseMipLevel : range->levelCount;
2561 }
2562
2563 static inline VkImageAspectFlags
2564 anv_image_expand_aspects(const struct anv_image *image,
2565 VkImageAspectFlags aspects)
2566 {
2567 /* If the underlying image has color plane aspects and
2568 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2569 * the underlying image. */
2570 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2571 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2572 return image->aspects;
2573
2574 return aspects;
2575 }
2576
2577 static inline bool
2578 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2579 VkImageAspectFlags aspects2)
2580 {
2581 if (aspects1 == aspects2)
2582 return true;
2583
2584 /* Only 1 color aspects are compatibles. */
2585 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2586 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2587 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2588 return true;
2589
2590 return false;
2591 }
2592
2593 struct anv_image_view {
2594 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2595
2596 VkImageAspectFlags aspect_mask;
2597 VkFormat vk_format;
2598 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2599
2600 unsigned n_planes;
2601 struct {
2602 uint32_t image_plane;
2603
2604 struct isl_view isl;
2605
2606 /**
2607 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2608 * image layout of SHADER_READ_ONLY_OPTIMAL or
2609 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2610 */
2611 struct anv_surface_state optimal_sampler_surface_state;
2612
2613 /**
2614 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2615 * image layout of GENERAL.
2616 */
2617 struct anv_surface_state general_sampler_surface_state;
2618
2619 /**
2620 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2621 * states for write-only and readable, using the real format for
2622 * write-only and the lowered format for readable.
2623 */
2624 struct anv_surface_state storage_surface_state;
2625 struct anv_surface_state writeonly_storage_surface_state;
2626
2627 struct brw_image_param storage_image_param;
2628 } planes[3];
2629 };
2630
2631 enum anv_image_view_state_flags {
2632 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2633 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2634 };
2635
2636 void anv_image_fill_surface_state(struct anv_device *device,
2637 const struct anv_image *image,
2638 VkImageAspectFlagBits aspect,
2639 const struct isl_view *view,
2640 isl_surf_usage_flags_t view_usage,
2641 enum isl_aux_usage aux_usage,
2642 const union isl_color_value *clear_color,
2643 enum anv_image_view_state_flags flags,
2644 struct anv_surface_state *state_inout,
2645 struct brw_image_param *image_param_out);
2646
2647 struct anv_image_create_info {
2648 const VkImageCreateInfo *vk_info;
2649
2650 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2651 isl_tiling_flags_t isl_tiling_flags;
2652
2653 /** These flags will be added to any derived from VkImageCreateInfo. */
2654 isl_surf_usage_flags_t isl_extra_usage_flags;
2655
2656 uint32_t stride;
2657 };
2658
2659 VkResult anv_image_create(VkDevice _device,
2660 const struct anv_image_create_info *info,
2661 const VkAllocationCallbacks* alloc,
2662 VkImage *pImage);
2663
2664 #ifdef ANDROID
2665 VkResult anv_image_from_gralloc(VkDevice device_h,
2666 const VkImageCreateInfo *base_info,
2667 const VkNativeBufferANDROID *gralloc_info,
2668 const VkAllocationCallbacks *alloc,
2669 VkImage *pImage);
2670 #endif
2671
2672 const struct anv_surface *
2673 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2674 VkImageAspectFlags aspect_mask);
2675
2676 enum isl_format
2677 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2678
2679 static inline struct VkExtent3D
2680 anv_sanitize_image_extent(const VkImageType imageType,
2681 const struct VkExtent3D imageExtent)
2682 {
2683 switch (imageType) {
2684 case VK_IMAGE_TYPE_1D:
2685 return (VkExtent3D) { imageExtent.width, 1, 1 };
2686 case VK_IMAGE_TYPE_2D:
2687 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2688 case VK_IMAGE_TYPE_3D:
2689 return imageExtent;
2690 default:
2691 unreachable("invalid image type");
2692 }
2693 }
2694
2695 static inline struct VkOffset3D
2696 anv_sanitize_image_offset(const VkImageType imageType,
2697 const struct VkOffset3D imageOffset)
2698 {
2699 switch (imageType) {
2700 case VK_IMAGE_TYPE_1D:
2701 return (VkOffset3D) { imageOffset.x, 0, 0 };
2702 case VK_IMAGE_TYPE_2D:
2703 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2704 case VK_IMAGE_TYPE_3D:
2705 return imageOffset;
2706 default:
2707 unreachable("invalid image type");
2708 }
2709 }
2710
2711
2712 void anv_fill_buffer_surface_state(struct anv_device *device,
2713 struct anv_state state,
2714 enum isl_format format,
2715 uint32_t offset, uint32_t range,
2716 uint32_t stride);
2717
2718
2719 struct anv_ycbcr_conversion {
2720 const struct anv_format * format;
2721 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2722 VkSamplerYcbcrRangeKHR ycbcr_range;
2723 VkComponentSwizzle mapping[4];
2724 VkChromaLocationKHR chroma_offsets[2];
2725 VkFilter chroma_filter;
2726 bool chroma_reconstruction;
2727 };
2728
2729 struct anv_sampler {
2730 uint32_t state[3][4];
2731 uint32_t n_planes;
2732 struct anv_ycbcr_conversion *conversion;
2733 };
2734
2735 struct anv_framebuffer {
2736 uint32_t width;
2737 uint32_t height;
2738 uint32_t layers;
2739
2740 uint32_t attachment_count;
2741 struct anv_image_view * attachments[0];
2742 };
2743
2744 struct anv_subpass {
2745 uint32_t attachment_count;
2746
2747 /**
2748 * A pointer to all attachment references used in this subpass.
2749 * Only valid if ::attachment_count > 0.
2750 */
2751 VkAttachmentReference * attachments;
2752 uint32_t input_count;
2753 VkAttachmentReference * input_attachments;
2754 uint32_t color_count;
2755 VkAttachmentReference * color_attachments;
2756 VkAttachmentReference * resolve_attachments;
2757
2758 VkAttachmentReference depth_stencil_attachment;
2759
2760 uint32_t view_mask;
2761
2762 /** Subpass has a depth/stencil self-dependency */
2763 bool has_ds_self_dep;
2764
2765 /** Subpass has at least one resolve attachment */
2766 bool has_resolve;
2767 };
2768
2769 static inline unsigned
2770 anv_subpass_view_count(const struct anv_subpass *subpass)
2771 {
2772 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2773 }
2774
2775 struct anv_render_pass_attachment {
2776 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2777 * its members individually.
2778 */
2779 VkFormat format;
2780 uint32_t samples;
2781 VkImageUsageFlags usage;
2782 VkAttachmentLoadOp load_op;
2783 VkAttachmentStoreOp store_op;
2784 VkAttachmentLoadOp stencil_load_op;
2785 VkImageLayout initial_layout;
2786 VkImageLayout final_layout;
2787 VkImageLayout first_subpass_layout;
2788
2789 /* The subpass id in which the attachment will be used last. */
2790 uint32_t last_subpass_idx;
2791 };
2792
2793 struct anv_render_pass {
2794 uint32_t attachment_count;
2795 uint32_t subpass_count;
2796 /* An array of subpass_count+1 flushes, one per subpass boundary */
2797 enum anv_pipe_bits * subpass_flushes;
2798 struct anv_render_pass_attachment * attachments;
2799 struct anv_subpass subpasses[0];
2800 };
2801
2802 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2803
2804 struct anv_query_pool {
2805 VkQueryType type;
2806 VkQueryPipelineStatisticFlags pipeline_statistics;
2807 /** Stride between slots, in bytes */
2808 uint32_t stride;
2809 /** Number of slots in this query pool */
2810 uint32_t slots;
2811 struct anv_bo bo;
2812 };
2813
2814 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2815 const char *name);
2816
2817 void anv_dump_image_to_ppm(struct anv_device *device,
2818 struct anv_image *image, unsigned miplevel,
2819 unsigned array_layer, VkImageAspectFlagBits aspect,
2820 const char *filename);
2821
2822 enum anv_dump_action {
2823 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2824 };
2825
2826 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2827 void anv_dump_finish(void);
2828
2829 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2830 struct anv_framebuffer *fb);
2831
2832 static inline uint32_t
2833 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2834 {
2835 /* This function must be called from within a subpass. */
2836 assert(cmd_state->pass && cmd_state->subpass);
2837
2838 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2839
2840 /* The id of this subpass shouldn't exceed the number of subpasses in this
2841 * render pass minus 1.
2842 */
2843 assert(subpass_id < cmd_state->pass->subpass_count);
2844 return subpass_id;
2845 }
2846
2847 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2848 \
2849 static inline struct __anv_type * \
2850 __anv_type ## _from_handle(__VkType _handle) \
2851 { \
2852 return (struct __anv_type *) _handle; \
2853 } \
2854 \
2855 static inline __VkType \
2856 __anv_type ## _to_handle(struct __anv_type *_obj) \
2857 { \
2858 return (__VkType) _obj; \
2859 }
2860
2861 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2862 \
2863 static inline struct __anv_type * \
2864 __anv_type ## _from_handle(__VkType _handle) \
2865 { \
2866 return (struct __anv_type *)(uintptr_t) _handle; \
2867 } \
2868 \
2869 static inline __VkType \
2870 __anv_type ## _to_handle(struct __anv_type *_obj) \
2871 { \
2872 return (__VkType)(uintptr_t) _obj; \
2873 }
2874
2875 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2876 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2877
2878 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2879 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2880 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2881 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2882 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2883
2884 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2885 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2886 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2887 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2888 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2889 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2890 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2891 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2892 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2893 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2894 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2895 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2896 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2897 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2898 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2899 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2900 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2901 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2902 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2903 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2904 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2905 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
2906 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
2907
2908 /* Gen-specific function declarations */
2909 #ifdef genX
2910 # include "anv_genX.h"
2911 #else
2912 # define genX(x) gen7_##x
2913 # include "anv_genX.h"
2914 # undef genX
2915 # define genX(x) gen75_##x
2916 # include "anv_genX.h"
2917 # undef genX
2918 # define genX(x) gen8_##x
2919 # include "anv_genX.h"
2920 # undef genX
2921 # define genX(x) gen9_##x
2922 # include "anv_genX.h"
2923 # undef genX
2924 # define genX(x) gen10_##x
2925 # include "anv_genX.h"
2926 # undef genX
2927 #endif
2928
2929 #endif /* ANV_PRIVATE_H */