2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_gem.h"
48 #include "dev/gen_device_info.h"
49 #include "blorp/blorp.h"
50 #include "compiler/brw_compiler.h"
51 #include "util/macros.h"
52 #include "util/hash_table.h"
53 #include "util/list.h"
55 #include "util/u_atomic.h"
56 #include "util/u_vector.h"
57 #include "util/u_math.h"
60 #include "vk_debug_report.h"
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t
;
66 typedef uint32_t xcb_visualid_t
;
67 typedef uint32_t xcb_window_t
;
70 struct anv_buffer_view
;
71 struct anv_image_view
;
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
80 #include "anv_android.h"
81 #include "anv_entrypoints.h"
82 #include "anv_extensions.h"
85 #include "common/gen_debug.h"
86 #include "common/intel_log.h"
87 #include "wsi_common.h"
89 /* anv Virtual Memory Layout
90 * =========================
92 * When the anv driver is determining the virtual graphics addresses of memory
93 * objects itself using the softpin mechanism, the following memory ranges
96 * Three special considerations to notice:
98 * (1) the dynamic state pool is located within the same 4 GiB as the low
99 * heap. This is to work around a VF cache issue described in a comment in
100 * anv_physical_device_init_heaps.
102 * (2) the binding table pool is located at lower addresses than the surface
103 * state pool, within a 4 GiB range. This allows surface state base addresses
104 * to cover both binding tables (16 bit offsets) and surface states (32 bit
107 * (3) the last 4 GiB of the address space is withheld from the high
108 * heap. Various hardware units will read past the end of an object for
109 * various reasons. This healthy margin prevents reads from wrapping around
112 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
113 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
114 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
115 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
116 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
117 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
118 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
119 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
120 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
121 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
122 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
123 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
125 #define LOW_HEAP_SIZE \
126 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
127 #define HIGH_HEAP_SIZE \
128 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
129 #define DYNAMIC_STATE_POOL_SIZE \
130 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
131 #define BINDING_TABLE_POOL_SIZE \
132 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
133 #define SURFACE_STATE_POOL_SIZE \
134 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
135 #define INSTRUCTION_STATE_POOL_SIZE \
136 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
138 /* Allowing different clear colors requires us to perform a depth resolve at
139 * the end of certain render passes. This is because while slow clears store
140 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
141 * See the PRMs for examples describing when additional resolves would be
142 * necessary. To enable fast clears without requiring extra resolves, we set
143 * the clear value to a globally-defined one. We could allow different values
144 * if the user doesn't expect coherent data during or after a render passes
145 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
146 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
147 * 1.0f seems to be the only value used. The only application that doesn't set
148 * this value does so through the usage of an seemingly uninitialized clear
151 #define ANV_HZ_FC_VAL 1.0f
154 #define MAX_XFB_BUFFERS 4
155 #define MAX_XFB_STREAMS 4
158 #define MAX_VIEWPORTS 16
159 #define MAX_SCISSORS 16
160 #define MAX_PUSH_CONSTANTS_SIZE 128
161 #define MAX_DYNAMIC_BUFFERS 16
162 #define MAX_IMAGES 64
163 #define MAX_GEN8_IMAGES 8
164 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
166 /* The kernel relocation API has a limitation of a 32-bit delta value
167 * applied to the address before it is written which, in spite of it being
168 * unsigned, is treated as signed . Because of the way that this maps to
169 * the Vulkan API, we cannot handle an offset into a buffer that does not
170 * fit into a signed 32 bits. The only mechanism we have for dealing with
171 * this at the moment is to limit all VkDeviceMemory objects to a maximum
172 * of 2GB each. The Vulkan spec allows us to do this:
174 * "Some platforms may have a limit on the maximum size of a single
175 * allocation. For example, certain systems may fail to create
176 * allocations with a size greater than or equal to 4GB. Such a limit is
177 * implementation-dependent, and if such a failure occurs then the error
178 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
180 * We don't use vk_error here because it's not an error so much as an
181 * indication to the application that the allocation is too large.
183 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
185 #define ANV_SVGS_VB_INDEX MAX_VBS
186 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
188 /* We reserve this MI ALU register for the purpose of handling predication.
189 * Other code which uses the MI ALU should leave it alone.
191 #define ANV_PREDICATE_RESULT_REG MI_ALU_REG15
193 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
195 static inline uint32_t
196 align_down_npot_u32(uint32_t v
, uint32_t a
)
201 static inline uint32_t
202 align_u32(uint32_t v
, uint32_t a
)
204 assert(a
!= 0 && a
== (a
& -a
));
205 return (v
+ a
- 1) & ~(a
- 1);
208 static inline uint64_t
209 align_u64(uint64_t v
, uint64_t a
)
211 assert(a
!= 0 && a
== (a
& -a
));
212 return (v
+ a
- 1) & ~(a
- 1);
215 static inline int32_t
216 align_i32(int32_t v
, int32_t a
)
218 assert(a
!= 0 && a
== (a
& -a
));
219 return (v
+ a
- 1) & ~(a
- 1);
222 /** Alignment must be a power of 2. */
224 anv_is_aligned(uintmax_t n
, uintmax_t a
)
226 assert(a
== (a
& -a
));
227 return (n
& (a
- 1)) == 0;
230 static inline uint32_t
231 anv_minify(uint32_t n
, uint32_t levels
)
233 if (unlikely(n
== 0))
236 return MAX2(n
>> levels
, 1);
240 anv_clamp_f(float f
, float min
, float max
)
253 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
255 if (*inout_mask
& clear_mask
) {
256 *inout_mask
&= ~clear_mask
;
263 static inline union isl_color_value
264 vk_to_isl_color(VkClearColorValue color
)
266 return (union isl_color_value
) {
276 #define for_each_bit(b, dword) \
277 for (uint32_t __dword = (dword); \
278 (b) = __builtin_ffs(__dword) - 1, __dword; \
279 __dword &= ~(1 << (b)))
281 #define typed_memcpy(dest, src, count) ({ \
282 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
283 memcpy((dest), (src), (count) * sizeof(*(src))); \
286 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
287 * to be added here in order to utilize mapping in debug/error/perf macros.
289 #define REPORT_OBJECT_TYPE(o) \
290 __builtin_choose_expr ( \
291 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
292 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
293 __builtin_choose_expr ( \
294 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
295 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
296 __builtin_choose_expr ( \
297 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
298 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
299 __builtin_choose_expr ( \
300 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
301 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
302 __builtin_choose_expr ( \
303 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
304 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
305 __builtin_choose_expr ( \
306 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
307 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
308 __builtin_choose_expr ( \
309 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
310 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
311 __builtin_choose_expr ( \
312 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
313 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), void*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
383 /* The void expression results in a compile-time error \
384 when assigning the result to something. */ \
385 (void)0)))))))))))))))))))))))))))))))
387 /* Whenever we generate an error, pass it through this function. Useful for
388 * debugging, where we can break on it. Only call at error site, not when
389 * propagating errors. Might be useful to plug in a stack trace here.
392 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
393 VkDebugReportObjectTypeEXT type
, VkResult error
,
394 const char *file
, int line
, const char *format
,
397 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
398 VkDebugReportObjectTypeEXT type
, VkResult error
,
399 const char *file
, int line
, const char *format
, ...);
402 #define vk_error(error) __vk_errorf(NULL, NULL,\
403 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
404 error, __FILE__, __LINE__, NULL)
405 #define vk_errorv(instance, obj, error, format, args)\
406 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
407 __FILE__, __LINE__, format, args)
408 #define vk_errorf(instance, obj, error, format, ...)\
409 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
410 __FILE__, __LINE__, format, ## __VA_ARGS__)
412 #define vk_error(error) error
413 #define vk_errorf(instance, obj, error, format, ...) error
417 * Warn on ignored extension structs.
419 * The Vulkan spec requires us to ignore unsupported or unknown structs in
420 * a pNext chain. In debug mode, emitting warnings for ignored structs may
421 * help us discover structs that we should not have ignored.
424 * From the Vulkan 1.0.38 spec:
426 * Any component of the implementation (the loader, any enabled layers,
427 * and drivers) must skip over, without processing (other than reading the
428 * sType and pNext members) any chained structures with sType values not
429 * defined by extensions supported by that component.
431 #define anv_debug_ignored_stype(sType) \
432 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
434 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
435 VkDebugReportObjectTypeEXT type
, const char *file
,
436 int line
, const char *format
, ...)
437 anv_printflike(6, 7);
438 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
439 void anv_loge_v(const char *format
, va_list va
);
442 * Print a FINISHME message, including its source location.
444 #define anv_finishme(format, ...) \
446 static bool reported = false; \
448 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
455 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
457 #define anv_perf_warn(instance, obj, format, ...) \
459 static bool reported = false; \
460 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
461 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
462 format, ##__VA_ARGS__); \
467 /* A non-fatal assert. Useful for debugging. */
469 #define anv_assert(x) ({ \
470 if (unlikely(!(x))) \
471 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
474 #define anv_assert(x)
477 /* A multi-pointer allocator
479 * When copying data structures from the user (such as a render pass), it's
480 * common to need to allocate data for a bunch of different things. Instead
481 * of doing several allocations and having to handle all of the error checking
482 * that entails, it can be easier to do a single allocation. This struct
483 * helps facilitate that. The intended usage looks like this:
486 * anv_multialloc_add(&ma, &main_ptr, 1);
487 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
488 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
490 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
491 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
493 struct anv_multialloc
{
501 #define ANV_MULTIALLOC_INIT \
502 ((struct anv_multialloc) { 0, })
504 #define ANV_MULTIALLOC(_name) \
505 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
507 __attribute__((always_inline
))
509 _anv_multialloc_add(struct anv_multialloc
*ma
,
510 void **ptr
, size_t size
, size_t align
)
512 size_t offset
= align_u64(ma
->size
, align
);
513 ma
->size
= offset
+ size
;
514 ma
->align
= MAX2(ma
->align
, align
);
516 /* Store the offset in the pointer. */
517 *ptr
= (void *)(uintptr_t)offset
;
519 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
520 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
523 #define anv_multialloc_add_size(_ma, _ptr, _size) \
524 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
526 #define anv_multialloc_add(_ma, _ptr, _count) \
527 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
529 __attribute__((always_inline
))
531 anv_multialloc_alloc(struct anv_multialloc
*ma
,
532 const VkAllocationCallbacks
*alloc
,
533 VkSystemAllocationScope scope
)
535 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
539 /* Fill out each of the pointers with their final value.
541 * for (uint32_t i = 0; i < ma->ptr_count; i++)
542 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
544 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
545 * constant, GCC is incapable of figuring this out and unrolling the loop
546 * so we have to give it a little help.
548 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
549 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
550 if ((_i) < ma->ptr_count) \
551 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
552 _ANV_MULTIALLOC_UPDATE_POINTER(0);
553 _ANV_MULTIALLOC_UPDATE_POINTER(1);
554 _ANV_MULTIALLOC_UPDATE_POINTER(2);
555 _ANV_MULTIALLOC_UPDATE_POINTER(3);
556 _ANV_MULTIALLOC_UPDATE_POINTER(4);
557 _ANV_MULTIALLOC_UPDATE_POINTER(5);
558 _ANV_MULTIALLOC_UPDATE_POINTER(6);
559 _ANV_MULTIALLOC_UPDATE_POINTER(7);
560 #undef _ANV_MULTIALLOC_UPDATE_POINTER
565 __attribute__((always_inline
))
567 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
568 const VkAllocationCallbacks
*parent_alloc
,
569 const VkAllocationCallbacks
*alloc
,
570 VkSystemAllocationScope scope
)
572 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
575 /* Extra ANV-defined BO flags which won't be passed to the kernel */
576 #define ANV_BO_EXTERNAL (1ull << 31)
577 #define ANV_BO_FLAG_MASK (1ull << 31)
582 /* Index into the current validation list. This is used by the
583 * validation list building alrogithm to track which buffers are already
584 * in the validation list so that we can ensure uniqueness.
588 /* Last known offset. This value is provided by the kernel when we
589 * execbuf and is used as the presumed offset for the next bunch of
597 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
602 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
604 bo
->gem_handle
= gem_handle
;
612 /* Represents a lock-free linked list of "free" things. This is used by
613 * both the block pool and the state pools. Unfortunately, in order to
614 * solve the ABA problem, we can't use a single uint32_t head.
616 union anv_free_list
{
620 /* A simple count that is incremented every time the head changes. */
626 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
628 struct anv_block_state
{
638 #define anv_block_pool_foreach_bo(bo, pool) \
639 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
641 #define ANV_MAX_BLOCK_POOL_BOS 20
643 struct anv_block_pool
{
644 struct anv_device
*device
;
648 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
654 /* The address where the start of the pool is pinned. The various bos that
655 * are created as the pool grows will have addresses in the range
656 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
658 uint64_t start_address
;
660 /* The offset from the start of the bo to the "center" of the block
661 * pool. Pointers to allocated blocks are given by
662 * bo.map + center_bo_offset + offsets.
664 uint32_t center_bo_offset
;
666 /* Current memory map of the block pool. This pointer may or may not
667 * point to the actual beginning of the block pool memory. If
668 * anv_block_pool_alloc_back has ever been called, then this pointer
669 * will point to the "center" position of the buffer and all offsets
670 * (negative or positive) given out by the block pool alloc functions
671 * will be valid relative to this pointer.
673 * In particular, map == bo.map + center_offset
675 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
676 * since it will handle the softpin case as well, where this points to NULL.
682 * Array of mmaps and gem handles owned by the block pool, reclaimed when
683 * the block pool is destroyed.
685 struct u_vector mmap_cleanups
;
687 struct anv_block_state state
;
689 struct anv_block_state back_state
;
692 /* Block pools are backed by a fixed-size 1GB memfd */
693 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
695 /* The center of the block pool is also the middle of the memfd. This may
696 * change in the future if we decide differently for some reason.
698 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
700 static inline uint32_t
701 anv_block_pool_size(struct anv_block_pool
*pool
)
703 return pool
->state
.end
+ pool
->back_state
.end
;
713 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
715 struct anv_fixed_size_state_pool
{
716 union anv_free_list free_list
;
717 struct anv_block_state block
;
720 #define ANV_MIN_STATE_SIZE_LOG2 6
721 #define ANV_MAX_STATE_SIZE_LOG2 20
723 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
725 struct anv_free_entry
{
727 struct anv_state state
;
730 struct anv_state_table
{
731 struct anv_device
*device
;
733 struct anv_free_entry
*map
;
735 struct anv_block_state state
;
736 struct u_vector mmap_cleanups
;
739 struct anv_state_pool
{
740 struct anv_block_pool block_pool
;
742 struct anv_state_table table
;
744 /* The size of blocks which will be allocated from the block pool */
747 /** Free list for "back" allocations */
748 union anv_free_list back_alloc_free_list
;
750 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
753 struct anv_state_stream_block
;
755 struct anv_state_stream
{
756 struct anv_state_pool
*state_pool
;
758 /* The size of blocks to allocate from the state pool */
761 /* Current block we're allocating from */
762 struct anv_state block
;
764 /* Offset into the current block at which to allocate the next state */
767 /* List of all blocks allocated from this pool */
768 struct anv_state_stream_block
*block_list
;
771 /* The block_pool functions exported for testing only. The block pool should
772 * only be used via a state pool (see below).
774 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
775 struct anv_device
*device
,
776 uint64_t start_address
,
777 uint32_t initial_size
,
779 void anv_block_pool_finish(struct anv_block_pool
*pool
);
780 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
781 uint32_t block_size
, uint32_t *padding
);
782 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
783 uint32_t block_size
);
784 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
786 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
787 struct anv_device
*device
,
788 uint64_t start_address
,
791 void anv_state_pool_finish(struct anv_state_pool
*pool
);
792 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
793 uint32_t state_size
, uint32_t alignment
);
794 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
795 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
796 void anv_state_stream_init(struct anv_state_stream
*stream
,
797 struct anv_state_pool
*state_pool
,
798 uint32_t block_size
);
799 void anv_state_stream_finish(struct anv_state_stream
*stream
);
800 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
801 uint32_t size
, uint32_t alignment
);
803 VkResult
anv_state_table_init(struct anv_state_table
*table
,
804 struct anv_device
*device
,
805 uint32_t initial_entries
);
806 void anv_state_table_finish(struct anv_state_table
*table
);
807 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
809 void anv_free_list_push(union anv_free_list
*list
,
810 struct anv_state_table
*table
,
811 uint32_t idx
, uint32_t count
);
812 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
813 struct anv_state_table
*table
);
816 static inline struct anv_state
*
817 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
819 return &table
->map
[idx
].state
;
822 * Implements a pool of re-usable BOs. The interface is identical to that
823 * of block_pool except that each block is its own BO.
826 struct anv_device
*device
;
833 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
835 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
836 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
838 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
840 struct anv_scratch_bo
{
845 struct anv_scratch_pool
{
846 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
847 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
850 void anv_scratch_pool_init(struct anv_device
*device
,
851 struct anv_scratch_pool
*pool
);
852 void anv_scratch_pool_finish(struct anv_device
*device
,
853 struct anv_scratch_pool
*pool
);
854 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
855 struct anv_scratch_pool
*pool
,
856 gl_shader_stage stage
,
857 unsigned per_thread_scratch
);
859 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
860 struct anv_bo_cache
{
861 struct hash_table
*bo_map
;
862 pthread_mutex_t mutex
;
865 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
866 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
867 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
868 struct anv_bo_cache
*cache
,
869 uint64_t size
, uint64_t bo_flags
,
871 VkResult
anv_bo_cache_import(struct anv_device
*device
,
872 struct anv_bo_cache
*cache
,
873 int fd
, uint64_t bo_flags
,
875 VkResult
anv_bo_cache_export(struct anv_device
*device
,
876 struct anv_bo_cache
*cache
,
877 struct anv_bo
*bo_in
, int *fd_out
);
878 void anv_bo_cache_release(struct anv_device
*device
,
879 struct anv_bo_cache
*cache
,
882 struct anv_memory_type
{
883 /* Standard bits passed on to the client */
884 VkMemoryPropertyFlags propertyFlags
;
887 /* Driver-internal book-keeping */
888 VkBufferUsageFlags valid_buffer_usage
;
891 struct anv_memory_heap
{
892 /* Standard bits passed on to the client */
894 VkMemoryHeapFlags flags
;
896 /* Driver-internal book-keeping */
897 bool supports_48bit_addresses
;
900 struct anv_physical_device
{
901 VK_LOADER_DATA _loader_data
;
903 struct anv_instance
* instance
;
914 struct gen_device_info info
;
915 /** Amount of "GPU memory" we want to advertise
917 * Clearly, this value is bogus since Intel is a UMA architecture. On
918 * gen7 platforms, we are limited by GTT size unless we want to implement
919 * fine-grained tracking and GTT splitting. On Broadwell and above we are
920 * practically unlimited. However, we will never report more than 3/4 of
921 * the total system ram to try and avoid running out of RAM.
923 bool supports_48bit_addresses
;
924 struct brw_compiler
* compiler
;
925 struct isl_device isl_dev
;
926 int cmd_parser_version
;
928 bool has_exec_capture
;
931 bool has_syncobj_wait
;
932 bool has_context_priority
;
934 bool has_context_isolation
;
936 struct anv_device_extension_table supported_extensions
;
939 uint32_t subslice_total
;
943 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
945 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
948 uint8_t driver_build_sha1
[20];
949 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
950 uint8_t driver_uuid
[VK_UUID_SIZE
];
951 uint8_t device_uuid
[VK_UUID_SIZE
];
953 struct disk_cache
* disk_cache
;
955 struct wsi_device wsi_device
;
960 struct anv_app_info
{
961 const char* app_name
;
962 uint32_t app_version
;
963 const char* engine_name
;
964 uint32_t engine_version
;
965 uint32_t api_version
;
968 struct anv_instance
{
969 VK_LOADER_DATA _loader_data
;
971 VkAllocationCallbacks alloc
;
973 struct anv_app_info app_info
;
975 struct anv_instance_extension_table enabled_extensions
;
976 struct anv_instance_dispatch_table dispatch
;
977 struct anv_device_dispatch_table device_dispatch
;
979 int physicalDeviceCount
;
980 struct anv_physical_device physicalDevice
;
982 bool pipeline_cache_enabled
;
984 struct vk_debug_report_instance debug_report_callbacks
;
987 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
988 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
990 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
991 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
995 VK_LOADER_DATA _loader_data
;
997 struct anv_device
* device
;
999 VkDeviceQueueCreateFlags flags
;
1002 struct anv_pipeline_cache
{
1003 struct anv_device
* device
;
1004 pthread_mutex_t mutex
;
1006 struct hash_table
* nir_cache
;
1008 struct hash_table
* cache
;
1011 struct nir_xfb_info
;
1012 struct anv_pipeline_bind_map
;
1014 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1015 struct anv_device
*device
,
1016 bool cache_enabled
);
1017 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1019 struct anv_shader_bin
*
1020 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1021 const void *key
, uint32_t key_size
);
1022 struct anv_shader_bin
*
1023 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1024 const void *key_data
, uint32_t key_size
,
1025 const void *kernel_data
, uint32_t kernel_size
,
1026 const void *constant_data
,
1027 uint32_t constant_data_size
,
1028 const struct brw_stage_prog_data
*prog_data
,
1029 uint32_t prog_data_size
,
1030 const struct nir_xfb_info
*xfb_info
,
1031 const struct anv_pipeline_bind_map
*bind_map
);
1033 struct anv_shader_bin
*
1034 anv_device_search_for_kernel(struct anv_device
*device
,
1035 struct anv_pipeline_cache
*cache
,
1036 const void *key_data
, uint32_t key_size
);
1038 struct anv_shader_bin
*
1039 anv_device_upload_kernel(struct anv_device
*device
,
1040 struct anv_pipeline_cache
*cache
,
1041 const void *key_data
, uint32_t key_size
,
1042 const void *kernel_data
, uint32_t kernel_size
,
1043 const void *constant_data
,
1044 uint32_t constant_data_size
,
1045 const struct brw_stage_prog_data
*prog_data
,
1046 uint32_t prog_data_size
,
1047 const struct nir_xfb_info
*xfb_info
,
1048 const struct anv_pipeline_bind_map
*bind_map
);
1051 struct nir_shader_compiler_options
;
1054 anv_device_search_for_nir(struct anv_device
*device
,
1055 struct anv_pipeline_cache
*cache
,
1056 const struct nir_shader_compiler_options
*nir_options
,
1057 unsigned char sha1_key
[20],
1061 anv_device_upload_nir(struct anv_device
*device
,
1062 struct anv_pipeline_cache
*cache
,
1063 const struct nir_shader
*nir
,
1064 unsigned char sha1_key
[20]);
1067 VK_LOADER_DATA _loader_data
;
1069 VkAllocationCallbacks alloc
;
1071 struct anv_instance
* instance
;
1072 uint32_t chipset_id
;
1074 struct gen_device_info info
;
1075 struct isl_device isl_dev
;
1078 bool can_chain_batches
;
1079 bool robust_buffer_access
;
1080 struct anv_device_extension_table enabled_extensions
;
1081 struct anv_device_dispatch_table dispatch
;
1083 pthread_mutex_t vma_mutex
;
1084 struct util_vma_heap vma_lo
;
1085 struct util_vma_heap vma_hi
;
1086 uint64_t vma_lo_available
;
1087 uint64_t vma_hi_available
;
1089 struct anv_bo_pool batch_bo_pool
;
1091 struct anv_bo_cache bo_cache
;
1093 struct anv_state_pool dynamic_state_pool
;
1094 struct anv_state_pool instruction_state_pool
;
1095 struct anv_state_pool binding_table_pool
;
1096 struct anv_state_pool surface_state_pool
;
1098 struct anv_bo workaround_bo
;
1099 struct anv_bo trivial_batch_bo
;
1100 struct anv_bo hiz_clear_bo
;
1102 struct anv_pipeline_cache default_pipeline_cache
;
1103 struct blorp_context blorp
;
1105 struct anv_state border_colors
;
1107 struct anv_queue queue
;
1109 struct anv_scratch_pool scratch_pool
;
1111 uint32_t default_mocs
;
1112 uint32_t external_mocs
;
1114 pthread_mutex_t mutex
;
1115 pthread_cond_t queue_submit
;
1119 static inline struct anv_state_pool
*
1120 anv_binding_table_pool(struct anv_device
*device
)
1122 if (device
->instance
->physicalDevice
.use_softpin
)
1123 return &device
->binding_table_pool
;
1125 return &device
->surface_state_pool
;
1128 static inline struct anv_state
1129 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1130 if (device
->instance
->physicalDevice
.use_softpin
)
1131 return anv_state_pool_alloc(&device
->binding_table_pool
,
1132 device
->binding_table_pool
.block_size
, 0);
1134 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1138 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1139 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1142 static inline uint32_t
1143 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1145 if (bo
->flags
& ANV_BO_EXTERNAL
)
1146 return device
->external_mocs
;
1148 return device
->default_mocs
;
1151 void anv_device_init_blorp(struct anv_device
*device
);
1152 void anv_device_finish_blorp(struct anv_device
*device
);
1154 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1155 const char *file
, int line
,
1156 const char *msg
, ...);
1157 #define anv_device_set_lost(dev, ...) \
1158 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1161 anv_device_is_lost(struct anv_device
*device
)
1163 return unlikely(device
->_lost
);
1166 VkResult
anv_device_execbuf(struct anv_device
*device
,
1167 struct drm_i915_gem_execbuffer2
*execbuf
,
1168 struct anv_bo
**execbuf_bos
);
1169 VkResult
anv_device_query_status(struct anv_device
*device
);
1170 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1171 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1174 void* anv_gem_mmap(struct anv_device
*device
,
1175 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1176 void anv_gem_munmap(void *p
, uint64_t size
);
1177 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1178 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1179 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1180 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1181 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1182 int anv_gem_execbuffer(struct anv_device
*device
,
1183 struct drm_i915_gem_execbuffer2
*execbuf
);
1184 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1185 uint32_t stride
, uint32_t tiling
);
1186 int anv_gem_create_context(struct anv_device
*device
);
1187 bool anv_gem_has_context_priority(int fd
);
1188 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1189 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1191 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1193 int anv_gem_get_param(int fd
, uint32_t param
);
1194 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1195 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1196 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1197 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1198 uint32_t *active
, uint32_t *pending
);
1199 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1200 int anv_gem_reg_read(struct anv_device
*device
,
1201 uint32_t offset
, uint64_t *result
);
1202 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1203 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1204 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1205 uint32_t read_domains
, uint32_t write_domain
);
1206 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1207 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1208 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1209 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1210 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1211 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1213 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1214 uint32_t handle
, int fd
);
1215 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1216 bool anv_gem_supports_syncobj_wait(int fd
);
1217 int anv_gem_syncobj_wait(struct anv_device
*device
,
1218 uint32_t *handles
, uint32_t num_handles
,
1219 int64_t abs_timeout_ns
, bool wait_all
);
1221 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1222 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1224 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1226 struct anv_reloc_list
{
1227 uint32_t num_relocs
;
1228 uint32_t array_length
;
1229 struct drm_i915_gem_relocation_entry
* relocs
;
1230 struct anv_bo
** reloc_bos
;
1234 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1235 const VkAllocationCallbacks
*alloc
);
1236 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1237 const VkAllocationCallbacks
*alloc
);
1239 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1240 const VkAllocationCallbacks
*alloc
,
1241 uint32_t offset
, struct anv_bo
*target_bo
,
1244 struct anv_batch_bo
{
1245 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1246 struct list_head link
;
1250 /* Bytes actually consumed in this batch BO */
1253 struct anv_reloc_list relocs
;
1257 const VkAllocationCallbacks
* alloc
;
1263 struct anv_reloc_list
* relocs
;
1265 /* This callback is called (with the associated user data) in the event
1266 * that the batch runs out of space.
1268 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1272 * Current error status of the command buffer. Used to track inconsistent
1273 * or incomplete command buffer states that are the consequence of run-time
1274 * errors such as out of memory scenarios. We want to track this in the
1275 * batch because the command buffer object is not visible to some parts
1281 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1282 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1283 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1284 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1285 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1286 struct anv_batch
*batch
);
1288 static inline VkResult
1289 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1291 assert(error
!= VK_SUCCESS
);
1292 if (batch
->status
== VK_SUCCESS
)
1293 batch
->status
= error
;
1294 return batch
->status
;
1298 anv_batch_has_error(struct anv_batch
*batch
)
1300 return batch
->status
!= VK_SUCCESS
;
1303 struct anv_address
{
1308 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1311 anv_address_is_null(struct anv_address addr
)
1313 return addr
.bo
== NULL
&& addr
.offset
== 0;
1316 static inline uint64_t
1317 anv_address_physical(struct anv_address addr
)
1319 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1320 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1322 return gen_canonical_address(addr
.offset
);
1325 static inline struct anv_address
1326 anv_address_add(struct anv_address addr
, uint64_t offset
)
1328 addr
.offset
+= offset
;
1333 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1335 unsigned reloc_size
= 0;
1336 if (device
->info
.gen
>= 8) {
1337 reloc_size
= sizeof(uint64_t);
1338 *(uint64_t *)p
= gen_canonical_address(v
);
1340 reloc_size
= sizeof(uint32_t);
1344 if (flush
&& !device
->info
.has_llc
)
1345 gen_flush_range(p
, reloc_size
);
1348 static inline uint64_t
1349 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1350 const struct anv_address address
, uint32_t delta
)
1352 if (address
.bo
== NULL
) {
1353 return address
.offset
+ delta
;
1355 assert(batch
->start
<= location
&& location
< batch
->end
);
1357 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1361 #define __gen_address_type struct anv_address
1362 #define __gen_user_data struct anv_batch
1363 #define __gen_combine_address _anv_combine_address
1365 /* Wrapper macros needed to work around preprocessor argument issues. In
1366 * particular, arguments don't get pre-evaluated if they are concatenated.
1367 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1368 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1369 * We can work around this easily enough with these helpers.
1371 #define __anv_cmd_length(cmd) cmd ## _length
1372 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1373 #define __anv_cmd_header(cmd) cmd ## _header
1374 #define __anv_cmd_pack(cmd) cmd ## _pack
1375 #define __anv_reg_num(reg) reg ## _num
1377 #define anv_pack_struct(dst, struc, ...) do { \
1378 struct struc __template = { \
1381 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1382 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1385 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1386 void *__dst = anv_batch_emit_dwords(batch, n); \
1388 struct cmd __template = { \
1389 __anv_cmd_header(cmd), \
1390 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1393 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1398 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1402 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1403 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1406 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1407 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1408 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1411 #define anv_batch_emit(batch, cmd, name) \
1412 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1413 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1414 __builtin_expect(_dst != NULL, 1); \
1415 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1416 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1420 /* MEMORY_OBJECT_CONTROL_STATE:
1421 * .GraphicsDataTypeGFDT = 0,
1422 * .LLCCacheabilityControlLLCCC = 0,
1423 * .L3CacheabilityControlL3CC = 1,
1427 /* MEMORY_OBJECT_CONTROL_STATE:
1428 * .LLCeLLCCacheabilityControlLLCCC = 0,
1429 * .L3CacheabilityControlL3CC = 1,
1431 #define GEN75_MOCS 1
1433 /* MEMORY_OBJECT_CONTROL_STATE:
1434 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1435 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1436 * .AgeforQUADLRU = 0
1438 #define GEN8_MOCS 0x78
1440 /* MEMORY_OBJECT_CONTROL_STATE:
1441 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1442 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1443 * .AgeforQUADLRU = 0
1445 #define GEN8_EXTERNAL_MOCS 0x18
1447 /* Skylake: MOCS is now an index into an array of 62 different caching
1448 * configurations programmed by the kernel.
1451 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1454 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1455 #define GEN9_EXTERNAL_MOCS 1
1457 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1458 #define GEN10_MOCS GEN9_MOCS
1459 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1461 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1462 #define GEN11_MOCS GEN9_MOCS
1463 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1465 struct anv_device_memory
{
1467 struct anv_memory_type
* type
;
1468 VkDeviceSize map_size
;
1471 /* If set, we are holding reference to AHardwareBuffer
1472 * which we must release when memory is freed.
1474 struct AHardwareBuffer
* ahw
;
1478 * Header for Vertex URB Entry (VUE)
1480 struct anv_vue_header
{
1482 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1483 uint32_t ViewportIndex
;
1487 struct anv_descriptor_set_binding_layout
{
1489 /* The type of the descriptors in this binding */
1490 VkDescriptorType type
;
1493 /* Number of array elements in this binding */
1494 uint16_t array_size
;
1496 /* Index into the flattend descriptor set */
1497 uint16_t descriptor_index
;
1499 /* Index into the dynamic state array for a dynamic buffer */
1500 int16_t dynamic_offset_index
;
1502 /* Index into the descriptor set buffer views */
1503 int16_t buffer_index
;
1506 /* Index into the binding table for the associated surface */
1507 int16_t surface_index
;
1509 /* Index into the sampler table for the associated sampler */
1510 int16_t sampler_index
;
1512 /* Index into the image table for the associated image */
1513 int16_t image_index
;
1514 } stage
[MESA_SHADER_STAGES
];
1516 /* Immutable samplers (or NULL if no immutable samplers) */
1517 struct anv_sampler
**immutable_samplers
;
1520 struct anv_descriptor_set_layout
{
1521 /* Descriptor set layouts can be destroyed at almost any time */
1524 /* Number of bindings in this descriptor set */
1525 uint16_t binding_count
;
1527 /* Total size of the descriptor set with room for all array entries */
1530 /* Shader stages affected by this descriptor set */
1531 uint16_t shader_stages
;
1533 /* Number of buffers in this descriptor set */
1534 uint16_t buffer_count
;
1536 /* Number of dynamic offsets used by this descriptor set */
1537 uint16_t dynamic_offset_count
;
1539 /* Bindings in this descriptor set */
1540 struct anv_descriptor_set_binding_layout binding
[0];
1544 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1546 assert(layout
&& layout
->ref_cnt
>= 1);
1547 p_atomic_inc(&layout
->ref_cnt
);
1551 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1552 struct anv_descriptor_set_layout
*layout
)
1554 assert(layout
&& layout
->ref_cnt
>= 1);
1555 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1556 vk_free(&device
->alloc
, layout
);
1559 struct anv_descriptor
{
1560 VkDescriptorType type
;
1564 VkImageLayout layout
;
1565 struct anv_image_view
*image_view
;
1566 struct anv_sampler
*sampler
;
1570 struct anv_buffer
*buffer
;
1575 struct anv_buffer_view
*buffer_view
;
1579 struct anv_descriptor_set
{
1580 struct anv_descriptor_set_layout
*layout
;
1582 uint32_t buffer_count
;
1583 struct anv_buffer_view
*buffer_views
;
1584 struct anv_descriptor descriptors
[0];
1587 struct anv_buffer_view
{
1588 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1589 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1591 struct anv_address address
;
1593 struct anv_state surface_state
;
1594 struct anv_state storage_surface_state
;
1595 struct anv_state writeonly_storage_surface_state
;
1597 struct brw_image_param storage_image_param
;
1600 struct anv_push_descriptor_set
{
1601 struct anv_descriptor_set set
;
1603 /* Put this field right behind anv_descriptor_set so it fills up the
1604 * descriptors[0] field. */
1605 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1606 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1609 struct anv_descriptor_pool
{
1614 struct anv_state_stream surface_state_stream
;
1615 void *surface_state_free_list
;
1620 enum anv_descriptor_template_entry_type
{
1621 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1622 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1623 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1626 struct anv_descriptor_template_entry
{
1627 /* The type of descriptor in this entry */
1628 VkDescriptorType type
;
1630 /* Binding in the descriptor set */
1633 /* Offset at which to write into the descriptor set binding */
1634 uint32_t array_element
;
1636 /* Number of elements to write into the descriptor set binding */
1637 uint32_t array_count
;
1639 /* Offset into the user provided data */
1642 /* Stride between elements into the user provided data */
1646 struct anv_descriptor_update_template
{
1647 VkPipelineBindPoint bind_point
;
1649 /* The descriptor set this template corresponds to. This value is only
1650 * valid if the template was created with the templateType
1651 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1655 /* Number of entries in this template */
1656 uint32_t entry_count
;
1658 /* Entries of the template */
1659 struct anv_descriptor_template_entry entries
[0];
1663 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1666 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1667 const struct gen_device_info
* const devinfo
,
1668 const VkDescriptorImageInfo
* const info
,
1669 VkDescriptorType type
,
1674 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1675 VkDescriptorType type
,
1676 struct anv_buffer_view
*buffer_view
,
1681 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1682 struct anv_device
*device
,
1683 struct anv_state_stream
*alloc_stream
,
1684 VkDescriptorType type
,
1685 struct anv_buffer
*buffer
,
1688 VkDeviceSize offset
,
1689 VkDeviceSize range
);
1692 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1693 struct anv_device
*device
,
1694 struct anv_state_stream
*alloc_stream
,
1695 const struct anv_descriptor_update_template
*template,
1699 anv_descriptor_set_create(struct anv_device
*device
,
1700 struct anv_descriptor_pool
*pool
,
1701 struct anv_descriptor_set_layout
*layout
,
1702 struct anv_descriptor_set
**out_set
);
1705 anv_descriptor_set_destroy(struct anv_device
*device
,
1706 struct anv_descriptor_pool
*pool
,
1707 struct anv_descriptor_set
*set
);
1709 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1710 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1712 struct anv_pipeline_binding
{
1713 /* The descriptor set this surface corresponds to. The special value of
1714 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1715 * to a color attachment and not a regular descriptor.
1719 /* Binding in the descriptor set */
1722 /* Index in the binding */
1725 /* Plane in the binding index */
1728 /* Input attachment index (relative to the subpass) */
1729 uint8_t input_attachment_index
;
1731 /* For a storage image, whether it is write-only */
1735 struct anv_pipeline_layout
{
1737 struct anv_descriptor_set_layout
*layout
;
1738 uint32_t dynamic_offset_start
;
1744 bool has_dynamic_offsets
;
1745 } stage
[MESA_SHADER_STAGES
];
1747 unsigned char sha1
[20];
1751 struct anv_device
* device
;
1754 VkBufferUsageFlags usage
;
1756 /* Set when bound */
1757 struct anv_address address
;
1760 static inline uint64_t
1761 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1763 assert(offset
<= buffer
->size
);
1764 if (range
== VK_WHOLE_SIZE
) {
1765 return buffer
->size
- offset
;
1767 assert(range
+ offset
>= range
);
1768 assert(range
+ offset
<= buffer
->size
);
1773 enum anv_cmd_dirty_bits
{
1774 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1775 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1776 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1777 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1778 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1779 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1780 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1781 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1782 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1783 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1784 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1785 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1786 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1787 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1789 typedef uint32_t anv_cmd_dirty_mask_t
;
1791 enum anv_pipe_bits
{
1792 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1793 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1794 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1795 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1796 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1797 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1798 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1799 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1800 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1801 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1802 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1804 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1805 * a flush has happened but not a CS stall. The next time we do any sort
1806 * of invalidation we need to insert a CS stall at that time. Otherwise,
1807 * we would have to CS stall on every flush which could be bad.
1809 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1811 /* This bit does not exist directly in PIPE_CONTROL. It means that render
1812 * target operations related to transfer commands with VkBuffer as
1813 * destination are ongoing. Some operations like copies on the command
1814 * streamer might need to be aware of this to trigger the appropriate stall
1815 * before they can proceed with the copy.
1817 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
1820 #define ANV_PIPE_FLUSH_BITS ( \
1821 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1822 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1823 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1825 #define ANV_PIPE_STALL_BITS ( \
1826 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1827 ANV_PIPE_DEPTH_STALL_BIT | \
1828 ANV_PIPE_CS_STALL_BIT)
1830 #define ANV_PIPE_INVALIDATE_BITS ( \
1831 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1832 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1833 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1834 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1835 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1836 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1838 static inline enum anv_pipe_bits
1839 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1841 enum anv_pipe_bits pipe_bits
= 0;
1844 for_each_bit(b
, flags
) {
1845 switch ((VkAccessFlagBits
)(1 << b
)) {
1846 case VK_ACCESS_SHADER_WRITE_BIT
:
1847 /* We're transitioning a buffer that was previously used as write
1848 * destination through the data port. To make its content available
1849 * to future operations, flush the data cache.
1851 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1853 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1854 /* We're transitioning a buffer that was previously used as render
1855 * target. To make its content available to future operations, flush
1856 * the render target cache.
1858 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1860 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1861 /* We're transitioning a buffer that was previously used as depth
1862 * buffer. To make its content available to future operations, flush
1865 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1867 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1868 /* We're transitioning a buffer that was previously used as a
1869 * transfer write destination. Generic write operations include color
1870 * & depth operations as well as buffer operations like :
1871 * - vkCmdClearColorImage()
1872 * - vkCmdClearDepthStencilImage()
1873 * - vkCmdBlitImage()
1874 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
1876 * Most of these operations are implemented using Blorp which writes
1877 * through the render target, so flush that cache to make it visible
1878 * to future operations. And for depth related operations we also
1879 * need to flush the depth cache.
1881 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1882 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1884 case VK_ACCESS_MEMORY_WRITE_BIT
:
1885 /* We're transitioning a buffer for generic write operations. Flush
1888 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1891 break; /* Nothing to do */
1898 static inline enum anv_pipe_bits
1899 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1901 enum anv_pipe_bits pipe_bits
= 0;
1904 for_each_bit(b
, flags
) {
1905 switch ((VkAccessFlagBits
)(1 << b
)) {
1906 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1907 /* Indirect draw commands take a buffer as input that we're going to
1908 * read from the command streamer to load some of the HW registers
1909 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
1910 * command streamer stall so that all the cache flushes have
1911 * completed before the command streamer loads from memory.
1913 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1914 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
1915 * through a vertex buffer, so invalidate that cache.
1917 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1918 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
1919 * UBO from the buffer, so we need to invalidate constant cache.
1921 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1923 case VK_ACCESS_INDEX_READ_BIT
:
1924 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1925 /* We transitioning a buffer to be used for as input for vkCmdDraw*
1926 * commands, so we invalidate the VF cache to make sure there is no
1927 * stale data when we start rendering.
1929 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1931 case VK_ACCESS_UNIFORM_READ_BIT
:
1932 /* We transitioning a buffer to be used as uniform data. Because
1933 * uniform is accessed through the data port & sampler, we need to
1934 * invalidate the texture cache (sampler) & constant cache (data
1935 * port) to avoid stale data.
1937 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1938 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1940 case VK_ACCESS_SHADER_READ_BIT
:
1941 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1942 case VK_ACCESS_TRANSFER_READ_BIT
:
1943 /* Transitioning a buffer to be read through the sampler, so
1944 * invalidate the texture cache, we don't want any stale data.
1946 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1948 case VK_ACCESS_MEMORY_READ_BIT
:
1949 /* Transitioning a buffer for generic read, invalidate all the
1952 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
1954 case VK_ACCESS_MEMORY_WRITE_BIT
:
1955 /* Generic write, make sure all previously written things land in
1958 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1960 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
1961 /* Transitioning a buffer for conditional rendering. We'll load the
1962 * content of this buffer into HW registers using the command
1963 * streamer, so we need to stall the command streamer to make sure
1964 * any in-flight flush operations have completed.
1966 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1969 break; /* Nothing to do */
1976 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1977 VK_IMAGE_ASPECT_COLOR_BIT | \
1978 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1979 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1980 VK_IMAGE_ASPECT_PLANE_2_BIT)
1981 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1982 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1983 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1984 VK_IMAGE_ASPECT_PLANE_2_BIT)
1986 struct anv_vertex_binding
{
1987 struct anv_buffer
* buffer
;
1988 VkDeviceSize offset
;
1991 struct anv_xfb_binding
{
1992 struct anv_buffer
* buffer
;
1993 VkDeviceSize offset
;
1997 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1998 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2000 struct anv_push_constants
{
2001 /* Current allocated size of this push constants data structure.
2002 * Because a decent chunk of it may not be used (images on SKL, for
2003 * instance), we won't actually allocate the entire structure up-front.
2007 /* Push constant data provided by the client through vkPushConstants */
2008 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2010 /* Used for vkCmdDispatchBase */
2011 uint32_t base_work_group_id
[3];
2013 /* Image data for image_load_store on pre-SKL */
2014 struct brw_image_param images
[MAX_GEN8_IMAGES
];
2017 struct anv_dynamic_state
{
2020 VkViewport viewports
[MAX_VIEWPORTS
];
2025 VkRect2D scissors
[MAX_SCISSORS
];
2036 float blend_constants
[4];
2046 } stencil_compare_mask
;
2051 } stencil_write_mask
;
2056 } stencil_reference
;
2059 extern const struct anv_dynamic_state default_dynamic_state
;
2061 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2062 const struct anv_dynamic_state
*src
,
2063 uint32_t copy_mask
);
2065 struct anv_surface_state
{
2066 struct anv_state state
;
2067 /** Address of the surface referred to by this state
2069 * This address is relative to the start of the BO.
2071 struct anv_address address
;
2072 /* Address of the aux surface, if any
2074 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2076 * With the exception of gen8, the bottom 12 bits of this address' offset
2077 * include extra aux information.
2079 struct anv_address aux_address
;
2080 /* Address of the clear color, if any
2082 * This address is relative to the start of the BO.
2084 struct anv_address clear_address
;
2088 * Attachment state when recording a renderpass instance.
2090 * The clear value is valid only if there exists a pending clear.
2092 struct anv_attachment_state
{
2093 enum isl_aux_usage aux_usage
;
2094 enum isl_aux_usage input_aux_usage
;
2095 struct anv_surface_state color
;
2096 struct anv_surface_state input
;
2098 VkImageLayout current_layout
;
2099 VkImageAspectFlags pending_clear_aspects
;
2100 VkImageAspectFlags pending_load_aspects
;
2102 VkClearValue clear_value
;
2103 bool clear_color_is_zero_one
;
2104 bool clear_color_is_zero
;
2106 /* When multiview is active, attachments with a renderpass clear
2107 * operation have their respective layers cleared on the first
2108 * subpass that uses them, and only in that subpass. We keep track
2109 * of this using a bitfield to indicate which layers of an attachment
2110 * have not been cleared yet when multiview is active.
2112 uint32_t pending_clear_views
;
2115 /** State tracking for particular pipeline bind point
2117 * This struct is the base struct for anv_cmd_graphics_state and
2118 * anv_cmd_compute_state. These are used to track state which is bound to a
2119 * particular type of pipeline. Generic state that applies per-stage such as
2120 * binding table offsets and push constants is tracked generically with a
2121 * per-stage array in anv_cmd_state.
2123 struct anv_cmd_pipeline_state
{
2124 struct anv_pipeline
*pipeline
;
2125 struct anv_pipeline_layout
*layout
;
2127 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2128 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2130 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2133 /** State tracking for graphics pipeline
2135 * This has anv_cmd_pipeline_state as a base struct to track things which get
2136 * bound to a graphics pipeline. Along with general pipeline bind point state
2137 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2138 * state which is graphics-specific.
2140 struct anv_cmd_graphics_state
{
2141 struct anv_cmd_pipeline_state base
;
2143 anv_cmd_dirty_mask_t dirty
;
2146 struct anv_dynamic_state dynamic
;
2149 struct anv_buffer
*index_buffer
;
2150 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2151 uint32_t index_offset
;
2155 /** State tracking for compute pipeline
2157 * This has anv_cmd_pipeline_state as a base struct to track things which get
2158 * bound to a compute pipeline. Along with general pipeline bind point state
2159 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2160 * state which is compute-specific.
2162 struct anv_cmd_compute_state
{
2163 struct anv_cmd_pipeline_state base
;
2165 bool pipeline_dirty
;
2167 struct anv_address num_workgroups
;
2170 /** State required while building cmd buffer */
2171 struct anv_cmd_state
{
2172 /* PIPELINE_SELECT.PipelineSelection */
2173 uint32_t current_pipeline
;
2174 const struct gen_l3_config
* current_l3_config
;
2176 struct anv_cmd_graphics_state gfx
;
2177 struct anv_cmd_compute_state compute
;
2179 enum anv_pipe_bits pending_pipe_bits
;
2180 VkShaderStageFlags descriptors_dirty
;
2181 VkShaderStageFlags push_constants_dirty
;
2183 struct anv_framebuffer
* framebuffer
;
2184 struct anv_render_pass
* pass
;
2185 struct anv_subpass
* subpass
;
2186 VkRect2D render_area
;
2187 uint32_t restart_index
;
2188 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2190 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2191 VkShaderStageFlags push_constant_stages
;
2192 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
2193 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2194 struct anv_state samplers
[MESA_SHADER_STAGES
];
2197 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2198 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2199 * and before invoking the secondary in ExecuteCommands.
2201 bool pma_fix_enabled
;
2204 * Whether or not we know for certain that HiZ is enabled for the current
2205 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2206 * enabled or not, this will be false.
2210 bool conditional_render_enabled
;
2213 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2214 * valid only when recording a render pass instance.
2216 struct anv_attachment_state
* attachments
;
2219 * Surface states for color render targets. These are stored in a single
2220 * flat array. For depth-stencil attachments, the surface state is simply
2223 struct anv_state render_pass_states
;
2226 * A null surface state of the right size to match the framebuffer. This
2227 * is one of the states in render_pass_states.
2229 struct anv_state null_surface_state
;
2232 struct anv_cmd_pool
{
2233 VkAllocationCallbacks alloc
;
2234 struct list_head cmd_buffers
;
2237 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2239 enum anv_cmd_buffer_exec_mode
{
2240 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2241 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2242 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2243 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2244 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2247 struct anv_cmd_buffer
{
2248 VK_LOADER_DATA _loader_data
;
2250 struct anv_device
* device
;
2252 struct anv_cmd_pool
* pool
;
2253 struct list_head pool_link
;
2255 struct anv_batch batch
;
2257 /* Fields required for the actual chain of anv_batch_bo's.
2259 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2261 struct list_head batch_bos
;
2262 enum anv_cmd_buffer_exec_mode exec_mode
;
2264 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2265 * referenced by this command buffer
2267 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2269 struct u_vector seen_bbos
;
2271 /* A vector of int32_t's for every block of binding tables.
2273 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2275 struct u_vector bt_block_states
;
2278 struct anv_reloc_list surface_relocs
;
2279 /** Last seen surface state block pool center bo offset */
2280 uint32_t last_ss_pool_center
;
2282 /* Serial for tracking buffer completion */
2285 /* Stream objects for storing temporary data */
2286 struct anv_state_stream surface_state_stream
;
2287 struct anv_state_stream dynamic_state_stream
;
2289 VkCommandBufferUsageFlags usage_flags
;
2290 VkCommandBufferLevel level
;
2292 struct anv_cmd_state state
;
2295 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2296 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2297 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2298 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2299 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2300 struct anv_cmd_buffer
*secondary
);
2301 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2302 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2303 struct anv_cmd_buffer
*cmd_buffer
,
2304 const VkSemaphore
*in_semaphores
,
2305 uint32_t num_in_semaphores
,
2306 const VkSemaphore
*out_semaphores
,
2307 uint32_t num_out_semaphores
,
2310 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2313 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2314 gl_shader_stage stage
, uint32_t size
);
2315 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2316 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2317 (offsetof(struct anv_push_constants, field) + \
2318 sizeof(cmd_buffer->state.push_constants[0]->field)))
2320 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2321 const void *data
, uint32_t size
, uint32_t alignment
);
2322 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2323 uint32_t *a
, uint32_t *b
,
2324 uint32_t dwords
, uint32_t alignment
);
2327 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2329 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2330 uint32_t entries
, uint32_t *state_offset
);
2332 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2334 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2335 uint32_t size
, uint32_t alignment
);
2338 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2340 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2341 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2342 bool depth_clamp_enable
);
2343 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2345 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2346 struct anv_render_pass
*pass
,
2347 struct anv_framebuffer
*framebuffer
,
2348 const VkClearValue
*clear_values
);
2350 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2353 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2354 gl_shader_stage stage
);
2356 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2358 const struct anv_image_view
*
2359 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2362 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2363 uint32_t num_entries
,
2364 uint32_t *state_offset
,
2365 struct anv_state
*bt_state
);
2367 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2369 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2371 enum anv_fence_type
{
2372 ANV_FENCE_TYPE_NONE
= 0,
2374 ANV_FENCE_TYPE_SYNCOBJ
,
2378 enum anv_bo_fence_state
{
2379 /** Indicates that this is a new (or newly reset fence) */
2380 ANV_BO_FENCE_STATE_RESET
,
2382 /** Indicates that this fence has been submitted to the GPU but is still
2383 * (as far as we know) in use by the GPU.
2385 ANV_BO_FENCE_STATE_SUBMITTED
,
2387 ANV_BO_FENCE_STATE_SIGNALED
,
2390 struct anv_fence_impl
{
2391 enum anv_fence_type type
;
2394 /** Fence implementation for BO fences
2396 * These fences use a BO and a set of CPU-tracked state flags. The BO
2397 * is added to the object list of the last execbuf call in a QueueSubmit
2398 * and is marked EXEC_WRITE. The state flags track when the BO has been
2399 * submitted to the kernel. We need to do this because Vulkan lets you
2400 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2401 * will say it's idle in this case.
2405 enum anv_bo_fence_state state
;
2408 /** DRM syncobj handle for syncobj-based fences */
2412 struct wsi_fence
*fence_wsi
;
2417 /* Permanent fence state. Every fence has some form of permanent state
2418 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2419 * cross-process fences) or it could just be a dummy for use internally.
2421 struct anv_fence_impl permanent
;
2423 /* Temporary fence state. A fence *may* have temporary state. That state
2424 * is added to the fence by an import operation and is reset back to
2425 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2426 * state cannot be signaled because the fence must already be signaled
2427 * before the temporary state can be exported from the fence in the other
2428 * process and imported here.
2430 struct anv_fence_impl temporary
;
2435 struct anv_state state
;
2438 enum anv_semaphore_type
{
2439 ANV_SEMAPHORE_TYPE_NONE
= 0,
2440 ANV_SEMAPHORE_TYPE_DUMMY
,
2441 ANV_SEMAPHORE_TYPE_BO
,
2442 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2443 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2446 struct anv_semaphore_impl
{
2447 enum anv_semaphore_type type
;
2450 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2451 * This BO will be added to the object list on any execbuf2 calls for
2452 * which this semaphore is used as a wait or signal fence. When used as
2453 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2457 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2458 * If the semaphore is in the unsignaled state due to either just being
2459 * created or because it has been used for a wait, fd will be -1.
2463 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2464 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2465 * import so we don't need to bother with a userspace cache.
2471 struct anv_semaphore
{
2472 /* Permanent semaphore state. Every semaphore has some form of permanent
2473 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2474 * (for cross-process semaphores0 or it could just be a dummy for use
2477 struct anv_semaphore_impl permanent
;
2479 /* Temporary semaphore state. A semaphore *may* have temporary state.
2480 * That state is added to the semaphore by an import operation and is reset
2481 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2482 * semaphore with temporary state cannot be signaled because the semaphore
2483 * must already be signaled before the temporary state can be exported from
2484 * the semaphore in the other process and imported here.
2486 struct anv_semaphore_impl temporary
;
2489 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2490 struct anv_semaphore
*semaphore
);
2492 struct anv_shader_module
{
2493 unsigned char sha1
[20];
2498 static inline gl_shader_stage
2499 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2501 assert(__builtin_popcount(vk_stage
) == 1);
2502 return ffs(vk_stage
) - 1;
2505 static inline VkShaderStageFlagBits
2506 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2508 return (1 << mesa_stage
);
2511 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2513 #define anv_foreach_stage(stage, stage_bits) \
2514 for (gl_shader_stage stage, \
2515 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2516 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2517 __tmp &= ~(1 << (stage)))
2519 struct anv_pipeline_bind_map
{
2520 uint32_t surface_count
;
2521 uint32_t sampler_count
;
2522 uint32_t image_count
;
2524 struct anv_pipeline_binding
* surface_to_descriptor
;
2525 struct anv_pipeline_binding
* sampler_to_descriptor
;
2528 struct anv_shader_bin_key
{
2533 struct anv_shader_bin
{
2536 const struct anv_shader_bin_key
*key
;
2538 struct anv_state kernel
;
2539 uint32_t kernel_size
;
2541 struct anv_state constant_data
;
2542 uint32_t constant_data_size
;
2544 const struct brw_stage_prog_data
*prog_data
;
2545 uint32_t prog_data_size
;
2547 struct nir_xfb_info
*xfb_info
;
2549 struct anv_pipeline_bind_map bind_map
;
2552 struct anv_shader_bin
*
2553 anv_shader_bin_create(struct anv_device
*device
,
2554 const void *key
, uint32_t key_size
,
2555 const void *kernel
, uint32_t kernel_size
,
2556 const void *constant_data
, uint32_t constant_data_size
,
2557 const struct brw_stage_prog_data
*prog_data
,
2558 uint32_t prog_data_size
, const void *prog_data_param
,
2559 const struct nir_xfb_info
*xfb_info
,
2560 const struct anv_pipeline_bind_map
*bind_map
);
2563 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2566 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2568 assert(shader
&& shader
->ref_cnt
>= 1);
2569 p_atomic_inc(&shader
->ref_cnt
);
2573 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2575 assert(shader
&& shader
->ref_cnt
>= 1);
2576 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2577 anv_shader_bin_destroy(device
, shader
);
2580 struct anv_pipeline
{
2581 struct anv_device
* device
;
2582 struct anv_batch batch
;
2583 uint32_t batch_data
[512];
2584 struct anv_reloc_list batch_relocs
;
2585 uint32_t dynamic_state_mask
;
2586 struct anv_dynamic_state dynamic_state
;
2588 struct anv_subpass
* subpass
;
2590 bool needs_data_cache
;
2592 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2595 const struct gen_l3_config
* l3_config
;
2596 uint32_t total_size
;
2599 VkShaderStageFlags active_stages
;
2600 struct anv_state blend_state
;
2603 struct anv_pipeline_vertex_binding
{
2606 uint32_t instance_divisor
;
2611 bool primitive_restart
;
2614 uint32_t cs_right_mask
;
2617 bool depth_test_enable
;
2618 bool writes_stencil
;
2619 bool stencil_test_enable
;
2620 bool depth_clamp_enable
;
2621 bool sample_shading_enable
;
2626 uint32_t depth_stencil_state
[3];
2632 uint32_t wm_depth_stencil
[3];
2636 uint32_t wm_depth_stencil
[4];
2639 uint32_t interface_descriptor_data
[8];
2643 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2644 gl_shader_stage stage
)
2646 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2649 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2650 static inline const struct brw_##prefix##_prog_data * \
2651 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2653 if (anv_pipeline_has_stage(pipeline, stage)) { \
2654 return (const struct brw_##prefix##_prog_data *) \
2655 pipeline->shaders[stage]->prog_data; \
2661 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2662 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2663 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2664 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2665 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2666 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2668 static inline const struct brw_vue_prog_data
*
2669 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2671 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2672 return &get_gs_prog_data(pipeline
)->base
;
2673 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2674 return &get_tes_prog_data(pipeline
)->base
;
2676 return &get_vs_prog_data(pipeline
)->base
;
2680 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2681 struct anv_pipeline_cache
*cache
,
2682 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2683 const VkAllocationCallbacks
*alloc
);
2686 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2687 struct anv_pipeline_cache
*cache
,
2688 const VkComputePipelineCreateInfo
*info
,
2689 const struct anv_shader_module
*module
,
2690 const char *entrypoint
,
2691 const VkSpecializationInfo
*spec_info
);
2693 struct anv_format_plane
{
2694 enum isl_format isl_format
:16;
2695 struct isl_swizzle swizzle
;
2697 /* Whether this plane contains chroma channels */
2700 /* For downscaling of YUV planes */
2701 uint8_t denominator_scales
[2];
2703 /* How to map sampled ycbcr planes to a single 4 component element. */
2704 struct isl_swizzle ycbcr_swizzle
;
2706 /* What aspect is associated to this plane */
2707 VkImageAspectFlags aspect
;
2712 struct anv_format_plane planes
[3];
2718 static inline uint32_t
2719 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2720 VkImageAspectFlags aspect_mask
)
2722 switch (aspect_mask
) {
2723 case VK_IMAGE_ASPECT_COLOR_BIT
:
2724 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2725 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2727 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2728 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2731 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2733 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2736 /* Purposefully assert with depth/stencil aspects. */
2737 unreachable("invalid image aspect");
2741 static inline VkImageAspectFlags
2742 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2745 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2746 if (util_bitcount(image_aspects
) > 1)
2747 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2748 return VK_IMAGE_ASPECT_COLOR_BIT
;
2750 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2751 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2752 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2753 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2756 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2757 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2759 const struct anv_format
*
2760 anv_get_format(VkFormat format
);
2762 static inline uint32_t
2763 anv_get_format_planes(VkFormat vk_format
)
2765 const struct anv_format
*format
= anv_get_format(vk_format
);
2767 return format
!= NULL
? format
->n_planes
: 0;
2770 struct anv_format_plane
2771 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2772 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2774 static inline enum isl_format
2775 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2776 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2778 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2781 static inline struct isl_swizzle
2782 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2784 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2785 * RGB as RGBA for texturing
2787 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2788 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2790 /* But it doesn't matter what we render to that channel */
2791 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2797 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2800 * Subsurface of an anv_image.
2802 struct anv_surface
{
2803 /** Valid only if isl_surf::size_B > 0. */
2804 struct isl_surf isl
;
2807 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2814 /* The original VkFormat provided by the client. This may not match any
2815 * of the actual surface formats.
2818 const struct anv_format
*format
;
2820 VkImageAspectFlags aspects
;
2823 uint32_t array_size
;
2824 uint32_t samples
; /**< VkImageCreateInfo::samples */
2826 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2827 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
2828 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2830 /** True if this is needs to be bound to an appropriately tiled BO.
2832 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2833 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2834 * we require a dedicated allocation so that we can know to allocate a
2837 bool needs_set_tiling
;
2840 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2841 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2843 uint64_t drm_format_mod
;
2848 /* Whether the image is made of several underlying buffer objects rather a
2849 * single one with different offsets.
2853 /* All the formats that can be used when creating views of this image
2854 * are CCS_E compatible.
2856 bool ccs_e_compatible
;
2858 /* Image was created with external format. */
2859 bool external_format
;
2864 * For each foo, anv_image::planes[x].surface is valid if and only if
2865 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2866 * to figure the number associated with a given aspect.
2868 * The hardware requires that the depth buffer and stencil buffer be
2869 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2870 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2871 * allocate the depth and stencil buffers as separate surfaces in the same
2876 * -----------------------
2878 * ----------------------- |
2879 * | shadow surface0 | |
2880 * ----------------------- | Plane 0
2881 * | aux surface0 | |
2882 * ----------------------- |
2883 * | fast clear colors0 | \|/
2884 * -----------------------
2886 * ----------------------- |
2887 * | shadow surface1 | |
2888 * ----------------------- | Plane 1
2889 * | aux surface1 | |
2890 * ----------------------- |
2891 * | fast clear colors1 | \|/
2892 * -----------------------
2895 * -----------------------
2899 * Offset of the entire plane (whenever the image is disjoint this is
2907 struct anv_surface surface
;
2910 * A surface which shadows the main surface and may have different
2911 * tiling. This is used for sampling using a tiling that isn't supported
2912 * for other operations.
2914 struct anv_surface shadow_surface
;
2917 * For color images, this is the aux usage for this image when not used
2918 * as a color attachment.
2920 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2921 * image has a HiZ buffer.
2923 enum isl_aux_usage aux_usage
;
2925 struct anv_surface aux_surface
;
2928 * Offset of the fast clear state (used to compute the
2929 * fast_clear_state_offset of the following planes).
2931 uint32_t fast_clear_state_offset
;
2934 * BO associated with this plane, set when bound.
2936 struct anv_address address
;
2939 * When destroying the image, also free the bo.
2945 /* The ordering of this enum is important */
2946 enum anv_fast_clear_type
{
2947 /** Image does not have/support any fast-clear blocks */
2948 ANV_FAST_CLEAR_NONE
= 0,
2949 /** Image has/supports fast-clear but only to the default value */
2950 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
2951 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2952 ANV_FAST_CLEAR_ANY
= 2,
2955 /* Returns the number of auxiliary buffer levels attached to an image. */
2956 static inline uint8_t
2957 anv_image_aux_levels(const struct anv_image
* const image
,
2958 VkImageAspectFlagBits aspect
)
2960 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2961 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
2962 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
2965 /* Returns the number of auxiliary buffer layers attached to an image. */
2966 static inline uint32_t
2967 anv_image_aux_layers(const struct anv_image
* const image
,
2968 VkImageAspectFlagBits aspect
,
2969 const uint8_t miplevel
)
2973 /* The miplevel must exist in the main buffer. */
2974 assert(miplevel
< image
->levels
);
2976 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
2977 /* There are no layers with auxiliary data because the miplevel has no
2982 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2983 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
2984 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2988 static inline struct anv_address
2989 anv_image_get_clear_color_addr(const struct anv_device
*device
,
2990 const struct anv_image
*image
,
2991 VkImageAspectFlagBits aspect
)
2993 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
2995 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2996 return anv_address_add(image
->planes
[plane
].address
,
2997 image
->planes
[plane
].fast_clear_state_offset
);
3000 static inline struct anv_address
3001 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3002 const struct anv_image
*image
,
3003 VkImageAspectFlagBits aspect
)
3005 struct anv_address addr
=
3006 anv_image_get_clear_color_addr(device
, image
, aspect
);
3008 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3009 device
->isl_dev
.ss
.clear_color_state_size
:
3010 device
->isl_dev
.ss
.clear_value_size
;
3011 return anv_address_add(addr
, clear_color_state_size
);
3014 static inline struct anv_address
3015 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3016 const struct anv_image
*image
,
3017 VkImageAspectFlagBits aspect
,
3018 uint32_t level
, uint32_t array_layer
)
3020 assert(level
< anv_image_aux_levels(image
, aspect
));
3021 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3022 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3023 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3025 struct anv_address addr
=
3026 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3027 addr
.offset
+= 4; /* Go past the fast clear type */
3029 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3030 for (uint32_t l
= 0; l
< level
; l
++)
3031 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3033 addr
.offset
+= level
* image
->array_size
* 4;
3035 addr
.offset
+= array_layer
* 4;
3040 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3042 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3043 const struct anv_image
*image
)
3045 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3048 if (devinfo
->gen
< 8)
3051 return image
->samples
== 1;
3055 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3056 const struct anv_image
*image
,
3057 VkImageAspectFlagBits aspect
,
3058 enum isl_aux_usage aux_usage
,
3060 uint32_t base_layer
,
3061 uint32_t layer_count
);
3064 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3065 const struct anv_image
*image
,
3066 VkImageAspectFlagBits aspect
,
3067 enum isl_aux_usage aux_usage
,
3068 enum isl_format format
, struct isl_swizzle swizzle
,
3069 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3070 VkRect2D area
, union isl_color_value clear_color
);
3072 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3073 const struct anv_image
*image
,
3074 VkImageAspectFlags aspects
,
3075 enum isl_aux_usage depth_aux_usage
,
3077 uint32_t base_layer
, uint32_t layer_count
,
3079 float depth_value
, uint8_t stencil_value
);
3081 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3082 const struct anv_image
*src_image
,
3083 enum isl_aux_usage src_aux_usage
,
3084 uint32_t src_level
, uint32_t src_base_layer
,
3085 const struct anv_image
*dst_image
,
3086 enum isl_aux_usage dst_aux_usage
,
3087 uint32_t dst_level
, uint32_t dst_base_layer
,
3088 VkImageAspectFlagBits aspect
,
3089 uint32_t src_x
, uint32_t src_y
,
3090 uint32_t dst_x
, uint32_t dst_y
,
3091 uint32_t width
, uint32_t height
,
3092 uint32_t layer_count
,
3093 enum blorp_filter filter
);
3095 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3096 const struct anv_image
*image
,
3097 VkImageAspectFlagBits aspect
, uint32_t level
,
3098 uint32_t base_layer
, uint32_t layer_count
,
3099 enum isl_aux_op hiz_op
);
3101 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3102 const struct anv_image
*image
,
3103 VkImageAspectFlags aspects
,
3105 uint32_t base_layer
, uint32_t layer_count
,
3106 VkRect2D area
, uint8_t stencil_value
);
3108 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3109 const struct anv_image
*image
,
3110 enum isl_format format
,
3111 VkImageAspectFlagBits aspect
,
3112 uint32_t base_layer
, uint32_t layer_count
,
3113 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3116 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3117 const struct anv_image
*image
,
3118 enum isl_format format
,
3119 VkImageAspectFlagBits aspect
, uint32_t level
,
3120 uint32_t base_layer
, uint32_t layer_count
,
3121 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3125 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3126 const struct anv_image
*image
,
3127 uint32_t base_level
, uint32_t level_count
,
3128 uint32_t base_layer
, uint32_t layer_count
);
3131 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3132 const struct anv_image
*image
,
3133 const VkImageAspectFlagBits aspect
,
3134 const VkImageLayout layout
);
3136 enum anv_fast_clear_type
3137 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3138 const struct anv_image
* const image
,
3139 const VkImageAspectFlagBits aspect
,
3140 const VkImageLayout layout
);
3142 /* This is defined as a macro so that it works for both
3143 * VkImageSubresourceRange and VkImageSubresourceLayers
3145 #define anv_get_layerCount(_image, _range) \
3146 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3147 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3149 static inline uint32_t
3150 anv_get_levelCount(const struct anv_image
*image
,
3151 const VkImageSubresourceRange
*range
)
3153 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3154 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3157 static inline VkImageAspectFlags
3158 anv_image_expand_aspects(const struct anv_image
*image
,
3159 VkImageAspectFlags aspects
)
3161 /* If the underlying image has color plane aspects and
3162 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3163 * the underlying image. */
3164 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3165 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3166 return image
->aspects
;
3172 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3173 VkImageAspectFlags aspects2
)
3175 if (aspects1
== aspects2
)
3178 /* Only 1 color aspects are compatibles. */
3179 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3180 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3181 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3187 struct anv_image_view
{
3188 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3190 VkImageAspectFlags aspect_mask
;
3192 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3196 uint32_t image_plane
;
3198 struct isl_view isl
;
3201 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3202 * image layout of SHADER_READ_ONLY_OPTIMAL or
3203 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3205 struct anv_surface_state optimal_sampler_surface_state
;
3208 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3209 * image layout of GENERAL.
3211 struct anv_surface_state general_sampler_surface_state
;
3214 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3215 * states for write-only and readable, using the real format for
3216 * write-only and the lowered format for readable.
3218 struct anv_surface_state storage_surface_state
;
3219 struct anv_surface_state writeonly_storage_surface_state
;
3221 struct brw_image_param storage_image_param
;
3225 enum anv_image_view_state_flags
{
3226 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3227 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3230 void anv_image_fill_surface_state(struct anv_device
*device
,
3231 const struct anv_image
*image
,
3232 VkImageAspectFlagBits aspect
,
3233 const struct isl_view
*view
,
3234 isl_surf_usage_flags_t view_usage
,
3235 enum isl_aux_usage aux_usage
,
3236 const union isl_color_value
*clear_color
,
3237 enum anv_image_view_state_flags flags
,
3238 struct anv_surface_state
*state_inout
,
3239 struct brw_image_param
*image_param_out
);
3241 struct anv_image_create_info
{
3242 const VkImageCreateInfo
*vk_info
;
3244 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3245 isl_tiling_flags_t isl_tiling_flags
;
3247 /** These flags will be added to any derived from VkImageCreateInfo. */
3248 isl_surf_usage_flags_t isl_extra_usage_flags
;
3251 bool external_format
;
3254 VkResult
anv_image_create(VkDevice _device
,
3255 const struct anv_image_create_info
*info
,
3256 const VkAllocationCallbacks
* alloc
,
3259 const struct anv_surface
*
3260 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3261 VkImageAspectFlags aspect_mask
);
3264 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3266 static inline struct VkExtent3D
3267 anv_sanitize_image_extent(const VkImageType imageType
,
3268 const struct VkExtent3D imageExtent
)
3270 switch (imageType
) {
3271 case VK_IMAGE_TYPE_1D
:
3272 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3273 case VK_IMAGE_TYPE_2D
:
3274 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3275 case VK_IMAGE_TYPE_3D
:
3278 unreachable("invalid image type");
3282 static inline struct VkOffset3D
3283 anv_sanitize_image_offset(const VkImageType imageType
,
3284 const struct VkOffset3D imageOffset
)
3286 switch (imageType
) {
3287 case VK_IMAGE_TYPE_1D
:
3288 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3289 case VK_IMAGE_TYPE_2D
:
3290 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3291 case VK_IMAGE_TYPE_3D
:
3294 unreachable("invalid image type");
3298 VkFormatFeatureFlags
3299 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3301 const struct anv_format
*anv_format
,
3302 VkImageTiling vk_tiling
);
3304 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3305 struct anv_state state
,
3306 enum isl_format format
,
3307 struct anv_address address
,
3308 uint32_t range
, uint32_t stride
);
3311 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3312 const struct anv_attachment_state
*att_state
,
3313 const struct anv_image_view
*iview
)
3315 const struct isl_format_layout
*view_fmtl
=
3316 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3318 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3319 if (view_fmtl->channels.c.bits) \
3320 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3322 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3323 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3324 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3325 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3327 #undef COPY_CLEAR_COLOR_CHANNEL
3331 struct anv_ycbcr_conversion
{
3332 const struct anv_format
* format
;
3333 VkSamplerYcbcrModelConversion ycbcr_model
;
3334 VkSamplerYcbcrRange ycbcr_range
;
3335 VkComponentSwizzle mapping
[4];
3336 VkChromaLocation chroma_offsets
[2];
3337 VkFilter chroma_filter
;
3338 bool chroma_reconstruction
;
3341 struct anv_sampler
{
3342 uint32_t state
[3][4];
3344 struct anv_ycbcr_conversion
*conversion
;
3347 struct anv_framebuffer
{
3352 uint32_t attachment_count
;
3353 struct anv_image_view
* attachments
[0];
3356 struct anv_subpass_attachment
{
3357 VkImageUsageFlagBits usage
;
3358 uint32_t attachment
;
3359 VkImageLayout layout
;
3362 struct anv_subpass
{
3363 uint32_t attachment_count
;
3366 * A pointer to all attachment references used in this subpass.
3367 * Only valid if ::attachment_count > 0.
3369 struct anv_subpass_attachment
* attachments
;
3370 uint32_t input_count
;
3371 struct anv_subpass_attachment
* input_attachments
;
3372 uint32_t color_count
;
3373 struct anv_subpass_attachment
* color_attachments
;
3374 struct anv_subpass_attachment
* resolve_attachments
;
3376 struct anv_subpass_attachment
* depth_stencil_attachment
;
3377 struct anv_subpass_attachment
* ds_resolve_attachment
;
3378 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3379 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3383 /** Subpass has a depth/stencil self-dependency */
3384 bool has_ds_self_dep
;
3386 /** Subpass has at least one color resolve attachment */
3387 bool has_color_resolve
;
3390 static inline unsigned
3391 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3393 return MAX2(1, util_bitcount(subpass
->view_mask
));
3396 struct anv_render_pass_attachment
{
3397 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3398 * its members individually.
3402 VkImageUsageFlags usage
;
3403 VkAttachmentLoadOp load_op
;
3404 VkAttachmentStoreOp store_op
;
3405 VkAttachmentLoadOp stencil_load_op
;
3406 VkImageLayout initial_layout
;
3407 VkImageLayout final_layout
;
3408 VkImageLayout first_subpass_layout
;
3410 /* The subpass id in which the attachment will be used last. */
3411 uint32_t last_subpass_idx
;
3414 struct anv_render_pass
{
3415 uint32_t attachment_count
;
3416 uint32_t subpass_count
;
3417 /* An array of subpass_count+1 flushes, one per subpass boundary */
3418 enum anv_pipe_bits
* subpass_flushes
;
3419 struct anv_render_pass_attachment
* attachments
;
3420 struct anv_subpass subpasses
[0];
3423 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3425 struct anv_query_pool
{
3427 VkQueryPipelineStatisticFlags pipeline_statistics
;
3428 /** Stride between slots, in bytes */
3430 /** Number of slots in this query pool */
3435 int anv_get_instance_entrypoint_index(const char *name
);
3436 int anv_get_device_entrypoint_index(const char *name
);
3439 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3440 const struct anv_instance_extension_table
*instance
);
3443 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3444 const struct anv_instance_extension_table
*instance
,
3445 const struct anv_device_extension_table
*device
);
3447 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3450 void anv_dump_image_to_ppm(struct anv_device
*device
,
3451 struct anv_image
*image
, unsigned miplevel
,
3452 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3453 const char *filename
);
3455 enum anv_dump_action
{
3456 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3459 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3460 void anv_dump_finish(void);
3462 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3463 struct anv_framebuffer
*fb
);
3465 static inline uint32_t
3466 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3468 /* This function must be called from within a subpass. */
3469 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3471 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3473 /* The id of this subpass shouldn't exceed the number of subpasses in this
3474 * render pass minus 1.
3476 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3480 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3482 static inline struct __anv_type * \
3483 __anv_type ## _from_handle(__VkType _handle) \
3485 return (struct __anv_type *) _handle; \
3488 static inline __VkType \
3489 __anv_type ## _to_handle(struct __anv_type *_obj) \
3491 return (__VkType) _obj; \
3494 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3496 static inline struct __anv_type * \
3497 __anv_type ## _from_handle(__VkType _handle) \
3499 return (struct __anv_type *)(uintptr_t) _handle; \
3502 static inline __VkType \
3503 __anv_type ## _to_handle(struct __anv_type *_obj) \
3505 return (__VkType)(uintptr_t) _obj; \
3508 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3509 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3511 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3512 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3513 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3514 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3515 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3517 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3518 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3519 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3520 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3521 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3522 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3523 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3524 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3525 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3526 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3527 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3528 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3529 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3530 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3531 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3532 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3533 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3534 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3535 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3536 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3537 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3538 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3539 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3541 /* Gen-specific function declarations */
3543 # include "anv_genX.h"
3545 # define genX(x) gen7_##x
3546 # include "anv_genX.h"
3548 # define genX(x) gen75_##x
3549 # include "anv_genX.h"
3551 # define genX(x) gen8_##x
3552 # include "anv_genX.h"
3554 # define genX(x) gen9_##x
3555 # include "anv_genX.h"
3557 # define genX(x) gen10_##x
3558 # include "anv_genX.h"
3560 # define genX(x) gen11_##x
3561 # include "anv_genX.h"
3565 #endif /* ANV_PRIVATE_H */