2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
61 #include "vk_debug_report.h"
63 /* Pre-declarations needed for WSI entrypoints */
66 typedef struct xcb_connection_t xcb_connection_t
;
67 typedef uint32_t xcb_visualid_t
;
68 typedef uint32_t xcb_window_t
;
71 struct anv_buffer_view
;
72 struct anv_image_view
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
81 #include "anv_android.h"
82 #include "anv_entrypoints.h"
83 #include "anv_extensions.h"
86 #include "dev/gen_debug.h"
87 #include "common/intel_log.h"
88 #include "wsi_common.h"
90 /* anv Virtual Memory Layout
91 * =========================
93 * When the anv driver is determining the virtual graphics addresses of memory
94 * objects itself using the softpin mechanism, the following memory ranges
97 * Three special considerations to notice:
99 * (1) the dynamic state pool is located within the same 4 GiB as the low
100 * heap. This is to work around a VF cache issue described in a comment in
101 * anv_physical_device_init_heaps.
103 * (2) the binding table pool is located at lower addresses than the surface
104 * state pool, within a 4 GiB range. This allows surface state base addresses
105 * to cover both binding tables (16 bit offsets) and surface states (32 bit
108 * (3) the last 4 GiB of the address space is withheld from the high
109 * heap. Various hardware units will read past the end of an object for
110 * various reasons. This healthy margin prevents reads from wrapping around
113 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
114 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
115 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
116 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
117 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
118 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
119 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
120 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
121 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
122 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
123 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
125 #define LOW_HEAP_SIZE \
126 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
127 #define DYNAMIC_STATE_POOL_SIZE \
128 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
129 #define BINDING_TABLE_POOL_SIZE \
130 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
131 #define SURFACE_STATE_POOL_SIZE \
132 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
133 #define INSTRUCTION_STATE_POOL_SIZE \
134 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
136 /* Allowing different clear colors requires us to perform a depth resolve at
137 * the end of certain render passes. This is because while slow clears store
138 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
139 * See the PRMs for examples describing when additional resolves would be
140 * necessary. To enable fast clears without requiring extra resolves, we set
141 * the clear value to a globally-defined one. We could allow different values
142 * if the user doesn't expect coherent data during or after a render passes
143 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
144 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
145 * 1.0f seems to be the only value used. The only application that doesn't set
146 * this value does so through the usage of an seemingly uninitialized clear
149 #define ANV_HZ_FC_VAL 1.0f
152 #define MAX_XFB_BUFFERS 4
153 #define MAX_XFB_STREAMS 4
156 #define MAX_VIEWPORTS 16
157 #define MAX_SCISSORS 16
158 #define MAX_PUSH_CONSTANTS_SIZE 128
159 #define MAX_DYNAMIC_BUFFERS 16
160 #define MAX_IMAGES 64
161 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
162 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
163 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
165 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
167 * "The surface state model is used when a Binding Table Index (specified
168 * in the message descriptor) of less than 240 is specified. In this model,
169 * the Binding Table Index is used to index into the binding table, and the
170 * binding table entry contains a pointer to the SURFACE_STATE."
172 * Binding table values above 240 are used for various things in the hardware
173 * such as stateless, stateless with incoherent cache, SLM, and bindless.
175 #define MAX_BINDING_TABLE_SIZE 240
177 /* The kernel relocation API has a limitation of a 32-bit delta value
178 * applied to the address before it is written which, in spite of it being
179 * unsigned, is treated as signed . Because of the way that this maps to
180 * the Vulkan API, we cannot handle an offset into a buffer that does not
181 * fit into a signed 32 bits. The only mechanism we have for dealing with
182 * this at the moment is to limit all VkDeviceMemory objects to a maximum
183 * of 2GB each. The Vulkan spec allows us to do this:
185 * "Some platforms may have a limit on the maximum size of a single
186 * allocation. For example, certain systems may fail to create
187 * allocations with a size greater than or equal to 4GB. Such a limit is
188 * implementation-dependent, and if such a failure occurs then the error
189 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
191 * We don't use vk_error here because it's not an error so much as an
192 * indication to the application that the allocation is too large.
194 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
196 #define ANV_SVGS_VB_INDEX MAX_VBS
197 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
199 /* We reserve this MI ALU register for the purpose of handling predication.
200 * Other code which uses the MI ALU should leave it alone.
202 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
204 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
206 static inline uint32_t
207 align_down_npot_u32(uint32_t v
, uint32_t a
)
212 static inline uint32_t
213 align_u32(uint32_t v
, uint32_t a
)
215 assert(a
!= 0 && a
== (a
& -a
));
216 return (v
+ a
- 1) & ~(a
- 1);
219 static inline uint64_t
220 align_u64(uint64_t v
, uint64_t a
)
222 assert(a
!= 0 && a
== (a
& -a
));
223 return (v
+ a
- 1) & ~(a
- 1);
226 static inline int32_t
227 align_i32(int32_t v
, int32_t a
)
229 assert(a
!= 0 && a
== (a
& -a
));
230 return (v
+ a
- 1) & ~(a
- 1);
233 /** Alignment must be a power of 2. */
235 anv_is_aligned(uintmax_t n
, uintmax_t a
)
237 assert(a
== (a
& -a
));
238 return (n
& (a
- 1)) == 0;
241 static inline uint32_t
242 anv_minify(uint32_t n
, uint32_t levels
)
244 if (unlikely(n
== 0))
247 return MAX2(n
>> levels
, 1);
251 anv_clamp_f(float f
, float min
, float max
)
264 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
266 if (*inout_mask
& clear_mask
) {
267 *inout_mask
&= ~clear_mask
;
274 static inline union isl_color_value
275 vk_to_isl_color(VkClearColorValue color
)
277 return (union isl_color_value
) {
287 #define for_each_bit(b, dword) \
288 for (uint32_t __dword = (dword); \
289 (b) = __builtin_ffs(__dword) - 1, __dword; \
290 __dword &= ~(1 << (b)))
292 #define typed_memcpy(dest, src, count) ({ \
293 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
294 memcpy((dest), (src), (count) * sizeof(*(src))); \
297 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
298 * to be added here in order to utilize mapping in debug/error/perf macros.
300 #define REPORT_OBJECT_TYPE(o) \
301 __builtin_choose_expr ( \
302 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
303 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
376 __builtin_choose_expr ( \
377 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
378 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
379 __builtin_choose_expr ( \
380 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
381 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
382 __builtin_choose_expr ( \
383 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
384 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
385 __builtin_choose_expr ( \
386 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
387 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
388 __builtin_choose_expr ( \
389 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
390 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
391 __builtin_choose_expr ( \
392 __builtin_types_compatible_p (__typeof (o), void*), \
393 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
394 /* The void expression results in a compile-time error \
395 when assigning the result to something. */ \
396 (void)0)))))))))))))))))))))))))))))))
398 /* Whenever we generate an error, pass it through this function. Useful for
399 * debugging, where we can break on it. Only call at error site, not when
400 * propagating errors. Might be useful to plug in a stack trace here.
403 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
404 VkDebugReportObjectTypeEXT type
, VkResult error
,
405 const char *file
, int line
, const char *format
,
408 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
409 VkDebugReportObjectTypeEXT type
, VkResult error
,
410 const char *file
, int line
, const char *format
, ...);
413 #define vk_error(error) __vk_errorf(NULL, NULL,\
414 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
415 error, __FILE__, __LINE__, NULL)
416 #define vk_errorv(instance, obj, error, format, args)\
417 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
418 __FILE__, __LINE__, format, args)
419 #define vk_errorf(instance, obj, error, format, ...)\
420 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
421 __FILE__, __LINE__, format, ## __VA_ARGS__)
423 #define vk_error(error) error
424 #define vk_errorf(instance, obj, error, format, ...) error
428 * Warn on ignored extension structs.
430 * The Vulkan spec requires us to ignore unsupported or unknown structs in
431 * a pNext chain. In debug mode, emitting warnings for ignored structs may
432 * help us discover structs that we should not have ignored.
435 * From the Vulkan 1.0.38 spec:
437 * Any component of the implementation (the loader, any enabled layers,
438 * and drivers) must skip over, without processing (other than reading the
439 * sType and pNext members) any chained structures with sType values not
440 * defined by extensions supported by that component.
442 #define anv_debug_ignored_stype(sType) \
443 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
445 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
446 VkDebugReportObjectTypeEXT type
, const char *file
,
447 int line
, const char *format
, ...)
448 anv_printflike(6, 7);
449 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
450 void anv_loge_v(const char *format
, va_list va
);
453 * Print a FINISHME message, including its source location.
455 #define anv_finishme(format, ...) \
457 static bool reported = false; \
459 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
466 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
468 #define anv_perf_warn(instance, obj, format, ...) \
470 static bool reported = false; \
471 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
472 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
473 format, ##__VA_ARGS__); \
478 /* A non-fatal assert. Useful for debugging. */
480 #define anv_assert(x) ({ \
481 if (unlikely(!(x))) \
482 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
485 #define anv_assert(x)
488 /* A multi-pointer allocator
490 * When copying data structures from the user (such as a render pass), it's
491 * common to need to allocate data for a bunch of different things. Instead
492 * of doing several allocations and having to handle all of the error checking
493 * that entails, it can be easier to do a single allocation. This struct
494 * helps facilitate that. The intended usage looks like this:
497 * anv_multialloc_add(&ma, &main_ptr, 1);
498 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
499 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
501 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
502 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
504 struct anv_multialloc
{
512 #define ANV_MULTIALLOC_INIT \
513 ((struct anv_multialloc) { 0, })
515 #define ANV_MULTIALLOC(_name) \
516 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
518 __attribute__((always_inline
))
520 _anv_multialloc_add(struct anv_multialloc
*ma
,
521 void **ptr
, size_t size
, size_t align
)
523 size_t offset
= align_u64(ma
->size
, align
);
524 ma
->size
= offset
+ size
;
525 ma
->align
= MAX2(ma
->align
, align
);
527 /* Store the offset in the pointer. */
528 *ptr
= (void *)(uintptr_t)offset
;
530 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
531 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
534 #define anv_multialloc_add_size(_ma, _ptr, _size) \
535 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
537 #define anv_multialloc_add(_ma, _ptr, _count) \
538 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
540 __attribute__((always_inline
))
542 anv_multialloc_alloc(struct anv_multialloc
*ma
,
543 const VkAllocationCallbacks
*alloc
,
544 VkSystemAllocationScope scope
)
546 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
550 /* Fill out each of the pointers with their final value.
552 * for (uint32_t i = 0; i < ma->ptr_count; i++)
553 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
555 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
556 * constant, GCC is incapable of figuring this out and unrolling the loop
557 * so we have to give it a little help.
559 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
560 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
561 if ((_i) < ma->ptr_count) \
562 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
563 _ANV_MULTIALLOC_UPDATE_POINTER(0);
564 _ANV_MULTIALLOC_UPDATE_POINTER(1);
565 _ANV_MULTIALLOC_UPDATE_POINTER(2);
566 _ANV_MULTIALLOC_UPDATE_POINTER(3);
567 _ANV_MULTIALLOC_UPDATE_POINTER(4);
568 _ANV_MULTIALLOC_UPDATE_POINTER(5);
569 _ANV_MULTIALLOC_UPDATE_POINTER(6);
570 _ANV_MULTIALLOC_UPDATE_POINTER(7);
571 #undef _ANV_MULTIALLOC_UPDATE_POINTER
576 __attribute__((always_inline
))
578 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
579 const VkAllocationCallbacks
*parent_alloc
,
580 const VkAllocationCallbacks
*alloc
,
581 VkSystemAllocationScope scope
)
583 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
586 /* Extra ANV-defined BO flags which won't be passed to the kernel */
587 #define ANV_BO_EXTERNAL (1ull << 31)
588 #define ANV_BO_FLAG_MASK (1ull << 31)
593 /* Index into the current validation list. This is used by the
594 * validation list building alrogithm to track which buffers are already
595 * in the validation list so that we can ensure uniqueness.
599 /* Last known offset. This value is provided by the kernel when we
600 * execbuf and is used as the presumed offset for the next bunch of
608 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
613 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
615 bo
->gem_handle
= gem_handle
;
623 /* Represents a lock-free linked list of "free" things. This is used by
624 * both the block pool and the state pools. Unfortunately, in order to
625 * solve the ABA problem, we can't use a single uint32_t head.
627 union anv_free_list
{
631 /* A simple count that is incremented every time the head changes. */
637 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
639 struct anv_block_state
{
649 #define anv_block_pool_foreach_bo(bo, pool) \
650 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
652 #define ANV_MAX_BLOCK_POOL_BOS 20
654 struct anv_block_pool
{
655 struct anv_device
*device
;
659 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
665 /* The address where the start of the pool is pinned. The various bos that
666 * are created as the pool grows will have addresses in the range
667 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
669 uint64_t start_address
;
671 /* The offset from the start of the bo to the "center" of the block
672 * pool. Pointers to allocated blocks are given by
673 * bo.map + center_bo_offset + offsets.
675 uint32_t center_bo_offset
;
677 /* Current memory map of the block pool. This pointer may or may not
678 * point to the actual beginning of the block pool memory. If
679 * anv_block_pool_alloc_back has ever been called, then this pointer
680 * will point to the "center" position of the buffer and all offsets
681 * (negative or positive) given out by the block pool alloc functions
682 * will be valid relative to this pointer.
684 * In particular, map == bo.map + center_offset
686 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
687 * since it will handle the softpin case as well, where this points to NULL.
693 * Array of mmaps and gem handles owned by the block pool, reclaimed when
694 * the block pool is destroyed.
696 struct u_vector mmap_cleanups
;
698 struct anv_block_state state
;
700 struct anv_block_state back_state
;
703 /* Block pools are backed by a fixed-size 1GB memfd */
704 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
706 /* The center of the block pool is also the middle of the memfd. This may
707 * change in the future if we decide differently for some reason.
709 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
711 static inline uint32_t
712 anv_block_pool_size(struct anv_block_pool
*pool
)
714 return pool
->state
.end
+ pool
->back_state
.end
;
724 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
726 struct anv_fixed_size_state_pool
{
727 union anv_free_list free_list
;
728 struct anv_block_state block
;
731 #define ANV_MIN_STATE_SIZE_LOG2 6
732 #define ANV_MAX_STATE_SIZE_LOG2 20
734 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
736 struct anv_free_entry
{
738 struct anv_state state
;
741 struct anv_state_table
{
742 struct anv_device
*device
;
744 struct anv_free_entry
*map
;
746 struct anv_block_state state
;
747 struct u_vector cleanups
;
750 struct anv_state_pool
{
751 struct anv_block_pool block_pool
;
753 struct anv_state_table table
;
755 /* The size of blocks which will be allocated from the block pool */
758 /** Free list for "back" allocations */
759 union anv_free_list back_alloc_free_list
;
761 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
764 struct anv_state_stream_block
;
766 struct anv_state_stream
{
767 struct anv_state_pool
*state_pool
;
769 /* The size of blocks to allocate from the state pool */
772 /* Current block we're allocating from */
773 struct anv_state block
;
775 /* Offset into the current block at which to allocate the next state */
778 /* List of all blocks allocated from this pool */
779 struct anv_state_stream_block
*block_list
;
782 /* The block_pool functions exported for testing only. The block pool should
783 * only be used via a state pool (see below).
785 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
786 struct anv_device
*device
,
787 uint64_t start_address
,
788 uint32_t initial_size
,
790 void anv_block_pool_finish(struct anv_block_pool
*pool
);
791 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
792 uint32_t block_size
, uint32_t *padding
);
793 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
794 uint32_t block_size
);
795 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
797 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
798 struct anv_device
*device
,
799 uint64_t start_address
,
802 void anv_state_pool_finish(struct anv_state_pool
*pool
);
803 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
804 uint32_t state_size
, uint32_t alignment
);
805 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
806 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
807 void anv_state_stream_init(struct anv_state_stream
*stream
,
808 struct anv_state_pool
*state_pool
,
809 uint32_t block_size
);
810 void anv_state_stream_finish(struct anv_state_stream
*stream
);
811 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
812 uint32_t size
, uint32_t alignment
);
814 VkResult
anv_state_table_init(struct anv_state_table
*table
,
815 struct anv_device
*device
,
816 uint32_t initial_entries
);
817 void anv_state_table_finish(struct anv_state_table
*table
);
818 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
820 void anv_free_list_push(union anv_free_list
*list
,
821 struct anv_state_table
*table
,
822 uint32_t idx
, uint32_t count
);
823 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
824 struct anv_state_table
*table
);
827 static inline struct anv_state
*
828 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
830 return &table
->map
[idx
].state
;
833 * Implements a pool of re-usable BOs. The interface is identical to that
834 * of block_pool except that each block is its own BO.
837 struct anv_device
*device
;
844 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
846 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
847 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
849 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
851 struct anv_scratch_bo
{
856 struct anv_scratch_pool
{
857 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
858 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
861 void anv_scratch_pool_init(struct anv_device
*device
,
862 struct anv_scratch_pool
*pool
);
863 void anv_scratch_pool_finish(struct anv_device
*device
,
864 struct anv_scratch_pool
*pool
);
865 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
866 struct anv_scratch_pool
*pool
,
867 gl_shader_stage stage
,
868 unsigned per_thread_scratch
);
870 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
871 struct anv_bo_cache
{
872 struct hash_table
*bo_map
;
873 pthread_mutex_t mutex
;
876 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
877 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
878 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
879 struct anv_bo_cache
*cache
,
880 uint64_t size
, uint64_t bo_flags
,
882 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
883 struct anv_bo_cache
*cache
,
884 void *host_ptr
, uint32_t size
,
885 uint64_t bo_flags
, struct anv_bo
**bo_out
);
886 VkResult
anv_bo_cache_import(struct anv_device
*device
,
887 struct anv_bo_cache
*cache
,
888 int fd
, uint64_t bo_flags
,
890 VkResult
anv_bo_cache_export(struct anv_device
*device
,
891 struct anv_bo_cache
*cache
,
892 struct anv_bo
*bo_in
, int *fd_out
);
893 void anv_bo_cache_release(struct anv_device
*device
,
894 struct anv_bo_cache
*cache
,
897 struct anv_memory_type
{
898 /* Standard bits passed on to the client */
899 VkMemoryPropertyFlags propertyFlags
;
902 /* Driver-internal book-keeping */
903 VkBufferUsageFlags valid_buffer_usage
;
906 struct anv_memory_heap
{
907 /* Standard bits passed on to the client */
909 VkMemoryHeapFlags flags
;
911 /* Driver-internal book-keeping */
914 bool supports_48bit_addresses
;
918 struct anv_physical_device
{
919 VK_LOADER_DATA _loader_data
;
921 struct anv_instance
* instance
;
932 struct gen_device_info info
;
933 /** Amount of "GPU memory" we want to advertise
935 * Clearly, this value is bogus since Intel is a UMA architecture. On
936 * gen7 platforms, we are limited by GTT size unless we want to implement
937 * fine-grained tracking and GTT splitting. On Broadwell and above we are
938 * practically unlimited. However, we will never report more than 3/4 of
939 * the total system ram to try and avoid running out of RAM.
941 bool supports_48bit_addresses
;
942 struct brw_compiler
* compiler
;
943 struct isl_device isl_dev
;
944 int cmd_parser_version
;
946 bool has_exec_capture
;
949 bool has_syncobj_wait
;
950 bool has_context_priority
;
952 bool has_context_isolation
;
953 bool has_mem_available
;
954 bool always_use_bindless
;
956 /** True if we can access buffers using A64 messages */
957 bool has_a64_buffer_access
;
958 /** True if we can use bindless access for images */
959 bool has_bindless_images
;
960 /** True if we can use bindless access for samplers */
961 bool has_bindless_samplers
;
963 struct anv_device_extension_table supported_extensions
;
966 uint32_t subslice_total
;
970 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
972 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
975 uint8_t driver_build_sha1
[20];
976 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
977 uint8_t driver_uuid
[VK_UUID_SIZE
];
978 uint8_t device_uuid
[VK_UUID_SIZE
];
980 struct disk_cache
* disk_cache
;
982 struct wsi_device wsi_device
;
987 struct anv_app_info
{
988 const char* app_name
;
989 uint32_t app_version
;
990 const char* engine_name
;
991 uint32_t engine_version
;
992 uint32_t api_version
;
995 struct anv_instance
{
996 VK_LOADER_DATA _loader_data
;
998 VkAllocationCallbacks alloc
;
1000 struct anv_app_info app_info
;
1002 struct anv_instance_extension_table enabled_extensions
;
1003 struct anv_instance_dispatch_table dispatch
;
1004 struct anv_device_dispatch_table device_dispatch
;
1006 int physicalDeviceCount
;
1007 struct anv_physical_device physicalDevice
;
1009 bool pipeline_cache_enabled
;
1011 struct vk_debug_report_instance debug_report_callbacks
;
1014 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1015 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1017 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1018 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1022 VK_LOADER_DATA _loader_data
;
1024 struct anv_device
* device
;
1026 VkDeviceQueueCreateFlags flags
;
1029 struct anv_pipeline_cache
{
1030 struct anv_device
* device
;
1031 pthread_mutex_t mutex
;
1033 struct hash_table
* nir_cache
;
1035 struct hash_table
* cache
;
1038 struct nir_xfb_info
;
1039 struct anv_pipeline_bind_map
;
1041 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1042 struct anv_device
*device
,
1043 bool cache_enabled
);
1044 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1046 struct anv_shader_bin
*
1047 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1048 const void *key
, uint32_t key_size
);
1049 struct anv_shader_bin
*
1050 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1051 const void *key_data
, uint32_t key_size
,
1052 const void *kernel_data
, uint32_t kernel_size
,
1053 const void *constant_data
,
1054 uint32_t constant_data_size
,
1055 const struct brw_stage_prog_data
*prog_data
,
1056 uint32_t prog_data_size
,
1057 const struct nir_xfb_info
*xfb_info
,
1058 const struct anv_pipeline_bind_map
*bind_map
);
1060 struct anv_shader_bin
*
1061 anv_device_search_for_kernel(struct anv_device
*device
,
1062 struct anv_pipeline_cache
*cache
,
1063 const void *key_data
, uint32_t key_size
,
1064 bool *user_cache_bit
);
1066 struct anv_shader_bin
*
1067 anv_device_upload_kernel(struct anv_device
*device
,
1068 struct anv_pipeline_cache
*cache
,
1069 const void *key_data
, uint32_t key_size
,
1070 const void *kernel_data
, uint32_t kernel_size
,
1071 const void *constant_data
,
1072 uint32_t constant_data_size
,
1073 const struct brw_stage_prog_data
*prog_data
,
1074 uint32_t prog_data_size
,
1075 const struct nir_xfb_info
*xfb_info
,
1076 const struct anv_pipeline_bind_map
*bind_map
);
1079 struct nir_shader_compiler_options
;
1082 anv_device_search_for_nir(struct anv_device
*device
,
1083 struct anv_pipeline_cache
*cache
,
1084 const struct nir_shader_compiler_options
*nir_options
,
1085 unsigned char sha1_key
[20],
1089 anv_device_upload_nir(struct anv_device
*device
,
1090 struct anv_pipeline_cache
*cache
,
1091 const struct nir_shader
*nir
,
1092 unsigned char sha1_key
[20]);
1095 VK_LOADER_DATA _loader_data
;
1097 VkAllocationCallbacks alloc
;
1099 struct anv_instance
* instance
;
1100 uint32_t chipset_id
;
1102 struct gen_device_info info
;
1103 struct isl_device isl_dev
;
1106 bool can_chain_batches
;
1107 bool robust_buffer_access
;
1108 struct anv_device_extension_table enabled_extensions
;
1109 struct anv_device_dispatch_table dispatch
;
1111 pthread_mutex_t vma_mutex
;
1112 struct util_vma_heap vma_lo
;
1113 struct util_vma_heap vma_hi
;
1114 uint64_t vma_lo_available
;
1115 uint64_t vma_hi_available
;
1117 /** List of all anv_device_memory objects */
1118 struct list_head memory_objects
;
1120 struct anv_bo_pool batch_bo_pool
;
1122 struct anv_bo_cache bo_cache
;
1124 struct anv_state_pool dynamic_state_pool
;
1125 struct anv_state_pool instruction_state_pool
;
1126 struct anv_state_pool binding_table_pool
;
1127 struct anv_state_pool surface_state_pool
;
1129 struct anv_bo workaround_bo
;
1130 struct anv_bo trivial_batch_bo
;
1131 struct anv_bo hiz_clear_bo
;
1133 struct anv_pipeline_cache default_pipeline_cache
;
1134 struct blorp_context blorp
;
1136 struct anv_state border_colors
;
1138 struct anv_queue queue
;
1140 struct anv_scratch_pool scratch_pool
;
1142 uint32_t default_mocs
;
1143 uint32_t external_mocs
;
1145 pthread_mutex_t mutex
;
1146 pthread_cond_t queue_submit
;
1149 struct gen_batch_decode_ctx decoder_ctx
;
1151 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1152 * the cmd_buffer's list.
1154 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1157 static inline struct anv_state_pool
*
1158 anv_binding_table_pool(struct anv_device
*device
)
1160 if (device
->instance
->physicalDevice
.use_softpin
)
1161 return &device
->binding_table_pool
;
1163 return &device
->surface_state_pool
;
1166 static inline struct anv_state
1167 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1168 if (device
->instance
->physicalDevice
.use_softpin
)
1169 return anv_state_pool_alloc(&device
->binding_table_pool
,
1170 device
->binding_table_pool
.block_size
, 0);
1172 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1176 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1177 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1180 static inline uint32_t
1181 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1183 if (bo
->flags
& ANV_BO_EXTERNAL
)
1184 return device
->external_mocs
;
1186 return device
->default_mocs
;
1189 void anv_device_init_blorp(struct anv_device
*device
);
1190 void anv_device_finish_blorp(struct anv_device
*device
);
1192 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1193 const char *file
, int line
,
1194 const char *msg
, ...);
1195 #define anv_device_set_lost(dev, ...) \
1196 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1199 anv_device_is_lost(struct anv_device
*device
)
1201 return unlikely(device
->_lost
);
1204 VkResult
anv_device_execbuf(struct anv_device
*device
,
1205 struct drm_i915_gem_execbuffer2
*execbuf
,
1206 struct anv_bo
**execbuf_bos
);
1207 VkResult
anv_device_query_status(struct anv_device
*device
);
1208 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1209 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1212 void* anv_gem_mmap(struct anv_device
*device
,
1213 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1214 void anv_gem_munmap(void *p
, uint64_t size
);
1215 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1216 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1217 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1218 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1219 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1220 int anv_gem_execbuffer(struct anv_device
*device
,
1221 struct drm_i915_gem_execbuffer2
*execbuf
);
1222 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1223 uint32_t stride
, uint32_t tiling
);
1224 int anv_gem_create_context(struct anv_device
*device
);
1225 bool anv_gem_has_context_priority(int fd
);
1226 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1227 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1229 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1231 int anv_gem_get_param(int fd
, uint32_t param
);
1232 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1233 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1234 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1235 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1236 uint32_t *active
, uint32_t *pending
);
1237 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1238 int anv_gem_reg_read(struct anv_device
*device
,
1239 uint32_t offset
, uint64_t *result
);
1240 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1241 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1242 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1243 uint32_t read_domains
, uint32_t write_domain
);
1244 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1245 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1246 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1247 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1248 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1249 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1251 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1252 uint32_t handle
, int fd
);
1253 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1254 bool anv_gem_supports_syncobj_wait(int fd
);
1255 int anv_gem_syncobj_wait(struct anv_device
*device
,
1256 uint32_t *handles
, uint32_t num_handles
,
1257 int64_t abs_timeout_ns
, bool wait_all
);
1259 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1260 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1262 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1264 struct anv_reloc_list
{
1265 uint32_t num_relocs
;
1266 uint32_t array_length
;
1267 struct drm_i915_gem_relocation_entry
* relocs
;
1268 struct anv_bo
** reloc_bos
;
1272 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1273 const VkAllocationCallbacks
*alloc
);
1274 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1275 const VkAllocationCallbacks
*alloc
);
1277 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1278 const VkAllocationCallbacks
*alloc
,
1279 uint32_t offset
, struct anv_bo
*target_bo
,
1282 struct anv_batch_bo
{
1283 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1284 struct list_head link
;
1288 /* Bytes actually consumed in this batch BO */
1291 struct anv_reloc_list relocs
;
1295 const VkAllocationCallbacks
* alloc
;
1301 struct anv_reloc_list
* relocs
;
1303 /* This callback is called (with the associated user data) in the event
1304 * that the batch runs out of space.
1306 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1310 * Current error status of the command buffer. Used to track inconsistent
1311 * or incomplete command buffer states that are the consequence of run-time
1312 * errors such as out of memory scenarios. We want to track this in the
1313 * batch because the command buffer object is not visible to some parts
1319 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1320 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1321 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1322 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1323 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1324 struct anv_batch
*batch
);
1326 static inline VkResult
1327 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1329 assert(error
!= VK_SUCCESS
);
1330 if (batch
->status
== VK_SUCCESS
)
1331 batch
->status
= error
;
1332 return batch
->status
;
1336 anv_batch_has_error(struct anv_batch
*batch
)
1338 return batch
->status
!= VK_SUCCESS
;
1341 struct anv_address
{
1346 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1349 anv_address_is_null(struct anv_address addr
)
1351 return addr
.bo
== NULL
&& addr
.offset
== 0;
1354 static inline uint64_t
1355 anv_address_physical(struct anv_address addr
)
1357 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1358 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1360 return gen_canonical_address(addr
.offset
);
1363 static inline struct anv_address
1364 anv_address_add(struct anv_address addr
, uint64_t offset
)
1366 addr
.offset
+= offset
;
1371 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1373 unsigned reloc_size
= 0;
1374 if (device
->info
.gen
>= 8) {
1375 reloc_size
= sizeof(uint64_t);
1376 *(uint64_t *)p
= gen_canonical_address(v
);
1378 reloc_size
= sizeof(uint32_t);
1382 if (flush
&& !device
->info
.has_llc
)
1383 gen_flush_range(p
, reloc_size
);
1386 static inline uint64_t
1387 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1388 const struct anv_address address
, uint32_t delta
)
1390 if (address
.bo
== NULL
) {
1391 return address
.offset
+ delta
;
1393 assert(batch
->start
<= location
&& location
< batch
->end
);
1395 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1399 #define __gen_address_type struct anv_address
1400 #define __gen_user_data struct anv_batch
1401 #define __gen_combine_address _anv_combine_address
1403 /* Wrapper macros needed to work around preprocessor argument issues. In
1404 * particular, arguments don't get pre-evaluated if they are concatenated.
1405 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1406 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1407 * We can work around this easily enough with these helpers.
1409 #define __anv_cmd_length(cmd) cmd ## _length
1410 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1411 #define __anv_cmd_header(cmd) cmd ## _header
1412 #define __anv_cmd_pack(cmd) cmd ## _pack
1413 #define __anv_reg_num(reg) reg ## _num
1415 #define anv_pack_struct(dst, struc, ...) do { \
1416 struct struc __template = { \
1419 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1420 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1423 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1424 void *__dst = anv_batch_emit_dwords(batch, n); \
1426 struct cmd __template = { \
1427 __anv_cmd_header(cmd), \
1428 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1431 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1436 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1440 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1441 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1444 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1445 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1446 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1449 #define anv_batch_emit(batch, cmd, name) \
1450 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1451 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1452 __builtin_expect(_dst != NULL, 1); \
1453 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1454 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1458 /* MEMORY_OBJECT_CONTROL_STATE:
1459 * .GraphicsDataTypeGFDT = 0,
1460 * .LLCCacheabilityControlLLCCC = 0,
1461 * .L3CacheabilityControlL3CC = 1,
1465 /* MEMORY_OBJECT_CONTROL_STATE:
1466 * .LLCeLLCCacheabilityControlLLCCC = 0,
1467 * .L3CacheabilityControlL3CC = 1,
1469 #define GEN75_MOCS 1
1471 /* MEMORY_OBJECT_CONTROL_STATE:
1472 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1473 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1474 * .AgeforQUADLRU = 0
1476 #define GEN8_MOCS 0x78
1478 /* MEMORY_OBJECT_CONTROL_STATE:
1479 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1480 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1481 * .AgeforQUADLRU = 0
1483 #define GEN8_EXTERNAL_MOCS 0x18
1485 /* Skylake: MOCS is now an index into an array of 62 different caching
1486 * configurations programmed by the kernel.
1489 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1490 #define GEN9_MOCS (2 << 1)
1492 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1493 #define GEN9_EXTERNAL_MOCS (1 << 1)
1495 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1496 #define GEN10_MOCS GEN9_MOCS
1497 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1499 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1500 #define GEN11_MOCS GEN9_MOCS
1501 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1503 struct anv_device_memory
{
1504 struct list_head link
;
1507 struct anv_memory_type
* type
;
1508 VkDeviceSize map_size
;
1511 /* If set, we are holding reference to AHardwareBuffer
1512 * which we must release when memory is freed.
1514 struct AHardwareBuffer
* ahw
;
1516 /* If set, this memory comes from a host pointer. */
1521 * Header for Vertex URB Entry (VUE)
1523 struct anv_vue_header
{
1525 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1526 uint32_t ViewportIndex
;
1530 /** Struct representing a sampled image descriptor
1532 * This descriptor layout is used for sampled images, bare sampler, and
1533 * combined image/sampler descriptors.
1535 struct anv_sampled_image_descriptor
{
1536 /** Bindless image handle
1538 * This is expected to already be shifted such that the 20-bit
1539 * SURFACE_STATE table index is in the top 20 bits.
1543 /** Bindless sampler handle
1545 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1546 * to the dynamic state base address.
1551 /** Struct representing a storage image descriptor */
1552 struct anv_storage_image_descriptor
{
1553 /** Bindless image handles
1555 * These are expected to already be shifted such that the 20-bit
1556 * SURFACE_STATE table index is in the top 20 bits.
1558 uint32_t read_write
;
1559 uint32_t write_only
;
1562 /** Struct representing a address/range descriptor
1564 * The fields of this struct correspond directly to the data layout of
1565 * nir_address_format_64bit_bounded_global addresses. The last field is the
1566 * offset in the NIR address so it must be zero so that when you load the
1567 * descriptor you get a pointer to the start of the range.
1569 struct anv_address_range_descriptor
{
1575 enum anv_descriptor_data
{
1576 /** The descriptor contains a BTI reference to a surface state */
1577 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1578 /** The descriptor contains a BTI reference to a sampler state */
1579 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1580 /** The descriptor contains an actual buffer view */
1581 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1582 /** The descriptor contains auxiliary image layout data */
1583 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1584 /** The descriptor contains auxiliary image layout data */
1585 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1586 /** anv_address_range_descriptor with a buffer address and range */
1587 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1588 /** Bindless surface handle */
1589 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1590 /** Storage image handles */
1591 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1594 struct anv_descriptor_set_binding_layout
{
1596 /* The type of the descriptors in this binding */
1597 VkDescriptorType type
;
1600 /* Flags provided when this binding was created */
1601 VkDescriptorBindingFlagsEXT flags
;
1603 /* Bitfield representing the type of data this descriptor contains */
1604 enum anv_descriptor_data data
;
1606 /* Maximum number of YCbCr texture/sampler planes */
1607 uint8_t max_plane_count
;
1609 /* Number of array elements in this binding (or size in bytes for inline
1612 uint16_t array_size
;
1614 /* Index into the flattend descriptor set */
1615 uint16_t descriptor_index
;
1617 /* Index into the dynamic state array for a dynamic buffer */
1618 int16_t dynamic_offset_index
;
1620 /* Index into the descriptor set buffer views */
1621 int16_t buffer_view_index
;
1623 /* Offset into the descriptor buffer where this descriptor lives */
1624 uint32_t descriptor_offset
;
1626 /* Immutable samplers (or NULL if no immutable samplers) */
1627 struct anv_sampler
**immutable_samplers
;
1630 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1632 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1633 VkDescriptorType type
);
1635 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1636 const struct anv_descriptor_set_binding_layout
*binding
,
1639 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1640 const struct anv_descriptor_set_binding_layout
*binding
,
1643 struct anv_descriptor_set_layout
{
1644 /* Descriptor set layouts can be destroyed at almost any time */
1647 /* Number of bindings in this descriptor set */
1648 uint16_t binding_count
;
1650 /* Total size of the descriptor set with room for all array entries */
1653 /* Shader stages affected by this descriptor set */
1654 uint16_t shader_stages
;
1656 /* Number of buffer views in this descriptor set */
1657 uint16_t buffer_view_count
;
1659 /* Number of dynamic offsets used by this descriptor set */
1660 uint16_t dynamic_offset_count
;
1662 /* Size of the descriptor buffer for this descriptor set */
1663 uint32_t descriptor_buffer_size
;
1665 /* Bindings in this descriptor set */
1666 struct anv_descriptor_set_binding_layout binding
[0];
1670 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1672 assert(layout
&& layout
->ref_cnt
>= 1);
1673 p_atomic_inc(&layout
->ref_cnt
);
1677 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1678 struct anv_descriptor_set_layout
*layout
)
1680 assert(layout
&& layout
->ref_cnt
>= 1);
1681 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1682 vk_free(&device
->alloc
, layout
);
1685 struct anv_descriptor
{
1686 VkDescriptorType type
;
1690 VkImageLayout layout
;
1691 struct anv_image_view
*image_view
;
1692 struct anv_sampler
*sampler
;
1696 struct anv_buffer
*buffer
;
1701 struct anv_buffer_view
*buffer_view
;
1705 struct anv_descriptor_set
{
1706 struct anv_descriptor_pool
*pool
;
1707 struct anv_descriptor_set_layout
*layout
;
1710 /* State relative to anv_descriptor_pool::bo */
1711 struct anv_state desc_mem
;
1712 /* Surface state for the descriptor buffer */
1713 struct anv_state desc_surface_state
;
1715 uint32_t buffer_view_count
;
1716 struct anv_buffer_view
*buffer_views
;
1718 /* Link to descriptor pool's desc_sets list . */
1719 struct list_head pool_link
;
1721 struct anv_descriptor descriptors
[0];
1724 struct anv_buffer_view
{
1725 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1726 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1728 struct anv_address address
;
1730 struct anv_state surface_state
;
1731 struct anv_state storage_surface_state
;
1732 struct anv_state writeonly_storage_surface_state
;
1734 struct brw_image_param storage_image_param
;
1737 struct anv_push_descriptor_set
{
1738 struct anv_descriptor_set set
;
1740 /* Put this field right behind anv_descriptor_set so it fills up the
1741 * descriptors[0] field. */
1742 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1744 /** True if the descriptor set buffer has been referenced by a draw or
1747 bool set_used_on_gpu
;
1749 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1752 struct anv_descriptor_pool
{
1758 struct util_vma_heap bo_heap
;
1760 struct anv_state_stream surface_state_stream
;
1761 void *surface_state_free_list
;
1763 struct list_head desc_sets
;
1768 enum anv_descriptor_template_entry_type
{
1769 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1770 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1771 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1774 struct anv_descriptor_template_entry
{
1775 /* The type of descriptor in this entry */
1776 VkDescriptorType type
;
1778 /* Binding in the descriptor set */
1781 /* Offset at which to write into the descriptor set binding */
1782 uint32_t array_element
;
1784 /* Number of elements to write into the descriptor set binding */
1785 uint32_t array_count
;
1787 /* Offset into the user provided data */
1790 /* Stride between elements into the user provided data */
1794 struct anv_descriptor_update_template
{
1795 VkPipelineBindPoint bind_point
;
1797 /* The descriptor set this template corresponds to. This value is only
1798 * valid if the template was created with the templateType
1799 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1803 /* Number of entries in this template */
1804 uint32_t entry_count
;
1806 /* Entries of the template */
1807 struct anv_descriptor_template_entry entries
[0];
1811 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1814 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1815 struct anv_descriptor_set
*set
,
1816 const VkDescriptorImageInfo
* const info
,
1817 VkDescriptorType type
,
1822 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1823 struct anv_descriptor_set
*set
,
1824 VkDescriptorType type
,
1825 struct anv_buffer_view
*buffer_view
,
1830 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1831 struct anv_descriptor_set
*set
,
1832 struct anv_state_stream
*alloc_stream
,
1833 VkDescriptorType type
,
1834 struct anv_buffer
*buffer
,
1837 VkDeviceSize offset
,
1838 VkDeviceSize range
);
1840 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1841 struct anv_descriptor_set
*set
,
1848 anv_descriptor_set_write_template(struct anv_device
*device
,
1849 struct anv_descriptor_set
*set
,
1850 struct anv_state_stream
*alloc_stream
,
1851 const struct anv_descriptor_update_template
*template,
1855 anv_descriptor_set_create(struct anv_device
*device
,
1856 struct anv_descriptor_pool
*pool
,
1857 struct anv_descriptor_set_layout
*layout
,
1858 struct anv_descriptor_set
**out_set
);
1861 anv_descriptor_set_destroy(struct anv_device
*device
,
1862 struct anv_descriptor_pool
*pool
,
1863 struct anv_descriptor_set
*set
);
1865 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1866 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1867 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1868 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1870 struct anv_pipeline_binding
{
1871 /* The descriptor set this surface corresponds to. The special value of
1872 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1873 * to a color attachment and not a regular descriptor.
1877 /* Binding in the descriptor set */
1880 /* Index in the binding */
1883 /* Plane in the binding index */
1886 /* Input attachment index (relative to the subpass) */
1887 uint8_t input_attachment_index
;
1889 /* For a storage image, whether it is write-only */
1893 struct anv_pipeline_layout
{
1895 struct anv_descriptor_set_layout
*layout
;
1896 uint32_t dynamic_offset_start
;
1901 unsigned char sha1
[20];
1905 struct anv_device
* device
;
1908 VkBufferUsageFlags usage
;
1910 /* Set when bound */
1911 struct anv_address address
;
1914 static inline uint64_t
1915 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1917 assert(offset
<= buffer
->size
);
1918 if (range
== VK_WHOLE_SIZE
) {
1919 return buffer
->size
- offset
;
1921 assert(range
+ offset
>= range
);
1922 assert(range
+ offset
<= buffer
->size
);
1927 enum anv_cmd_dirty_bits
{
1928 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1929 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1930 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1931 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1932 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1933 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1934 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1935 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1936 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1937 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1938 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1939 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1940 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1941 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1943 typedef uint32_t anv_cmd_dirty_mask_t
;
1945 enum anv_pipe_bits
{
1946 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1947 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1948 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1949 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1950 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1951 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1952 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1953 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1954 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1955 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1956 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1958 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1959 * a flush has happened but not a CS stall. The next time we do any sort
1960 * of invalidation we need to insert a CS stall at that time. Otherwise,
1961 * we would have to CS stall on every flush which could be bad.
1963 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1965 /* This bit does not exist directly in PIPE_CONTROL. It means that render
1966 * target operations related to transfer commands with VkBuffer as
1967 * destination are ongoing. Some operations like copies on the command
1968 * streamer might need to be aware of this to trigger the appropriate stall
1969 * before they can proceed with the copy.
1971 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
1974 #define ANV_PIPE_FLUSH_BITS ( \
1975 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1976 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1977 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1979 #define ANV_PIPE_STALL_BITS ( \
1980 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1981 ANV_PIPE_DEPTH_STALL_BIT | \
1982 ANV_PIPE_CS_STALL_BIT)
1984 #define ANV_PIPE_INVALIDATE_BITS ( \
1985 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1986 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1987 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1988 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1989 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1990 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1992 static inline enum anv_pipe_bits
1993 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1995 enum anv_pipe_bits pipe_bits
= 0;
1998 for_each_bit(b
, flags
) {
1999 switch ((VkAccessFlagBits
)(1 << b
)) {
2000 case VK_ACCESS_SHADER_WRITE_BIT
:
2001 /* We're transitioning a buffer that was previously used as write
2002 * destination through the data port. To make its content available
2003 * to future operations, flush the data cache.
2005 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2007 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2008 /* We're transitioning a buffer that was previously used as render
2009 * target. To make its content available to future operations, flush
2010 * the render target cache.
2012 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2014 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2015 /* We're transitioning a buffer that was previously used as depth
2016 * buffer. To make its content available to future operations, flush
2019 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2021 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2022 /* We're transitioning a buffer that was previously used as a
2023 * transfer write destination. Generic write operations include color
2024 * & depth operations as well as buffer operations like :
2025 * - vkCmdClearColorImage()
2026 * - vkCmdClearDepthStencilImage()
2027 * - vkCmdBlitImage()
2028 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2030 * Most of these operations are implemented using Blorp which writes
2031 * through the render target, so flush that cache to make it visible
2032 * to future operations. And for depth related operations we also
2033 * need to flush the depth cache.
2035 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2036 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2038 case VK_ACCESS_MEMORY_WRITE_BIT
:
2039 /* We're transitioning a buffer for generic write operations. Flush
2042 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2045 break; /* Nothing to do */
2052 static inline enum anv_pipe_bits
2053 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2055 enum anv_pipe_bits pipe_bits
= 0;
2058 for_each_bit(b
, flags
) {
2059 switch ((VkAccessFlagBits
)(1 << b
)) {
2060 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2061 /* Indirect draw commands take a buffer as input that we're going to
2062 * read from the command streamer to load some of the HW registers
2063 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2064 * command streamer stall so that all the cache flushes have
2065 * completed before the command streamer loads from memory.
2067 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2068 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2069 * through a vertex buffer, so invalidate that cache.
2071 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2072 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2073 * UBO from the buffer, so we need to invalidate constant cache.
2075 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2077 case VK_ACCESS_INDEX_READ_BIT
:
2078 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2079 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2080 * commands, so we invalidate the VF cache to make sure there is no
2081 * stale data when we start rendering.
2083 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2085 case VK_ACCESS_UNIFORM_READ_BIT
:
2086 /* We transitioning a buffer to be used as uniform data. Because
2087 * uniform is accessed through the data port & sampler, we need to
2088 * invalidate the texture cache (sampler) & constant cache (data
2089 * port) to avoid stale data.
2091 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2092 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2094 case VK_ACCESS_SHADER_READ_BIT
:
2095 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2096 case VK_ACCESS_TRANSFER_READ_BIT
:
2097 /* Transitioning a buffer to be read through the sampler, so
2098 * invalidate the texture cache, we don't want any stale data.
2100 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2102 case VK_ACCESS_MEMORY_READ_BIT
:
2103 /* Transitioning a buffer for generic read, invalidate all the
2106 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2108 case VK_ACCESS_MEMORY_WRITE_BIT
:
2109 /* Generic write, make sure all previously written things land in
2112 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2114 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2115 /* Transitioning a buffer for conditional rendering. We'll load the
2116 * content of this buffer into HW registers using the command
2117 * streamer, so we need to stall the command streamer to make sure
2118 * any in-flight flush operations have completed.
2120 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2123 break; /* Nothing to do */
2130 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2131 VK_IMAGE_ASPECT_COLOR_BIT | \
2132 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2133 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2134 VK_IMAGE_ASPECT_PLANE_2_BIT)
2135 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2136 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2137 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2138 VK_IMAGE_ASPECT_PLANE_2_BIT)
2140 struct anv_vertex_binding
{
2141 struct anv_buffer
* buffer
;
2142 VkDeviceSize offset
;
2145 struct anv_xfb_binding
{
2146 struct anv_buffer
* buffer
;
2147 VkDeviceSize offset
;
2151 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2152 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2153 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2155 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2156 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2157 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2159 struct anv_push_constants
{
2160 /* Push constant data provided by the client through vkPushConstants */
2161 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2163 /* Used for vkCmdDispatchBase */
2164 uint32_t base_work_group_id
[3];
2167 struct anv_dynamic_state
{
2170 VkViewport viewports
[MAX_VIEWPORTS
];
2175 VkRect2D scissors
[MAX_SCISSORS
];
2186 float blend_constants
[4];
2196 } stencil_compare_mask
;
2201 } stencil_write_mask
;
2206 } stencil_reference
;
2209 extern const struct anv_dynamic_state default_dynamic_state
;
2211 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2212 const struct anv_dynamic_state
*src
,
2213 uint32_t copy_mask
);
2215 struct anv_surface_state
{
2216 struct anv_state state
;
2217 /** Address of the surface referred to by this state
2219 * This address is relative to the start of the BO.
2221 struct anv_address address
;
2222 /* Address of the aux surface, if any
2224 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2226 * With the exception of gen8, the bottom 12 bits of this address' offset
2227 * include extra aux information.
2229 struct anv_address aux_address
;
2230 /* Address of the clear color, if any
2232 * This address is relative to the start of the BO.
2234 struct anv_address clear_address
;
2238 * Attachment state when recording a renderpass instance.
2240 * The clear value is valid only if there exists a pending clear.
2242 struct anv_attachment_state
{
2243 enum isl_aux_usage aux_usage
;
2244 enum isl_aux_usage input_aux_usage
;
2245 struct anv_surface_state color
;
2246 struct anv_surface_state input
;
2248 VkImageLayout current_layout
;
2249 VkImageAspectFlags pending_clear_aspects
;
2250 VkImageAspectFlags pending_load_aspects
;
2252 VkClearValue clear_value
;
2253 bool clear_color_is_zero_one
;
2254 bool clear_color_is_zero
;
2256 /* When multiview is active, attachments with a renderpass clear
2257 * operation have their respective layers cleared on the first
2258 * subpass that uses them, and only in that subpass. We keep track
2259 * of this using a bitfield to indicate which layers of an attachment
2260 * have not been cleared yet when multiview is active.
2262 uint32_t pending_clear_views
;
2265 /** State tracking for particular pipeline bind point
2267 * This struct is the base struct for anv_cmd_graphics_state and
2268 * anv_cmd_compute_state. These are used to track state which is bound to a
2269 * particular type of pipeline. Generic state that applies per-stage such as
2270 * binding table offsets and push constants is tracked generically with a
2271 * per-stage array in anv_cmd_state.
2273 struct anv_cmd_pipeline_state
{
2274 struct anv_pipeline
*pipeline
;
2275 struct anv_pipeline_layout
*layout
;
2277 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2278 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2280 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2283 /** State tracking for graphics pipeline
2285 * This has anv_cmd_pipeline_state as a base struct to track things which get
2286 * bound to a graphics pipeline. Along with general pipeline bind point state
2287 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2288 * state which is graphics-specific.
2290 struct anv_cmd_graphics_state
{
2291 struct anv_cmd_pipeline_state base
;
2293 anv_cmd_dirty_mask_t dirty
;
2296 struct anv_dynamic_state dynamic
;
2299 struct anv_buffer
*index_buffer
;
2300 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2301 uint32_t index_offset
;
2305 /** State tracking for compute pipeline
2307 * This has anv_cmd_pipeline_state as a base struct to track things which get
2308 * bound to a compute pipeline. Along with general pipeline bind point state
2309 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2310 * state which is compute-specific.
2312 struct anv_cmd_compute_state
{
2313 struct anv_cmd_pipeline_state base
;
2315 bool pipeline_dirty
;
2317 struct anv_address num_workgroups
;
2320 /** State required while building cmd buffer */
2321 struct anv_cmd_state
{
2322 /* PIPELINE_SELECT.PipelineSelection */
2323 uint32_t current_pipeline
;
2324 const struct gen_l3_config
* current_l3_config
;
2326 struct anv_cmd_graphics_state gfx
;
2327 struct anv_cmd_compute_state compute
;
2329 enum anv_pipe_bits pending_pipe_bits
;
2330 VkShaderStageFlags descriptors_dirty
;
2331 VkShaderStageFlags push_constants_dirty
;
2333 struct anv_framebuffer
* framebuffer
;
2334 struct anv_render_pass
* pass
;
2335 struct anv_subpass
* subpass
;
2336 VkRect2D render_area
;
2337 uint32_t restart_index
;
2338 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2340 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2341 VkShaderStageFlags push_constant_stages
;
2342 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2343 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2344 struct anv_state samplers
[MESA_SHADER_STAGES
];
2347 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2348 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2349 * and before invoking the secondary in ExecuteCommands.
2351 bool pma_fix_enabled
;
2354 * Whether or not we know for certain that HiZ is enabled for the current
2355 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2356 * enabled or not, this will be false.
2360 bool conditional_render_enabled
;
2363 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2364 * valid only when recording a render pass instance.
2366 struct anv_attachment_state
* attachments
;
2369 * Surface states for color render targets. These are stored in a single
2370 * flat array. For depth-stencil attachments, the surface state is simply
2373 struct anv_state render_pass_states
;
2376 * A null surface state of the right size to match the framebuffer. This
2377 * is one of the states in render_pass_states.
2379 struct anv_state null_surface_state
;
2382 struct anv_cmd_pool
{
2383 VkAllocationCallbacks alloc
;
2384 struct list_head cmd_buffers
;
2387 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2389 enum anv_cmd_buffer_exec_mode
{
2390 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2391 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2392 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2393 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2394 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2397 struct anv_cmd_buffer
{
2398 VK_LOADER_DATA _loader_data
;
2400 struct anv_device
* device
;
2402 struct anv_cmd_pool
* pool
;
2403 struct list_head pool_link
;
2405 struct anv_batch batch
;
2407 /* Fields required for the actual chain of anv_batch_bo's.
2409 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2411 struct list_head batch_bos
;
2412 enum anv_cmd_buffer_exec_mode exec_mode
;
2414 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2415 * referenced by this command buffer
2417 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2419 struct u_vector seen_bbos
;
2421 /* A vector of int32_t's for every block of binding tables.
2423 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2425 struct u_vector bt_block_states
;
2428 struct anv_reloc_list surface_relocs
;
2429 /** Last seen surface state block pool center bo offset */
2430 uint32_t last_ss_pool_center
;
2432 /* Serial for tracking buffer completion */
2435 /* Stream objects for storing temporary data */
2436 struct anv_state_stream surface_state_stream
;
2437 struct anv_state_stream dynamic_state_stream
;
2439 VkCommandBufferUsageFlags usage_flags
;
2440 VkCommandBufferLevel level
;
2442 struct anv_cmd_state state
;
2445 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2446 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2447 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2448 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2449 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2450 struct anv_cmd_buffer
*secondary
);
2451 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2452 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2453 struct anv_cmd_buffer
*cmd_buffer
,
2454 const VkSemaphore
*in_semaphores
,
2455 uint32_t num_in_semaphores
,
2456 const VkSemaphore
*out_semaphores
,
2457 uint32_t num_out_semaphores
,
2460 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2462 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2463 const void *data
, uint32_t size
, uint32_t alignment
);
2464 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2465 uint32_t *a
, uint32_t *b
,
2466 uint32_t dwords
, uint32_t alignment
);
2469 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2471 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2472 uint32_t entries
, uint32_t *state_offset
);
2474 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2476 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2477 uint32_t size
, uint32_t alignment
);
2480 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2482 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2483 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2484 bool depth_clamp_enable
);
2485 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2487 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2488 struct anv_render_pass
*pass
,
2489 struct anv_framebuffer
*framebuffer
,
2490 const VkClearValue
*clear_values
);
2492 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2495 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2496 gl_shader_stage stage
);
2498 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2500 const struct anv_image_view
*
2501 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2504 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2505 uint32_t num_entries
,
2506 uint32_t *state_offset
,
2507 struct anv_state
*bt_state
);
2509 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2511 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2513 enum anv_fence_type
{
2514 ANV_FENCE_TYPE_NONE
= 0,
2516 ANV_FENCE_TYPE_SYNCOBJ
,
2520 enum anv_bo_fence_state
{
2521 /** Indicates that this is a new (or newly reset fence) */
2522 ANV_BO_FENCE_STATE_RESET
,
2524 /** Indicates that this fence has been submitted to the GPU but is still
2525 * (as far as we know) in use by the GPU.
2527 ANV_BO_FENCE_STATE_SUBMITTED
,
2529 ANV_BO_FENCE_STATE_SIGNALED
,
2532 struct anv_fence_impl
{
2533 enum anv_fence_type type
;
2536 /** Fence implementation for BO fences
2538 * These fences use a BO and a set of CPU-tracked state flags. The BO
2539 * is added to the object list of the last execbuf call in a QueueSubmit
2540 * and is marked EXEC_WRITE. The state flags track when the BO has been
2541 * submitted to the kernel. We need to do this because Vulkan lets you
2542 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2543 * will say it's idle in this case.
2547 enum anv_bo_fence_state state
;
2550 /** DRM syncobj handle for syncobj-based fences */
2554 struct wsi_fence
*fence_wsi
;
2559 /* Permanent fence state. Every fence has some form of permanent state
2560 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2561 * cross-process fences) or it could just be a dummy for use internally.
2563 struct anv_fence_impl permanent
;
2565 /* Temporary fence state. A fence *may* have temporary state. That state
2566 * is added to the fence by an import operation and is reset back to
2567 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2568 * state cannot be signaled because the fence must already be signaled
2569 * before the temporary state can be exported from the fence in the other
2570 * process and imported here.
2572 struct anv_fence_impl temporary
;
2577 struct anv_state state
;
2580 enum anv_semaphore_type
{
2581 ANV_SEMAPHORE_TYPE_NONE
= 0,
2582 ANV_SEMAPHORE_TYPE_DUMMY
,
2583 ANV_SEMAPHORE_TYPE_BO
,
2584 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2585 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2588 struct anv_semaphore_impl
{
2589 enum anv_semaphore_type type
;
2592 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2593 * This BO will be added to the object list on any execbuf2 calls for
2594 * which this semaphore is used as a wait or signal fence. When used as
2595 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2599 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2600 * If the semaphore is in the unsignaled state due to either just being
2601 * created or because it has been used for a wait, fd will be -1.
2605 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2606 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2607 * import so we don't need to bother with a userspace cache.
2613 struct anv_semaphore
{
2614 /* Permanent semaphore state. Every semaphore has some form of permanent
2615 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2616 * (for cross-process semaphores0 or it could just be a dummy for use
2619 struct anv_semaphore_impl permanent
;
2621 /* Temporary semaphore state. A semaphore *may* have temporary state.
2622 * That state is added to the semaphore by an import operation and is reset
2623 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2624 * semaphore with temporary state cannot be signaled because the semaphore
2625 * must already be signaled before the temporary state can be exported from
2626 * the semaphore in the other process and imported here.
2628 struct anv_semaphore_impl temporary
;
2631 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2632 struct anv_semaphore
*semaphore
);
2634 struct anv_shader_module
{
2635 unsigned char sha1
[20];
2640 static inline gl_shader_stage
2641 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2643 assert(__builtin_popcount(vk_stage
) == 1);
2644 return ffs(vk_stage
) - 1;
2647 static inline VkShaderStageFlagBits
2648 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2650 return (1 << mesa_stage
);
2653 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2655 #define anv_foreach_stage(stage, stage_bits) \
2656 for (gl_shader_stage stage, \
2657 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2658 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2659 __tmp &= ~(1 << (stage)))
2661 struct anv_pipeline_bind_map
{
2662 uint32_t surface_count
;
2663 uint32_t sampler_count
;
2665 struct anv_pipeline_binding
* surface_to_descriptor
;
2666 struct anv_pipeline_binding
* sampler_to_descriptor
;
2669 struct anv_shader_bin_key
{
2674 struct anv_shader_bin
{
2677 const struct anv_shader_bin_key
*key
;
2679 struct anv_state kernel
;
2680 uint32_t kernel_size
;
2682 struct anv_state constant_data
;
2683 uint32_t constant_data_size
;
2685 const struct brw_stage_prog_data
*prog_data
;
2686 uint32_t prog_data_size
;
2688 struct nir_xfb_info
*xfb_info
;
2690 struct anv_pipeline_bind_map bind_map
;
2693 struct anv_shader_bin
*
2694 anv_shader_bin_create(struct anv_device
*device
,
2695 const void *key
, uint32_t key_size
,
2696 const void *kernel
, uint32_t kernel_size
,
2697 const void *constant_data
, uint32_t constant_data_size
,
2698 const struct brw_stage_prog_data
*prog_data
,
2699 uint32_t prog_data_size
, const void *prog_data_param
,
2700 const struct nir_xfb_info
*xfb_info
,
2701 const struct anv_pipeline_bind_map
*bind_map
);
2704 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2707 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2709 assert(shader
&& shader
->ref_cnt
>= 1);
2710 p_atomic_inc(&shader
->ref_cnt
);
2714 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2716 assert(shader
&& shader
->ref_cnt
>= 1);
2717 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2718 anv_shader_bin_destroy(device
, shader
);
2721 struct anv_pipeline
{
2722 struct anv_device
* device
;
2723 struct anv_batch batch
;
2724 uint32_t batch_data
[512];
2725 struct anv_reloc_list batch_relocs
;
2726 uint32_t dynamic_state_mask
;
2727 struct anv_dynamic_state dynamic_state
;
2729 struct anv_subpass
* subpass
;
2731 bool needs_data_cache
;
2733 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2736 const struct gen_l3_config
* l3_config
;
2737 uint32_t total_size
;
2740 VkShaderStageFlags active_stages
;
2741 struct anv_state blend_state
;
2744 struct anv_pipeline_vertex_binding
{
2747 uint32_t instance_divisor
;
2752 bool primitive_restart
;
2755 uint32_t cs_right_mask
;
2758 bool depth_test_enable
;
2759 bool writes_stencil
;
2760 bool stencil_test_enable
;
2761 bool depth_clamp_enable
;
2762 bool depth_clip_enable
;
2763 bool sample_shading_enable
;
2768 uint32_t depth_stencil_state
[3];
2774 uint32_t wm_depth_stencil
[3];
2778 uint32_t wm_depth_stencil
[4];
2781 uint32_t interface_descriptor_data
[8];
2785 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2786 gl_shader_stage stage
)
2788 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2791 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2792 static inline const struct brw_##prefix##_prog_data * \
2793 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2795 if (anv_pipeline_has_stage(pipeline, stage)) { \
2796 return (const struct brw_##prefix##_prog_data *) \
2797 pipeline->shaders[stage]->prog_data; \
2803 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2804 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2805 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2806 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2807 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2808 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2810 static inline const struct brw_vue_prog_data
*
2811 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2813 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2814 return &get_gs_prog_data(pipeline
)->base
;
2815 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2816 return &get_tes_prog_data(pipeline
)->base
;
2818 return &get_vs_prog_data(pipeline
)->base
;
2822 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2823 struct anv_pipeline_cache
*cache
,
2824 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2825 const VkAllocationCallbacks
*alloc
);
2828 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2829 struct anv_pipeline_cache
*cache
,
2830 const VkComputePipelineCreateInfo
*info
,
2831 const struct anv_shader_module
*module
,
2832 const char *entrypoint
,
2833 const VkSpecializationInfo
*spec_info
);
2835 struct anv_format_plane
{
2836 enum isl_format isl_format
:16;
2837 struct isl_swizzle swizzle
;
2839 /* Whether this plane contains chroma channels */
2842 /* For downscaling of YUV planes */
2843 uint8_t denominator_scales
[2];
2845 /* How to map sampled ycbcr planes to a single 4 component element. */
2846 struct isl_swizzle ycbcr_swizzle
;
2848 /* What aspect is associated to this plane */
2849 VkImageAspectFlags aspect
;
2854 struct anv_format_plane planes
[3];
2860 static inline uint32_t
2861 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2862 VkImageAspectFlags aspect_mask
)
2864 switch (aspect_mask
) {
2865 case VK_IMAGE_ASPECT_COLOR_BIT
:
2866 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2867 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2869 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2870 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2873 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2875 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2878 /* Purposefully assert with depth/stencil aspects. */
2879 unreachable("invalid image aspect");
2883 static inline VkImageAspectFlags
2884 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2887 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2888 if (util_bitcount(image_aspects
) > 1)
2889 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2890 return VK_IMAGE_ASPECT_COLOR_BIT
;
2892 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2893 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2894 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2895 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2898 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2899 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2901 const struct anv_format
*
2902 anv_get_format(VkFormat format
);
2904 static inline uint32_t
2905 anv_get_format_planes(VkFormat vk_format
)
2907 const struct anv_format
*format
= anv_get_format(vk_format
);
2909 return format
!= NULL
? format
->n_planes
: 0;
2912 struct anv_format_plane
2913 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2914 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2916 static inline enum isl_format
2917 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2918 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2920 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2923 static inline struct isl_swizzle
2924 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2926 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2927 * RGB as RGBA for texturing
2929 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2930 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2932 /* But it doesn't matter what we render to that channel */
2933 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2939 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2942 * Subsurface of an anv_image.
2944 struct anv_surface
{
2945 /** Valid only if isl_surf::size_B > 0. */
2946 struct isl_surf isl
;
2949 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2955 VkImageType type
; /**< VkImageCreateInfo::imageType */
2956 /* The original VkFormat provided by the client. This may not match any
2957 * of the actual surface formats.
2960 const struct anv_format
*format
;
2962 VkImageAspectFlags aspects
;
2965 uint32_t array_size
;
2966 uint32_t samples
; /**< VkImageCreateInfo::samples */
2968 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2969 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
2970 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2972 /** True if this is needs to be bound to an appropriately tiled BO.
2974 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2975 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2976 * we require a dedicated allocation so that we can know to allocate a
2979 bool needs_set_tiling
;
2982 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2983 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2985 uint64_t drm_format_mod
;
2990 /* Whether the image is made of several underlying buffer objects rather a
2991 * single one with different offsets.
2995 /* All the formats that can be used when creating views of this image
2996 * are CCS_E compatible.
2998 bool ccs_e_compatible
;
3000 /* Image was created with external format. */
3001 bool external_format
;
3006 * For each foo, anv_image::planes[x].surface is valid if and only if
3007 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3008 * to figure the number associated with a given aspect.
3010 * The hardware requires that the depth buffer and stencil buffer be
3011 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3012 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3013 * allocate the depth and stencil buffers as separate surfaces in the same
3018 * -----------------------
3020 * ----------------------- |
3021 * | shadow surface0 | |
3022 * ----------------------- | Plane 0
3023 * | aux surface0 | |
3024 * ----------------------- |
3025 * | fast clear colors0 | \|/
3026 * -----------------------
3028 * ----------------------- |
3029 * | shadow surface1 | |
3030 * ----------------------- | Plane 1
3031 * | aux surface1 | |
3032 * ----------------------- |
3033 * | fast clear colors1 | \|/
3034 * -----------------------
3037 * -----------------------
3041 * Offset of the entire plane (whenever the image is disjoint this is
3049 struct anv_surface surface
;
3052 * A surface which shadows the main surface and may have different
3053 * tiling. This is used for sampling using a tiling that isn't supported
3054 * for other operations.
3056 struct anv_surface shadow_surface
;
3059 * For color images, this is the aux usage for this image when not used
3060 * as a color attachment.
3062 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3063 * image has a HiZ buffer.
3065 enum isl_aux_usage aux_usage
;
3067 struct anv_surface aux_surface
;
3070 * Offset of the fast clear state (used to compute the
3071 * fast_clear_state_offset of the following planes).
3073 uint32_t fast_clear_state_offset
;
3076 * BO associated with this plane, set when bound.
3078 struct anv_address address
;
3081 * When destroying the image, also free the bo.
3087 /* The ordering of this enum is important */
3088 enum anv_fast_clear_type
{
3089 /** Image does not have/support any fast-clear blocks */
3090 ANV_FAST_CLEAR_NONE
= 0,
3091 /** Image has/supports fast-clear but only to the default value */
3092 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3093 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3094 ANV_FAST_CLEAR_ANY
= 2,
3097 /* Returns the number of auxiliary buffer levels attached to an image. */
3098 static inline uint8_t
3099 anv_image_aux_levels(const struct anv_image
* const image
,
3100 VkImageAspectFlagBits aspect
)
3102 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3103 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3104 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
3107 /* Returns the number of auxiliary buffer layers attached to an image. */
3108 static inline uint32_t
3109 anv_image_aux_layers(const struct anv_image
* const image
,
3110 VkImageAspectFlagBits aspect
,
3111 const uint8_t miplevel
)
3115 /* The miplevel must exist in the main buffer. */
3116 assert(miplevel
< image
->levels
);
3118 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3119 /* There are no layers with auxiliary data because the miplevel has no
3124 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3125 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
3126 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
3130 static inline struct anv_address
3131 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3132 const struct anv_image
*image
,
3133 VkImageAspectFlagBits aspect
)
3135 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3137 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3138 return anv_address_add(image
->planes
[plane
].address
,
3139 image
->planes
[plane
].fast_clear_state_offset
);
3142 static inline struct anv_address
3143 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3144 const struct anv_image
*image
,
3145 VkImageAspectFlagBits aspect
)
3147 struct anv_address addr
=
3148 anv_image_get_clear_color_addr(device
, image
, aspect
);
3150 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3151 device
->isl_dev
.ss
.clear_color_state_size
:
3152 device
->isl_dev
.ss
.clear_value_size
;
3153 return anv_address_add(addr
, clear_color_state_size
);
3156 static inline struct anv_address
3157 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3158 const struct anv_image
*image
,
3159 VkImageAspectFlagBits aspect
,
3160 uint32_t level
, uint32_t array_layer
)
3162 assert(level
< anv_image_aux_levels(image
, aspect
));
3163 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3164 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3165 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3167 struct anv_address addr
=
3168 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3169 addr
.offset
+= 4; /* Go past the fast clear type */
3171 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3172 for (uint32_t l
= 0; l
< level
; l
++)
3173 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3175 addr
.offset
+= level
* image
->array_size
* 4;
3177 addr
.offset
+= array_layer
* 4;
3182 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3184 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3185 const struct anv_image
*image
)
3187 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3190 if (devinfo
->gen
< 8)
3193 return image
->samples
== 1;
3197 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3198 const struct anv_image
*image
,
3199 VkImageAspectFlagBits aspect
,
3200 enum isl_aux_usage aux_usage
,
3202 uint32_t base_layer
,
3203 uint32_t layer_count
);
3206 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3207 const struct anv_image
*image
,
3208 VkImageAspectFlagBits aspect
,
3209 enum isl_aux_usage aux_usage
,
3210 enum isl_format format
, struct isl_swizzle swizzle
,
3211 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3212 VkRect2D area
, union isl_color_value clear_color
);
3214 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3215 const struct anv_image
*image
,
3216 VkImageAspectFlags aspects
,
3217 enum isl_aux_usage depth_aux_usage
,
3219 uint32_t base_layer
, uint32_t layer_count
,
3221 float depth_value
, uint8_t stencil_value
);
3223 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3224 const struct anv_image
*src_image
,
3225 enum isl_aux_usage src_aux_usage
,
3226 uint32_t src_level
, uint32_t src_base_layer
,
3227 const struct anv_image
*dst_image
,
3228 enum isl_aux_usage dst_aux_usage
,
3229 uint32_t dst_level
, uint32_t dst_base_layer
,
3230 VkImageAspectFlagBits aspect
,
3231 uint32_t src_x
, uint32_t src_y
,
3232 uint32_t dst_x
, uint32_t dst_y
,
3233 uint32_t width
, uint32_t height
,
3234 uint32_t layer_count
,
3235 enum blorp_filter filter
);
3237 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3238 const struct anv_image
*image
,
3239 VkImageAspectFlagBits aspect
, uint32_t level
,
3240 uint32_t base_layer
, uint32_t layer_count
,
3241 enum isl_aux_op hiz_op
);
3243 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3244 const struct anv_image
*image
,
3245 VkImageAspectFlags aspects
,
3247 uint32_t base_layer
, uint32_t layer_count
,
3248 VkRect2D area
, uint8_t stencil_value
);
3250 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3251 const struct anv_image
*image
,
3252 enum isl_format format
,
3253 VkImageAspectFlagBits aspect
,
3254 uint32_t base_layer
, uint32_t layer_count
,
3255 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3258 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3259 const struct anv_image
*image
,
3260 enum isl_format format
,
3261 VkImageAspectFlagBits aspect
, uint32_t level
,
3262 uint32_t base_layer
, uint32_t layer_count
,
3263 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3267 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3268 const struct anv_image
*image
,
3269 uint32_t base_level
, uint32_t level_count
,
3270 uint32_t base_layer
, uint32_t layer_count
);
3273 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3274 const struct anv_image
*image
,
3275 const VkImageAspectFlagBits aspect
,
3276 const VkImageLayout layout
);
3278 enum anv_fast_clear_type
3279 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3280 const struct anv_image
* const image
,
3281 const VkImageAspectFlagBits aspect
,
3282 const VkImageLayout layout
);
3284 /* This is defined as a macro so that it works for both
3285 * VkImageSubresourceRange and VkImageSubresourceLayers
3287 #define anv_get_layerCount(_image, _range) \
3288 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3289 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3291 static inline uint32_t
3292 anv_get_levelCount(const struct anv_image
*image
,
3293 const VkImageSubresourceRange
*range
)
3295 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3296 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3299 static inline VkImageAspectFlags
3300 anv_image_expand_aspects(const struct anv_image
*image
,
3301 VkImageAspectFlags aspects
)
3303 /* If the underlying image has color plane aspects and
3304 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3305 * the underlying image. */
3306 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3307 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3308 return image
->aspects
;
3314 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3315 VkImageAspectFlags aspects2
)
3317 if (aspects1
== aspects2
)
3320 /* Only 1 color aspects are compatibles. */
3321 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3322 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3323 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3329 struct anv_image_view
{
3330 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3332 VkImageAspectFlags aspect_mask
;
3334 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3338 uint32_t image_plane
;
3340 struct isl_view isl
;
3343 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3344 * image layout of SHADER_READ_ONLY_OPTIMAL or
3345 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3347 struct anv_surface_state optimal_sampler_surface_state
;
3350 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3351 * image layout of GENERAL.
3353 struct anv_surface_state general_sampler_surface_state
;
3356 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3357 * states for write-only and readable, using the real format for
3358 * write-only and the lowered format for readable.
3360 struct anv_surface_state storage_surface_state
;
3361 struct anv_surface_state writeonly_storage_surface_state
;
3363 struct brw_image_param storage_image_param
;
3367 enum anv_image_view_state_flags
{
3368 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3369 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3372 void anv_image_fill_surface_state(struct anv_device
*device
,
3373 const struct anv_image
*image
,
3374 VkImageAspectFlagBits aspect
,
3375 const struct isl_view
*view
,
3376 isl_surf_usage_flags_t view_usage
,
3377 enum isl_aux_usage aux_usage
,
3378 const union isl_color_value
*clear_color
,
3379 enum anv_image_view_state_flags flags
,
3380 struct anv_surface_state
*state_inout
,
3381 struct brw_image_param
*image_param_out
);
3383 struct anv_image_create_info
{
3384 const VkImageCreateInfo
*vk_info
;
3386 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3387 isl_tiling_flags_t isl_tiling_flags
;
3389 /** These flags will be added to any derived from VkImageCreateInfo. */
3390 isl_surf_usage_flags_t isl_extra_usage_flags
;
3393 bool external_format
;
3396 VkResult
anv_image_create(VkDevice _device
,
3397 const struct anv_image_create_info
*info
,
3398 const VkAllocationCallbacks
* alloc
,
3401 const struct anv_surface
*
3402 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3403 VkImageAspectFlags aspect_mask
);
3406 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3408 static inline struct VkExtent3D
3409 anv_sanitize_image_extent(const VkImageType imageType
,
3410 const struct VkExtent3D imageExtent
)
3412 switch (imageType
) {
3413 case VK_IMAGE_TYPE_1D
:
3414 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3415 case VK_IMAGE_TYPE_2D
:
3416 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3417 case VK_IMAGE_TYPE_3D
:
3420 unreachable("invalid image type");
3424 static inline struct VkOffset3D
3425 anv_sanitize_image_offset(const VkImageType imageType
,
3426 const struct VkOffset3D imageOffset
)
3428 switch (imageType
) {
3429 case VK_IMAGE_TYPE_1D
:
3430 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3431 case VK_IMAGE_TYPE_2D
:
3432 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3433 case VK_IMAGE_TYPE_3D
:
3436 unreachable("invalid image type");
3440 VkFormatFeatureFlags
3441 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3443 const struct anv_format
*anv_format
,
3444 VkImageTiling vk_tiling
);
3446 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3447 struct anv_state state
,
3448 enum isl_format format
,
3449 struct anv_address address
,
3450 uint32_t range
, uint32_t stride
);
3453 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3454 const struct anv_attachment_state
*att_state
,
3455 const struct anv_image_view
*iview
)
3457 const struct isl_format_layout
*view_fmtl
=
3458 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3460 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3461 if (view_fmtl->channels.c.bits) \
3462 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3464 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3465 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3466 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3467 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3469 #undef COPY_CLEAR_COLOR_CHANNEL
3473 struct anv_ycbcr_conversion
{
3474 const struct anv_format
* format
;
3475 VkSamplerYcbcrModelConversion ycbcr_model
;
3476 VkSamplerYcbcrRange ycbcr_range
;
3477 VkComponentSwizzle mapping
[4];
3478 VkChromaLocation chroma_offsets
[2];
3479 VkFilter chroma_filter
;
3480 bool chroma_reconstruction
;
3483 struct anv_sampler
{
3484 uint32_t state
[3][4];
3486 struct anv_ycbcr_conversion
*conversion
;
3488 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3489 * and with a 32-byte stride for use as bindless samplers.
3491 struct anv_state bindless_state
;
3494 struct anv_framebuffer
{
3499 uint32_t attachment_count
;
3500 struct anv_image_view
* attachments
[0];
3503 struct anv_subpass_attachment
{
3504 VkImageUsageFlagBits usage
;
3505 uint32_t attachment
;
3506 VkImageLayout layout
;
3509 struct anv_subpass
{
3510 uint32_t attachment_count
;
3513 * A pointer to all attachment references used in this subpass.
3514 * Only valid if ::attachment_count > 0.
3516 struct anv_subpass_attachment
* attachments
;
3517 uint32_t input_count
;
3518 struct anv_subpass_attachment
* input_attachments
;
3519 uint32_t color_count
;
3520 struct anv_subpass_attachment
* color_attachments
;
3521 struct anv_subpass_attachment
* resolve_attachments
;
3523 struct anv_subpass_attachment
* depth_stencil_attachment
;
3524 struct anv_subpass_attachment
* ds_resolve_attachment
;
3525 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3526 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3530 /** Subpass has a depth/stencil self-dependency */
3531 bool has_ds_self_dep
;
3533 /** Subpass has at least one color resolve attachment */
3534 bool has_color_resolve
;
3537 static inline unsigned
3538 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3540 return MAX2(1, util_bitcount(subpass
->view_mask
));
3543 struct anv_render_pass_attachment
{
3544 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3545 * its members individually.
3549 VkImageUsageFlags usage
;
3550 VkAttachmentLoadOp load_op
;
3551 VkAttachmentStoreOp store_op
;
3552 VkAttachmentLoadOp stencil_load_op
;
3553 VkImageLayout initial_layout
;
3554 VkImageLayout final_layout
;
3555 VkImageLayout first_subpass_layout
;
3557 /* The subpass id in which the attachment will be used last. */
3558 uint32_t last_subpass_idx
;
3561 struct anv_render_pass
{
3562 uint32_t attachment_count
;
3563 uint32_t subpass_count
;
3564 /* An array of subpass_count+1 flushes, one per subpass boundary */
3565 enum anv_pipe_bits
* subpass_flushes
;
3566 struct anv_render_pass_attachment
* attachments
;
3567 struct anv_subpass subpasses
[0];
3570 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3572 struct anv_query_pool
{
3574 VkQueryPipelineStatisticFlags pipeline_statistics
;
3575 /** Stride between slots, in bytes */
3577 /** Number of slots in this query pool */
3582 int anv_get_instance_entrypoint_index(const char *name
);
3583 int anv_get_device_entrypoint_index(const char *name
);
3586 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3587 const struct anv_instance_extension_table
*instance
);
3590 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3591 const struct anv_instance_extension_table
*instance
,
3592 const struct anv_device_extension_table
*device
);
3594 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3597 void anv_dump_image_to_ppm(struct anv_device
*device
,
3598 struct anv_image
*image
, unsigned miplevel
,
3599 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3600 const char *filename
);
3602 enum anv_dump_action
{
3603 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3606 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3607 void anv_dump_finish(void);
3609 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3610 struct anv_framebuffer
*fb
);
3612 static inline uint32_t
3613 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3615 /* This function must be called from within a subpass. */
3616 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3618 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3620 /* The id of this subpass shouldn't exceed the number of subpasses in this
3621 * render pass minus 1.
3623 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3627 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3629 static inline struct __anv_type * \
3630 __anv_type ## _from_handle(__VkType _handle) \
3632 return (struct __anv_type *) _handle; \
3635 static inline __VkType \
3636 __anv_type ## _to_handle(struct __anv_type *_obj) \
3638 return (__VkType) _obj; \
3641 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3643 static inline struct __anv_type * \
3644 __anv_type ## _from_handle(__VkType _handle) \
3646 return (struct __anv_type *)(uintptr_t) _handle; \
3649 static inline __VkType \
3650 __anv_type ## _to_handle(struct __anv_type *_obj) \
3652 return (__VkType)(uintptr_t) _obj; \
3655 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3656 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3658 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3659 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3660 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3661 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3662 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3664 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3665 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3666 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3667 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3668 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3669 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3670 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3671 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3672 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3673 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3674 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3675 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3676 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3677 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3678 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3679 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3680 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3681 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3682 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3683 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3684 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3685 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3686 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3688 /* Gen-specific function declarations */
3690 # include "anv_genX.h"
3692 # define genX(x) gen7_##x
3693 # include "anv_genX.h"
3695 # define genX(x) gen75_##x
3696 # include "anv_genX.h"
3698 # define genX(x) gen8_##x
3699 # include "anv_genX.h"
3701 # define genX(x) gen9_##x
3702 # include "anv_genX.h"
3704 # define genX(x) gen10_##x
3705 # include "anv_genX.h"
3707 # define genX(x) gen11_##x
3708 # include "anv_genX.h"
3712 #endif /* ANV_PRIVATE_H */