src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34 #include "common/gen_guardband.h"
  35
  36 #if GEN_GEN == 8
  37 void
  38 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  39 {
  40    struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
  41    uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count;
  42    const VkViewport *viewports =
  43       cmd_buffer->state.gfx.dynamic.viewport.viewports;
  44    struct anv_state sf_clip_state =
  45       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  46
  47    for (uint32_t i = 0; i < count; i++) {
  48       const VkViewport *vp = &viewports[i];
  49
  50       /* The gen7 state struct has just the matrix and guardband fields, the
  51        * gen8 struct adds the min/max viewport fields. */
  52       struct GENX(SF_CLIP_VIEWPORT) sfv = {
  53          .ViewportMatrixElementm00 = vp->width / 2,
  54          .ViewportMatrixElementm11 = vp->height / 2,
  55          .ViewportMatrixElementm22 = vp->maxDepth - vp->minDepth,
  56          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  57          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  58          .ViewportMatrixElementm32 = vp->minDepth,
  59          .XMinClipGuardband = -1.0f,
  60          .XMaxClipGuardband = 1.0f,
  61          .YMinClipGuardband = -1.0f,
  62          .YMaxClipGuardband = 1.0f,
  63          .XMinViewPort = vp->x,
  64          .XMaxViewPort = vp->x + vp->width - 1,
  65          .YMinViewPort = MIN2(vp->y, vp->y + vp->height),
  66          .YMaxViewPort = MAX2(vp->y, vp->y + vp->height) - 1,
  67       };
  68
  69       if (fb) {
  70          /* We can only calculate a "real" guardband clip if we know the
  71           * framebuffer at the time we emit the packet.  Otherwise, we have
  72           * fall back to a worst-case guardband of [-1, 1].
  73           */
  74          gen_calculate_guardband_size(fb->width, fb->height,
  75                                       sfv.ViewportMatrixElementm00,
  76                                       sfv.ViewportMatrixElementm11,
  77                                       sfv.ViewportMatrixElementm30,
  78                                       sfv.ViewportMatrixElementm31,
  79                                       &sfv.XMinClipGuardband,
  80                                       &sfv.XMaxClipGuardband,
  81                                       &sfv.YMinClipGuardband,
  82                                       &sfv.YMaxClipGuardband);
  83       }
  84
  85       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, &sfv);
  86    }
  87
  88    anv_batch_emit(&cmd_buffer->batch,
  89                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  90       clip.SFClipViewportPointer = sf_clip_state.offset;
  91    }
  92 }
  93
  94 void
  95 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  96                                     bool depth_clamp_enable)
  97 {
  98    uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count;
  99    const VkViewport *viewports =
 100       cmd_buffer->state.gfx.dynamic.viewport.viewports;
 101    struct anv_state cc_state =
 102       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
 103
 104    for (uint32_t i = 0; i < count; i++) {
 105       const VkViewport *vp = &viewports[i];
 106
 107       struct GENX(CC_VIEWPORT) cc_viewport = {
 108          .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
 109          .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
 110       };
 111
 112       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
 113    }
 114
 115    anv_batch_emit(&cmd_buffer->batch,
 116                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 117       cc.CCViewportPointer = cc_state.offset;
 118    }
 119 }
 120 #endif
 121
 122 void
 123 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
 124 {
 125    if (cmd_buffer->state.pma_fix_enabled == enable)
 126       return;
 127
 128    cmd_buffer->state.pma_fix_enabled = enable;
 129
 130    /* According to the Broadwell PIPE_CONTROL documentation, software should
 131     * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
 132     * prior to the LRI.  If stencil buffer writes are enabled, then a Render
 133     * Cache Flush is also necessary.
 134     *
 135     * The Skylake docs say to use a depth stall rather than a command
 136     * streamer stall.  However, the hardware seems to violently disagree.
 137     * A full command streamer stall seems to be needed in both cases.
 138     */
 139    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 140       pc.DepthCacheFlushEnable = true;
 141       pc.CommandStreamerStallEnable = true;
 142       pc.RenderTargetCacheFlushEnable = true;
 143 #if GEN_GEN >= 12
 144       pc.TileCacheFlushEnable = true;
 145
 146       /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
 147        * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
 148        */
 149       pc.DepthStallEnable = true;
 150 #endif
 151    }
 152
 153 #if GEN_GEN == 9
 154
 155    uint32_t cache_mode;
 156    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
 157                    .STCPMAOptimizationEnable = enable,
 158                    .STCPMAOptimizationEnableMask = true);
 159    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 160       lri.RegisterOffset   = GENX(CACHE_MODE_0_num);
 161       lri.DataDWord        = cache_mode;
 162    }
 163
 164 #elif GEN_GEN == 8
 165
 166    uint32_t cache_mode;
 167    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_1),
 168                    .NPPMAFixEnable = enable,
 169                    .NPEarlyZFailsDisable = enable,
 170                    .NPPMAFixEnableMask = true,
 171                    .NPEarlyZFailsDisableMask = true);
 172    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 173       lri.RegisterOffset   = GENX(CACHE_MODE_1_num);
 174       lri.DataDWord        = cache_mode;
 175    }
 176
 177 #endif /* GEN_GEN == 8 */
 178
 179    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 180     * Flush bits is often necessary.  We do it regardless because it's easier.
 181     * The render cache flush is also necessary if stencil writes are enabled.
 182     *
 183     * Again, the Skylake docs give a different set of flushes but the BDW
 184     * flushes seem to work just as well.
 185     */
 186    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 187       pc.DepthStallEnable = true;
 188       pc.DepthCacheFlushEnable = true;
 189       pc.RenderTargetCacheFlushEnable = true;
 190 #if GEN_GEN >= 12
 191       pc.TileCacheFlushEnable = true;
 192 #endif
 193    }
 194 }
 195
 196 UNUSED static bool
 197 want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 198 {
 199    assert(GEN_GEN == 8);
 200
 201    /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
 202     *
 203     *    SW must set this bit in order to enable this fix when following
 204     *    expression is TRUE.
 205     *
 206     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 207     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 208     *    (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 209     *    (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
 210     *    !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
 211     *    (3DSTATE_PS_EXTRA::PixelShaderValid) &&
 212     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 213     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 214     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 215     *      3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 216     *    (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
 217     *    (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 218     *       3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 219     *       3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 220     *       3DSTATE_PS_BLEND::AlphaTestEnable ||
 221     *       3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 222     *      3DSTATE_WM::ForceKillPix != ForceOff &&
 223     *      ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 224     *        3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 225     *       (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 226     *        3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 227     *        3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 228     *     (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 229     */
 230
 231    /* These are always true:
 232     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 233     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 234     */
 235
 236    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 237     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 238     * and there is no harm.
 239     *
 240     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 241     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 242     */
 243    if (!cmd_buffer->state.hiz_enabled)
 244       return false;
 245
 246    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 247    struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
 248    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 249       return false;
 250
 251    /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
 252    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 253    if (wm_prog_data->early_fragment_tests)
 254       return false;
 255
 256    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 257     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 258     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 259     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 260     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 261     */
 262
 263    /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
 264    if (!pipeline->depth_test_enable)
 265       return false;
 266
 267    /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 268     *    3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 269     *    3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 270     *    3DSTATE_PS_BLEND::AlphaTestEnable ||
 271     *    3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 272     *   3DSTATE_WM::ForceKillPix != ForceOff &&
 273     *   ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 274     *     3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 275     *    (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 276     *     3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 277     *     3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 278     *  (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 279     */
 280    return (pipeline->kill_pixel && (pipeline->writes_depth ||
 281                                     pipeline->writes_stencil)) ||
 282           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 283 }
 284
 285 UNUSED static bool
 286 want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 287 {
 288    if (GEN_GEN > 9)
 289       return false;
 290    assert(GEN_GEN == 9);
 291
 292    /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
 293     *
 294     *    Clearing this bit will force the STC cache to wait for pending
 295     *    retirement of pixels at the HZ-read stage and do the STC-test for
 296     *    Non-promoted, R-computed and Computed depth modes instead of
 297     *    postponing the STC-test to RCPFE.
 298     *
 299     *    STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 300     *                  3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 301     *
 302     *    STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 303     *                   (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 304     *                    3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 305     *
 306     *    COMP_STC_EN = STC_TEST_EN &&
 307     *                  3DSTATE_PS_EXTRA::PixelShaderComputesStencil
 308     *
 309     *    SW parses the pipeline states to generate the following logical
 310     *    signal indicating if PMA FIX can be enabled.
 311     *
 312     *    STC_PMA_OPT =
 313     *       3DSTATE_WM::ForceThreadDispatch != 1 &&
 314     *       !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 315     *       3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 316     *       3DSTATE_DEPTH_BUFFER::HIZ Enable &&
 317     *       !(3DSTATE_WM::EDSC_Mode == 2) &&
 318     *       3DSTATE_PS_EXTRA::PixelShaderValid &&
 319     *       !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 320     *         3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 321     *         3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 322     *         3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 323     *       (COMP_STC_EN || STC_WRITE_EN) &&
 324     *       ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 325     *         3DSTATE_WM::ForceKillPix == ON ||
 326     *         3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 327     *         3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 328     *         3DSTATE_PS_BLEND::AlphaTestEnable ||
 329     *         3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 330     *        (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 331     */
 332
 333    /* These are always true:
 334     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 335     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 336     */
 337
 338    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 339     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 340     * and there is no harm.
 341     *
 342     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 343     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 344     */
 345    if (!cmd_buffer->state.hiz_enabled)
 346       return false;
 347
 348    /* We can't possibly know if HiZ is enabled without the framebuffer */
 349    assert(cmd_buffer->state.framebuffer);
 350
 351    /* HiZ is enabled so we had better have a depth buffer with HiZ */
 352    const struct anv_image_view *ds_iview =
 353       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 354    assert(ds_iview && ds_iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
 355
 356    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 357    struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
 358    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 359       return false;
 360
 361    /* !(3DSTATE_WM::EDSC_Mode == 2) */
 362    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 363    if (wm_prog_data->early_fragment_tests)
 364       return false;
 365
 366    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 367    *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 368     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 369     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 370     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 371     */
 372
 373    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 374     * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 375     */
 376    const bool stc_test_en =
 377       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 378       pipeline->stencil_test_enable;
 379
 380    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 381     * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 382     *  3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 383     */
 384    const bool stc_write_en =
 385       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 386       (cmd_buffer->state.gfx.dynamic.stencil_write_mask.front ||
 387        cmd_buffer->state.gfx.dynamic.stencil_write_mask.back) &&
 388       pipeline->writes_stencil;
 389
 390    /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
 391    const bool comp_stc_en = stc_test_en && wm_prog_data->computed_stencil;
 392
 393    /* COMP_STC_EN || STC_WRITE_EN */
 394    if (!(comp_stc_en || stc_write_en))
 395       return false;
 396
 397    /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 398     *  3DSTATE_WM::ForceKillPix == ON ||
 399     *  3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 400     *  3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 401     *  3DSTATE_PS_BLEND::AlphaTestEnable ||
 402     *  3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 403     * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
 404     */
 405    return pipeline->kill_pixel ||
 406           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 407 }
 408
 409 void
 410 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 411 {
 412    struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
 413    struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
 414
 415    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 416                                       ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 417       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 418       struct GENX(3DSTATE_SF) sf = {
 419          GENX(3DSTATE_SF_header),
 420       };
 421 #if GEN_GEN == 8
 422       if (cmd_buffer->device->info.is_cherryview) {
 423          sf.CHVLineWidth = d->line_width;
 424       } else {
 425          sf.LineWidth = d->line_width;
 426       }
 427 #else
 428       sf.LineWidth = d->line_width,
 429 #endif
 430       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 431       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
 432    }
 433
 434    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 435                                       ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 436       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 437       struct GENX(3DSTATE_RASTER) raster = {
 438          GENX(3DSTATE_RASTER_header),
 439          .GlobalDepthOffsetConstant = d->depth_bias.bias,
 440          .GlobalDepthOffsetScale = d->depth_bias.slope,
 441          .GlobalDepthOffsetClamp = d->depth_bias.clamp
 442       };
 443       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 444       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 445                            pipeline->gen8.raster);
 446    }
 447
 448    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 449     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 450     * across different state packets for gen8 and gen9. We handle that by
 451     * using a big old #if switch here.
 452     */
 453 #if GEN_GEN == 8
 454    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 455                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 456       struct anv_state cc_state =
 457          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 458                                             GENX(COLOR_CALC_STATE_length) * 4,
 459                                             64);
 460       struct GENX(COLOR_CALC_STATE) cc = {
 461          .BlendConstantColorRed = d->blend_constants[0],
 462          .BlendConstantColorGreen = d->blend_constants[1],
 463          .BlendConstantColorBlue = d->blend_constants[2],
 464          .BlendConstantColorAlpha = d->blend_constants[3],
 465          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 466          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 467       };
 468       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 469
 470       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 471          ccp.ColorCalcStatePointer        = cc_state.offset;
 472          ccp.ColorCalcStatePointerValid   = true;
 473       }
 474    }
 475
 476    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 477                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 478                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 479                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 480       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 481
 482       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 483          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 484
 485          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 486          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 487
 488          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 489          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 490
 491          .StencilBufferWriteEnable =
 492             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 493             pipeline->writes_stencil,
 494       };
 495       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 496                                           &wm_depth_stencil);
 497
 498       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 499                            pipeline->gen8.wm_depth_stencil);
 500
 501       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 502                                       want_depth_pma_fix(cmd_buffer));
 503    }
 504 #else
 505    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 506       struct anv_state cc_state =
 507          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 508                                             GENX(COLOR_CALC_STATE_length) * 4,
 509                                             64);
 510       struct GENX(COLOR_CALC_STATE) cc = {
 511          .BlendConstantColorRed = d->blend_constants[0],
 512          .BlendConstantColorGreen = d->blend_constants[1],
 513          .BlendConstantColorBlue = d->blend_constants[2],
 514          .BlendConstantColorAlpha = d->blend_constants[3],
 515       };
 516       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 517
 518       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 519          ccp.ColorCalcStatePointer = cc_state.offset;
 520          ccp.ColorCalcStatePointerValid = true;
 521       }
 522    }
 523
 524    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 525                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 526                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 527                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 528                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 529       uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 530       struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 531          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 532
 533          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 534          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 535
 536          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 537          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 538
 539          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 540          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 541
 542          .StencilBufferWriteEnable =
 543             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 544             pipeline->writes_stencil,
 545       };
 546       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dwords, &wm_depth_stencil);
 547
 548       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 549                            pipeline->gen9.wm_depth_stencil);
 550
 551       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 552                                       want_stencil_pma_fix(cmd_buffer));
 553    }
 554 #endif
 555
 556 #if GEN_GEN >= 12
 557    if(cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 558                                      ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
 559       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BOUNDS), db) {
 560          db.DepthBoundsTestValueModifyDisable = false;
 561          db.DepthBoundsTestEnableModifyDisable = false;
 562          db.DepthBoundsTestEnable = pipeline->depth_bounds_test_enable;
 563          db.DepthBoundsTestMinValue = d->depth_bounds.min;
 564          db.DepthBoundsTestMaxValue = d->depth_bounds.max;
 565       }
 566    }
 567 #endif
 568
 569    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) {
 570       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
 571          ls.LineStipplePattern = d->line_stipple.pattern;
 572          ls.LineStippleInverseRepeatCount =
 573             1.0f / MAX2(1, d->line_stipple.factor);
 574          ls.LineStippleRepeatCount = d->line_stipple.factor;
 575       }
 576    }
 577
 578    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 579                                       ANV_CMD_DIRTY_INDEX_BUFFER)) {
 580       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 581          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 582          vf.CutIndex                   = cmd_buffer->state.restart_index;
 583       }
 584    }
 585
 586    cmd_buffer->state.gfx.dirty = 0;
 587 }
 588
 589 static uint32_t vk_to_gen_index_type(VkIndexType type)
 590 {
 591    switch (type) {
 592    case VK_INDEX_TYPE_UINT8_EXT:
 593       return INDEX_BYTE;
 594    case VK_INDEX_TYPE_UINT16:
 595       return INDEX_WORD;
 596    case VK_INDEX_TYPE_UINT32:
 597       return INDEX_DWORD;
 598    default:
 599       unreachable("invalid index type");
 600    }
 601 }
 602
 603 static uint32_t restart_index_for_type(VkIndexType type)
 604 {
 605    switch (type) {
 606    case VK_INDEX_TYPE_UINT8_EXT:
 607       return UINT8_MAX;
 608    case VK_INDEX_TYPE_UINT16:
 609       return UINT16_MAX;
 610    case VK_INDEX_TYPE_UINT32:
 611       return UINT32_MAX;
 612    default:
 613       unreachable("invalid index type");
 614    }
 615 }
 616
 617 void genX(CmdBindIndexBuffer)(
 618     VkCommandBuffer                             commandBuffer,
 619     VkBuffer                                    _buffer,
 620     VkDeviceSize                                offset,
 621     VkIndexType                                 indexType)
 622 {
 623    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 624    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 625
 626    cmd_buffer->state.restart_index = restart_index_for_type(indexType);
 627
 628    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 629       ib.IndexFormat                = vk_to_gen_index_type(indexType);
 630       ib.MOCS                       = anv_mocs_for_bo(cmd_buffer->device,
 631                                                       buffer->address.bo);
 632       ib.BufferStartingAddress      = anv_address_add(buffer->address, offset);
 633       ib.BufferSize                 = buffer->size - offset;
 634    }
 635
 636    cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 637 }