src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 void
  37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  38 {
  39    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  40    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  41    struct anv_state sf_clip_state =
  42       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  43
  44    for (uint32_t i = 0; i < count; i++) {
  45       const VkViewport *vp = &viewports[i];
  46
  47       /* The gen7 state struct has just the matrix and guardband fields, the
  48        * gen8 struct adds the min/max viewport fields. */
  49       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  50          .ViewportMatrixElementm00 = vp->width / 2,
  51          .ViewportMatrixElementm11 = vp->height / 2,
  52          .ViewportMatrixElementm22 = 1.0,
  53          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  54          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  55          .ViewportMatrixElementm32 = 0.0,
  56          .XMinClipGuardband = -1.0f,
  57          .XMaxClipGuardband = 1.0f,
  58          .YMinClipGuardband = -1.0f,
  59          .YMaxClipGuardband = 1.0f,
  60          .XMinViewPort = vp->x,
  61          .XMaxViewPort = vp->x + vp->width - 1,
  62          .YMinViewPort = MIN2(vp->y, vp->y + vp->height),
  63          .YMaxViewPort = MAX2(vp->y, vp->y + vp->height) - 1,
  64       };
  65
  66       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  67                                  &sf_clip_viewport);
  68    }
  69
  70    if (!cmd_buffer->device->info.has_llc)
  71       anv_state_clflush(sf_clip_state);
  72
  73    anv_batch_emit(&cmd_buffer->batch,
  74                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  75       clip.SFClipViewportPointer = sf_clip_state.offset;
  76    }
  77 }
  78
  79 void
  80 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  81                                     bool depth_clamp_enable)
  82 {
  83    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  84    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  85    struct anv_state cc_state =
  86       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  87
  88    for (uint32_t i = 0; i < count; i++) {
  89       const VkViewport *vp = &viewports[i];
  90
  91       struct GENX(CC_VIEWPORT) cc_viewport = {
  92          .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
  93          .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
  94       };
  95
  96       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  97    }
  98
  99    if (!cmd_buffer->device->info.has_llc)
 100       anv_state_clflush(cc_state);
 101
 102    anv_batch_emit(&cmd_buffer->batch,
 103                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 104       cc.CCViewportPointer = cc_state.offset;
 105    }
 106 }
 107 #endif
 108
 109 static void
 110 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
 111 {
 112       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 113       struct GENX(3DSTATE_SF) sf = {
 114          GENX(3DSTATE_SF_header),
 115          .LineWidth = cmd_buffer->state.dynamic.line_width,
 116       };
 117       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 118       /* FIXME: gen9.fs */
 119       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 120                            cmd_buffer->state.pipeline->gen8.sf);
 121 }
 122
 123 void
 124 gen9_emit_sf_state(struct anv_cmd_buffer *cmd_buffer);
 125
 126 #if GEN_GEN == 9
 127
 128 void
 129 gen9_emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 130 {
 131    __emit_genx_sf_state(cmd_buffer);
 132 }
 133
 134 #endif
 135
 136 #if GEN_GEN == 8
 137
 138 static void
 139 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 140 {
 141    if (cmd_buffer->device->info.is_cherryview)
 142       gen9_emit_sf_state(cmd_buffer);
 143    else
 144       __emit_genx_sf_state(cmd_buffer);
 145 }
 146
 147 #else
 148
 149 static void
 150 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 151 {
 152    __emit_genx_sf_state(cmd_buffer);
 153 }
 154
 155 #endif
 156
 157 void
 158 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
 159 {
 160 #if GEN_GEN == 8
 161    if (cmd_buffer->state.pma_fix_enabled == enable)
 162       return;
 163
 164    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 165       pc.DepthCacheFlushEnable = true;
 166       pc.CommandStreamerStallEnable = true;
 167       pc.RenderTargetCacheFlushEnable = true;
 168    }
 169
 170    uint32_t cache_mode;
 171    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_1),
 172                    .NPPMAFixEnable = enable,
 173                    .NPEarlyZFailsDisable = enable,
 174                    .NPPMAFixEnableMask = true,
 175                    .NPEarlyZFailsDisableMask = true);
 176    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 177       lri.RegisterOffset   = GENX(CACHE_MODE_1_num);
 178       lri.DataDWord        = cache_mode;
 179    }
 180
 181    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 182     * Flush bits is often necessary.  We do it regardless because it's easier.
 183     * The render cache flush is also necessary if stencil writes are enabled.
 184     */
 185    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 186       pc.DepthStallEnable = true;
 187       pc.DepthCacheFlushEnable = true;
 188       pc.RenderTargetCacheFlushEnable = true;
 189    }
 190
 191    cmd_buffer->state.pma_fix_enabled = enable;
 192 #endif /* GEN_GEN == 8 */
 193 }
 194
 195 static inline bool
 196 want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 197 {
 198    assert(GEN_GEN == 8);
 199
 200    /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
 201     *
 202     *    SW must set this bit in order to enable this fix when following
 203     *    expression is TRUE.
 204     *
 205     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 206     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 207     *    (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 208     *    (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
 209     *    !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
 210     *    (3DSTATE_PS_EXTRA::PixelShaderValid) &&
 211     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 212     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 213     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 214     *      3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 215     *    (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
 216     *    (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 217     *       3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 218     *       3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 219     *       3DSTATE_PS_BLEND::AlphaTestEnable ||
 220     *       3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 221     *      3DSTATE_WM::ForceKillPix != ForceOff &&
 222     *      ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 223     *        3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 224     *       (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 225     *        3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 226     *        3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 227     *     (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 228     */
 229
 230    /* These are always true:
 231     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 232     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 233     */
 234
 235    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 236     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 237     * and there is no harm.
 238     *
 239     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 240     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 241     */
 242    if (!cmd_buffer->state.hiz_enabled)
 243       return false;
 244
 245    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 246    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 247    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 248       return false;
 249
 250    /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
 251    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 252    if (wm_prog_data->early_fragment_tests)
 253       return false;
 254
 255    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 256     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 257     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 258     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 259     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 260     */
 261
 262    /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
 263    if (!pipeline->depth_test_enable)
 264       return false;
 265
 266    /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 267     *    3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 268     *    3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 269     *    3DSTATE_PS_BLEND::AlphaTestEnable ||
 270     *    3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 271     *   3DSTATE_WM::ForceKillPix != ForceOff &&
 272     *   ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 273     *     3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 274     *    (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 275     *     3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 276     *     3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 277     *  (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 278     */
 279    return (pipeline->kill_pixel && (pipeline->writes_depth ||
 280                                     pipeline->writes_stencil)) ||
 281           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 282 }
 283
 284 void
 285 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 286 {
 287    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 288
 289    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 290                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 291       __emit_sf_state(cmd_buffer);
 292    }
 293
 294    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 295                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 296       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 297       struct GENX(3DSTATE_RASTER) raster = {
 298          GENX(3DSTATE_RASTER_header),
 299          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 300          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 301          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 302       };
 303       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 304       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 305                            pipeline->gen8.raster);
 306    }
 307
 308    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 309     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 310     * across different state packets for gen8 and gen9. We handle that by
 311     * using a big old #if switch here.
 312     */
 313 #if GEN_GEN == 8
 314    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 315                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 316       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 317       struct anv_state cc_state =
 318          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 319                                             GENX(COLOR_CALC_STATE_length) * 4,
 320                                             64);
 321       struct GENX(COLOR_CALC_STATE) cc = {
 322          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 323          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 324          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 325          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 326          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 327          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 328       };
 329       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 330
 331       if (!cmd_buffer->device->info.has_llc)
 332          anv_state_clflush(cc_state);
 333
 334       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 335          ccp.ColorCalcStatePointer        = cc_state.offset;
 336          ccp.ColorCalcStatePointerValid   = true;
 337       }
 338    }
 339
 340    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 341                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 342                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 343                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 344       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 345       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 346
 347       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 348          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 349
 350          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 351          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 352
 353          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 354          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 355
 356          .StencilBufferWriteEnable =
 357             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 358             pipeline->writes_stencil,
 359       };
 360       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 361                                           &wm_depth_stencil);
 362
 363       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 364                            pipeline->gen8.wm_depth_stencil);
 365
 366       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 367                                       want_depth_pma_fix(cmd_buffer));
 368    }
 369 #else
 370    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 371       struct anv_state cc_state =
 372          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 373                                             GEN9_COLOR_CALC_STATE_length * 4,
 374                                             64);
 375       struct GEN9_COLOR_CALC_STATE cc = {
 376          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 377          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 378          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 379          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 380       };
 381       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 382
 383       if (!cmd_buffer->device->info.has_llc)
 384          anv_state_clflush(cc_state);
 385
 386       anv_batch_emit(&cmd_buffer->batch, GEN9_3DSTATE_CC_STATE_POINTERS, ccp) {
 387          ccp.ColorCalcStatePointer = cc_state.offset;
 388          ccp.ColorCalcStatePointerValid = true;
 389       }
 390    }
 391
 392    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 393                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 394                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 395                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 396       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 397       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 398       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 399          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 400
 401          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 402          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 403
 404          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 405          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 406
 407          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 408          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 409
 410          .StencilBufferWriteEnable =
 411             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 412             pipeline->writes_stencil,
 413       };
 414       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 415
 416       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 417                            pipeline->gen9.wm_depth_stencil);
 418    }
 419 #endif
 420
 421    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 422                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 423       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 424          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 425          vf.CutIndex                   = cmd_buffer->state.restart_index;
 426       }
 427    }
 428
 429    cmd_buffer->state.dirty = 0;
 430 }
 431
 432 void genX(CmdBindIndexBuffer)(
 433     VkCommandBuffer                             commandBuffer,
 434     VkBuffer                                    _buffer,
 435     VkDeviceSize                                offset,
 436     VkIndexType                                 indexType)
 437 {
 438    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 439    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 440
 441    static const uint32_t vk_to_gen_index_type[] = {
 442       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 443       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 444    };
 445
 446    static const uint32_t restart_index_for_type[] = {
 447       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 448       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 449    };
 450
 451    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 452
 453    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 454       ib.IndexFormat                = vk_to_gen_index_type[indexType];
 455       ib.MemoryObjectControlState   = GENX(MOCS);
 456       ib.BufferStartingAddress      =
 457          (struct anv_address) { buffer->bo, buffer->offset + offset };
 458       ib.BufferSize                 = buffer->size - offset;
 459    }
 460
 461    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 462 }
 463
 464 /* Set of stage bits for which are pipelined, i.e. they get queued by the
 465  * command streamer for later execution.
 466  */
 467 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
 468    (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
 469     VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
 470     VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
 471     VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
 472     VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
 473     VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
 474     VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
 475     VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
 476     VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
 477     VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
 478     VK_PIPELINE_STAGE_TRANSFER_BIT | \
 479     VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
 480     VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
 481     VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
 482
 483 void genX(CmdSetEvent)(
 484     VkCommandBuffer                             commandBuffer,
 485     VkEvent                                     _event,
 486     VkPipelineStageFlags                        stageMask)
 487 {
 488    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 489    ANV_FROM_HANDLE(anv_event, event, _event);
 490
 491    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 492       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 493          pc.StallAtPixelScoreboard = true;
 494          pc.CommandStreamerStallEnable = true;
 495       }
 496
 497       pc.DestinationAddressType  = DAT_PPGTT,
 498       pc.PostSyncOperation       = WriteImmediateData,
 499       pc.Address = (struct anv_address) {
 500          &cmd_buffer->device->dynamic_state_block_pool.bo,
 501          event->state.offset
 502       };
 503       pc.ImmediateData           = VK_EVENT_SET;
 504    }
 505 }
 506
 507 void genX(CmdResetEvent)(
 508     VkCommandBuffer                             commandBuffer,
 509     VkEvent                                     _event,
 510     VkPipelineStageFlags                        stageMask)
 511 {
 512    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 513    ANV_FROM_HANDLE(anv_event, event, _event);
 514
 515    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 516       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 517          pc.StallAtPixelScoreboard = true;
 518          pc.CommandStreamerStallEnable = true;
 519       }
 520
 521       pc.DestinationAddressType  = DAT_PPGTT;
 522       pc.PostSyncOperation       = WriteImmediateData;
 523       pc.Address = (struct anv_address) {
 524          &cmd_buffer->device->dynamic_state_block_pool.bo,
 525          event->state.offset
 526       };
 527       pc.ImmediateData           = VK_EVENT_RESET;
 528    }
 529 }
 530
 531 void genX(CmdWaitEvents)(
 532     VkCommandBuffer                             commandBuffer,
 533     uint32_t                                    eventCount,
 534     const VkEvent*                              pEvents,
 535     VkPipelineStageFlags                        srcStageMask,
 536     VkPipelineStageFlags                        destStageMask,
 537     uint32_t                                    memoryBarrierCount,
 538     const VkMemoryBarrier*                      pMemoryBarriers,
 539     uint32_t                                    bufferMemoryBarrierCount,
 540     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 541     uint32_t                                    imageMemoryBarrierCount,
 542     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 543 {
 544    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 545    for (uint32_t i = 0; i < eventCount; i++) {
 546       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 547
 548       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
 549          sem.WaitMode            = PollingMode,
 550          sem.CompareOperation    = COMPARE_SAD_EQUAL_SDD,
 551          sem.SemaphoreDataDword  = VK_EVENT_SET,
 552          sem.SemaphoreAddress = (struct anv_address) {
 553             &cmd_buffer->device->dynamic_state_block_pool.bo,
 554             event->state.offset
 555          };
 556       }
 557    }
 558
 559    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 560                             false, /* byRegion */
 561                             memoryBarrierCount, pMemoryBarriers,
 562                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 563                             imageMemoryBarrierCount, pImageMemoryBarriers);
 564 }