2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
183 const struct anv_image_view
*image_view
,
184 const uint32_t plane
,
185 struct anv_surface_state state
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
188 const struct anv_image
*image
= image_view
->image
;
189 uint32_t image_plane
= image_view
->planes
[plane
].image_plane
;
191 add_surface_state_reloc(cmd_buffer
, state
.state
,
192 image
->planes
[image_plane
].bo
, state
.address
);
194 if (state
.aux_address
) {
196 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
197 &cmd_buffer
->pool
->alloc
,
198 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
199 image
->planes
[image_plane
].bo
, state
.aux_address
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
206 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
208 if (isl_format_has_int_channel(format
)) {
209 for (unsigned i
= 0; i
< 4; i
++) {
210 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
214 for (unsigned i
= 0; i
< 4; i
++) {
215 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
224 color_attachment_compute_aux_usage(struct anv_device
* device
,
225 struct anv_cmd_state
* cmd_state
,
226 uint32_t att
, VkRect2D render_area
,
227 union isl_color_value
*fast_clear_color
)
229 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
230 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
232 assert(iview
->n_planes
== 1);
234 if (iview
->planes
[0].isl
.base_array_layer
>=
235 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
236 iview
->planes
[0].isl
.base_level
)) {
237 /* There is no aux buffer which corresponds to the level and layer(s)
240 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
241 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
242 att_state
->fast_clear
= false;
244 } else if (iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_MCS
) {
245 att_state
->aux_usage
= ISL_AUX_USAGE_MCS
;
246 att_state
->input_aux_usage
= ISL_AUX_USAGE_MCS
;
247 att_state
->fast_clear
= false;
249 } else if (iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
250 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
251 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
253 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
254 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
256 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
257 * setting is only allowed if Surface Format supported for Fast
258 * Clear. In addition, if the surface is bound to the sampling
259 * engine, Surface Format must be supported for Render Target
260 * Compression for surfaces bound to the sampling engine."
262 * In other words, we can only sample from a fast-cleared image if it
263 * also supports color compression.
265 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
266 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
268 /* While fast-clear resolves and partial resolves are fairly cheap in the
269 * case where you render to most of the pixels, full resolves are not
270 * because they potentially involve reading and writing the entire
271 * framebuffer. If we can't texture with CCS_E, we should leave it off and
272 * limit ourselves to fast clears.
274 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
275 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
276 anv_perf_warn(device
->instance
, iview
->image
,
277 "Not temporarily enabling CCS_E.");
280 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
284 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
286 att_state
->clear_color_is_zero_one
=
287 color_is_zero_one(att_state
->clear_value
.color
, iview
->planes
[0].isl
.format
);
288 att_state
->clear_color_is_zero
=
289 att_state
->clear_value
.color
.uint32
[0] == 0 &&
290 att_state
->clear_value
.color
.uint32
[1] == 0 &&
291 att_state
->clear_value
.color
.uint32
[2] == 0 &&
292 att_state
->clear_value
.color
.uint32
[3] == 0;
294 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
295 /* Start off assuming fast clears are possible */
296 att_state
->fast_clear
= true;
298 /* Potentially, we could do partial fast-clears but doing so has crazy
299 * alignment restrictions. It's easier to just restrict to full size
300 * fast clears for now.
302 if (render_area
.offset
.x
!= 0 ||
303 render_area
.offset
.y
!= 0 ||
304 render_area
.extent
.width
!= iview
->extent
.width
||
305 render_area
.extent
.height
!= iview
->extent
.height
)
306 att_state
->fast_clear
= false;
308 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
309 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
310 att_state
->fast_clear
= false;
312 /* We allow fast clears when all aux layers of the miplevel are targeted.
313 * See add_fast_clear_state_buffer() for more information. Also, because
314 * we only either do a fast clear or a normal clear and not both, this
315 * complies with the gen7 restriction of not fast-clearing multiple
318 if (cmd_state
->framebuffer
->layers
!=
319 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
320 iview
->planes
[0].isl
.base_level
)) {
321 att_state
->fast_clear
= false;
323 anv_perf_warn(device
->instance
, iview
->image
,
324 "Not fast-clearing the first layer in "
325 "a multi-layer fast clear.");
329 /* We only allow fast clears in the GENERAL layout if the auxiliary
330 * buffer is always enabled and the fast-clear value is all 0's. See
331 * add_fast_clear_state_buffer() for more information.
333 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
334 VK_IMAGE_LAYOUT_GENERAL
&&
335 (!att_state
->clear_color_is_zero
||
336 iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_NONE
)) {
337 att_state
->fast_clear
= false;
340 if (att_state
->fast_clear
) {
341 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
342 sizeof(fast_clear_color
->u32
));
345 att_state
->fast_clear
= false;
350 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
352 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
355 /* We only allocate input attachment states for color surfaces. Compression
356 * is not yet enabled for depth textures and stencil doesn't allow
357 * compression so we can just use the texture surface state from the view.
359 return vk_format_is_color(att
->format
);
362 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
363 * the initial layout is undefined, the HiZ buffer and depth buffer will
364 * represent the same data at the end of this operation.
367 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
368 const struct anv_image
*image
,
369 VkImageLayout initial_layout
,
370 VkImageLayout final_layout
)
374 /* A transition is a no-op if HiZ is not enabled, or if the initial and
375 * final layouts are equal.
377 * The undefined layout indicates that the user doesn't care about the data
378 * that's currently in the buffer. Therefore, a data-preserving resolve
379 * operation is not needed.
381 if (image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_HIZ
|| initial_layout
== final_layout
)
384 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
385 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
386 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
387 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
388 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
389 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
391 enum blorp_hiz_op hiz_op
;
392 if (hiz_enabled
&& !enable_hiz
) {
393 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
394 } else if (!hiz_enabled
&& enable_hiz
) {
395 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
397 assert(hiz_enabled
== enable_hiz
);
398 /* If the same buffer will be used, no resolves are necessary. */
399 hiz_op
= BLORP_HIZ_OP_NONE
;
402 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
403 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
406 #define MI_PREDICATE_SRC0 0x2400
407 #define MI_PREDICATE_SRC1 0x2408
409 /* Manages the state of an color image subresource to ensure resolves are
410 * performed properly.
413 genX(set_image_needs_resolve
)(struct anv_cmd_buffer
*cmd_buffer
,
414 const struct anv_image
*image
,
415 VkImageAspectFlagBits aspect
,
416 unsigned level
, bool needs_resolve
)
418 assert(cmd_buffer
&& image
);
419 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
420 assert(level
< anv_image_aux_levels(image
, aspect
));
422 /* The HW docs say that there is no way to guarantee the completion of
423 * the following command. We use it nevertheless because it shows no
424 * issues in testing is currently being used in the GL driver.
426 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
427 sdi
.Address
= anv_image_get_needs_resolve_addr(cmd_buffer
->device
,
428 image
, aspect
, level
);
429 sdi
.ImmediateData
= needs_resolve
;
434 genX(load_needs_resolve_predicate
)(struct anv_cmd_buffer
*cmd_buffer
,
435 const struct anv_image
*image
,
436 VkImageAspectFlagBits aspect
,
439 assert(cmd_buffer
&& image
);
440 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
441 assert(level
< anv_image_aux_levels(image
, aspect
));
443 const struct anv_address resolve_flag_addr
=
444 anv_image_get_needs_resolve_addr(cmd_buffer
->device
,
445 image
, aspect
, level
);
447 /* Make the pending predicated resolve a no-op if one is not needed.
448 * predicate = do_resolve = resolve_flag != 0;
450 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
451 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
452 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, 0);
453 emit_lrm(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4,
454 resolve_flag_addr
.bo
, resolve_flag_addr
.offset
);
455 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
456 mip
.LoadOperation
= LOAD_LOADINV
;
457 mip
.CombineOperation
= COMBINE_SET
;
458 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
463 init_fast_clear_state_entry(struct anv_cmd_buffer
*cmd_buffer
,
464 const struct anv_image
*image
,
465 VkImageAspectFlagBits aspect
,
468 assert(cmd_buffer
&& image
);
469 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
470 assert(level
< anv_image_aux_levels(image
, aspect
));
472 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
473 enum isl_aux_usage aux_usage
= image
->planes
[plane
].aux_usage
;
475 /* The resolve flag should updated to signify that fast-clear/compression
476 * data needs to be removed when leaving the undefined layout. Such data
477 * may need to be removed if it would cause accesses to the color buffer
478 * to return incorrect data. The fast clear data in CCS_D buffers should
479 * be removed because CCS_D isn't enabled all the time.
481 genX(set_image_needs_resolve
)(cmd_buffer
, image
, aspect
, level
,
482 aux_usage
== ISL_AUX_USAGE_NONE
);
484 /* The fast clear value dword(s) will be copied into a surface state object.
485 * Ensure that the restrictions of the fields in the dword(s) are followed.
487 * CCS buffers on SKL+ can have any value set for the clear colors.
489 if (image
->samples
== 1 && GEN_GEN
>= 9)
492 /* Other combinations of auxiliary buffers and platforms require specific
493 * values in the clear value dword(s).
495 struct anv_address addr
=
496 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
, level
);
498 for (; i
< cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
; i
+= 4) {
499 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
503 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
504 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
505 sdi
.ImmediateData
= 0;
506 } else if (GEN_VERSIONx10
>= 75) {
507 /* Pre-SKL, the dword containing the clear values also contains
508 * other fields, so we need to initialize those fields to match the
509 * values that would be in a color attachment.
512 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
513 ISL_CHANNEL_SELECT_GREEN
<< 22 |
514 ISL_CHANNEL_SELECT_BLUE
<< 19 |
515 ISL_CHANNEL_SELECT_ALPHA
<< 16;
516 } else if (GEN_VERSIONx10
== 70) {
517 /* On IVB, the dword containing the clear values also contains
518 * other fields that must be zero or can be zero.
521 sdi
.ImmediateData
= 0;
529 /* Copy the fast-clear value dword(s) between a surface state object and an
530 * image's fast clear state buffer.
533 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
534 struct anv_state surface_state
,
535 const struct anv_image
*image
,
536 VkImageAspectFlagBits aspect
,
538 bool copy_from_surface_state
)
540 assert(cmd_buffer
&& image
);
541 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
542 assert(level
< anv_image_aux_levels(image
, aspect
));
544 struct anv_bo
*ss_bo
=
545 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
546 uint32_t ss_clear_offset
= surface_state
.offset
+
547 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
548 const struct anv_address entry_addr
=
549 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
, level
);
550 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
552 if (copy_from_surface_state
) {
553 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
554 ss_bo
, ss_clear_offset
, copy_size
);
556 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
557 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
559 /* Updating a surface state object may require that the state cache be
560 * invalidated. From the SKL PRM, Shared Functions -> State -> State
563 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
564 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
565 * modified [...], the L1 state cache must be invalidated to ensure
566 * the new surface or sampler state is fetched from system memory.
568 * In testing, SKL doesn't actually seem to need this, but HSW does.
570 cmd_buffer
->state
.pending_pipe_bits
|=
571 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
576 * @brief Transitions a color buffer from one layout to another.
578 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
581 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
582 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
583 * this represents the maximum layers to transition at each
584 * specified miplevel.
587 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
588 const struct anv_image
*image
,
589 VkImageAspectFlagBits aspect
,
590 const uint32_t base_level
, uint32_t level_count
,
591 uint32_t base_layer
, uint32_t layer_count
,
592 VkImageLayout initial_layout
,
593 VkImageLayout final_layout
)
595 /* Validate the inputs. */
597 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
598 /* These values aren't supported for simplicity's sake. */
599 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
600 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
601 /* Ensure the subresource range is valid. */
602 uint64_t last_level_num
= base_level
+ level_count
;
603 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
604 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
605 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
606 assert(last_level_num
<= image
->levels
);
607 /* The spec disallows these final layouts. */
608 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
609 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
611 /* No work is necessary if the layout stays the same or if this subresource
612 * range lacks auxiliary data.
614 if (initial_layout
== final_layout
)
617 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
619 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
620 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
621 /* This surface is a linear compressed image with a tiled shadow surface
622 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
623 * we need to ensure the shadow copy is up-to-date.
625 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
626 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
627 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
628 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
630 anv_image_copy_to_shadow(cmd_buffer
, image
,
631 base_level
, level_count
,
632 base_layer
, layer_count
);
635 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
638 /* A transition of a 3D subresource works on all slices at a time. */
639 if (image
->type
== VK_IMAGE_TYPE_3D
) {
641 layer_count
= anv_minify(image
->extent
.depth
, base_level
);
644 /* We're interested in the subresource range subset that has aux data. */
645 level_count
= MIN2(level_count
, anv_image_aux_levels(image
, aspect
) - base_level
);
646 layer_count
= MIN2(layer_count
,
647 anv_image_aux_layers(image
, aspect
, base_level
) - base_layer
);
648 last_level_num
= base_level
+ level_count
;
650 /* Record whether or not the layout is undefined. Pre-initialized images
651 * with auxiliary buffers have a non-linear layout and are thus undefined.
653 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
654 const bool undef_layout
= initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
655 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
;
657 /* Do preparatory work before the resolve operation or return early if no
658 * resolve is actually needed.
661 /* A subresource in the undefined layout may have been aliased and
662 * populated with any arrangement of bits. Therefore, we must initialize
663 * the related aux buffer and clear buffer entry with desirable values.
665 * Initialize the relevant clear buffer entries.
667 for (unsigned level
= base_level
; level
< last_level_num
; level
++)
668 init_fast_clear_state_entry(cmd_buffer
, image
, aspect
, level
);
670 /* Initialize the aux buffers to enable correct rendering. This operation
671 * requires up to two steps: one to rid the aux buffer of data that may
672 * cause GPU hangs, and another to ensure that writes done without aux
673 * will be visible to reads done with aux.
675 * Having an aux buffer with invalid data is possible for CCS buffers
676 * SKL+ and for MCS buffers with certain sample counts (2x and 8x). One
677 * easy way to get to a valid state is to fast-clear the specified range.
679 * Even for MCS buffers that have sample counts that don't require
680 * certain bits to be reserved (4x and 8x), we're unsure if the hardware
681 * will be okay with the sample mappings given by the undefined buffer.
682 * We don't have any data to show that this is a problem, but we want to
683 * avoid causing difficult-to-debug problems.
685 if ((GEN_GEN
>= 9 && image
->samples
== 1) || image
->samples
> 1) {
686 if (image
->samples
== 4 || image
->samples
== 16) {
687 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
688 "Doing a potentially unnecessary fast-clear to "
689 "define an MCS buffer.");
692 if (image
->samples
== 1) {
693 for (uint32_t l
= 0; l
< level_count
; l
++) {
694 const uint32_t level
= base_level
+ l
;
695 const uint32_t level_layer_count
=
696 MIN2(layer_count
, anv_image_aux_layers(image
, aspect
, level
));
697 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
698 base_layer
, level_layer_count
,
699 ISL_AUX_OP_FAST_CLEAR
, false);
702 assert(image
->samples
> 1);
703 assert(base_level
== 0 && level_count
== 1);
704 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
705 base_layer
, layer_count
,
706 ISL_AUX_OP_FAST_CLEAR
, false);
709 /* At this point, some elements of the CCS buffer may have the fast-clear
710 * bit-arrangement. As the user writes to a subresource, we need to have
711 * the associated CCS elements enter the ambiguated state. This enables
712 * reads (implicit or explicit) to reflect the user-written data instead
713 * of the clear color. The only time such elements will not change their
714 * state as described above, is in a final layout that doesn't have CCS
715 * enabled. In this case, we must force the associated CCS buffers of the
716 * specified range to enter the ambiguated state in advance.
718 if (image
->samples
== 1 &&
719 image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
720 final_layout
!= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
721 /* The CCS_D buffer may not be enabled in the final layout. Continue
722 * executing this function to perform a resolve.
724 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
725 "Performing an additional resolve for CCS_D layout "
726 "transition. Consider always leaving it on or "
727 "performing an ambiguation pass.");
729 /* Writes in the final layout will be aware of the auxiliary buffer.
730 * In addition, the clear buffer entries and the auxiliary buffers
731 * have been populated with values that will result in correct
736 } else if (initial_layout
!= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
737 /* Resolves are only necessary if the subresource may contain blocks
738 * fast-cleared to values unsupported in other layouts. This only occurs
739 * if the initial layout is COLOR_ATTACHMENT_OPTIMAL.
742 } else if (image
->samples
> 1) {
743 /* MCS buffers don't need resolving. */
747 /* Perform a resolve to synchronize data between the main and aux buffer.
748 * Before we begin, we must satisfy the cache flushing requirement specified
749 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
751 * Any transition from any value in {Clear, Render, Resolve} to a
752 * different value in {Clear, Render, Resolve} requires end of pipe
755 * We perform a flush of the write cache before and after the clear and
756 * resolve operations to meet this requirement.
758 * Unlike other drawing, fast clear operations are not properly
759 * synchronized. The first PIPE_CONTROL here likely ensures that the
760 * contents of the previous render or clear hit the render target before we
761 * resolve and the second likely ensures that the resolve is complete before
762 * we do any more rendering or clearing.
764 cmd_buffer
->state
.pending_pipe_bits
|=
765 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
767 for (uint32_t level
= base_level
; level
< last_level_num
; level
++) {
769 /* The number of layers changes at each 3D miplevel. */
770 if (image
->type
== VK_IMAGE_TYPE_3D
) {
771 layer_count
= MIN2(layer_count
, anv_image_aux_layers(image
, aspect
, level
));
774 genX(load_needs_resolve_predicate
)(cmd_buffer
, image
, aspect
, level
);
776 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
777 base_layer
, layer_count
,
778 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
?
779 ISL_AUX_OP_PARTIAL_RESOLVE
: ISL_AUX_OP_FULL_RESOLVE
,
782 genX(set_image_needs_resolve
)(cmd_buffer
, image
, aspect
, level
, false);
785 cmd_buffer
->state
.pending_pipe_bits
|=
786 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
790 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
793 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
794 struct anv_render_pass
*pass
,
795 const VkRenderPassBeginInfo
*begin
)
797 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
798 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
800 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
802 if (pass
->attachment_count
> 0) {
803 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
804 pass
->attachment_count
*
805 sizeof(state
->attachments
[0]),
806 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
807 if (state
->attachments
== NULL
) {
808 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
809 return anv_batch_set_error(&cmd_buffer
->batch
,
810 VK_ERROR_OUT_OF_HOST_MEMORY
);
813 state
->attachments
= NULL
;
816 /* Reserve one for the NULL state. */
817 unsigned num_states
= 1;
818 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
819 if (vk_format_is_color(pass
->attachments
[i
].format
))
822 if (need_input_attachment_state(&pass
->attachments
[i
]))
826 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
827 state
->render_pass_states
=
828 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
829 num_states
* ss_stride
, isl_dev
->ss
.align
);
831 struct anv_state next_state
= state
->render_pass_states
;
832 next_state
.alloc_size
= isl_dev
->ss
.size
;
834 state
->null_surface_state
= next_state
;
835 next_state
.offset
+= ss_stride
;
836 next_state
.map
+= ss_stride
;
838 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
839 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
840 state
->attachments
[i
].color
.state
= next_state
;
841 next_state
.offset
+= ss_stride
;
842 next_state
.map
+= ss_stride
;
845 if (need_input_attachment_state(&pass
->attachments
[i
])) {
846 state
->attachments
[i
].input
.state
= next_state
;
847 next_state
.offset
+= ss_stride
;
848 next_state
.map
+= ss_stride
;
851 assert(next_state
.offset
== state
->render_pass_states
.offset
+
852 state
->render_pass_states
.alloc_size
);
855 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
856 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
858 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
859 isl_extent3d(framebuffer
->width
,
861 framebuffer
->layers
));
863 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
864 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
865 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
866 VkImageAspectFlags clear_aspects
= 0;
868 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
869 /* color attachment */
870 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
871 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
874 /* depthstencil attachment */
875 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
876 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
877 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
879 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
880 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
881 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
885 state
->attachments
[i
].current_layout
= att
->initial_layout
;
886 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
888 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
890 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
891 anv_assert(iview
->vk_format
== att
->format
);
892 anv_assert(iview
->n_planes
== 1);
894 union isl_color_value clear_color
= { .u32
= { 0, } };
895 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
896 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
897 color_attachment_compute_aux_usage(cmd_buffer
->device
,
898 state
, i
, begin
->renderArea
,
901 anv_image_fill_surface_state(cmd_buffer
->device
,
903 VK_IMAGE_ASPECT_COLOR_BIT
,
904 &iview
->planes
[0].isl
,
905 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
906 state
->attachments
[i
].aux_usage
,
909 &state
->attachments
[i
].color
,
912 add_image_view_relocs(cmd_buffer
, iview
, 0,
913 state
->attachments
[i
].color
);
915 /* This field will be initialized after the first subpass
918 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
920 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
923 if (need_input_attachment_state(&pass
->attachments
[i
])) {
924 anv_image_fill_surface_state(cmd_buffer
->device
,
926 VK_IMAGE_ASPECT_COLOR_BIT
,
927 &iview
->planes
[0].isl
,
928 ISL_SURF_USAGE_TEXTURE_BIT
,
929 state
->attachments
[i
].input_aux_usage
,
932 &state
->attachments
[i
].input
,
935 add_image_view_relocs(cmd_buffer
, iview
, 0,
936 state
->attachments
[i
].input
);
945 genX(BeginCommandBuffer
)(
946 VkCommandBuffer commandBuffer
,
947 const VkCommandBufferBeginInfo
* pBeginInfo
)
949 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
951 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
952 * command buffer's state. Otherwise, we must *reset* its state. In both
955 * From the Vulkan 1.0 spec:
957 * If a command buffer is in the executable state and the command buffer
958 * was allocated from a command pool with the
959 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
960 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
961 * as if vkResetCommandBuffer had been called with
962 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
963 * the command buffer in the recording state.
965 anv_cmd_buffer_reset(cmd_buffer
);
967 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
969 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
970 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
972 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
974 /* We sometimes store vertex data in the dynamic state buffer for blorp
975 * operations and our dynamic state stream may re-use data from previous
976 * command buffers. In order to prevent stale cache data, we flush the VF
977 * cache. We could do this on every blorp call but that's not really
978 * needed as all of the data will get written by the CPU prior to the GPU
979 * executing anything. The chances are fairly high that they will use
980 * blorp at least once per primary command buffer so it shouldn't be
983 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
984 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
986 /* We send an "Indirect State Pointers Disable" packet at
987 * EndCommandBuffer, so all push contant packets are ignored during a
988 * context restore. Documentation says after that command, we need to
989 * emit push constants again before any rendering operation. So we
990 * flag them dirty here to make sure they get emitted.
992 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
994 VkResult result
= VK_SUCCESS
;
995 if (cmd_buffer
->usage_flags
&
996 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
997 assert(pBeginInfo
->pInheritanceInfo
);
998 cmd_buffer
->state
.pass
=
999 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1000 cmd_buffer
->state
.subpass
=
1001 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1003 /* This is optional in the inheritance info. */
1004 cmd_buffer
->state
.framebuffer
=
1005 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1007 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1008 cmd_buffer
->state
.pass
, NULL
);
1010 /* Record that HiZ is enabled if we can. */
1011 if (cmd_buffer
->state
.framebuffer
) {
1012 const struct anv_image_view
* const iview
=
1013 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1016 VkImageLayout layout
=
1017 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.layout
;
1019 enum isl_aux_usage aux_usage
=
1020 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1021 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1023 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1027 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1033 /* From the PRM, Volume 2a:
1035 * "Indirect State Pointers Disable
1037 * At the completion of the post-sync operation associated with this pipe
1038 * control packet, the indirect state pointers in the hardware are
1039 * considered invalid; the indirect pointers are not saved in the context.
1040 * If any new indirect state commands are executed in the command stream
1041 * while the pipe control is pending, the new indirect state commands are
1044 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1045 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1046 * commands are only considered as Indirect State Pointers. Once ISP is
1047 * issued in a context, SW must initialize by programming push constant
1048 * commands for all the shaders (at least to zero length) before attempting
1049 * any rendering operation for the same context."
1051 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1052 * even though they point to a BO that has been already unreferenced at
1053 * the end of the previous batch buffer. This has been fine so far since
1054 * we are protected by these scratch page (every address not covered by
1055 * a BO should be pointing to the scratch page). But on CNL, it is
1056 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1059 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1060 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1061 * context restore, so the mentioned hang doesn't happen. However,
1062 * software must program push constant commands for all stages prior to
1063 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1066 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1068 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1069 pc
.IndirectStatePointersDisable
= true;
1070 pc
.CommandStreamerStallEnable
= true;
1075 genX(EndCommandBuffer
)(
1076 VkCommandBuffer commandBuffer
)
1078 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1080 if (anv_batch_has_error(&cmd_buffer
->batch
))
1081 return cmd_buffer
->batch
.status
;
1083 /* We want every command buffer to start with the PMA fix in a known state,
1084 * so we disable it at the end of the command buffer.
1086 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1088 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1090 emit_isp_disable(cmd_buffer
);
1092 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1098 genX(CmdExecuteCommands
)(
1099 VkCommandBuffer commandBuffer
,
1100 uint32_t commandBufferCount
,
1101 const VkCommandBuffer
* pCmdBuffers
)
1103 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1105 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1107 if (anv_batch_has_error(&primary
->batch
))
1110 /* The secondary command buffers will assume that the PMA fix is disabled
1111 * when they begin executing. Make sure this is true.
1113 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1115 /* The secondary command buffer doesn't know which textures etc. have been
1116 * flushed prior to their execution. Apply those flushes now.
1118 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1120 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1121 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1123 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1124 assert(!anv_batch_has_error(&secondary
->batch
));
1126 if (secondary
->usage_flags
&
1127 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1128 /* If we're continuing a render pass from the primary, we need to
1129 * copy the surface states for the current subpass into the storage
1130 * we allocated for them in BeginCommandBuffer.
1132 struct anv_bo
*ss_bo
=
1133 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1134 struct anv_state src_state
= primary
->state
.render_pass_states
;
1135 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1136 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1138 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1139 ss_bo
, src_state
.offset
,
1140 src_state
.alloc_size
);
1143 anv_cmd_buffer_add_secondary(primary
, secondary
);
1146 /* The secondary may have selected a different pipeline (3D or compute) and
1147 * may have changed the current L3$ configuration. Reset our tracking
1148 * variables to invalid values to ensure that we re-emit these in the case
1149 * where we do any draws or compute dispatches from the primary after the
1150 * secondary has returned.
1152 primary
->state
.current_pipeline
= UINT32_MAX
;
1153 primary
->state
.current_l3_config
= NULL
;
1155 /* Each of the secondary command buffers will use its own state base
1156 * address. We need to re-emit state base address for the primary after
1157 * all of the secondaries are done.
1159 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1162 genX(cmd_buffer_emit_state_base_address
)(primary
);
1165 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1166 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1167 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1170 * Program the hardware to use the specified L3 configuration.
1173 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1174 const struct gen_l3_config
*cfg
)
1177 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1180 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1181 intel_logd("L3 config transition: ");
1182 gen_dump_l3_config(cfg
, stderr
);
1185 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1187 /* According to the hardware docs, the L3 partitioning can only be changed
1188 * while the pipeline is completely drained and the caches are flushed,
1189 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1191 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1192 pc
.DCFlushEnable
= true;
1193 pc
.PostSyncOperation
= NoWrite
;
1194 pc
.CommandStreamerStallEnable
= true;
1197 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1198 * invalidation of the relevant caches. Note that because RO invalidation
1199 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1200 * command is processed by the CS) we cannot combine it with the previous
1201 * stalling flush as the hardware documentation suggests, because that
1202 * would cause the CS to stall on previous rendering *after* RO
1203 * invalidation and wouldn't prevent the RO caches from being polluted by
1204 * concurrent rendering before the stall completes. This intentionally
1205 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1206 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1207 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1208 * already guarantee that there is no concurrent GPGPU kernel execution
1209 * (see SKL HSD 2132585).
1211 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1212 pc
.TextureCacheInvalidationEnable
= true;
1213 pc
.ConstantCacheInvalidationEnable
= true;
1214 pc
.InstructionCacheInvalidateEnable
= true;
1215 pc
.StateCacheInvalidationEnable
= true;
1216 pc
.PostSyncOperation
= NoWrite
;
1219 /* Now send a third stalling flush to make sure that invalidation is
1220 * complete when the L3 configuration registers are modified.
1222 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1223 pc
.DCFlushEnable
= true;
1224 pc
.PostSyncOperation
= NoWrite
;
1225 pc
.CommandStreamerStallEnable
= true;
1230 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1233 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1234 .SLMEnable
= has_slm
,
1235 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1236 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1237 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1238 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1240 /* Set up the L3 partitioning. */
1241 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1245 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1246 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1247 cfg
->n
[GEN_L3P_ALL
];
1248 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1249 cfg
->n
[GEN_L3P_ALL
];
1250 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1251 cfg
->n
[GEN_L3P_ALL
];
1253 assert(!cfg
->n
[GEN_L3P_ALL
]);
1255 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1256 * the matching space on the remaining banks has to be allocated to a
1257 * client (URB for all validated configurations) set to the
1258 * lower-bandwidth 2-bank address hashing mode.
1260 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1261 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1262 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1264 /* Minimum number of ways that can be allocated to the URB. */
1265 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1266 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1268 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1269 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1270 .ConvertDC_UC
= !has_dc
,
1271 .ConvertIS_UC
= !has_is
,
1272 .ConvertC_UC
= !has_c
,
1273 .ConvertT_UC
= !has_t
);
1275 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1276 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1277 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1279 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1280 .SLMEnable
= has_slm
,
1281 .URBLowBandwidth
= urb_low_bw
,
1282 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1284 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1286 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1287 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1289 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1290 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1291 .ISLowBandwidth
= 0,
1292 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1294 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1295 .TLowBandwidth
= 0);
1297 /* Set up the L3 partitioning. */
1298 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1299 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1300 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1303 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1304 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1305 * them disabled to avoid crashing the system hard.
1307 uint32_t scratch1
, chicken3
;
1308 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1309 .L3AtomicDisable
= !has_dc
);
1310 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1311 .L3AtomicDisableMask
= true,
1312 .L3AtomicDisable
= !has_dc
);
1313 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1314 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1320 cmd_buffer
->state
.current_l3_config
= cfg
;
1324 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1326 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1328 /* Flushes are pipelined while invalidations are handled immediately.
1329 * Therefore, if we're flushing anything then we need to schedule a stall
1330 * before any invalidations can happen.
1332 if (bits
& ANV_PIPE_FLUSH_BITS
)
1333 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1335 /* If we're going to do an invalidate and we have a pending CS stall that
1336 * has yet to be resolved, we do the CS stall now.
1338 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1339 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1340 bits
|= ANV_PIPE_CS_STALL_BIT
;
1341 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1344 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1345 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1346 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1347 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1348 pipe
.RenderTargetCacheFlushEnable
=
1349 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1351 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1352 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1353 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1356 * According to the Broadwell documentation, any PIPE_CONTROL with the
1357 * "Command Streamer Stall" bit set must also have another bit set,
1358 * with five different options:
1360 * - Render Target Cache Flush
1361 * - Depth Cache Flush
1362 * - Stall at Pixel Scoreboard
1363 * - Post-Sync Operation
1367 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1368 * mesa and it seems to work fine. The choice is fairly arbitrary.
1370 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1371 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1372 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1373 pipe
.StallAtPixelScoreboard
= true;
1376 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1379 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1380 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1381 pipe
.StateCacheInvalidationEnable
=
1382 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1383 pipe
.ConstantCacheInvalidationEnable
=
1384 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1385 pipe
.VFCacheInvalidationEnable
=
1386 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1387 pipe
.TextureCacheInvalidationEnable
=
1388 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1389 pipe
.InstructionCacheInvalidateEnable
=
1390 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1393 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1396 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1399 void genX(CmdPipelineBarrier
)(
1400 VkCommandBuffer commandBuffer
,
1401 VkPipelineStageFlags srcStageMask
,
1402 VkPipelineStageFlags destStageMask
,
1404 uint32_t memoryBarrierCount
,
1405 const VkMemoryBarrier
* pMemoryBarriers
,
1406 uint32_t bufferMemoryBarrierCount
,
1407 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1408 uint32_t imageMemoryBarrierCount
,
1409 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1411 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1413 /* XXX: Right now, we're really dumb and just flush whatever categories
1414 * the app asks for. One of these days we may make this a bit better
1415 * but right now that's all the hardware allows for in most areas.
1417 VkAccessFlags src_flags
= 0;
1418 VkAccessFlags dst_flags
= 0;
1420 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1421 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1422 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1425 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1426 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1427 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1430 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1431 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1432 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1433 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1434 const VkImageSubresourceRange
*range
=
1435 &pImageMemoryBarriers
[i
].subresourceRange
;
1437 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1438 transition_depth_buffer(cmd_buffer
, image
,
1439 pImageMemoryBarriers
[i
].oldLayout
,
1440 pImageMemoryBarriers
[i
].newLayout
);
1441 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1442 VkImageAspectFlags color_aspects
=
1443 anv_image_expand_aspects(image
, range
->aspectMask
);
1444 uint32_t aspect_bit
;
1446 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1447 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1448 range
->baseMipLevel
,
1449 anv_get_levelCount(image
, range
),
1450 range
->baseArrayLayer
,
1451 anv_get_layerCount(image
, range
),
1452 pImageMemoryBarriers
[i
].oldLayout
,
1453 pImageMemoryBarriers
[i
].newLayout
);
1458 cmd_buffer
->state
.pending_pipe_bits
|=
1459 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1460 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1464 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1466 VkShaderStageFlags stages
=
1467 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1469 /* In order to avoid thrash, we assume that vertex and fragment stages
1470 * always exist. In the rare case where one is missing *and* the other
1471 * uses push concstants, this may be suboptimal. However, avoiding stalls
1472 * seems more important.
1474 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1476 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1480 const unsigned push_constant_kb
= 32;
1481 #elif GEN_IS_HASWELL
1482 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1484 const unsigned push_constant_kb
= 16;
1487 const unsigned num_stages
=
1488 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1489 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1491 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1492 * units of 2KB. Incidentally, these are the same platforms that have
1493 * 32KB worth of push constant space.
1495 if (push_constant_kb
== 32)
1496 size_per_stage
&= ~1u;
1498 uint32_t kb_used
= 0;
1499 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1500 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1501 anv_batch_emit(&cmd_buffer
->batch
,
1502 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1503 alloc
._3DCommandSubOpcode
= 18 + i
;
1504 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1505 alloc
.ConstantBufferSize
= push_size
;
1507 kb_used
+= push_size
;
1510 anv_batch_emit(&cmd_buffer
->batch
,
1511 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1512 alloc
.ConstantBufferOffset
= kb_used
;
1513 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1516 cmd_buffer
->state
.push_constant_stages
= stages
;
1518 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1520 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1521 * the next 3DPRIMITIVE command after programming the
1522 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1524 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1525 * pipeline setup, we need to dirty push constants.
1527 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1530 static const struct anv_descriptor
*
1531 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1532 const struct anv_pipeline_binding
*binding
)
1534 assert(binding
->set
< MAX_SETS
);
1535 const struct anv_descriptor_set
*set
=
1536 pipe_state
->descriptors
[binding
->set
];
1537 const uint32_t offset
=
1538 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1539 return &set
->descriptors
[offset
+ binding
->index
];
1543 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1544 const struct anv_pipeline_binding
*binding
)
1546 assert(binding
->set
< MAX_SETS
);
1547 const struct anv_descriptor_set
*set
=
1548 pipe_state
->descriptors
[binding
->set
];
1550 uint32_t dynamic_offset_idx
=
1551 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1552 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1555 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1559 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1560 gl_shader_stage stage
,
1561 struct anv_state
*bt_state
)
1563 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1564 struct anv_cmd_pipeline_state
*pipe_state
;
1565 struct anv_pipeline
*pipeline
;
1566 uint32_t bias
, state_offset
;
1569 case MESA_SHADER_COMPUTE
:
1570 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1574 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1578 pipeline
= pipe_state
->pipeline
;
1580 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1581 *bt_state
= (struct anv_state
) { 0, };
1585 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1586 if (bias
+ map
->surface_count
== 0) {
1587 *bt_state
= (struct anv_state
) { 0, };
1591 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1592 bias
+ map
->surface_count
,
1594 uint32_t *bt_map
= bt_state
->map
;
1596 if (bt_state
->map
== NULL
)
1597 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1599 if (stage
== MESA_SHADER_COMPUTE
&&
1600 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1601 struct anv_bo
*bo
= cmd_buffer
->state
.compute
.num_workgroups
.bo
;
1602 uint32_t bo_offset
= cmd_buffer
->state
.compute
.num_workgroups
.offset
;
1604 struct anv_state surface_state
;
1606 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1608 const enum isl_format format
=
1609 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1610 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1611 format
, bo_offset
, 12, 1);
1613 bt_map
[0] = surface_state
.offset
+ state_offset
;
1614 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1617 if (map
->surface_count
== 0)
1620 if (map
->image_count
> 0) {
1622 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1623 if (result
!= VK_SUCCESS
)
1626 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1630 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1631 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1633 struct anv_state surface_state
;
1635 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1636 /* Color attachment binding */
1637 assert(stage
== MESA_SHADER_FRAGMENT
);
1638 assert(binding
->binding
== 0);
1639 if (binding
->index
< subpass
->color_count
) {
1640 const unsigned att
=
1641 subpass
->color_attachments
[binding
->index
].attachment
;
1643 /* From the Vulkan 1.0.46 spec:
1645 * "If any color or depth/stencil attachments are
1646 * VK_ATTACHMENT_UNUSED, then no writes occur for those
1649 if (att
== VK_ATTACHMENT_UNUSED
) {
1650 surface_state
= cmd_buffer
->state
.null_surface_state
;
1652 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
1655 surface_state
= cmd_buffer
->state
.null_surface_state
;
1658 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1662 const struct anv_descriptor
*desc
=
1663 anv_descriptor_for_binding(pipe_state
, binding
);
1665 switch (desc
->type
) {
1666 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1667 /* Nothing for us to do here */
1670 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1671 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
1672 struct anv_surface_state sstate
=
1673 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
1674 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
1675 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
1676 surface_state
= sstate
.state
;
1677 assert(surface_state
.alloc_size
);
1678 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1679 binding
->plane
, sstate
);
1682 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1683 assert(stage
== MESA_SHADER_FRAGMENT
);
1684 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
1685 /* For depth and stencil input attachments, we treat it like any
1686 * old texture that a user may have bound.
1688 struct anv_surface_state sstate
=
1689 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
1690 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
1691 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
1692 surface_state
= sstate
.state
;
1693 assert(surface_state
.alloc_size
);
1694 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1695 binding
->plane
, sstate
);
1697 /* For color input attachments, we create the surface state at
1698 * vkBeginRenderPass time so that we can include aux and clear
1699 * color information.
1701 assert(binding
->input_attachment_index
< subpass
->input_count
);
1702 const unsigned subpass_att
= binding
->input_attachment_index
;
1703 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1704 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
1708 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1709 struct anv_surface_state sstate
= (binding
->write_only
)
1710 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
1711 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
1712 surface_state
= sstate
.state
;
1713 assert(surface_state
.alloc_size
);
1714 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1715 binding
->plane
, sstate
);
1717 struct brw_image_param
*image_param
=
1718 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1720 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
1721 image_param
->surface_idx
= bias
+ s
;
1725 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1726 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1727 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1728 surface_state
= desc
->buffer_view
->surface_state
;
1729 assert(surface_state
.alloc_size
);
1730 add_surface_state_reloc(cmd_buffer
, surface_state
,
1731 desc
->buffer_view
->bo
,
1732 desc
->buffer_view
->offset
);
1735 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1736 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
1737 /* Compute the offset within the buffer */
1738 uint32_t dynamic_offset
=
1739 dynamic_offset_for_binding(pipe_state
, binding
);
1740 uint64_t offset
= desc
->offset
+ dynamic_offset
;
1741 /* Clamp to the buffer size */
1742 offset
= MIN2(offset
, desc
->buffer
->size
);
1743 /* Clamp the range to the buffer size */
1744 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
1747 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
1748 enum isl_format format
=
1749 anv_isl_format_for_descriptor_type(desc
->type
);
1751 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1752 format
, offset
, range
, 1);
1753 add_surface_state_reloc(cmd_buffer
, surface_state
,
1755 desc
->buffer
->offset
+ offset
);
1759 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1760 surface_state
= (binding
->write_only
)
1761 ? desc
->buffer_view
->writeonly_storage_surface_state
1762 : desc
->buffer_view
->storage_surface_state
;
1763 assert(surface_state
.alloc_size
);
1764 add_surface_state_reloc(cmd_buffer
, surface_state
,
1765 desc
->buffer_view
->bo
,
1766 desc
->buffer_view
->offset
);
1768 struct brw_image_param
*image_param
=
1769 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1771 *image_param
= desc
->buffer_view
->storage_image_param
;
1772 image_param
->surface_idx
= bias
+ s
;
1776 assert(!"Invalid descriptor type");
1780 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1782 assert(image
== map
->image_count
);
1785 anv_state_flush(cmd_buffer
->device
, *bt_state
);
1791 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1792 gl_shader_stage stage
,
1793 struct anv_state
*state
)
1795 struct anv_cmd_pipeline_state
*pipe_state
=
1796 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
1797 &cmd_buffer
->state
.gfx
.base
;
1798 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
1800 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1801 *state
= (struct anv_state
) { 0, };
1805 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1806 if (map
->sampler_count
== 0) {
1807 *state
= (struct anv_state
) { 0, };
1811 uint32_t size
= map
->sampler_count
* 16;
1812 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1814 if (state
->map
== NULL
)
1815 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1817 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1818 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1819 const struct anv_descriptor
*desc
=
1820 anv_descriptor_for_binding(pipe_state
, binding
);
1822 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1823 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1826 struct anv_sampler
*sampler
= desc
->sampler
;
1828 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1829 * happens to be zero.
1831 if (sampler
== NULL
)
1834 memcpy(state
->map
+ (s
* 16),
1835 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
1838 anv_state_flush(cmd_buffer
->device
, *state
);
1844 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1846 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
1848 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1849 pipeline
->active_stages
;
1851 VkResult result
= VK_SUCCESS
;
1852 anv_foreach_stage(s
, dirty
) {
1853 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1854 if (result
!= VK_SUCCESS
)
1856 result
= emit_binding_table(cmd_buffer
, s
,
1857 &cmd_buffer
->state
.binding_tables
[s
]);
1858 if (result
!= VK_SUCCESS
)
1862 if (result
!= VK_SUCCESS
) {
1863 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1865 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1866 if (result
!= VK_SUCCESS
)
1869 /* Re-emit state base addresses so we get the new surface state base
1870 * address before we start emitting binding tables etc.
1872 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1874 /* Re-emit all active binding tables */
1875 dirty
|= pipeline
->active_stages
;
1876 anv_foreach_stage(s
, dirty
) {
1877 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1878 if (result
!= VK_SUCCESS
) {
1879 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1882 result
= emit_binding_table(cmd_buffer
, s
,
1883 &cmd_buffer
->state
.binding_tables
[s
]);
1884 if (result
!= VK_SUCCESS
) {
1885 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1891 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1897 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1900 static const uint32_t sampler_state_opcodes
[] = {
1901 [MESA_SHADER_VERTEX
] = 43,
1902 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1903 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1904 [MESA_SHADER_GEOMETRY
] = 46,
1905 [MESA_SHADER_FRAGMENT
] = 47,
1906 [MESA_SHADER_COMPUTE
] = 0,
1909 static const uint32_t binding_table_opcodes
[] = {
1910 [MESA_SHADER_VERTEX
] = 38,
1911 [MESA_SHADER_TESS_CTRL
] = 39,
1912 [MESA_SHADER_TESS_EVAL
] = 40,
1913 [MESA_SHADER_GEOMETRY
] = 41,
1914 [MESA_SHADER_FRAGMENT
] = 42,
1915 [MESA_SHADER_COMPUTE
] = 0,
1918 anv_foreach_stage(s
, stages
) {
1919 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
1920 assert(binding_table_opcodes
[s
] > 0);
1922 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1923 anv_batch_emit(&cmd_buffer
->batch
,
1924 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1925 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1926 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1930 /* Always emit binding table pointers if we're asked to, since on SKL
1931 * this is what flushes push constants. */
1932 anv_batch_emit(&cmd_buffer
->batch
,
1933 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1934 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1935 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1941 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1942 VkShaderStageFlags dirty_stages
)
1944 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
1945 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
1947 static const uint32_t push_constant_opcodes
[] = {
1948 [MESA_SHADER_VERTEX
] = 21,
1949 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1950 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1951 [MESA_SHADER_GEOMETRY
] = 22,
1952 [MESA_SHADER_FRAGMENT
] = 23,
1953 [MESA_SHADER_COMPUTE
] = 0,
1956 VkShaderStageFlags flushed
= 0;
1958 anv_foreach_stage(stage
, dirty_stages
) {
1959 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
1960 assert(push_constant_opcodes
[stage
] > 0);
1962 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1963 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1965 if (anv_pipeline_has_stage(pipeline
, stage
)) {
1966 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1967 const struct brw_stage_prog_data
*prog_data
=
1968 pipeline
->shaders
[stage
]->prog_data
;
1969 const struct anv_pipeline_bind_map
*bind_map
=
1970 &pipeline
->shaders
[stage
]->bind_map
;
1972 /* The Skylake PRM contains the following restriction:
1974 * "The driver must ensure The following case does not occur
1975 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
1976 * buffer 3 read length equal to zero committed followed by a
1977 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
1980 * To avoid this, we program the buffers in the highest slots.
1981 * This way, slot 0 is only used if slot 3 is also used.
1985 for (int i
= 3; i
>= 0; i
--) {
1986 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
1987 if (range
->length
== 0)
1990 const unsigned surface
=
1991 prog_data
->binding_table
.ubo_start
+ range
->block
;
1993 assert(surface
<= bind_map
->surface_count
);
1994 const struct anv_pipeline_binding
*binding
=
1995 &bind_map
->surface_to_descriptor
[surface
];
1997 const struct anv_descriptor
*desc
=
1998 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2000 struct anv_address read_addr
;
2002 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2003 read_len
= MIN2(range
->length
,
2004 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2005 read_addr
= (struct anv_address
) {
2006 .bo
= desc
->buffer_view
->bo
,
2007 .offset
= desc
->buffer_view
->offset
+
2011 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2013 uint32_t dynamic_offset
=
2014 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2015 uint32_t buf_offset
=
2016 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2017 uint32_t buf_range
=
2018 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2020 read_len
= MIN2(range
->length
,
2021 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2022 read_addr
= (struct anv_address
) {
2023 .bo
= desc
->buffer
->bo
,
2024 .offset
= desc
->buffer
->offset
+ buf_offset
+
2030 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2031 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2036 struct anv_state state
=
2037 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2039 if (state
.alloc_size
> 0) {
2040 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2041 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2042 .offset
= state
.offset
,
2044 c
.ConstantBody
.ReadLength
[n
] =
2045 DIV_ROUND_UP(state
.alloc_size
, 32);
2048 /* For Ivy Bridge, the push constants packets have a different
2049 * rule that would require us to iterate in the other direction
2050 * and possibly mess around with dynamic state base address.
2051 * Don't bother; just emit regular push constants at n = 0.
2053 struct anv_state state
=
2054 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2056 if (state
.alloc_size
> 0) {
2057 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2058 c
.ConstantBody
.ReadLength
[0] =
2059 DIV_ROUND_UP(state
.alloc_size
, 32);
2065 flushed
|= mesa_to_vk_shader_stage(stage
);
2068 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2072 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2074 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2077 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2079 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2081 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2083 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2086 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2087 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2089 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2090 GENX(3DSTATE_VERTEX_BUFFERS
));
2092 for_each_bit(vb
, vb_emit
) {
2093 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2094 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2096 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2097 .VertexBufferIndex
= vb
,
2100 .MemoryObjectControlState
= GENX(MOCS
),
2102 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2103 /* Our implementation of VK_KHR_multiview uses instancing to draw
2104 * the different views. If the client asks for instancing, we
2105 * need to use the Instance Data Step Rate to ensure that we
2106 * repeat the client's per-instance data once for each view.
2108 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2109 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2112 .AddressModifyEnable
= true,
2113 .BufferPitch
= pipeline
->binding_stride
[vb
],
2114 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
2117 .BufferSize
= buffer
->size
- offset
2119 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
2123 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2128 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2130 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2131 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2133 /* The exact descriptor layout is pulled from the pipeline, so we need
2134 * to re-emit binding tables on every pipeline change.
2136 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2138 /* If the pipeline changed, we may need to re-allocate push constant
2141 cmd_buffer_alloc_push_constants(cmd_buffer
);
2145 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2146 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2147 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2149 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2150 * stall needs to be sent just prior to any 3DSTATE_VS,
2151 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2152 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2153 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2154 * PIPE_CONTROL needs to be sent before any combination of VS
2155 * associated 3DSTATE."
2157 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2158 pc
.DepthStallEnable
= true;
2159 pc
.PostSyncOperation
= WriteImmediateData
;
2161 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2166 /* Render targets live in the same binding table as fragment descriptors */
2167 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2168 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2170 /* We emit the binding tables and sampler tables first, then emit push
2171 * constants and then finally emit binding table and sampler table
2172 * pointers. It has to happen in this order, since emitting the binding
2173 * tables may change the push constants (in case of storage images). After
2174 * emitting push constants, on SKL+ we have to emit the corresponding
2175 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2178 if (cmd_buffer
->state
.descriptors_dirty
)
2179 dirty
= flush_descriptor_sets(cmd_buffer
);
2181 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2182 /* Because we're pushing UBOs, we have to push whenever either
2183 * descriptors or push constants is dirty.
2185 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2186 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2187 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2191 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2193 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2194 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2196 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2197 ANV_CMD_DIRTY_PIPELINE
)) {
2198 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2199 pipeline
->depth_clamp_enable
);
2202 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2203 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2205 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2207 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2211 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2212 struct anv_bo
*bo
, uint32_t offset
,
2213 uint32_t size
, uint32_t index
)
2215 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2216 GENX(3DSTATE_VERTEX_BUFFERS
));
2218 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2219 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2220 .VertexBufferIndex
= index
,
2221 .AddressModifyEnable
= true,
2224 .MemoryObjectControlState
= GENX(MOCS
),
2225 .BufferStartingAddress
= { bo
, offset
},
2228 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2229 .BufferStartingAddress
= { bo
, offset
},
2230 .EndAddress
= { bo
, offset
+ size
},
2236 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2237 struct anv_bo
*bo
, uint32_t offset
)
2239 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
2243 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2244 uint32_t base_vertex
, uint32_t base_instance
)
2246 struct anv_state id_state
=
2247 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2249 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2250 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2252 anv_state_flush(cmd_buffer
->device
, id_state
);
2254 emit_base_vertex_instance_bo(cmd_buffer
,
2255 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
2259 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2261 struct anv_state state
=
2262 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2264 ((uint32_t *)state
.map
)[0] = draw_index
;
2266 anv_state_flush(cmd_buffer
->device
, state
);
2268 emit_vertex_bo(cmd_buffer
,
2269 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2270 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
2274 VkCommandBuffer commandBuffer
,
2275 uint32_t vertexCount
,
2276 uint32_t instanceCount
,
2277 uint32_t firstVertex
,
2278 uint32_t firstInstance
)
2280 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2281 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2282 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2284 if (anv_batch_has_error(&cmd_buffer
->batch
))
2287 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2289 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2290 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2291 if (vs_prog_data
->uses_drawid
)
2292 emit_draw_index(cmd_buffer
, 0);
2294 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2295 * different views. We need to multiply instanceCount by the view count.
2297 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2299 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2300 prim
.VertexAccessType
= SEQUENTIAL
;
2301 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2302 prim
.VertexCountPerInstance
= vertexCount
;
2303 prim
.StartVertexLocation
= firstVertex
;
2304 prim
.InstanceCount
= instanceCount
;
2305 prim
.StartInstanceLocation
= firstInstance
;
2306 prim
.BaseVertexLocation
= 0;
2310 void genX(CmdDrawIndexed
)(
2311 VkCommandBuffer commandBuffer
,
2312 uint32_t indexCount
,
2313 uint32_t instanceCount
,
2314 uint32_t firstIndex
,
2315 int32_t vertexOffset
,
2316 uint32_t firstInstance
)
2318 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2319 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2320 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2322 if (anv_batch_has_error(&cmd_buffer
->batch
))
2325 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2327 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2328 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2329 if (vs_prog_data
->uses_drawid
)
2330 emit_draw_index(cmd_buffer
, 0);
2332 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2333 * different views. We need to multiply instanceCount by the view count.
2335 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2337 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2338 prim
.VertexAccessType
= RANDOM
;
2339 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2340 prim
.VertexCountPerInstance
= indexCount
;
2341 prim
.StartVertexLocation
= firstIndex
;
2342 prim
.InstanceCount
= instanceCount
;
2343 prim
.StartInstanceLocation
= firstInstance
;
2344 prim
.BaseVertexLocation
= vertexOffset
;
2348 /* Auto-Draw / Indirect Registers */
2349 #define GEN7_3DPRIM_END_OFFSET 0x2420
2350 #define GEN7_3DPRIM_START_VERTEX 0x2430
2351 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2352 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2353 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2354 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2356 /* MI_MATH only exists on Haswell+ */
2357 #if GEN_IS_HASWELL || GEN_GEN >= 8
2360 mi_alu(uint32_t opcode
, uint32_t op1
, uint32_t op2
)
2362 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
2363 .ALUOpcode
= opcode
,
2369 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
2374 #define CS_GPR(n) (0x2600 + (n) * 8)
2376 /* Emit dwords to multiply GPR0 by N */
2378 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2380 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2382 #define append_alu(opcode, operand1, operand2) \
2383 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2386 unsigned top_bit
= 31 - __builtin_clz(N
);
2387 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2388 /* We get our initial data in GPR0 and we write the final data out to
2389 * GPR0 but we use GPR1 as our scratch register.
2391 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2392 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2394 /* Shift the current value left by 1 */
2395 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2396 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2397 append_alu(MI_ALU_ADD
, 0, 0);
2400 /* Store ACCU to R1 and add R0 to R1 */
2401 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2402 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2403 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2404 append_alu(MI_ALU_ADD
, 0, 0);
2407 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2414 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2416 uint32_t num_dwords
;
2417 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2419 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2420 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2423 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2426 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2427 struct anv_buffer
*buffer
, uint64_t offset
,
2430 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2431 struct anv_bo
*bo
= buffer
->bo
;
2432 uint32_t bo_offset
= buffer
->offset
+ offset
;
2434 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2436 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2437 if (view_count
> 1) {
2438 #if GEN_IS_HASWELL || GEN_GEN >= 8
2439 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2440 emit_mul_gpr0(batch
, view_count
);
2441 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2443 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2444 "MI_MATH is not supported on Ivy Bridge");
2445 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2448 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2451 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2454 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2455 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2457 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2458 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2462 void genX(CmdDrawIndirect
)(
2463 VkCommandBuffer commandBuffer
,
2465 VkDeviceSize offset
,
2469 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2470 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2471 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2472 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2474 if (anv_batch_has_error(&cmd_buffer
->batch
))
2477 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2479 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2480 struct anv_bo
*bo
= buffer
->bo
;
2481 uint32_t bo_offset
= buffer
->offset
+ offset
;
2483 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2484 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2485 if (vs_prog_data
->uses_drawid
)
2486 emit_draw_index(cmd_buffer
, i
);
2488 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2490 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2491 prim
.IndirectParameterEnable
= true;
2492 prim
.VertexAccessType
= SEQUENTIAL
;
2493 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2500 void genX(CmdDrawIndexedIndirect
)(
2501 VkCommandBuffer commandBuffer
,
2503 VkDeviceSize offset
,
2507 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2508 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2509 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2510 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2512 if (anv_batch_has_error(&cmd_buffer
->batch
))
2515 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2517 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2518 struct anv_bo
*bo
= buffer
->bo
;
2519 uint32_t bo_offset
= buffer
->offset
+ offset
;
2521 /* TODO: We need to stomp base vertex to 0 somehow */
2522 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2523 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2524 if (vs_prog_data
->uses_drawid
)
2525 emit_draw_index(cmd_buffer
, i
);
2527 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2529 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2530 prim
.IndirectParameterEnable
= true;
2531 prim
.VertexAccessType
= RANDOM
;
2532 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2540 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2542 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2543 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2546 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2547 if (result
!= VK_SUCCESS
) {
2548 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2550 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2551 if (result
!= VK_SUCCESS
)
2554 /* Re-emit state base addresses so we get the new surface state base
2555 * address before we start emitting binding tables etc.
2557 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2559 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2560 if (result
!= VK_SUCCESS
) {
2561 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2566 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2567 if (result
!= VK_SUCCESS
) {
2568 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2572 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2573 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2574 .BindingTablePointer
= surfaces
.offset
,
2575 .SamplerStatePointer
= samplers
.offset
,
2577 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2579 struct anv_state state
=
2580 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2581 pipeline
->interface_descriptor_data
,
2582 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2585 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2586 anv_batch_emit(&cmd_buffer
->batch
,
2587 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2588 mid
.InterfaceDescriptorTotalLength
= size
;
2589 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2596 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2598 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2599 MAYBE_UNUSED VkResult result
;
2601 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2603 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2605 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2607 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
2608 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2610 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2611 * the only bits that are changed are scoreboard related: Scoreboard
2612 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2613 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2616 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2617 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2619 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2622 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2623 cmd_buffer
->state
.compute
.pipeline_dirty
) {
2624 /* FIXME: figure out descriptors for gen7 */
2625 result
= flush_compute_descriptor_set(cmd_buffer
);
2626 if (result
!= VK_SUCCESS
)
2629 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
2632 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
2633 struct anv_state push_state
=
2634 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
2636 if (push_state
.alloc_size
) {
2637 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
2638 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
2639 curbe
.CURBEDataStartAddress
= push_state
.offset
;
2644 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
2646 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2652 verify_cmd_parser(const struct anv_device
*device
,
2653 int required_version
,
2654 const char *function
)
2656 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
2657 return vk_errorf(device
->instance
, device
->instance
,
2658 VK_ERROR_FEATURE_NOT_PRESENT
,
2659 "cmd parser version %d is required for %s",
2660 required_version
, function
);
2668 void genX(CmdDispatch
)(
2669 VkCommandBuffer commandBuffer
,
2674 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2675 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2676 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2678 if (anv_batch_has_error(&cmd_buffer
->batch
))
2681 if (prog_data
->uses_num_work_groups
) {
2682 struct anv_state state
=
2683 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
2684 uint32_t *sizes
= state
.map
;
2688 anv_state_flush(cmd_buffer
->device
, state
);
2689 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
2690 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2691 .offset
= state
.offset
,
2695 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2697 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
2698 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2699 ggw
.ThreadDepthCounterMaximum
= 0;
2700 ggw
.ThreadHeightCounterMaximum
= 0;
2701 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2702 ggw
.ThreadGroupIDXDimension
= x
;
2703 ggw
.ThreadGroupIDYDimension
= y
;
2704 ggw
.ThreadGroupIDZDimension
= z
;
2705 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2706 ggw
.BottomExecutionMask
= 0xffffffff;
2709 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2712 #define GPGPU_DISPATCHDIMX 0x2500
2713 #define GPGPU_DISPATCHDIMY 0x2504
2714 #define GPGPU_DISPATCHDIMZ 0x2508
2716 void genX(CmdDispatchIndirect
)(
2717 VkCommandBuffer commandBuffer
,
2719 VkDeviceSize offset
)
2721 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2722 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2723 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2724 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2725 struct anv_bo
*bo
= buffer
->bo
;
2726 uint32_t bo_offset
= buffer
->offset
+ offset
;
2727 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2730 /* Linux 4.4 added command parser version 5 which allows the GPGPU
2731 * indirect dispatch registers to be written.
2733 if (verify_cmd_parser(cmd_buffer
->device
, 5,
2734 "vkCmdDispatchIndirect") != VK_SUCCESS
)
2738 if (prog_data
->uses_num_work_groups
) {
2739 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
2741 .offset
= bo_offset
,
2745 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2747 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2748 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2749 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2752 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2753 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2754 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2755 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2757 /* Load compute_dispatch_indirect_x_size into SRC0 */
2758 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2760 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2761 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2762 mip
.LoadOperation
= LOAD_LOAD
;
2763 mip
.CombineOperation
= COMBINE_SET
;
2764 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2767 /* Load compute_dispatch_indirect_y_size into SRC0 */
2768 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2770 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2771 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2772 mip
.LoadOperation
= LOAD_LOAD
;
2773 mip
.CombineOperation
= COMBINE_OR
;
2774 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2777 /* Load compute_dispatch_indirect_z_size into SRC0 */
2778 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2780 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2781 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2782 mip
.LoadOperation
= LOAD_LOAD
;
2783 mip
.CombineOperation
= COMBINE_OR
;
2784 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2787 /* predicate = !predicate; */
2788 #define COMPARE_FALSE 1
2789 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2790 mip
.LoadOperation
= LOAD_LOADINV
;
2791 mip
.CombineOperation
= COMBINE_OR
;
2792 mip
.CompareOperation
= COMPARE_FALSE
;
2796 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2797 ggw
.IndirectParameterEnable
= true;
2798 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2799 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2800 ggw
.ThreadDepthCounterMaximum
= 0;
2801 ggw
.ThreadHeightCounterMaximum
= 0;
2802 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2803 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2804 ggw
.BottomExecutionMask
= 0xffffffff;
2807 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2811 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
2814 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2816 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
2819 #if GEN_GEN >= 8 && GEN_GEN < 10
2820 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2822 * Software must clear the COLOR_CALC_STATE Valid field in
2823 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2824 * with Pipeline Select set to GPGPU.
2826 * The internal hardware docs recommend the same workaround for Gen9
2829 if (pipeline
== GPGPU
)
2830 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2833 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2834 * PIPELINE_SELECT [DevBWR+]":
2838 * Software must ensure all the write caches are flushed through a
2839 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2840 * command to invalidate read only caches prior to programming
2841 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2843 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2844 pc
.RenderTargetCacheFlushEnable
= true;
2845 pc
.DepthCacheFlushEnable
= true;
2846 pc
.DCFlushEnable
= true;
2847 pc
.PostSyncOperation
= NoWrite
;
2848 pc
.CommandStreamerStallEnable
= true;
2851 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2852 pc
.TextureCacheInvalidationEnable
= true;
2853 pc
.ConstantCacheInvalidationEnable
= true;
2854 pc
.StateCacheInvalidationEnable
= true;
2855 pc
.InstructionCacheInvalidateEnable
= true;
2856 pc
.PostSyncOperation
= NoWrite
;
2859 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2863 ps
.PipelineSelection
= pipeline
;
2867 if (devinfo
->is_geminilake
) {
2870 * "This chicken bit works around a hardware issue with barrier logic
2871 * encountered when switching between GPGPU and 3D pipelines. To
2872 * workaround the issue, this mode bit should be set after a pipeline
2876 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
2878 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
2879 : GLK_BARRIER_MODE_3D_HULL
,
2880 .GLKBarrierModeMask
= 1);
2881 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
2885 cmd_buffer
->state
.current_pipeline
= pipeline
;
2889 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2891 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
2895 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2897 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
2901 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2906 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2908 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2909 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2910 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2911 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2912 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2913 * Depth Flush Bit set, followed by another pipelined depth stall
2914 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2915 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2916 * via a preceding MI_FLUSH)."
2918 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2919 pipe
.DepthStallEnable
= true;
2921 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2922 pipe
.DepthCacheFlushEnable
= true;
2924 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2925 pipe
.DepthStallEnable
= true;
2930 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2932 struct anv_device
*device
= cmd_buffer
->device
;
2933 const struct anv_image_view
*iview
=
2934 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2935 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2937 /* FIXME: Width and Height are wrong */
2939 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2941 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
2942 device
->isl_dev
.ds
.size
/ 4);
2946 struct isl_depth_stencil_hiz_emit_info info
= {
2947 .mocs
= device
->default_mocs
,
2951 info
.view
= &iview
->planes
[0].isl
;
2953 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
2954 uint32_t depth_plane
=
2955 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
2956 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
2958 info
.depth_surf
= &surface
->isl
;
2960 info
.depth_address
=
2961 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2962 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
2963 image
->planes
[depth_plane
].bo
,
2964 image
->planes
[depth_plane
].bo_offset
+
2968 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
2969 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
2970 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
2971 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
2974 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2975 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
2976 image
->planes
[depth_plane
].bo
,
2977 image
->planes
[depth_plane
].bo_offset
+
2978 image
->planes
[depth_plane
].aux_surface
.offset
);
2980 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
2984 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2985 uint32_t stencil_plane
=
2986 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
2987 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
2989 info
.stencil_surf
= &surface
->isl
;
2991 info
.stencil_address
=
2992 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2993 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
2994 image
->planes
[stencil_plane
].bo
,
2995 image
->planes
[stencil_plane
].bo_offset
+ surface
->offset
);
2998 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3000 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3005 * @brief Perform any layout transitions required at the beginning and/or end
3006 * of the current subpass for depth buffers.
3008 * TODO: Consider preprocessing the attachment reference array at render pass
3009 * create time to determine if no layout transition is needed at the
3010 * beginning and/or end of each subpass.
3012 * @param cmd_buffer The command buffer the transition is happening within.
3013 * @param subpass_end If true, marks that the transition is happening at the
3014 * end of the subpass.
3017 cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer
* const cmd_buffer
,
3018 const bool subpass_end
)
3020 /* We need a non-NULL command buffer. */
3023 const struct anv_cmd_state
* const cmd_state
= &cmd_buffer
->state
;
3024 const struct anv_subpass
* const subpass
= cmd_state
->subpass
;
3026 /* This function must be called within a subpass. */
3029 /* If there are attachment references, the array shouldn't be NULL.
3031 if (subpass
->attachment_count
> 0)
3032 assert(subpass
->attachments
);
3034 /* Iterate over the array of attachment references. */
3035 for (const VkAttachmentReference
*att_ref
= subpass
->attachments
;
3036 att_ref
< subpass
->attachments
+ subpass
->attachment_count
; att_ref
++) {
3038 /* If the attachment is unused, we can't perform a layout transition. */
3039 if (att_ref
->attachment
== VK_ATTACHMENT_UNUSED
)
3042 /* This attachment index shouldn't go out of bounds. */
3043 assert(att_ref
->attachment
< cmd_state
->pass
->attachment_count
);
3045 const struct anv_render_pass_attachment
* const att_desc
=
3046 &cmd_state
->pass
->attachments
[att_ref
->attachment
];
3047 struct anv_attachment_state
* const att_state
=
3048 &cmd_buffer
->state
.attachments
[att_ref
->attachment
];
3050 /* The attachment should not be used in a subpass after its last. */
3051 assert(att_desc
->last_subpass_idx
>= anv_get_subpass_id(cmd_state
));
3053 if (subpass_end
&& anv_get_subpass_id(cmd_state
) <
3054 att_desc
->last_subpass_idx
) {
3055 /* We're calling this function on a buffer twice in one subpass and
3056 * this is not the last use of the buffer. The layout should not have
3057 * changed from the first call and no transition is necessary.
3059 assert(att_state
->current_layout
== att_ref
->layout
||
3060 att_state
->current_layout
==
3061 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
3065 /* The attachment index must be less than the number of attachments
3066 * within the framebuffer.
3068 assert(att_ref
->attachment
< cmd_state
->framebuffer
->attachment_count
);
3070 const struct anv_image_view
* const iview
=
3071 cmd_state
->framebuffer
->attachments
[att_ref
->attachment
];
3072 const struct anv_image
* const image
= iview
->image
;
3074 /* Get the appropriate target layout for this attachment. */
3075 VkImageLayout target_layout
;
3077 /* A resolve is necessary before use as an input attachment if the clear
3078 * color or auxiliary buffer usage isn't supported by the sampler.
3080 const bool input_needs_resolve
=
3081 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3082 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3084 target_layout
= att_desc
->final_layout
;
3085 } else if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3086 !input_needs_resolve
) {
3087 /* Layout transitions before the final only help to enable sampling as
3088 * an input attachment. If the input attachment supports sampling
3089 * using the auxiliary surface, we can skip such transitions by making
3090 * the target layout one that is CCS-aware.
3092 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3094 target_layout
= att_ref
->layout
;
3097 /* Perform the layout transition. */
3098 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3099 transition_depth_buffer(cmd_buffer
, image
,
3100 att_state
->current_layout
, target_layout
);
3101 att_state
->aux_usage
=
3102 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3103 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3104 } else if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3105 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3106 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3107 iview
->planes
[0].isl
.base_level
, 1,
3108 iview
->planes
[0].isl
.base_array_layer
,
3109 iview
->planes
[0].isl
.array_len
,
3110 att_state
->current_layout
, target_layout
);
3113 att_state
->current_layout
= target_layout
;
3117 /* Update the clear value dword(s) in surface state objects or the fast clear
3118 * state buffer entry for the color attachments used in this subpass.
3121 cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer
*cmd_buffer
)
3123 assert(cmd_buffer
&& cmd_buffer
->state
.subpass
);
3125 const struct anv_cmd_state
*state
= &cmd_buffer
->state
;
3127 /* Iterate through every color attachment used in this subpass. */
3128 for (uint32_t i
= 0; i
< state
->subpass
->color_count
; ++i
) {
3130 /* The attachment should be one of the attachments described in the
3131 * render pass and used in the subpass.
3133 const uint32_t a
= state
->subpass
->color_attachments
[i
].attachment
;
3134 if (a
== VK_ATTACHMENT_UNUSED
)
3137 assert(a
< state
->pass
->attachment_count
);
3139 /* Store some information regarding this attachment. */
3140 const struct anv_attachment_state
*att_state
= &state
->attachments
[a
];
3141 const struct anv_image_view
*iview
= state
->framebuffer
->attachments
[a
];
3142 const struct anv_render_pass_attachment
*rp_att
=
3143 &state
->pass
->attachments
[a
];
3145 if (att_state
->aux_usage
== ISL_AUX_USAGE_NONE
)
3148 /* The fast clear state entry must be updated if a fast clear is going to
3149 * happen. The surface state must be updated if the clear value from a
3150 * prior fast clear may be needed.
3152 if (att_state
->pending_clear_aspects
&& att_state
->fast_clear
) {
3153 /* Update the fast clear state entry. */
3154 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3156 VK_IMAGE_ASPECT_COLOR_BIT
,
3157 iview
->planes
[0].isl
.base_level
,
3158 true /* copy from ss */);
3160 /* Fast-clears impact whether or not a resolve will be necessary. */
3161 if (iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_CCS_E
&&
3162 att_state
->clear_color_is_zero
) {
3163 /* This image always has the auxiliary buffer enabled. We can mark
3164 * the subresource as not needing a resolve because the clear color
3165 * will match what's in every RENDER_SURFACE_STATE object when it's
3166 * being used for sampling.
3168 genX(set_image_needs_resolve
)(cmd_buffer
, iview
->image
,
3169 VK_IMAGE_ASPECT_COLOR_BIT
,
3170 iview
->planes
[0].isl
.base_level
,
3173 genX(set_image_needs_resolve
)(cmd_buffer
, iview
->image
,
3174 VK_IMAGE_ASPECT_COLOR_BIT
,
3175 iview
->planes
[0].isl
.base_level
,
3178 } else if (rp_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
3179 /* The attachment may have been fast-cleared in a previous render
3180 * pass and the value is needed now. Update the surface state(s).
3182 * TODO: Do this only once per render pass instead of every subpass.
3184 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3186 VK_IMAGE_ASPECT_COLOR_BIT
,
3187 iview
->planes
[0].isl
.base_level
,
3188 false /* copy to ss */);
3190 if (need_input_attachment_state(rp_att
) &&
3191 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3192 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3194 VK_IMAGE_ASPECT_COLOR_BIT
,
3195 iview
->planes
[0].isl
.base_level
,
3196 false /* copy to ss */);
3204 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
3205 struct anv_subpass
*subpass
)
3207 cmd_buffer
->state
.subpass
= subpass
;
3209 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3211 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3212 * different views. If the client asks for instancing, we need to use the
3213 * Instance Data Step Rate to ensure that we repeat the client's
3214 * per-instance data once for each view. Since this bit is in
3215 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3219 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3221 /* It is possible to start a render pass with an old pipeline. Because the
3222 * render pass and subpass index are both baked into the pipeline, this is
3223 * highly unlikely. In order to do so, it requires that you have a render
3224 * pass with a single subpass and that you use that render pass twice
3225 * back-to-back and use the same pipeline at the start of the second render
3226 * pass as at the end of the first. In order to avoid unpredictable issues
3227 * with this edge case, we just dirty the pipeline at the start of every
3230 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3232 /* Perform transitions to the subpass layout before any writes have
3235 cmd_buffer_subpass_transition_layouts(cmd_buffer
, false);
3237 /* Update clear values *after* performing automatic layout transitions.
3238 * This ensures that transitions from the UNDEFINED layout have had a chance
3239 * to populate the clear value buffer with the correct values for the
3240 * LOAD_OP_LOAD loadOp and that the fast-clears will update the buffer
3241 * without the aforementioned layout transition overwriting the fast-clear
3244 cmd_buffer_subpass_sync_fast_clear_values(cmd_buffer
);
3246 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3248 anv_cmd_buffer_clear_subpass(cmd_buffer
);
3251 void genX(CmdBeginRenderPass
)(
3252 VkCommandBuffer commandBuffer
,
3253 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3254 VkSubpassContents contents
)
3256 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3257 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3258 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3260 cmd_buffer
->state
.framebuffer
= framebuffer
;
3261 cmd_buffer
->state
.pass
= pass
;
3262 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3264 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3266 /* If we failed to setup the attachments we should not try to go further */
3267 if (result
!= VK_SUCCESS
) {
3268 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3272 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3274 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
3276 cmd_buffer
->state
.pending_pipe_bits
|=
3277 cmd_buffer
->state
.pass
->subpass_flushes
[0];
3280 void genX(CmdNextSubpass
)(
3281 VkCommandBuffer commandBuffer
,
3282 VkSubpassContents contents
)
3284 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3286 if (anv_batch_has_error(&cmd_buffer
->batch
))
3289 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3291 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3293 /* Perform transitions to the final layout after all writes have occurred.
3295 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
3297 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
3299 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3300 cmd_buffer
->state
.pending_pipe_bits
|=
3301 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3304 void genX(CmdEndRenderPass
)(
3305 VkCommandBuffer commandBuffer
)
3307 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3309 if (anv_batch_has_error(&cmd_buffer
->batch
))
3312 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3314 /* Perform transitions to the final layout after all writes have occurred.
3316 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
3318 cmd_buffer
->state
.pending_pipe_bits
|=
3319 cmd_buffer
->state
.pass
->subpass_flushes
[cmd_buffer
->state
.pass
->subpass_count
];
3321 cmd_buffer
->state
.hiz_enabled
= false;
3324 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3327 /* Remove references to render pass specific state. This enables us to
3328 * detect whether or not we're in a renderpass.
3330 cmd_buffer
->state
.framebuffer
= NULL
;
3331 cmd_buffer
->state
.pass
= NULL
;
3332 cmd_buffer
->state
.subpass
= NULL
;