2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
56 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
58 /* If we are emitting a new state base address we probably need to re-emit
61 cmd_buffer
->state
.descriptors_dirty
|= ~0;
63 /* Emit a render target cache flush.
65 * This isn't documented anywhere in the PRM. However, it seems to be
66 * necessary prior to changing the surface state base adress. Without
67 * this, we get GPU hangs when using multi-level command buffers which
68 * clear depth, reset state base address, and then go render stuff.
70 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
71 pc
.DCFlushEnable
= true;
72 pc
.RenderTargetCacheFlushEnable
= true;
73 pc
.CommandStreamerStallEnable
= true;
75 pc
.TileCacheFlushEnable
= true;
79 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
80 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
81 sba
.GeneralStateMOCS
= mocs
;
82 sba
.GeneralStateBaseAddressModifyEnable
= true;
84 sba
.StatelessDataPortAccessMOCS
= mocs
;
86 sba
.SurfaceStateBaseAddress
=
87 anv_cmd_buffer_surface_base_address(cmd_buffer
);
88 sba
.SurfaceStateMOCS
= mocs
;
89 sba
.SurfaceStateBaseAddressModifyEnable
= true;
91 sba
.DynamicStateBaseAddress
=
92 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
93 sba
.DynamicStateMOCS
= mocs
;
94 sba
.DynamicStateBaseAddressModifyEnable
= true;
96 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
97 sba
.IndirectObjectMOCS
= mocs
;
98 sba
.IndirectObjectBaseAddressModifyEnable
= true;
100 sba
.InstructionBaseAddress
=
101 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
102 sba
.InstructionMOCS
= mocs
;
103 sba
.InstructionBaseAddressModifyEnable
= true;
106 /* Broadwell requires that we specify a buffer size for a bunch of
107 * these fields. However, since we will be growing the BO's live, we
108 * just set them all to the maximum.
110 sba
.GeneralStateBufferSize
= 0xfffff;
111 sba
.GeneralStateBufferSizeModifyEnable
= true;
112 sba
.DynamicStateBufferSize
= 0xfffff;
113 sba
.DynamicStateBufferSizeModifyEnable
= true;
114 sba
.IndirectObjectBufferSize
= 0xfffff;
115 sba
.IndirectObjectBufferSizeModifyEnable
= true;
116 sba
.InstructionBufferSize
= 0xfffff;
117 sba
.InstructionBuffersizeModifyEnable
= true;
119 /* On gen7, we have upper bounds instead. According to the docs,
120 * setting an upper bound of zero means that no bounds checking is
121 * performed so, in theory, we should be able to leave them zero.
122 * However, border color is broken and the GPU bounds-checks anyway.
123 * To avoid this and other potential problems, we may as well set it
126 sba
.GeneralStateAccessUpperBound
=
127 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
128 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
129 sba
.DynamicStateAccessUpperBound
=
130 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
131 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
132 sba
.InstructionAccessUpperBound
=
133 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
134 sba
.InstructionAccessUpperBoundModifyEnable
= true;
137 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
138 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
139 .bo
= device
->surface_state_pool
.block_pool
.bo
,
142 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
144 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
145 sba
.BindlessSurfaceStateSize
= 0;
147 sba
.BindlessSurfaceStateMOCS
= mocs
;
148 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
151 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
152 sba
.BindlessSamplerStateMOCS
= mocs
;
153 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
154 sba
.BindlessSamplerStateBufferSize
= 0;
158 /* After re-setting the surface state base address, we have to do some
159 * cache flusing so that the sampler engine will pick up the new
160 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
161 * Shared Function > 3D Sampler > State > State Caching (page 96):
163 * Coherency with system memory in the state cache, like the texture
164 * cache is handled partially by software. It is expected that the
165 * command stream or shader will issue Cache Flush operation or
166 * Cache_Flush sampler message to ensure that the L1 cache remains
167 * coherent with system memory.
171 * Whenever the value of the Dynamic_State_Base_Addr,
172 * Surface_State_Base_Addr are altered, the L1 state cache must be
173 * invalidated to ensure the new surface or sampler state is fetched
174 * from system memory.
176 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
177 * which, according the PIPE_CONTROL instruction documentation in the
180 * Setting this bit is independent of any other bit in this packet.
181 * This bit controls the invalidation of the L1 and L2 state caches
182 * at the top of the pipe i.e. at the parsing time.
184 * Unfortunately, experimentation seems to indicate that state cache
185 * invalidation through a PIPE_CONTROL does nothing whatsoever in
186 * regards to surface state and binding tables. In stead, it seems that
187 * invalidating the texture cache is what is actually needed.
189 * XXX: As far as we have been able to determine through
190 * experimentation, shows that flush the texture cache appears to be
191 * sufficient. The theory here is that all of the sampling/rendering
192 * units cache the binding table in the texture cache. However, we have
193 * yet to be able to actually confirm this.
195 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
196 pc
.TextureCacheInvalidationEnable
= true;
197 pc
.ConstantCacheInvalidationEnable
= true;
198 pc
.StateCacheInvalidationEnable
= true;
203 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
204 struct anv_state state
, struct anv_address addr
)
206 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
209 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
210 state
.offset
+ isl_dev
->ss
.addr_offset
,
211 addr
.bo
, addr
.offset
, NULL
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
217 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
218 struct anv_surface_state state
)
220 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
222 assert(!anv_address_is_null(state
.address
));
223 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
225 if (!anv_address_is_null(state
.aux_address
)) {
227 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
228 &cmd_buffer
->pool
->alloc
,
229 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
230 state
.aux_address
.bo
,
231 state
.aux_address
.offset
,
233 if (result
!= VK_SUCCESS
)
234 anv_batch_set_error(&cmd_buffer
->batch
, result
);
237 if (!anv_address_is_null(state
.clear_address
)) {
239 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
240 &cmd_buffer
->pool
->alloc
,
242 isl_dev
->ss
.clear_color_state_offset
,
243 state
.clear_address
.bo
,
244 state
.clear_address
.offset
,
246 if (result
!= VK_SUCCESS
)
247 anv_batch_set_error(&cmd_buffer
->batch
, result
);
252 color_attachment_compute_aux_usage(struct anv_device
* device
,
253 struct anv_cmd_state
* cmd_state
,
254 uint32_t att
, VkRect2D render_area
,
255 union isl_color_value
*fast_clear_color
)
257 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
258 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
260 assert(iview
->n_planes
== 1);
262 if (iview
->planes
[0].isl
.base_array_layer
>=
263 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
264 iview
->planes
[0].isl
.base_level
)) {
265 /* There is no aux buffer which corresponds to the level and layer(s)
268 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
269 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
270 att_state
->fast_clear
= false;
274 att_state
->aux_usage
=
275 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
276 VK_IMAGE_ASPECT_COLOR_BIT
,
277 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
279 /* If we don't have aux, then we should have returned early in the layer
280 * check above. If we got here, we must have something.
282 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
284 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
285 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
286 att_state
->input_aux_usage
= att_state
->aux_usage
;
288 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
290 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
291 * setting is only allowed if Surface Format supported for Fast
292 * Clear. In addition, if the surface is bound to the sampling
293 * engine, Surface Format must be supported for Render Target
294 * Compression for surfaces bound to the sampling engine."
296 * In other words, we can only sample from a fast-cleared image if it
297 * also supports color compression.
299 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
300 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
301 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
303 /* While fast-clear resolves and partial resolves are fairly cheap in the
304 * case where you render to most of the pixels, full resolves are not
305 * because they potentially involve reading and writing the entire
306 * framebuffer. If we can't texture with CCS_E, we should leave it off and
307 * limit ourselves to fast clears.
309 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
310 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
311 anv_perf_warn(device
->instance
, iview
->image
,
312 "Not temporarily enabling CCS_E.");
315 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
319 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
320 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
322 union isl_color_value clear_color
= {};
323 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
325 att_state
->clear_color_is_zero_one
=
326 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
327 att_state
->clear_color_is_zero
=
328 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
330 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
331 /* Start by getting the fast clear type. We use the first subpass
332 * layout here because we don't want to fast-clear if the first subpass
333 * to use the attachment can't handle fast-clears.
335 enum anv_fast_clear_type fast_clear_type
=
336 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
337 VK_IMAGE_ASPECT_COLOR_BIT
,
338 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
339 switch (fast_clear_type
) {
340 case ANV_FAST_CLEAR_NONE
:
341 att_state
->fast_clear
= false;
343 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
344 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
346 case ANV_FAST_CLEAR_ANY
:
347 att_state
->fast_clear
= true;
351 /* Potentially, we could do partial fast-clears but doing so has crazy
352 * alignment restrictions. It's easier to just restrict to full size
353 * fast clears for now.
355 if (render_area
.offset
.x
!= 0 ||
356 render_area
.offset
.y
!= 0 ||
357 render_area
.extent
.width
!= iview
->extent
.width
||
358 render_area
.extent
.height
!= iview
->extent
.height
)
359 att_state
->fast_clear
= false;
361 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
362 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
363 att_state
->fast_clear
= false;
365 /* We only allow fast clears to the first slice of an image (level 0,
366 * layer 0) and only for the entire slice. This guarantees us that, at
367 * any given time, there is only one clear color on any given image at
368 * any given time. At the time of our testing (Jan 17, 2018), there
369 * were no known applications which would benefit from fast-clearing
370 * more than just the first slice.
372 if (att_state
->fast_clear
&&
373 (iview
->planes
[0].isl
.base_level
> 0 ||
374 iview
->planes
[0].isl
.base_array_layer
> 0)) {
375 anv_perf_warn(device
->instance
, iview
->image
,
376 "Rendering with multi-lod or multi-layer framebuffer "
377 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
378 "baseArrayLayer > 0. Not fast clearing.");
379 att_state
->fast_clear
= false;
380 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
381 anv_perf_warn(device
->instance
, iview
->image
,
382 "Rendering to a multi-layer framebuffer with "
383 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
386 if (att_state
->fast_clear
)
387 *fast_clear_color
= clear_color
;
389 att_state
->fast_clear
= false;
394 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
395 struct anv_cmd_state
*cmd_state
,
396 uint32_t att
, VkRect2D render_area
)
398 struct anv_render_pass_attachment
*pass_att
=
399 &cmd_state
->pass
->attachments
[att
];
400 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
401 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
403 /* These will be initialized after the first subpass transition. */
404 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
405 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
408 /* We don't do any HiZ or depth fast-clears on gen7 yet */
409 att_state
->fast_clear
= false;
413 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
414 /* If we're just clearing stencil, we can always HiZ clear */
415 att_state
->fast_clear
= true;
419 /* Default to false for now */
420 att_state
->fast_clear
= false;
422 /* We must have depth in order to have HiZ */
423 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
426 const enum isl_aux_usage first_subpass_aux_usage
=
427 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
428 VK_IMAGE_ASPECT_DEPTH_BIT
,
429 pass_att
->first_subpass_layout
);
430 if (!blorp_can_hiz_clear_depth(&device
->info
,
431 &iview
->image
->planes
[0].surface
.isl
,
432 first_subpass_aux_usage
,
433 iview
->planes
[0].isl
.base_level
,
434 iview
->planes
[0].isl
.base_array_layer
,
435 render_area
.offset
.x
,
436 render_area
.offset
.y
,
437 render_area
.offset
.x
+
438 render_area
.extent
.width
,
439 render_area
.offset
.y
+
440 render_area
.extent
.height
))
443 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
446 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
447 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
448 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
449 * only supports returning 0.0f. Gens prior to gen8 do not support this
455 /* If we got here, then we can fast clear */
456 att_state
->fast_clear
= true;
460 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
462 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
465 /* We only allocate input attachment states for color surfaces. Compression
466 * is not yet enabled for depth textures and stencil doesn't allow
467 * compression so we can just use the texture surface state from the view.
469 return vk_format_is_color(att
->format
);
472 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
473 * the initial layout is undefined, the HiZ buffer and depth buffer will
474 * represent the same data at the end of this operation.
477 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
478 const struct anv_image
*image
,
479 VkImageLayout initial_layout
,
480 VkImageLayout final_layout
)
482 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
483 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
484 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
485 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
486 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
487 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
489 enum isl_aux_op hiz_op
;
490 if (hiz_enabled
&& !enable_hiz
) {
491 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
492 } else if (!hiz_enabled
&& enable_hiz
) {
493 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
495 assert(hiz_enabled
== enable_hiz
);
496 /* If the same buffer will be used, no resolves are necessary. */
497 hiz_op
= ISL_AUX_OP_NONE
;
500 if (hiz_op
!= ISL_AUX_OP_NONE
)
501 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
506 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
508 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
509 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
510 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
513 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
514 * the initial layout is undefined, the HiZ buffer and depth buffer will
515 * represent the same data at the end of this operation.
518 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
519 const struct anv_image
*image
,
520 uint32_t base_level
, uint32_t level_count
,
521 uint32_t base_layer
, uint32_t layer_count
,
522 VkImageLayout initial_layout
,
523 VkImageLayout final_layout
)
526 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
527 VK_IMAGE_ASPECT_STENCIL_BIT
);
529 /* On gen7, we have to store a texturable version of the stencil buffer in
530 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
531 * forth at strategic points. Stencil writes are only allowed in following
534 * - VK_IMAGE_LAYOUT_GENERAL
535 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
536 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
537 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
538 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
540 * For general, we have no nice opportunity to transition so we do the copy
541 * to the shadow unconditionally at the end of the subpass. For transfer
542 * destinations, we can update it as part of the transfer op. For the other
543 * layouts, we delay the copy until a transition into some other layout.
545 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
546 vk_image_layout_stencil_write_optimal(initial_layout
) &&
547 !vk_image_layout_stencil_write_optimal(final_layout
)) {
548 anv_image_copy_to_shadow(cmd_buffer
, image
,
549 VK_IMAGE_ASPECT_STENCIL_BIT
,
550 base_level
, level_count
,
551 base_layer
, layer_count
);
553 #endif /* GEN_GEN == 7 */
556 #define MI_PREDICATE_SRC0 0x2400
557 #define MI_PREDICATE_SRC1 0x2408
558 #define MI_PREDICATE_RESULT 0x2418
561 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
562 const struct anv_image
*image
,
563 VkImageAspectFlagBits aspect
,
565 uint32_t base_layer
, uint32_t layer_count
,
568 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
570 /* We only have compression tracking for CCS_E */
571 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
574 for (uint32_t a
= 0; a
< layer_count
; a
++) {
575 uint32_t layer
= base_layer
+ a
;
576 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
577 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
580 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
586 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
587 const struct anv_image
*image
,
588 VkImageAspectFlagBits aspect
,
589 enum anv_fast_clear_type fast_clear
)
591 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
592 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
594 sdi
.ImmediateData
= fast_clear
;
597 /* Whenever we have fast-clear, we consider that slice to be compressed.
598 * This makes building predicates much easier.
600 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
601 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
604 /* This is only really practical on haswell and above because it requires
605 * MI math in order to get it correct.
607 #if GEN_GEN >= 8 || GEN_IS_HASWELL
609 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
610 const struct anv_image
*image
,
611 VkImageAspectFlagBits aspect
,
612 uint32_t level
, uint32_t array_layer
,
613 enum isl_aux_op resolve_op
,
614 enum anv_fast_clear_type fast_clear_supported
)
616 struct gen_mi_builder b
;
617 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
619 const struct gen_mi_value fast_clear_type
=
620 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
623 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
624 /* In this case, we're doing a full resolve which means we want the
625 * resolve to happen if any compression (including fast-clears) is
628 * In order to simplify the logic a bit, we make the assumption that,
629 * if the first slice has been fast-cleared, it is also marked as
630 * compressed. See also set_image_fast_clear_state.
632 const struct gen_mi_value compression_state
=
633 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
635 level
, array_layer
));
636 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
638 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
640 if (level
== 0 && array_layer
== 0) {
641 /* If the predicate is true, we want to write 0 to the fast clear type
642 * and, if it's false, leave it alone. We can do this by writing
644 * clear_type = clear_type & ~predicate;
646 struct gen_mi_value new_fast_clear_type
=
647 gen_mi_iand(&b
, fast_clear_type
,
648 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
649 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
651 } else if (level
== 0 && array_layer
== 0) {
652 /* In this case, we are doing a partial resolve to get rid of fast-clear
653 * colors. We don't care about the compression state but we do care
654 * about how much fast clear is allowed by the final layout.
656 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
657 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
659 /* We need to compute (fast_clear_supported < image->fast_clear) */
660 struct gen_mi_value pred
=
661 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
662 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
663 gen_mi_value_ref(&b
, pred
));
665 /* If the predicate is true, we want to write 0 to the fast clear type
666 * and, if it's false, leave it alone. We can do this by writing
668 * clear_type = clear_type & ~predicate;
670 struct gen_mi_value new_fast_clear_type
=
671 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
672 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
674 /* In this case, we're trying to do a partial resolve on a slice that
675 * doesn't have clear color. There's nothing to do.
677 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
681 /* Set src1 to 0 and use a != condition */
682 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
684 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
685 mip
.LoadOperation
= LOAD_LOADINV
;
686 mip
.CombineOperation
= COMBINE_SET
;
687 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
690 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
694 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
695 const struct anv_image
*image
,
696 VkImageAspectFlagBits aspect
,
697 uint32_t level
, uint32_t array_layer
,
698 enum isl_aux_op resolve_op
,
699 enum anv_fast_clear_type fast_clear_supported
)
701 struct gen_mi_builder b
;
702 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
704 struct gen_mi_value fast_clear_type_mem
=
705 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
708 /* This only works for partial resolves and only when the clear color is
709 * all or nothing. On the upside, this emits less command streamer code
710 * and works on Ivybridge and Bay Trail.
712 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
713 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
715 /* We don't support fast clears on anything other than the first slice. */
716 if (level
> 0 || array_layer
> 0)
719 /* On gen8, we don't have a concept of default clear colors because we
720 * can't sample from CCS surfaces. It's enough to just load the fast clear
721 * state into the predicate register.
723 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
724 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
725 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
727 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
728 mip
.LoadOperation
= LOAD_LOADINV
;
729 mip
.CombineOperation
= COMBINE_SET
;
730 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
733 #endif /* GEN_GEN <= 8 */
736 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
737 const struct anv_image
*image
,
738 enum isl_format format
,
739 VkImageAspectFlagBits aspect
,
740 uint32_t level
, uint32_t array_layer
,
741 enum isl_aux_op resolve_op
,
742 enum anv_fast_clear_type fast_clear_supported
)
744 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
747 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
748 aspect
, level
, array_layer
,
749 resolve_op
, fast_clear_supported
);
750 #else /* GEN_GEN <= 8 */
751 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
752 aspect
, level
, array_layer
,
753 resolve_op
, fast_clear_supported
);
756 /* CCS_D only supports full resolves and BLORP will assert on us if we try
757 * to do a partial resolve on a CCS_D surface.
759 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
760 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
761 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
763 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
764 array_layer
, 1, resolve_op
, NULL
, true);
768 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
769 const struct anv_image
*image
,
770 enum isl_format format
,
771 VkImageAspectFlagBits aspect
,
772 uint32_t array_layer
,
773 enum isl_aux_op resolve_op
,
774 enum anv_fast_clear_type fast_clear_supported
)
776 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
777 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
781 aspect
, 0, array_layer
,
782 resolve_op
, fast_clear_supported
);
784 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
785 array_layer
, 1, resolve_op
, NULL
, true);
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
792 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
793 const struct anv_image
*image
,
794 VkImageAspectFlagBits aspect
,
795 enum isl_aux_usage aux_usage
,
798 uint32_t layer_count
)
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
808 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
809 aux_usage
!= ISL_AUX_USAGE_MCS
)
812 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
813 level
, base_layer
, layer_count
, true);
817 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
818 const struct anv_image
*image
,
819 VkImageAspectFlagBits aspect
)
821 assert(cmd_buffer
&& image
);
822 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
824 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
825 ANV_FAST_CLEAR_NONE
);
827 /* Initialize the struct fields that are accessed for fast-clears so that
828 * the HW restrictions on the field values are satisfied.
830 struct anv_address addr
=
831 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
834 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
835 const unsigned num_dwords
= GEN_GEN
>= 10 ?
836 isl_dev
->ss
.clear_color_state_size
/ 4 :
837 isl_dev
->ss
.clear_value_size
/ 4;
838 for (unsigned i
= 0; i
< num_dwords
; i
++) {
839 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
841 sdi
.Address
.offset
+= i
* 4;
842 sdi
.ImmediateData
= 0;
846 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
848 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
849 /* Pre-SKL, the dword containing the clear values also contains
850 * other fields, so we need to initialize those fields to match the
851 * values that would be in a color attachment.
853 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
854 ISL_CHANNEL_SELECT_GREEN
<< 22 |
855 ISL_CHANNEL_SELECT_BLUE
<< 19 |
856 ISL_CHANNEL_SELECT_ALPHA
<< 16;
857 } else if (GEN_GEN
== 7) {
858 /* On IVB, the dword containing the clear values also contains
859 * other fields that must be zero or can be zero.
861 sdi
.ImmediateData
= 0;
867 /* Copy the fast-clear value dword(s) between a surface state object and an
868 * image's fast clear state buffer.
871 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
872 struct anv_state surface_state
,
873 const struct anv_image
*image
,
874 VkImageAspectFlagBits aspect
,
875 bool copy_from_surface_state
)
877 assert(cmd_buffer
&& image
);
878 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
880 struct anv_address ss_clear_addr
= {
881 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
882 .offset
= surface_state
.offset
+
883 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
885 const struct anv_address entry_addr
=
886 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
887 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
890 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
891 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
892 * in-flight when they are issued even if the memory touched is not
893 * currently active for rendering. The weird bit is that it is not the
894 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
895 * rendering hangs such that the next stalling command after the
896 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
898 * It is unclear exactly why this hang occurs. Both MI commands come with
899 * warnings about the 3D pipeline but that doesn't seem to fully explain
900 * it. My (Jason's) best theory is that it has something to do with the
901 * fact that we're using a GPU state register as our temporary and that
902 * something with reading/writing it is causing problems.
904 * In order to work around this issue, we emit a PIPE_CONTROL with the
905 * command streamer stall bit set.
907 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
908 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
911 struct gen_mi_builder b
;
912 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
914 if (copy_from_surface_state
) {
915 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
917 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
919 /* Updating a surface state object may require that the state cache be
920 * invalidated. From the SKL PRM, Shared Functions -> State -> State
923 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
924 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
925 * modified [...], the L1 state cache must be invalidated to ensure
926 * the new surface or sampler state is fetched from system memory.
928 * In testing, SKL doesn't actually seem to need this, but HSW does.
930 cmd_buffer
->state
.pending_pipe_bits
|=
931 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
936 * @brief Transitions a color buffer from one layout to another.
938 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
941 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
942 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
943 * this represents the maximum layers to transition at each
944 * specified miplevel.
947 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
948 const struct anv_image
*image
,
949 VkImageAspectFlagBits aspect
,
950 const uint32_t base_level
, uint32_t level_count
,
951 uint32_t base_layer
, uint32_t layer_count
,
952 VkImageLayout initial_layout
,
953 VkImageLayout final_layout
)
955 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
956 /* Validate the inputs. */
958 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
959 /* These values aren't supported for simplicity's sake. */
960 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
961 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
962 /* Ensure the subresource range is valid. */
963 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
964 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
965 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
966 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
967 assert(last_level_num
<= image
->levels
);
968 /* The spec disallows these final layouts. */
969 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
970 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
972 /* No work is necessary if the layout stays the same or if this subresource
973 * range lacks auxiliary data.
975 if (initial_layout
== final_layout
)
978 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
980 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
981 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
982 /* This surface is a linear compressed image with a tiled shadow surface
983 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
984 * we need to ensure the shadow copy is up-to-date.
986 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
987 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
988 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
989 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
991 anv_image_copy_to_shadow(cmd_buffer
, image
,
992 VK_IMAGE_ASPECT_COLOR_BIT
,
993 base_level
, level_count
,
994 base_layer
, layer_count
);
997 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1000 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
1002 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1003 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1004 /* A subresource in the undefined layout may have been aliased and
1005 * populated with any arrangement of bits. Therefore, we must initialize
1006 * the related aux buffer and clear buffer entry with desirable values.
1007 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1008 * images with VK_IMAGE_TILING_OPTIMAL.
1010 * Initialize the relevant clear buffer entries.
1012 if (base_level
== 0 && base_layer
== 0)
1013 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1015 /* Initialize the aux buffers to enable correct rendering. In order to
1016 * ensure that things such as storage images work correctly, aux buffers
1017 * need to be initialized to valid data.
1019 * Having an aux buffer with invalid data is a problem for two reasons:
1021 * 1) Having an invalid value in the buffer can confuse the hardware.
1022 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1023 * invalid and leads to the hardware doing strange things. It
1024 * doesn't hang as far as we can tell but rendering corruption can
1027 * 2) If this transition is into the GENERAL layout and we then use the
1028 * image as a storage image, then we must have the aux buffer in the
1029 * pass-through state so that, if we then go to texture from the
1030 * image, we get the results of our storage image writes and not the
1031 * fast clear color or other random data.
1033 * For CCS both of the problems above are real demonstrable issues. In
1034 * that case, the only thing we can do is to perform an ambiguate to
1035 * transition the aux surface into the pass-through state.
1037 * For MCS, (2) is never an issue because we don't support multisampled
1038 * storage images. In theory, issue (1) is a problem with MCS but we've
1039 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1040 * theory, be interpreted as something but we don't know that all bit
1041 * patterns are actually valid. For 2x and 8x, you could easily end up
1042 * with the MCS referring to an invalid plane because not all bits of
1043 * the MCS value are actually used. Even though we've never seen issues
1044 * in the wild, it's best to play it safe and initialize the MCS. We
1045 * can use a fast-clear for MCS because we only ever touch from render
1046 * and texture (no image load store).
1048 if (image
->samples
== 1) {
1049 for (uint32_t l
= 0; l
< level_count
; l
++) {
1050 const uint32_t level
= base_level
+ l
;
1052 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1053 if (base_layer
>= aux_layers
)
1054 break; /* We will only get fewer layers as level increases */
1055 uint32_t level_layer_count
=
1056 MIN2(layer_count
, aux_layers
- base_layer
);
1058 anv_image_ccs_op(cmd_buffer
, image
,
1059 image
->planes
[plane
].surface
.isl
.format
,
1060 aspect
, level
, base_layer
, level_layer_count
,
1061 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1063 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1064 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1065 level
, base_layer
, level_layer_count
,
1070 if (image
->samples
== 4 || image
->samples
== 16) {
1071 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1072 "Doing a potentially unnecessary fast-clear to "
1073 "define an MCS buffer.");
1076 assert(base_level
== 0 && level_count
== 1);
1077 anv_image_mcs_op(cmd_buffer
, image
,
1078 image
->planes
[plane
].surface
.isl
.format
,
1079 aspect
, base_layer
, layer_count
,
1080 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1085 const enum isl_aux_usage initial_aux_usage
=
1086 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1087 const enum isl_aux_usage final_aux_usage
=
1088 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1090 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1091 * We can handle transitions between CCS_D/E to and from NONE. What we
1092 * don't yet handle is switching between CCS_E and CCS_D within a given
1093 * image. Doing so in a performant way requires more detailed aux state
1094 * tracking such as what is done in i965. For now, just assume that we
1095 * only have one type of compression.
1097 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1098 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1099 initial_aux_usage
== final_aux_usage
);
1101 /* If initial aux usage is NONE, there is nothing to resolve */
1102 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1105 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1107 /* If the initial layout supports more fast clear than the final layout
1108 * then we need at least a partial resolve.
1110 const enum anv_fast_clear_type initial_fast_clear
=
1111 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1112 const enum anv_fast_clear_type final_fast_clear
=
1113 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1114 if (final_fast_clear
< initial_fast_clear
)
1115 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1117 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1118 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1119 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1121 if (resolve_op
== ISL_AUX_OP_NONE
)
1124 /* Perform a resolve to synchronize data between the main and aux buffer.
1125 * Before we begin, we must satisfy the cache flushing requirement specified
1126 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1128 * Any transition from any value in {Clear, Render, Resolve} to a
1129 * different value in {Clear, Render, Resolve} requires end of pipe
1132 * We perform a flush of the write cache before and after the clear and
1133 * resolve operations to meet this requirement.
1135 * Unlike other drawing, fast clear operations are not properly
1136 * synchronized. The first PIPE_CONTROL here likely ensures that the
1137 * contents of the previous render or clear hit the render target before we
1138 * resolve and the second likely ensures that the resolve is complete before
1139 * we do any more rendering or clearing.
1141 cmd_buffer
->state
.pending_pipe_bits
|=
1142 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1144 for (uint32_t l
= 0; l
< level_count
; l
++) {
1145 uint32_t level
= base_level
+ l
;
1147 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1148 if (base_layer
>= aux_layers
)
1149 break; /* We will only get fewer layers as level increases */
1150 uint32_t level_layer_count
=
1151 MIN2(layer_count
, aux_layers
- base_layer
);
1153 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1154 uint32_t array_layer
= base_layer
+ a
;
1155 if (image
->samples
== 1) {
1156 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1157 image
->planes
[plane
].surface
.isl
.format
,
1158 aspect
, level
, array_layer
, resolve_op
,
1161 /* We only support fast-clear on the first layer so partial
1162 * resolves should not be used on other layers as they will use
1163 * the clear color stored in memory that is only valid for layer0.
1165 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1169 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1170 image
->planes
[plane
].surface
.isl
.format
,
1171 aspect
, array_layer
, resolve_op
,
1177 cmd_buffer
->state
.pending_pipe_bits
|=
1178 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1182 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1185 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1186 struct anv_render_pass
*pass
,
1187 const VkRenderPassBeginInfo
*begin
)
1189 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1190 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1191 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1193 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1195 if (pass
->attachment_count
> 0) {
1196 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1197 pass
->attachment_count
*
1198 sizeof(state
->attachments
[0]),
1199 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1200 if (state
->attachments
== NULL
) {
1201 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1202 return anv_batch_set_error(&cmd_buffer
->batch
,
1203 VK_ERROR_OUT_OF_HOST_MEMORY
);
1206 state
->attachments
= NULL
;
1209 /* Reserve one for the NULL state. */
1210 unsigned num_states
= 1;
1211 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1212 if (vk_format_is_color(pass
->attachments
[i
].format
))
1215 if (need_input_attachment_state(&pass
->attachments
[i
]))
1219 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1220 state
->render_pass_states
=
1221 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1222 num_states
* ss_stride
, isl_dev
->ss
.align
);
1224 struct anv_state next_state
= state
->render_pass_states
;
1225 next_state
.alloc_size
= isl_dev
->ss
.size
;
1227 state
->null_surface_state
= next_state
;
1228 next_state
.offset
+= ss_stride
;
1229 next_state
.map
+= ss_stride
;
1231 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1232 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1234 if (begin
&& !begin_attachment
)
1235 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1237 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1238 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1239 state
->attachments
[i
].color
.state
= next_state
;
1240 next_state
.offset
+= ss_stride
;
1241 next_state
.map
+= ss_stride
;
1244 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1245 state
->attachments
[i
].input
.state
= next_state
;
1246 next_state
.offset
+= ss_stride
;
1247 next_state
.map
+= ss_stride
;
1250 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1251 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1252 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1253 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1254 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1255 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1258 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1259 state
->render_pass_states
.alloc_size
);
1262 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1263 isl_extent3d(framebuffer
->width
,
1264 framebuffer
->height
,
1265 framebuffer
->layers
));
1267 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1268 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1269 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1270 VkImageAspectFlags clear_aspects
= 0;
1271 VkImageAspectFlags load_aspects
= 0;
1273 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1274 /* color attachment */
1275 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1276 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1277 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1278 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1281 /* depthstencil attachment */
1282 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1283 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1284 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1285 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1286 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1289 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1290 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1291 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1292 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1293 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1298 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1299 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1300 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1301 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1303 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1305 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1306 anv_assert(iview
->vk_format
== att
->format
);
1308 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1309 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1311 union isl_color_value clear_color
= { .u32
= { 0, } };
1312 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1313 anv_assert(iview
->n_planes
== 1);
1314 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1315 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1316 state
, i
, begin
->renderArea
,
1319 anv_image_fill_surface_state(cmd_buffer
->device
,
1321 VK_IMAGE_ASPECT_COLOR_BIT
,
1322 &iview
->planes
[0].isl
,
1323 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1324 state
->attachments
[i
].aux_usage
,
1327 &state
->attachments
[i
].color
,
1330 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1332 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1337 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1338 anv_image_fill_surface_state(cmd_buffer
->device
,
1340 VK_IMAGE_ASPECT_COLOR_BIT
,
1341 &iview
->planes
[0].isl
,
1342 ISL_SURF_USAGE_TEXTURE_BIT
,
1343 state
->attachments
[i
].input_aux_usage
,
1346 &state
->attachments
[i
].input
,
1349 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1358 genX(BeginCommandBuffer
)(
1359 VkCommandBuffer commandBuffer
,
1360 const VkCommandBufferBeginInfo
* pBeginInfo
)
1362 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1364 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1365 * command buffer's state. Otherwise, we must *reset* its state. In both
1366 * cases we reset it.
1368 * From the Vulkan 1.0 spec:
1370 * If a command buffer is in the executable state and the command buffer
1371 * was allocated from a command pool with the
1372 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1373 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1374 * as if vkResetCommandBuffer had been called with
1375 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1376 * the command buffer in the recording state.
1378 anv_cmd_buffer_reset(cmd_buffer
);
1380 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1382 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1383 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1385 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1387 /* We sometimes store vertex data in the dynamic state buffer for blorp
1388 * operations and our dynamic state stream may re-use data from previous
1389 * command buffers. In order to prevent stale cache data, we flush the VF
1390 * cache. We could do this on every blorp call but that's not really
1391 * needed as all of the data will get written by the CPU prior to the GPU
1392 * executing anything. The chances are fairly high that they will use
1393 * blorp at least once per primary command buffer so it shouldn't be
1396 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1397 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1399 /* We send an "Indirect State Pointers Disable" packet at
1400 * EndCommandBuffer, so all push contant packets are ignored during a
1401 * context restore. Documentation says after that command, we need to
1402 * emit push constants again before any rendering operation. So we
1403 * flag them dirty here to make sure they get emitted.
1405 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1407 VkResult result
= VK_SUCCESS
;
1408 if (cmd_buffer
->usage_flags
&
1409 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1410 assert(pBeginInfo
->pInheritanceInfo
);
1411 cmd_buffer
->state
.pass
=
1412 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1413 cmd_buffer
->state
.subpass
=
1414 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1416 /* This is optional in the inheritance info. */
1417 cmd_buffer
->state
.framebuffer
=
1418 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1420 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1421 cmd_buffer
->state
.pass
, NULL
);
1423 /* Record that HiZ is enabled if we can. */
1424 if (cmd_buffer
->state
.framebuffer
) {
1425 const struct anv_image_view
* const iview
=
1426 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1429 VkImageLayout layout
=
1430 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1432 enum isl_aux_usage aux_usage
=
1433 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1434 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1436 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1440 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1443 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1444 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1445 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1446 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1448 /* If secondary buffer supports conditional rendering
1449 * we should emit commands as if conditional rendering is enabled.
1451 cmd_buffer
->state
.conditional_render_enabled
=
1452 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1459 /* From the PRM, Volume 2a:
1461 * "Indirect State Pointers Disable
1463 * At the completion of the post-sync operation associated with this pipe
1464 * control packet, the indirect state pointers in the hardware are
1465 * considered invalid; the indirect pointers are not saved in the context.
1466 * If any new indirect state commands are executed in the command stream
1467 * while the pipe control is pending, the new indirect state commands are
1470 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1471 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1472 * commands are only considered as Indirect State Pointers. Once ISP is
1473 * issued in a context, SW must initialize by programming push constant
1474 * commands for all the shaders (at least to zero length) before attempting
1475 * any rendering operation for the same context."
1477 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1478 * even though they point to a BO that has been already unreferenced at
1479 * the end of the previous batch buffer. This has been fine so far since
1480 * we are protected by these scratch page (every address not covered by
1481 * a BO should be pointing to the scratch page). But on CNL, it is
1482 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1485 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1486 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1487 * context restore, so the mentioned hang doesn't happen. However,
1488 * software must program push constant commands for all stages prior to
1489 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1491 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1492 * constants have been loaded into the EUs prior to disable the push constants
1493 * so that it doesn't hang a previous 3DPRIMITIVE.
1496 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1498 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1499 pc
.StallAtPixelScoreboard
= true;
1500 pc
.CommandStreamerStallEnable
= true;
1502 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1503 pc
.IndirectStatePointersDisable
= true;
1504 pc
.CommandStreamerStallEnable
= true;
1509 genX(EndCommandBuffer
)(
1510 VkCommandBuffer commandBuffer
)
1512 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1514 if (anv_batch_has_error(&cmd_buffer
->batch
))
1515 return cmd_buffer
->batch
.status
;
1517 /* We want every command buffer to start with the PMA fix in a known state,
1518 * so we disable it at the end of the command buffer.
1520 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1522 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1524 emit_isp_disable(cmd_buffer
);
1526 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1532 genX(CmdExecuteCommands
)(
1533 VkCommandBuffer commandBuffer
,
1534 uint32_t commandBufferCount
,
1535 const VkCommandBuffer
* pCmdBuffers
)
1537 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1539 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1541 if (anv_batch_has_error(&primary
->batch
))
1544 /* The secondary command buffers will assume that the PMA fix is disabled
1545 * when they begin executing. Make sure this is true.
1547 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1549 /* The secondary command buffer doesn't know which textures etc. have been
1550 * flushed prior to their execution. Apply those flushes now.
1552 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1554 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1555 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1557 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1558 assert(!anv_batch_has_error(&secondary
->batch
));
1560 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1561 if (secondary
->state
.conditional_render_enabled
) {
1562 if (!primary
->state
.conditional_render_enabled
) {
1563 /* Secondary buffer is constructed as if it will be executed
1564 * with conditional rendering, we should satisfy this dependency
1565 * regardless of conditional rendering being enabled in primary.
1567 struct gen_mi_builder b
;
1568 gen_mi_builder_init(&b
, &primary
->batch
);
1569 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1570 gen_mi_imm(UINT64_MAX
));
1575 if (secondary
->usage_flags
&
1576 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1577 /* If we're continuing a render pass from the primary, we need to
1578 * copy the surface states for the current subpass into the storage
1579 * we allocated for them in BeginCommandBuffer.
1581 struct anv_bo
*ss_bo
=
1582 primary
->device
->surface_state_pool
.block_pool
.bo
;
1583 struct anv_state src_state
= primary
->state
.render_pass_states
;
1584 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1585 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1587 genX(cmd_buffer_so_memcpy
)(primary
,
1588 (struct anv_address
) {
1590 .offset
= dst_state
.offset
,
1592 (struct anv_address
) {
1594 .offset
= src_state
.offset
,
1596 src_state
.alloc_size
);
1599 anv_cmd_buffer_add_secondary(primary
, secondary
);
1602 /* The secondary may have selected a different pipeline (3D or compute) and
1603 * may have changed the current L3$ configuration. Reset our tracking
1604 * variables to invalid values to ensure that we re-emit these in the case
1605 * where we do any draws or compute dispatches from the primary after the
1606 * secondary has returned.
1608 primary
->state
.current_pipeline
= UINT32_MAX
;
1609 primary
->state
.current_l3_config
= NULL
;
1610 primary
->state
.current_hash_scale
= 0;
1612 /* Each of the secondary command buffers will use its own state base
1613 * address. We need to re-emit state base address for the primary after
1614 * all of the secondaries are done.
1616 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1619 genX(cmd_buffer_emit_state_base_address
)(primary
);
1622 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1623 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1624 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1627 * Program the hardware to use the specified L3 configuration.
1630 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1631 const struct gen_l3_config
*cfg
)
1634 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1637 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1638 intel_logd("L3 config transition: ");
1639 gen_dump_l3_config(cfg
, stderr
);
1642 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1644 /* According to the hardware docs, the L3 partitioning can only be changed
1645 * while the pipeline is completely drained and the caches are flushed,
1646 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1648 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1649 pc
.DCFlushEnable
= true;
1650 pc
.PostSyncOperation
= NoWrite
;
1651 pc
.CommandStreamerStallEnable
= true;
1654 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1655 * invalidation of the relevant caches. Note that because RO invalidation
1656 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1657 * command is processed by the CS) we cannot combine it with the previous
1658 * stalling flush as the hardware documentation suggests, because that
1659 * would cause the CS to stall on previous rendering *after* RO
1660 * invalidation and wouldn't prevent the RO caches from being polluted by
1661 * concurrent rendering before the stall completes. This intentionally
1662 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1663 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1664 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1665 * already guarantee that there is no concurrent GPGPU kernel execution
1666 * (see SKL HSD 2132585).
1668 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1669 pc
.TextureCacheInvalidationEnable
= true;
1670 pc
.ConstantCacheInvalidationEnable
= true;
1671 pc
.InstructionCacheInvalidateEnable
= true;
1672 pc
.StateCacheInvalidationEnable
= true;
1673 pc
.PostSyncOperation
= NoWrite
;
1676 /* Now send a third stalling flush to make sure that invalidation is
1677 * complete when the L3 configuration registers are modified.
1679 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1680 pc
.DCFlushEnable
= true;
1681 pc
.PostSyncOperation
= NoWrite
;
1682 pc
.CommandStreamerStallEnable
= true;
1687 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1690 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1691 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1693 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1694 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1698 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1700 .SLMEnable
= has_slm
,
1703 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1704 * in L3CNTLREG register. The default setting of the bit is not the
1705 * desirable behavior.
1707 .ErrorDetectionBehaviorControl
= true,
1708 .UseFullWays
= true,
1710 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1711 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1712 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1713 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1715 /* Set up the L3 partitioning. */
1716 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1720 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1721 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1722 cfg
->n
[GEN_L3P_ALL
];
1723 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1724 cfg
->n
[GEN_L3P_ALL
];
1725 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1726 cfg
->n
[GEN_L3P_ALL
];
1728 assert(!cfg
->n
[GEN_L3P_ALL
]);
1730 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1731 * the matching space on the remaining banks has to be allocated to a
1732 * client (URB for all validated configurations) set to the
1733 * lower-bandwidth 2-bank address hashing mode.
1735 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1736 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1737 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1739 /* Minimum number of ways that can be allocated to the URB. */
1740 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1741 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1743 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1744 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1745 .ConvertDC_UC
= !has_dc
,
1746 .ConvertIS_UC
= !has_is
,
1747 .ConvertC_UC
= !has_c
,
1748 .ConvertT_UC
= !has_t
);
1750 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1751 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1752 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1754 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1755 .SLMEnable
= has_slm
,
1756 .URBLowBandwidth
= urb_low_bw
,
1757 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1759 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1761 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1762 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1764 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1765 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1766 .ISLowBandwidth
= 0,
1767 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1769 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1770 .TLowBandwidth
= 0);
1772 /* Set up the L3 partitioning. */
1773 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1774 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1775 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1778 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1779 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1780 * them disabled to avoid crashing the system hard.
1782 uint32_t scratch1
, chicken3
;
1783 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1784 .L3AtomicDisable
= !has_dc
);
1785 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1786 .L3AtomicDisableMask
= true,
1787 .L3AtomicDisable
= !has_dc
);
1788 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1789 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1795 cmd_buffer
->state
.current_l3_config
= cfg
;
1799 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1801 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1803 /* Flushes are pipelined while invalidations are handled immediately.
1804 * Therefore, if we're flushing anything then we need to schedule a stall
1805 * before any invalidations can happen.
1807 if (bits
& ANV_PIPE_FLUSH_BITS
)
1808 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1810 /* If we're going to do an invalidate and we have a pending CS stall that
1811 * has yet to be resolved, we do the CS stall now.
1813 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1814 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1815 bits
|= ANV_PIPE_CS_STALL_BIT
;
1816 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1819 if (GEN_GEN
>= 12 &&
1820 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
1821 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
1822 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
1825 * Unified Cache (Tile Cache Disabled):
1827 * When the Color and Depth (Z) streams are enabled to be cached in
1828 * the DC space of L2, Software must use "Render Target Cache Flush
1829 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
1830 * Flush" for getting the color and depth (Z) write data to be
1831 * globally observable. In this mode of operation it is not required
1832 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
1834 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1837 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1838 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1840 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1842 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1843 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1844 pipe
.RenderTargetCacheFlushEnable
=
1845 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1847 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1848 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1849 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1852 * According to the Broadwell documentation, any PIPE_CONTROL with the
1853 * "Command Streamer Stall" bit set must also have another bit set,
1854 * with five different options:
1856 * - Render Target Cache Flush
1857 * - Depth Cache Flush
1858 * - Stall at Pixel Scoreboard
1859 * - Post-Sync Operation
1863 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1864 * mesa and it seems to work fine. The choice is fairly arbitrary.
1866 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1867 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1868 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1869 pipe
.StallAtPixelScoreboard
= true;
1872 /* If a render target flush was emitted, then we can toggle off the bit
1873 * saying that render target writes are ongoing.
1875 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1876 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1878 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1881 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1882 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1884 * "If the VF Cache Invalidation Enable is set to a 1 in a
1885 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1886 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1887 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1890 * This appears to hang Broadwell, so we restrict it to just gen9.
1892 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1893 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1895 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1896 pipe
.StateCacheInvalidationEnable
=
1897 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1898 pipe
.ConstantCacheInvalidationEnable
=
1899 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1900 pipe
.VFCacheInvalidationEnable
=
1901 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1902 pipe
.TextureCacheInvalidationEnable
=
1903 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1904 pipe
.InstructionCacheInvalidateEnable
=
1905 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1907 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1909 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1910 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1911 * “Write Timestamp”.
1913 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1914 pipe
.PostSyncOperation
= WriteImmediateData
;
1916 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
1920 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1923 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1926 void genX(CmdPipelineBarrier
)(
1927 VkCommandBuffer commandBuffer
,
1928 VkPipelineStageFlags srcStageMask
,
1929 VkPipelineStageFlags destStageMask
,
1931 uint32_t memoryBarrierCount
,
1932 const VkMemoryBarrier
* pMemoryBarriers
,
1933 uint32_t bufferMemoryBarrierCount
,
1934 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1935 uint32_t imageMemoryBarrierCount
,
1936 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1938 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1940 /* XXX: Right now, we're really dumb and just flush whatever categories
1941 * the app asks for. One of these days we may make this a bit better
1942 * but right now that's all the hardware allows for in most areas.
1944 VkAccessFlags src_flags
= 0;
1945 VkAccessFlags dst_flags
= 0;
1947 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1948 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1949 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1952 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1953 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1954 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1957 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1958 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1959 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1960 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1961 const VkImageSubresourceRange
*range
=
1962 &pImageMemoryBarriers
[i
].subresourceRange
;
1964 uint32_t base_layer
, layer_count
;
1965 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1967 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1969 base_layer
= range
->baseArrayLayer
;
1970 layer_count
= anv_get_layerCount(image
, range
);
1973 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1974 transition_depth_buffer(cmd_buffer
, image
,
1975 pImageMemoryBarriers
[i
].oldLayout
,
1976 pImageMemoryBarriers
[i
].newLayout
);
1979 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1980 transition_stencil_buffer(cmd_buffer
, image
,
1981 range
->baseMipLevel
,
1982 anv_get_levelCount(image
, range
),
1983 base_layer
, layer_count
,
1984 pImageMemoryBarriers
[i
].oldLayout
,
1985 pImageMemoryBarriers
[i
].newLayout
);
1988 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1989 VkImageAspectFlags color_aspects
=
1990 anv_image_expand_aspects(image
, range
->aspectMask
);
1991 uint32_t aspect_bit
;
1992 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1993 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1994 range
->baseMipLevel
,
1995 anv_get_levelCount(image
, range
),
1996 base_layer
, layer_count
,
1997 pImageMemoryBarriers
[i
].oldLayout
,
1998 pImageMemoryBarriers
[i
].newLayout
);
2003 cmd_buffer
->state
.pending_pipe_bits
|=
2004 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2005 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2009 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2011 VkShaderStageFlags stages
=
2012 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
2014 /* In order to avoid thrash, we assume that vertex and fragment stages
2015 * always exist. In the rare case where one is missing *and* the other
2016 * uses push concstants, this may be suboptimal. However, avoiding stalls
2017 * seems more important.
2019 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2021 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2025 const unsigned push_constant_kb
= 32;
2026 #elif GEN_IS_HASWELL
2027 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2029 const unsigned push_constant_kb
= 16;
2032 const unsigned num_stages
=
2033 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2034 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2036 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2037 * units of 2KB. Incidentally, these are the same platforms that have
2038 * 32KB worth of push constant space.
2040 if (push_constant_kb
== 32)
2041 size_per_stage
&= ~1u;
2043 uint32_t kb_used
= 0;
2044 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2045 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2046 anv_batch_emit(&cmd_buffer
->batch
,
2047 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2048 alloc
._3DCommandSubOpcode
= 18 + i
;
2049 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2050 alloc
.ConstantBufferSize
= push_size
;
2052 kb_used
+= push_size
;
2055 anv_batch_emit(&cmd_buffer
->batch
,
2056 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2057 alloc
.ConstantBufferOffset
= kb_used
;
2058 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2061 cmd_buffer
->state
.push_constant_stages
= stages
;
2063 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2065 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2066 * the next 3DPRIMITIVE command after programming the
2067 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2069 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2070 * pipeline setup, we need to dirty push constants.
2072 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2075 static const struct anv_descriptor
*
2076 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2077 const struct anv_pipeline_binding
*binding
)
2079 assert(binding
->set
< MAX_SETS
);
2080 const struct anv_descriptor_set
*set
=
2081 pipe_state
->descriptors
[binding
->set
];
2082 const uint32_t offset
=
2083 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2084 return &set
->descriptors
[offset
+ binding
->index
];
2088 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2089 const struct anv_pipeline_binding
*binding
)
2091 assert(binding
->set
< MAX_SETS
);
2092 const struct anv_descriptor_set
*set
=
2093 pipe_state
->descriptors
[binding
->set
];
2095 uint32_t dynamic_offset_idx
=
2096 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2097 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2100 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2103 static struct anv_address
2104 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2105 struct anv_descriptor_set
*set
)
2108 /* This is a normal descriptor set */
2109 return (struct anv_address
) {
2110 .bo
= set
->pool
->bo
,
2111 .offset
= set
->desc_mem
.offset
,
2114 /* This is a push descriptor set. We have to flag it as used on the GPU
2115 * so that the next time we push descriptors, we grab a new memory.
2117 struct anv_push_descriptor_set
*push_set
=
2118 (struct anv_push_descriptor_set
*)set
;
2119 push_set
->set_used_on_gpu
= true;
2121 return (struct anv_address
) {
2122 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2123 .offset
= set
->desc_mem
.offset
,
2129 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2130 gl_shader_stage stage
,
2131 struct anv_state
*bt_state
)
2133 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2134 struct anv_cmd_pipeline_state
*pipe_state
;
2135 struct anv_pipeline
*pipeline
;
2136 uint32_t state_offset
;
2139 case MESA_SHADER_COMPUTE
:
2140 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2143 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2146 pipeline
= pipe_state
->pipeline
;
2148 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2149 *bt_state
= (struct anv_state
) { 0, };
2153 struct anv_shader_bin
*bin
= pipeline
->shaders
[stage
];
2154 struct anv_pipeline_bind_map
*map
= &bin
->bind_map
;
2155 if (map
->surface_count
== 0) {
2156 *bt_state
= (struct anv_state
) { 0, };
2160 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2163 uint32_t *bt_map
= bt_state
->map
;
2165 if (bt_state
->map
== NULL
)
2166 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2168 /* We only need to emit relocs if we're not using softpin. If we are using
2169 * softpin then we always keep all user-allocated memory objects resident.
2171 const bool need_client_mem_relocs
=
2172 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2174 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2175 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2177 struct anv_state surface_state
;
2179 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2180 /* Color attachment binding */
2181 assert(stage
== MESA_SHADER_FRAGMENT
);
2182 assert(binding
->binding
== 0);
2183 if (binding
->index
< subpass
->color_count
) {
2184 const unsigned att
=
2185 subpass
->color_attachments
[binding
->index
].attachment
;
2187 /* From the Vulkan 1.0.46 spec:
2189 * "If any color or depth/stencil attachments are
2190 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2193 if (att
== VK_ATTACHMENT_UNUSED
) {
2194 surface_state
= cmd_buffer
->state
.null_surface_state
;
2196 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2199 surface_state
= cmd_buffer
->state
.null_surface_state
;
2202 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2204 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2205 struct anv_state surface_state
=
2206 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2208 struct anv_address constant_data
= {
2209 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2210 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2212 unsigned constant_data_size
=
2213 pipeline
->shaders
[stage
]->constant_data_size
;
2215 const enum isl_format format
=
2216 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2217 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2218 surface_state
, format
,
2219 constant_data
, constant_data_size
, 1);
2221 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2222 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2224 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2225 /* This is always the first binding for compute shaders */
2226 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2227 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2230 struct anv_state surface_state
=
2231 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2233 const enum isl_format format
=
2234 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2235 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2237 cmd_buffer
->state
.compute
.num_workgroups
,
2239 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2240 if (need_client_mem_relocs
) {
2241 add_surface_reloc(cmd_buffer
, surface_state
,
2242 cmd_buffer
->state
.compute
.num_workgroups
);
2245 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2246 /* This is a descriptor set buffer so the set index is actually
2247 * given by binding->binding. (Yes, that's confusing.)
2249 struct anv_descriptor_set
*set
=
2250 pipe_state
->descriptors
[binding
->binding
];
2251 assert(set
->desc_mem
.alloc_size
);
2252 assert(set
->desc_surface_state
.alloc_size
);
2253 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2254 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2255 anv_descriptor_set_address(cmd_buffer
, set
));
2259 const struct anv_descriptor
*desc
=
2260 anv_descriptor_for_binding(pipe_state
, binding
);
2262 switch (desc
->type
) {
2263 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2264 /* Nothing for us to do here */
2267 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2268 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2269 struct anv_surface_state sstate
=
2270 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2271 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2272 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2273 surface_state
= sstate
.state
;
2274 assert(surface_state
.alloc_size
);
2275 if (need_client_mem_relocs
)
2276 add_surface_state_relocs(cmd_buffer
, sstate
);
2279 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2280 assert(stage
== MESA_SHADER_FRAGMENT
);
2281 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2282 /* For depth and stencil input attachments, we treat it like any
2283 * old texture that a user may have bound.
2285 assert(desc
->image_view
->n_planes
== 1);
2286 struct anv_surface_state sstate
=
2287 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2288 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2289 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2290 surface_state
= sstate
.state
;
2291 assert(surface_state
.alloc_size
);
2292 if (need_client_mem_relocs
)
2293 add_surface_state_relocs(cmd_buffer
, sstate
);
2295 /* For color input attachments, we create the surface state at
2296 * vkBeginRenderPass time so that we can include aux and clear
2297 * color information.
2299 assert(binding
->input_attachment_index
< subpass
->input_count
);
2300 const unsigned subpass_att
= binding
->input_attachment_index
;
2301 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2302 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2306 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2307 struct anv_surface_state sstate
= (binding
->write_only
)
2308 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2309 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2310 surface_state
= sstate
.state
;
2311 assert(surface_state
.alloc_size
);
2312 if (need_client_mem_relocs
)
2313 add_surface_state_relocs(cmd_buffer
, sstate
);
2317 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2318 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2319 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2320 surface_state
= desc
->buffer_view
->surface_state
;
2321 assert(surface_state
.alloc_size
);
2322 if (need_client_mem_relocs
) {
2323 add_surface_reloc(cmd_buffer
, surface_state
,
2324 desc
->buffer_view
->address
);
2328 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2329 /* If the shader never does any UBO pulls (this is a fairly common
2330 * case) then we don't need to fill out those binding table entries.
2331 * The real cost savings here is that we don't have to build the
2332 * surface state for them which is surprisingly expensive when it's
2335 if (!bin
->prog_data
->has_ubo_pull
)
2339 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2340 /* Compute the offset within the buffer */
2341 uint32_t dynamic_offset
=
2342 dynamic_offset_for_binding(pipe_state
, binding
);
2343 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2344 /* Clamp to the buffer size */
2345 offset
= MIN2(offset
, desc
->buffer
->size
);
2346 /* Clamp the range to the buffer size */
2347 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2349 struct anv_address address
=
2350 anv_address_add(desc
->buffer
->address
, offset
);
2353 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2354 enum isl_format format
=
2355 anv_isl_format_for_descriptor_type(desc
->type
);
2357 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2358 format
, address
, range
, 1);
2359 if (need_client_mem_relocs
)
2360 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2364 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2365 surface_state
= (binding
->write_only
)
2366 ? desc
->buffer_view
->writeonly_storage_surface_state
2367 : desc
->buffer_view
->storage_surface_state
;
2368 assert(surface_state
.alloc_size
);
2369 if (need_client_mem_relocs
) {
2370 add_surface_reloc(cmd_buffer
, surface_state
,
2371 desc
->buffer_view
->address
);
2376 assert(!"Invalid descriptor type");
2380 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2387 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2388 gl_shader_stage stage
,
2389 struct anv_state
*state
)
2391 struct anv_cmd_pipeline_state
*pipe_state
=
2392 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2393 &cmd_buffer
->state
.gfx
.base
;
2394 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2396 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2397 *state
= (struct anv_state
) { 0, };
2401 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2402 if (map
->sampler_count
== 0) {
2403 *state
= (struct anv_state
) { 0, };
2407 uint32_t size
= map
->sampler_count
* 16;
2408 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2410 if (state
->map
== NULL
)
2411 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2413 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2414 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2415 const struct anv_descriptor
*desc
=
2416 anv_descriptor_for_binding(pipe_state
, binding
);
2418 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2419 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2422 struct anv_sampler
*sampler
= desc
->sampler
;
2424 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2425 * happens to be zero.
2427 if (sampler
== NULL
)
2430 memcpy(state
->map
+ (s
* 16),
2431 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2438 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2440 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2442 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2443 pipeline
->active_stages
;
2445 VkResult result
= VK_SUCCESS
;
2446 anv_foreach_stage(s
, dirty
) {
2447 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2448 if (result
!= VK_SUCCESS
)
2450 result
= emit_binding_table(cmd_buffer
, s
,
2451 &cmd_buffer
->state
.binding_tables
[s
]);
2452 if (result
!= VK_SUCCESS
)
2456 if (result
!= VK_SUCCESS
) {
2457 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2459 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2460 if (result
!= VK_SUCCESS
)
2463 /* Re-emit state base addresses so we get the new surface state base
2464 * address before we start emitting binding tables etc.
2466 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2468 /* Re-emit all active binding tables */
2469 dirty
|= pipeline
->active_stages
;
2470 anv_foreach_stage(s
, dirty
) {
2471 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2472 if (result
!= VK_SUCCESS
) {
2473 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2476 result
= emit_binding_table(cmd_buffer
, s
,
2477 &cmd_buffer
->state
.binding_tables
[s
]);
2478 if (result
!= VK_SUCCESS
) {
2479 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2485 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2491 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2494 static const uint32_t sampler_state_opcodes
[] = {
2495 [MESA_SHADER_VERTEX
] = 43,
2496 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2497 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2498 [MESA_SHADER_GEOMETRY
] = 46,
2499 [MESA_SHADER_FRAGMENT
] = 47,
2500 [MESA_SHADER_COMPUTE
] = 0,
2503 static const uint32_t binding_table_opcodes
[] = {
2504 [MESA_SHADER_VERTEX
] = 38,
2505 [MESA_SHADER_TESS_CTRL
] = 39,
2506 [MESA_SHADER_TESS_EVAL
] = 40,
2507 [MESA_SHADER_GEOMETRY
] = 41,
2508 [MESA_SHADER_FRAGMENT
] = 42,
2509 [MESA_SHADER_COMPUTE
] = 0,
2512 anv_foreach_stage(s
, stages
) {
2513 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2514 assert(binding_table_opcodes
[s
] > 0);
2516 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2517 anv_batch_emit(&cmd_buffer
->batch
,
2518 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2519 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2520 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2524 /* Always emit binding table pointers if we're asked to, since on SKL
2525 * this is what flushes push constants. */
2526 anv_batch_emit(&cmd_buffer
->batch
,
2527 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2528 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2529 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2535 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2536 VkShaderStageFlags dirty_stages
)
2538 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2539 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2541 static const uint32_t push_constant_opcodes
[] = {
2542 [MESA_SHADER_VERTEX
] = 21,
2543 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2544 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2545 [MESA_SHADER_GEOMETRY
] = 22,
2546 [MESA_SHADER_FRAGMENT
] = 23,
2547 [MESA_SHADER_COMPUTE
] = 0,
2550 VkShaderStageFlags flushed
= 0;
2552 anv_foreach_stage(stage
, dirty_stages
) {
2553 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2554 assert(push_constant_opcodes
[stage
] > 0);
2556 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2557 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2559 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2560 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2561 const struct brw_stage_prog_data
*prog_data
=
2562 pipeline
->shaders
[stage
]->prog_data
;
2563 const struct anv_pipeline_bind_map
*bind_map
=
2564 &pipeline
->shaders
[stage
]->bind_map
;
2566 /* The Skylake PRM contains the following restriction:
2568 * "The driver must ensure The following case does not occur
2569 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2570 * buffer 3 read length equal to zero committed followed by a
2571 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2574 * To avoid this, we program the buffers in the highest slots.
2575 * This way, slot 0 is only used if slot 3 is also used.
2579 for (int i
= 3; i
>= 0; i
--) {
2580 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2581 if (range
->length
== 0)
2584 const unsigned surface
=
2585 prog_data
->binding_table
.ubo_start
+ range
->block
;
2587 assert(surface
<= bind_map
->surface_count
);
2588 const struct anv_pipeline_binding
*binding
=
2589 &bind_map
->surface_to_descriptor
[surface
];
2591 struct anv_address read_addr
;
2593 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2594 struct anv_address constant_data
= {
2595 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2596 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2598 unsigned constant_data_size
=
2599 pipeline
->shaders
[stage
]->constant_data_size
;
2601 read_len
= MIN2(range
->length
,
2602 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2603 read_addr
= anv_address_add(constant_data
,
2605 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2606 /* This is a descriptor set buffer so the set index is
2607 * actually given by binding->binding. (Yes, that's
2610 struct anv_descriptor_set
*set
=
2611 gfx_state
->base
.descriptors
[binding
->binding
];
2612 struct anv_address desc_buffer_addr
=
2613 anv_descriptor_set_address(cmd_buffer
, set
);
2614 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2616 read_len
= MIN2(range
->length
,
2617 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2618 read_addr
= anv_address_add(desc_buffer_addr
,
2621 const struct anv_descriptor
*desc
=
2622 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2624 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2625 read_len
= MIN2(range
->length
,
2626 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2627 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2630 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2632 uint32_t dynamic_offset
=
2633 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2634 uint32_t buf_offset
=
2635 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2636 uint32_t buf_range
=
2637 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2639 read_len
= MIN2(range
->length
,
2640 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2641 read_addr
= anv_address_add(desc
->buffer
->address
,
2642 buf_offset
+ range
->start
* 32);
2647 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2648 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2653 struct anv_state state
=
2654 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2656 if (state
.alloc_size
> 0) {
2657 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2658 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2659 .offset
= state
.offset
,
2661 c
.ConstantBody
.ReadLength
[n
] =
2662 DIV_ROUND_UP(state
.alloc_size
, 32);
2665 /* For Ivy Bridge, the push constants packets have a different
2666 * rule that would require us to iterate in the other direction
2667 * and possibly mess around with dynamic state base address.
2668 * Don't bother; just emit regular push constants at n = 0.
2670 struct anv_state state
=
2671 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2673 if (state
.alloc_size
> 0) {
2674 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2675 c
.ConstantBody
.ReadLength
[0] =
2676 DIV_ROUND_UP(state
.alloc_size
, 32);
2682 flushed
|= mesa_to_vk_shader_stage(stage
);
2685 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2690 genX(cmd_buffer_aux_map_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2692 void *aux_map_ctx
= cmd_buffer
->device
->aux_map_ctx
;
2695 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
2696 if (cmd_buffer
->state
.last_aux_map_state
!= aux_map_state_num
) {
2697 /* If the aux-map state number increased, then we need to rewrite the
2698 * register. Rewriting the register is used to both set the aux-map
2699 * translation table address, and also to invalidate any previously
2700 * cached translations.
2702 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
2703 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2704 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
);
2705 lri
.DataDWord
= base_addr
& 0xffffffff;
2707 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2708 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
) + 4;
2709 lri
.DataDWord
= base_addr
>> 32;
2711 cmd_buffer
->state
.last_aux_map_state
= aux_map_state_num
;
2717 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2719 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2722 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2723 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2724 vb_emit
|= pipeline
->vb_used
;
2726 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2728 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2730 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
2732 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2735 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
2739 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2740 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2742 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2743 GENX(3DSTATE_VERTEX_BUFFERS
));
2745 for_each_bit(vb
, vb_emit
) {
2746 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2747 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2749 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2750 .VertexBufferIndex
= vb
,
2752 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2754 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2755 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2758 .AddressModifyEnable
= true,
2759 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2760 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2763 .BufferSize
= buffer
->size
- offset
2765 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2769 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2774 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2777 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2778 /* We don't need any per-buffer dirty tracking because you're not
2779 * allowed to bind different XFB buffers while XFB is enabled.
2781 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2782 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2783 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2785 sob
.SOBufferIndex
= idx
;
2787 sob
._3DCommandOpcode
= 0;
2788 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
2791 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2792 sob
.SOBufferEnable
= true;
2793 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
2794 sob
.StreamOffsetWriteEnable
= false;
2795 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2797 /* Size is in DWords - 1 */
2798 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2803 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2805 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2809 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2810 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2812 /* The exact descriptor layout is pulled from the pipeline, so we need
2813 * to re-emit binding tables on every pipeline change.
2815 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2817 /* If the pipeline changed, we may need to re-allocate push constant
2820 cmd_buffer_alloc_push_constants(cmd_buffer
);
2824 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2825 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2826 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2828 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2829 * stall needs to be sent just prior to any 3DSTATE_VS,
2830 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2831 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2832 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2833 * PIPE_CONTROL needs to be sent before any combination of VS
2834 * associated 3DSTATE."
2836 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2837 pc
.DepthStallEnable
= true;
2838 pc
.PostSyncOperation
= WriteImmediateData
;
2840 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2845 /* Render targets live in the same binding table as fragment descriptors */
2846 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2847 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2849 /* We emit the binding tables and sampler tables first, then emit push
2850 * constants and then finally emit binding table and sampler table
2851 * pointers. It has to happen in this order, since emitting the binding
2852 * tables may change the push constants (in case of storage images). After
2853 * emitting push constants, on SKL+ we have to emit the corresponding
2854 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2857 if (cmd_buffer
->state
.descriptors_dirty
)
2858 dirty
= flush_descriptor_sets(cmd_buffer
);
2860 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2861 /* Because we're pushing UBOs, we have to push whenever either
2862 * descriptors or push constants is dirty.
2864 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2865 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2866 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2870 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2872 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2873 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2875 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2876 ANV_CMD_DIRTY_PIPELINE
)) {
2877 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2878 pipeline
->depth_clamp_enable
);
2881 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2882 ANV_CMD_DIRTY_RENDER_TARGETS
))
2883 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2885 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2887 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2891 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2892 struct anv_address addr
,
2893 uint32_t size
, uint32_t index
)
2895 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2896 GENX(3DSTATE_VERTEX_BUFFERS
));
2898 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2899 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2900 .VertexBufferIndex
= index
,
2901 .AddressModifyEnable
= true,
2903 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2905 .BufferStartingAddress
= addr
,
2908 .BufferStartingAddress
= addr
,
2909 .EndAddress
= anv_address_add(addr
, size
),
2915 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2916 struct anv_address addr
)
2918 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2922 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2923 uint32_t base_vertex
, uint32_t base_instance
)
2925 struct anv_state id_state
=
2926 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2928 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2929 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2931 struct anv_address addr
= {
2932 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2933 .offset
= id_state
.offset
,
2936 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2940 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2942 struct anv_state state
=
2943 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2945 ((uint32_t *)state
.map
)[0] = draw_index
;
2947 struct anv_address addr
= {
2948 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2949 .offset
= state
.offset
,
2952 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2956 VkCommandBuffer commandBuffer
,
2957 uint32_t vertexCount
,
2958 uint32_t instanceCount
,
2959 uint32_t firstVertex
,
2960 uint32_t firstInstance
)
2962 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2963 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2964 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2966 if (anv_batch_has_error(&cmd_buffer
->batch
))
2969 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2971 if (cmd_buffer
->state
.conditional_render_enabled
)
2972 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2974 if (vs_prog_data
->uses_firstvertex
||
2975 vs_prog_data
->uses_baseinstance
)
2976 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2977 if (vs_prog_data
->uses_drawid
)
2978 emit_draw_index(cmd_buffer
, 0);
2980 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2981 * different views. We need to multiply instanceCount by the view count.
2983 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2985 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2986 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2987 prim
.VertexAccessType
= SEQUENTIAL
;
2988 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2989 prim
.VertexCountPerInstance
= vertexCount
;
2990 prim
.StartVertexLocation
= firstVertex
;
2991 prim
.InstanceCount
= instanceCount
;
2992 prim
.StartInstanceLocation
= firstInstance
;
2993 prim
.BaseVertexLocation
= 0;
2997 void genX(CmdDrawIndexed
)(
2998 VkCommandBuffer commandBuffer
,
2999 uint32_t indexCount
,
3000 uint32_t instanceCount
,
3001 uint32_t firstIndex
,
3002 int32_t vertexOffset
,
3003 uint32_t firstInstance
)
3005 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3006 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3007 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3009 if (anv_batch_has_error(&cmd_buffer
->batch
))
3012 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3014 if (cmd_buffer
->state
.conditional_render_enabled
)
3015 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3017 if (vs_prog_data
->uses_firstvertex
||
3018 vs_prog_data
->uses_baseinstance
)
3019 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3020 if (vs_prog_data
->uses_drawid
)
3021 emit_draw_index(cmd_buffer
, 0);
3023 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3024 * different views. We need to multiply instanceCount by the view count.
3026 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3028 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3029 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3030 prim
.VertexAccessType
= RANDOM
;
3031 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3032 prim
.VertexCountPerInstance
= indexCount
;
3033 prim
.StartVertexLocation
= firstIndex
;
3034 prim
.InstanceCount
= instanceCount
;
3035 prim
.StartInstanceLocation
= firstInstance
;
3036 prim
.BaseVertexLocation
= vertexOffset
;
3040 /* Auto-Draw / Indirect Registers */
3041 #define GEN7_3DPRIM_END_OFFSET 0x2420
3042 #define GEN7_3DPRIM_START_VERTEX 0x2430
3043 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3044 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3045 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3046 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3048 void genX(CmdDrawIndirectByteCountEXT
)(
3049 VkCommandBuffer commandBuffer
,
3050 uint32_t instanceCount
,
3051 uint32_t firstInstance
,
3052 VkBuffer counterBuffer
,
3053 VkDeviceSize counterBufferOffset
,
3054 uint32_t counterOffset
,
3055 uint32_t vertexStride
)
3057 #if GEN_IS_HASWELL || GEN_GEN >= 8
3058 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3059 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3060 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3061 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3063 /* firstVertex is always zero for this draw function */
3064 const uint32_t firstVertex
= 0;
3066 if (anv_batch_has_error(&cmd_buffer
->batch
))
3069 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3071 if (vs_prog_data
->uses_firstvertex
||
3072 vs_prog_data
->uses_baseinstance
)
3073 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3074 if (vs_prog_data
->uses_drawid
)
3075 emit_draw_index(cmd_buffer
, 0);
3077 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3078 * different views. We need to multiply instanceCount by the view count.
3080 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3082 struct gen_mi_builder b
;
3083 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3084 struct gen_mi_value count
=
3085 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3086 counterBufferOffset
));
3088 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3089 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3090 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3092 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3093 gen_mi_imm(firstVertex
));
3094 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3095 gen_mi_imm(instanceCount
));
3096 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3097 gen_mi_imm(firstInstance
));
3098 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3100 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3101 prim
.IndirectParameterEnable
= true;
3102 prim
.VertexAccessType
= SEQUENTIAL
;
3103 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3105 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3109 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3110 struct anv_address addr
,
3113 struct gen_mi_builder b
;
3114 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3116 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3117 gen_mi_mem32(anv_address_add(addr
, 0)));
3119 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3120 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3121 if (view_count
> 1) {
3122 #if GEN_IS_HASWELL || GEN_GEN >= 8
3123 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3125 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3126 "MI_MATH is not supported on Ivy Bridge");
3129 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3131 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3132 gen_mi_mem32(anv_address_add(addr
, 8)));
3135 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3136 gen_mi_mem32(anv_address_add(addr
, 12)));
3137 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3138 gen_mi_mem32(anv_address_add(addr
, 16)));
3140 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3141 gen_mi_mem32(anv_address_add(addr
, 12)));
3142 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3146 void genX(CmdDrawIndirect
)(
3147 VkCommandBuffer commandBuffer
,
3149 VkDeviceSize offset
,
3153 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3154 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3155 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3156 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3158 if (anv_batch_has_error(&cmd_buffer
->batch
))
3161 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3163 if (cmd_buffer
->state
.conditional_render_enabled
)
3164 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3166 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3167 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3169 if (vs_prog_data
->uses_firstvertex
||
3170 vs_prog_data
->uses_baseinstance
)
3171 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3172 if (vs_prog_data
->uses_drawid
)
3173 emit_draw_index(cmd_buffer
, i
);
3175 load_indirect_parameters(cmd_buffer
, draw
, false);
3177 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3178 prim
.IndirectParameterEnable
= true;
3179 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3180 prim
.VertexAccessType
= SEQUENTIAL
;
3181 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3188 void genX(CmdDrawIndexedIndirect
)(
3189 VkCommandBuffer commandBuffer
,
3191 VkDeviceSize offset
,
3195 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3196 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3197 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3198 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3200 if (anv_batch_has_error(&cmd_buffer
->batch
))
3203 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3205 if (cmd_buffer
->state
.conditional_render_enabled
)
3206 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3208 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3209 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3211 /* TODO: We need to stomp base vertex to 0 somehow */
3212 if (vs_prog_data
->uses_firstvertex
||
3213 vs_prog_data
->uses_baseinstance
)
3214 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3215 if (vs_prog_data
->uses_drawid
)
3216 emit_draw_index(cmd_buffer
, i
);
3218 load_indirect_parameters(cmd_buffer
, draw
, true);
3220 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3221 prim
.IndirectParameterEnable
= true;
3222 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3223 prim
.VertexAccessType
= RANDOM
;
3224 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3231 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3234 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3235 struct anv_address count_address
,
3236 const bool conditional_render_enabled
)
3238 struct gen_mi_builder b
;
3239 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3241 if (conditional_render_enabled
) {
3242 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3243 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3244 gen_mi_mem32(count_address
));
3247 /* Upload the current draw count from the draw parameters buffer to
3248 * MI_PREDICATE_SRC0.
3250 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3251 gen_mi_mem32(count_address
));
3253 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3258 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3259 uint32_t draw_index
)
3261 struct gen_mi_builder b
;
3262 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3264 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3265 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3267 if (draw_index
== 0) {
3268 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3269 mip
.LoadOperation
= LOAD_LOADINV
;
3270 mip
.CombineOperation
= COMBINE_SET
;
3271 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3274 /* While draw_index < draw_count the predicate's result will be
3275 * (draw_index == draw_count) ^ TRUE = TRUE
3276 * When draw_index == draw_count the result is
3277 * (TRUE) ^ TRUE = FALSE
3278 * After this all results will be:
3279 * (FALSE) ^ FALSE = FALSE
3281 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3282 mip
.LoadOperation
= LOAD_LOAD
;
3283 mip
.CombineOperation
= COMBINE_XOR
;
3284 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3289 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3291 emit_draw_count_predicate_with_conditional_render(
3292 struct anv_cmd_buffer
*cmd_buffer
,
3293 uint32_t draw_index
)
3295 struct gen_mi_builder b
;
3296 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3298 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3299 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3300 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3303 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3305 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3306 * so we emit MI_PREDICATE to set it.
3309 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3310 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3312 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3313 mip
.LoadOperation
= LOAD_LOADINV
;
3314 mip
.CombineOperation
= COMBINE_SET
;
3315 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3321 void genX(CmdDrawIndirectCountKHR
)(
3322 VkCommandBuffer commandBuffer
,
3324 VkDeviceSize offset
,
3325 VkBuffer _countBuffer
,
3326 VkDeviceSize countBufferOffset
,
3327 uint32_t maxDrawCount
,
3330 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3331 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3332 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3333 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3334 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3335 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3337 if (anv_batch_has_error(&cmd_buffer
->batch
))
3340 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3342 struct anv_address count_address
=
3343 anv_address_add(count_buffer
->address
, countBufferOffset
);
3345 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3346 cmd_state
->conditional_render_enabled
);
3348 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3349 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3351 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3352 if (cmd_state
->conditional_render_enabled
) {
3353 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3355 emit_draw_count_predicate(cmd_buffer
, i
);
3358 emit_draw_count_predicate(cmd_buffer
, i
);
3361 if (vs_prog_data
->uses_firstvertex
||
3362 vs_prog_data
->uses_baseinstance
)
3363 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3364 if (vs_prog_data
->uses_drawid
)
3365 emit_draw_index(cmd_buffer
, i
);
3367 load_indirect_parameters(cmd_buffer
, draw
, false);
3369 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3370 prim
.IndirectParameterEnable
= true;
3371 prim
.PredicateEnable
= true;
3372 prim
.VertexAccessType
= SEQUENTIAL
;
3373 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3380 void genX(CmdDrawIndexedIndirectCountKHR
)(
3381 VkCommandBuffer commandBuffer
,
3383 VkDeviceSize offset
,
3384 VkBuffer _countBuffer
,
3385 VkDeviceSize countBufferOffset
,
3386 uint32_t maxDrawCount
,
3389 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3390 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3391 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3392 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3393 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3394 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3396 if (anv_batch_has_error(&cmd_buffer
->batch
))
3399 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3401 struct anv_address count_address
=
3402 anv_address_add(count_buffer
->address
, countBufferOffset
);
3404 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3405 cmd_state
->conditional_render_enabled
);
3407 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3408 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3410 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3411 if (cmd_state
->conditional_render_enabled
) {
3412 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3414 emit_draw_count_predicate(cmd_buffer
, i
);
3417 emit_draw_count_predicate(cmd_buffer
, i
);
3420 /* TODO: We need to stomp base vertex to 0 somehow */
3421 if (vs_prog_data
->uses_firstvertex
||
3422 vs_prog_data
->uses_baseinstance
)
3423 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3424 if (vs_prog_data
->uses_drawid
)
3425 emit_draw_index(cmd_buffer
, i
);
3427 load_indirect_parameters(cmd_buffer
, draw
, true);
3429 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3430 prim
.IndirectParameterEnable
= true;
3431 prim
.PredicateEnable
= true;
3432 prim
.VertexAccessType
= RANDOM
;
3433 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3440 void genX(CmdBeginTransformFeedbackEXT
)(
3441 VkCommandBuffer commandBuffer
,
3442 uint32_t firstCounterBuffer
,
3443 uint32_t counterBufferCount
,
3444 const VkBuffer
* pCounterBuffers
,
3445 const VkDeviceSize
* pCounterBufferOffsets
)
3447 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3449 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3450 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3451 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3453 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3455 * "Ssoftware must ensure that no HW stream output operations can be in
3456 * process or otherwise pending at the point that the MI_LOAD/STORE
3457 * commands are processed. This will likely require a pipeline flush."
3459 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3460 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3462 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3463 /* If we have a counter buffer, this is a resume so we need to load the
3464 * value into the streamout offset register. Otherwise, this is a begin
3465 * and we need to reset it to zero.
3467 if (pCounterBuffers
&&
3468 idx
>= firstCounterBuffer
&&
3469 idx
- firstCounterBuffer
< counterBufferCount
&&
3470 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3471 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3472 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3473 uint64_t offset
= pCounterBufferOffsets
?
3474 pCounterBufferOffsets
[cb_idx
] : 0;
3476 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3477 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3478 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3482 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3483 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3489 cmd_buffer
->state
.xfb_enabled
= true;
3490 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3493 void genX(CmdEndTransformFeedbackEXT
)(
3494 VkCommandBuffer commandBuffer
,
3495 uint32_t firstCounterBuffer
,
3496 uint32_t counterBufferCount
,
3497 const VkBuffer
* pCounterBuffers
,
3498 const VkDeviceSize
* pCounterBufferOffsets
)
3500 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3502 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3503 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3504 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3506 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3508 * "Ssoftware must ensure that no HW stream output operations can be in
3509 * process or otherwise pending at the point that the MI_LOAD/STORE
3510 * commands are processed. This will likely require a pipeline flush."
3512 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3513 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3515 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3516 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3518 /* If we have a counter buffer, this is a resume so we need to load the
3519 * value into the streamout offset register. Otherwise, this is a begin
3520 * and we need to reset it to zero.
3522 if (pCounterBuffers
&&
3523 cb_idx
< counterBufferCount
&&
3524 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3525 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3526 uint64_t offset
= pCounterBufferOffsets
?
3527 pCounterBufferOffsets
[cb_idx
] : 0;
3529 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3530 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3532 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3537 cmd_buffer
->state
.xfb_enabled
= false;
3538 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3542 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3544 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3545 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3548 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3549 if (result
!= VK_SUCCESS
) {
3550 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3552 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3553 if (result
!= VK_SUCCESS
)
3556 /* Re-emit state base addresses so we get the new surface state base
3557 * address before we start emitting binding tables etc.
3559 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3561 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3562 if (result
!= VK_SUCCESS
) {
3563 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3568 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3569 if (result
!= VK_SUCCESS
) {
3570 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3574 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3575 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3576 .BindingTablePointer
= surfaces
.offset
,
3577 .SamplerStatePointer
= samplers
.offset
,
3579 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3581 struct anv_state state
=
3582 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3583 pipeline
->interface_descriptor_data
,
3584 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3587 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3588 anv_batch_emit(&cmd_buffer
->batch
,
3589 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3590 mid
.InterfaceDescriptorTotalLength
= size
;
3591 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3598 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3600 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3603 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3605 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3607 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3610 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
3613 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3614 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3616 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3617 * the only bits that are changed are scoreboard related: Scoreboard
3618 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3619 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3622 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3623 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3625 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3628 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3629 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3630 /* FIXME: figure out descriptors for gen7 */
3631 result
= flush_compute_descriptor_set(cmd_buffer
);
3632 if (result
!= VK_SUCCESS
)
3635 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3638 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3639 struct anv_state push_state
=
3640 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3642 if (push_state
.alloc_size
) {
3643 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3644 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3645 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3649 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3652 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3654 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3660 verify_cmd_parser(const struct anv_device
*device
,
3661 int required_version
,
3662 const char *function
)
3664 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3665 return vk_errorf(device
->instance
, device
->instance
,
3666 VK_ERROR_FEATURE_NOT_PRESENT
,
3667 "cmd parser version %d is required for %s",
3668 required_version
, function
);
3677 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3678 uint32_t baseGroupX
,
3679 uint32_t baseGroupY
,
3680 uint32_t baseGroupZ
)
3682 if (anv_batch_has_error(&cmd_buffer
->batch
))
3685 struct anv_push_constants
*push
=
3686 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3687 if (push
->base_work_group_id
[0] != baseGroupX
||
3688 push
->base_work_group_id
[1] != baseGroupY
||
3689 push
->base_work_group_id
[2] != baseGroupZ
) {
3690 push
->base_work_group_id
[0] = baseGroupX
;
3691 push
->base_work_group_id
[1] = baseGroupY
;
3692 push
->base_work_group_id
[2] = baseGroupZ
;
3694 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3698 void genX(CmdDispatch
)(
3699 VkCommandBuffer commandBuffer
,
3704 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3707 void genX(CmdDispatchBase
)(
3708 VkCommandBuffer commandBuffer
,
3709 uint32_t baseGroupX
,
3710 uint32_t baseGroupY
,
3711 uint32_t baseGroupZ
,
3712 uint32_t groupCountX
,
3713 uint32_t groupCountY
,
3714 uint32_t groupCountZ
)
3716 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3717 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3718 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3720 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3721 baseGroupY
, baseGroupZ
);
3723 if (anv_batch_has_error(&cmd_buffer
->batch
))
3726 if (prog_data
->uses_num_work_groups
) {
3727 struct anv_state state
=
3728 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3729 uint32_t *sizes
= state
.map
;
3730 sizes
[0] = groupCountX
;
3731 sizes
[1] = groupCountY
;
3732 sizes
[2] = groupCountZ
;
3733 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3734 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3735 .offset
= state
.offset
,
3739 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3741 if (cmd_buffer
->state
.conditional_render_enabled
)
3742 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3744 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3745 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3746 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3747 ggw
.ThreadDepthCounterMaximum
= 0;
3748 ggw
.ThreadHeightCounterMaximum
= 0;
3749 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3750 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3751 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3752 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3753 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3754 ggw
.BottomExecutionMask
= 0xffffffff;
3757 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3760 #define GPGPU_DISPATCHDIMX 0x2500
3761 #define GPGPU_DISPATCHDIMY 0x2504
3762 #define GPGPU_DISPATCHDIMZ 0x2508
3764 void genX(CmdDispatchIndirect
)(
3765 VkCommandBuffer commandBuffer
,
3767 VkDeviceSize offset
)
3769 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3770 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3771 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3772 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3773 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3774 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3776 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3779 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3780 * indirect dispatch registers to be written.
3782 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3783 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3787 if (prog_data
->uses_num_work_groups
)
3788 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3790 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3792 struct gen_mi_builder b
;
3793 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3795 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3796 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3797 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3799 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3800 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3801 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3804 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3805 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3806 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3807 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3808 mip
.LoadOperation
= LOAD_LOAD
;
3809 mip
.CombineOperation
= COMBINE_SET
;
3810 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3813 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3814 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3815 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3816 mip
.LoadOperation
= LOAD_LOAD
;
3817 mip
.CombineOperation
= COMBINE_OR
;
3818 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3821 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3822 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3823 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3824 mip
.LoadOperation
= LOAD_LOAD
;
3825 mip
.CombineOperation
= COMBINE_OR
;
3826 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3829 /* predicate = !predicate; */
3830 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3831 mip
.LoadOperation
= LOAD_LOADINV
;
3832 mip
.CombineOperation
= COMBINE_OR
;
3833 mip
.CompareOperation
= COMPARE_FALSE
;
3837 if (cmd_buffer
->state
.conditional_render_enabled
) {
3838 /* predicate &= !(conditional_rendering_predicate == 0); */
3839 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3840 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3841 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3842 mip
.LoadOperation
= LOAD_LOADINV
;
3843 mip
.CombineOperation
= COMBINE_AND
;
3844 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3849 #else /* GEN_GEN > 7 */
3850 if (cmd_buffer
->state
.conditional_render_enabled
)
3851 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3854 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3855 ggw
.IndirectParameterEnable
= true;
3856 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3857 cmd_buffer
->state
.conditional_render_enabled
;
3858 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3859 ggw
.ThreadDepthCounterMaximum
= 0;
3860 ggw
.ThreadHeightCounterMaximum
= 0;
3861 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3862 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3863 ggw
.BottomExecutionMask
= 0xffffffff;
3866 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3870 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3873 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3875 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3878 #if GEN_GEN >= 8 && GEN_GEN < 10
3879 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3881 * Software must clear the COLOR_CALC_STATE Valid field in
3882 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3883 * with Pipeline Select set to GPGPU.
3885 * The internal hardware docs recommend the same workaround for Gen9
3888 if (pipeline
== GPGPU
)
3889 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3893 if (pipeline
== _3D
) {
3894 /* There is a mid-object preemption workaround which requires you to
3895 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
3896 * even without preemption, we have issues with geometry flickering when
3897 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
3900 const uint32_t subslices
=
3901 MAX2(cmd_buffer
->device
->instance
->physicalDevice
.subslice_total
, 1);
3902 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
3903 vfe
.MaximumNumberofThreads
=
3904 devinfo
->max_cs_threads
* subslices
- 1;
3905 vfe
.NumberofURBEntries
= 2;
3906 vfe
.URBEntryAllocationSize
= 2;
3911 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3912 * PIPELINE_SELECT [DevBWR+]":
3916 * Software must ensure all the write caches are flushed through a
3917 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3918 * command to invalidate read only caches prior to programming
3919 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3921 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3922 pc
.RenderTargetCacheFlushEnable
= true;
3923 pc
.DepthCacheFlushEnable
= true;
3924 pc
.DCFlushEnable
= true;
3925 pc
.PostSyncOperation
= NoWrite
;
3926 pc
.CommandStreamerStallEnable
= true;
3928 pc
.TileCacheFlushEnable
= true;
3932 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3933 pc
.TextureCacheInvalidationEnable
= true;
3934 pc
.ConstantCacheInvalidationEnable
= true;
3935 pc
.StateCacheInvalidationEnable
= true;
3936 pc
.InstructionCacheInvalidateEnable
= true;
3937 pc
.PostSyncOperation
= NoWrite
;
3939 pc
.TileCacheFlushEnable
= true;
3943 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3947 ps
.PipelineSelection
= pipeline
;
3951 if (devinfo
->is_geminilake
) {
3954 * "This chicken bit works around a hardware issue with barrier logic
3955 * encountered when switching between GPGPU and 3D pipelines. To
3956 * workaround the issue, this mode bit should be set after a pipeline
3960 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3962 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3963 : GLK_BARRIER_MODE_3D_HULL
,
3964 .GLKBarrierModeMask
= 1);
3965 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3969 cmd_buffer
->state
.current_pipeline
= pipeline
;
3973 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3975 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3979 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3981 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3985 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3990 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3992 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3993 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3994 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3995 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3996 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3997 * Depth Flush Bit set, followed by another pipelined depth stall
3998 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3999 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4000 * via a preceding MI_FLUSH)."
4002 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4003 pipe
.DepthStallEnable
= true;
4005 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4006 pipe
.DepthCacheFlushEnable
= true;
4008 pipe
.TileCacheFlushEnable
= true;
4011 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4012 pipe
.DepthStallEnable
= true;
4017 * Update the pixel hashing modes that determine the balancing of PS threads
4018 * across subslices and slices.
4020 * \param width Width bound of the rendering area (already scaled down if \p
4021 * scale is greater than 1).
4022 * \param height Height bound of the rendering area (already scaled down if \p
4023 * scale is greater than 1).
4024 * \param scale The number of framebuffer samples that could potentially be
4025 * affected by an individual channel of the PS thread. This is
4026 * typically one for single-sampled rendering, but for operations
4027 * like CCS resolves and fast clears a single PS invocation may
4028 * update a huge number of pixels, in which case a finer
4029 * balancing is desirable in order to maximally utilize the
4030 * bandwidth available. UINT_MAX can be used as shorthand for
4031 * "finest hashing mode available".
4034 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4035 unsigned width
, unsigned height
,
4039 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4040 const unsigned slice_hashing
[] = {
4041 /* Because all Gen9 platforms with more than one slice require
4042 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4043 * block is guaranteed to suffer from substantial imbalance, with one
4044 * subslice receiving twice as much work as the other two in the
4047 * The performance impact of that would be particularly severe when
4048 * three-way hashing is also in use for slice balancing (which is the
4049 * case for all Gen9 GT4 platforms), because one of the slices
4050 * receives one every three 16x16 blocks in either direction, which
4051 * is roughly the periodicity of the underlying subslice imbalance
4052 * pattern ("roughly" because in reality the hardware's
4053 * implementation of three-way hashing doesn't do exact modulo 3
4054 * arithmetic, which somewhat decreases the magnitude of this effect
4055 * in practice). This leads to a systematic subslice imbalance
4056 * within that slice regardless of the size of the primitive. The
4057 * 32x32 hashing mode guarantees that the subslice imbalance within a
4058 * single slice hashing block is minimal, largely eliminating this
4062 /* Finest slice hashing mode available. */
4065 const unsigned subslice_hashing
[] = {
4066 /* 16x16 would provide a slight cache locality benefit especially
4067 * visible in the sampler L1 cache efficiency of low-bandwidth
4068 * non-LLC platforms, but it comes at the cost of greater subslice
4069 * imbalance for primitives of dimensions approximately intermediate
4070 * between 16x4 and 16x16.
4073 /* Finest subslice hashing mode available. */
4076 /* Dimensions of the smallest hashing block of a given hashing mode. If
4077 * the rendering area is smaller than this there can't possibly be any
4078 * benefit from switching to this mode, so we optimize out the
4081 const unsigned min_size
[][2] = {
4085 const unsigned idx
= scale
> 1;
4087 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4088 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4091 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4092 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4093 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4094 .SubsliceHashing
= subslice_hashing
[idx
],
4095 .SubsliceHashingMask
= -1);
4097 cmd_buffer
->state
.pending_pipe_bits
|=
4098 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4099 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4101 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4103 cmd_buffer
->state
.current_hash_scale
= scale
;
4109 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4111 struct anv_device
*device
= cmd_buffer
->device
;
4112 const struct anv_image_view
*iview
=
4113 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4114 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4116 /* FIXME: Width and Height are wrong */
4118 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4120 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4121 device
->isl_dev
.ds
.size
/ 4);
4125 struct isl_depth_stencil_hiz_emit_info info
= { };
4128 info
.view
= &iview
->planes
[0].isl
;
4130 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4131 uint32_t depth_plane
=
4132 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4133 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4135 info
.depth_surf
= &surface
->isl
;
4137 info
.depth_address
=
4138 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4139 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4140 image
->planes
[depth_plane
].address
.bo
,
4141 image
->planes
[depth_plane
].address
.offset
+
4144 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4147 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4148 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4149 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4150 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4153 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4154 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4155 image
->planes
[depth_plane
].address
.bo
,
4156 image
->planes
[depth_plane
].address
.offset
+
4157 image
->planes
[depth_plane
].aux_surface
.offset
);
4159 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4163 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4164 uint32_t stencil_plane
=
4165 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4166 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4168 info
.stencil_surf
= &surface
->isl
;
4170 info
.stencil_address
=
4171 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4172 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4173 image
->planes
[stencil_plane
].address
.bo
,
4174 image
->planes
[stencil_plane
].address
.offset
+
4177 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4180 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4182 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4186 * This ANDs the view mask of the current subpass with the pending clear
4187 * views in the attachment to get the mask of views active in the subpass
4188 * that still need to be cleared.
4190 static inline uint32_t
4191 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4192 const struct anv_attachment_state
*att_state
)
4194 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4198 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4199 const struct anv_attachment_state
*att_state
)
4201 if (!cmd_state
->subpass
->view_mask
)
4204 uint32_t pending_clear_mask
=
4205 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4207 return pending_clear_mask
& 1;
4211 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4214 const uint32_t last_subpass_idx
=
4215 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4216 const struct anv_subpass
*last_subpass
=
4217 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4218 return last_subpass
== cmd_state
->subpass
;
4222 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4223 uint32_t subpass_id
)
4225 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4226 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4227 cmd_state
->subpass
= subpass
;
4229 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4231 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4232 * different views. If the client asks for instancing, we need to use the
4233 * Instance Data Step Rate to ensure that we repeat the client's
4234 * per-instance data once for each view. Since this bit is in
4235 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4239 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4241 /* It is possible to start a render pass with an old pipeline. Because the
4242 * render pass and subpass index are both baked into the pipeline, this is
4243 * highly unlikely. In order to do so, it requires that you have a render
4244 * pass with a single subpass and that you use that render pass twice
4245 * back-to-back and use the same pipeline at the start of the second render
4246 * pass as at the end of the first. In order to avoid unpredictable issues
4247 * with this edge case, we just dirty the pipeline at the start of every
4250 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4252 /* Accumulate any subpass flushes that need to happen before the subpass */
4253 cmd_buffer
->state
.pending_pipe_bits
|=
4254 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4256 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4257 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4259 bool is_multiview
= subpass
->view_mask
!= 0;
4261 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4262 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4263 if (a
== VK_ATTACHMENT_UNUSED
)
4266 assert(a
< cmd_state
->pass
->attachment_count
);
4267 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4269 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4270 const struct anv_image
*image
= iview
->image
;
4272 /* A resolve is necessary before use as an input attachment if the clear
4273 * color or auxiliary buffer usage isn't supported by the sampler.
4275 const bool input_needs_resolve
=
4276 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4277 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4279 VkImageLayout target_layout
, target_stencil_layout
;
4280 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4281 !input_needs_resolve
) {
4282 /* Layout transitions before the final only help to enable sampling
4283 * as an input attachment. If the input attachment supports sampling
4284 * using the auxiliary surface, we can skip such transitions by
4285 * making the target layout one that is CCS-aware.
4287 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4289 target_layout
= subpass
->attachments
[i
].layout
;
4290 target_stencil_layout
= subpass
->attachments
[i
].stencil_layout
;
4293 uint32_t base_layer
, layer_count
;
4294 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4296 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4297 iview
->planes
[0].isl
.base_level
);
4299 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4300 layer_count
= fb
->layers
;
4303 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4304 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4305 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4306 iview
->planes
[0].isl
.base_level
, 1,
4307 base_layer
, layer_count
,
4308 att_state
->current_layout
, target_layout
);
4311 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4312 transition_depth_buffer(cmd_buffer
, image
,
4313 att_state
->current_layout
, target_layout
);
4314 att_state
->aux_usage
=
4315 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4316 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4319 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4320 transition_stencil_buffer(cmd_buffer
, image
,
4321 iview
->planes
[0].isl
.base_level
, 1,
4322 base_layer
, layer_count
,
4323 att_state
->current_stencil_layout
,
4324 target_stencil_layout
);
4326 att_state
->current_layout
= target_layout
;
4327 att_state
->current_stencil_layout
= target_stencil_layout
;
4329 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4330 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4332 /* Multi-planar images are not supported as attachments */
4333 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4334 assert(image
->n_planes
== 1);
4336 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4337 uint32_t clear_layer_count
= fb
->layers
;
4339 if (att_state
->fast_clear
&&
4340 do_first_layer_clear(cmd_state
, att_state
)) {
4341 /* We only support fast-clears on the first layer */
4342 assert(iview
->planes
[0].isl
.base_level
== 0);
4343 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4345 union isl_color_value clear_color
= {};
4346 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4347 if (iview
->image
->samples
== 1) {
4348 anv_image_ccs_op(cmd_buffer
, image
,
4349 iview
->planes
[0].isl
.format
,
4350 VK_IMAGE_ASPECT_COLOR_BIT
,
4351 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4355 anv_image_mcs_op(cmd_buffer
, image
,
4356 iview
->planes
[0].isl
.format
,
4357 VK_IMAGE_ASPECT_COLOR_BIT
,
4358 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4363 clear_layer_count
--;
4365 att_state
->pending_clear_views
&= ~1;
4367 if (att_state
->clear_color_is_zero
) {
4368 /* This image has the auxiliary buffer enabled. We can mark the
4369 * subresource as not needing a resolve because the clear color
4370 * will match what's in every RENDER_SURFACE_STATE object when
4371 * it's being used for sampling.
4373 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4374 VK_IMAGE_ASPECT_COLOR_BIT
,
4375 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4377 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4378 VK_IMAGE_ASPECT_COLOR_BIT
,
4379 ANV_FAST_CLEAR_ANY
);
4383 /* From the VkFramebufferCreateInfo spec:
4385 * "If the render pass uses multiview, then layers must be one and each
4386 * attachment requires a number of layers that is greater than the
4387 * maximum bit index set in the view mask in the subpasses in which it
4390 * So if multiview is active we ignore the number of layers in the
4391 * framebuffer and instead we honor the view mask from the subpass.
4394 assert(image
->n_planes
== 1);
4395 uint32_t pending_clear_mask
=
4396 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4399 for_each_bit(layer_idx
, pending_clear_mask
) {
4401 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4403 anv_image_clear_color(cmd_buffer
, image
,
4404 VK_IMAGE_ASPECT_COLOR_BIT
,
4405 att_state
->aux_usage
,
4406 iview
->planes
[0].isl
.format
,
4407 iview
->planes
[0].isl
.swizzle
,
4408 iview
->planes
[0].isl
.base_level
,
4411 vk_to_isl_color(att_state
->clear_value
.color
));
4414 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4415 } else if (clear_layer_count
> 0) {
4416 assert(image
->n_planes
== 1);
4417 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4418 att_state
->aux_usage
,
4419 iview
->planes
[0].isl
.format
,
4420 iview
->planes
[0].isl
.swizzle
,
4421 iview
->planes
[0].isl
.base_level
,
4422 base_clear_layer
, clear_layer_count
,
4424 vk_to_isl_color(att_state
->clear_value
.color
));
4426 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4427 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4428 if (att_state
->fast_clear
&& !is_multiview
) {
4429 /* We currently only support HiZ for single-layer images */
4430 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4431 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4432 assert(iview
->planes
[0].isl
.base_level
== 0);
4433 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4434 assert(fb
->layers
== 1);
4437 anv_image_hiz_clear(cmd_buffer
, image
,
4438 att_state
->pending_clear_aspects
,
4439 iview
->planes
[0].isl
.base_level
,
4440 iview
->planes
[0].isl
.base_array_layer
,
4441 fb
->layers
, render_area
,
4442 att_state
->clear_value
.depthStencil
.stencil
);
4443 } else if (is_multiview
) {
4444 uint32_t pending_clear_mask
=
4445 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4448 for_each_bit(layer_idx
, pending_clear_mask
) {
4450 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4452 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4453 att_state
->pending_clear_aspects
,
4454 att_state
->aux_usage
,
4455 iview
->planes
[0].isl
.base_level
,
4458 att_state
->clear_value
.depthStencil
.depth
,
4459 att_state
->clear_value
.depthStencil
.stencil
);
4462 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4464 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4465 att_state
->pending_clear_aspects
,
4466 att_state
->aux_usage
,
4467 iview
->planes
[0].isl
.base_level
,
4468 iview
->planes
[0].isl
.base_array_layer
,
4469 fb
->layers
, render_area
,
4470 att_state
->clear_value
.depthStencil
.depth
,
4471 att_state
->clear_value
.depthStencil
.stencil
);
4474 assert(att_state
->pending_clear_aspects
== 0);
4478 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4479 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4480 iview
->planes
[0].isl
.base_level
== 0 &&
4481 iview
->planes
[0].isl
.base_array_layer
== 0) {
4482 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4483 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4484 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4485 false /* copy to ss */);
4488 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4489 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4490 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4491 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4492 false /* copy to ss */);
4496 if (subpass
->attachments
[i
].usage
==
4497 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4498 /* We assume that if we're starting a subpass, we're going to do some
4499 * rendering so we may end up with compressed data.
4501 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4502 VK_IMAGE_ASPECT_COLOR_BIT
,
4503 att_state
->aux_usage
,
4504 iview
->planes
[0].isl
.base_level
,
4505 iview
->planes
[0].isl
.base_array_layer
,
4507 } else if (subpass
->attachments
[i
].usage
==
4508 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4509 /* We may be writing depth or stencil so we need to mark the surface.
4510 * Unfortunately, there's no way to know at this point whether the
4511 * depth or stencil tests used will actually write to the surface.
4513 * Even though stencil may be plane 1, it always shares a base_level
4516 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4517 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4518 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4519 VK_IMAGE_ASPECT_DEPTH_BIT
,
4520 att_state
->aux_usage
,
4521 ds_view
->base_level
,
4522 ds_view
->base_array_layer
,
4525 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4526 /* Even though stencil may be plane 1, it always shares a
4527 * base_level with depth.
4529 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4530 VK_IMAGE_ASPECT_STENCIL_BIT
,
4532 ds_view
->base_level
,
4533 ds_view
->base_array_layer
,
4538 /* If multiview is enabled, then we are only done clearing when we no
4539 * longer have pending layers to clear, or when we have processed the
4540 * last subpass that uses this attachment.
4542 if (!is_multiview
||
4543 att_state
->pending_clear_views
== 0 ||
4544 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4545 att_state
->pending_clear_aspects
= 0;
4548 att_state
->pending_load_aspects
= 0;
4551 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4554 /* The PIPE_CONTROL command description says:
4556 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
4557 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
4558 * Target Cache Flush by enabling this bit. When render target flush
4559 * is set due to new association of BTI, PS Scoreboard Stall bit must
4560 * be set in this packet."
4562 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4563 pc
.RenderTargetCacheFlushEnable
= true;
4564 pc
.StallAtPixelScoreboard
= true;
4566 pc
.TileCacheFlushEnable
= true;
4572 static enum blorp_filter
4573 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4576 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4577 return BLORP_FILTER_SAMPLE_0
;
4578 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4579 return BLORP_FILTER_AVERAGE
;
4580 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4581 return BLORP_FILTER_MIN_SAMPLE
;
4582 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4583 return BLORP_FILTER_MAX_SAMPLE
;
4585 return BLORP_FILTER_NONE
;
4590 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4592 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4593 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4594 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4595 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4597 if (subpass
->has_color_resolve
) {
4598 /* We are about to do some MSAA resolves. We need to flush so that the
4599 * result of writes to the MSAA color attachments show up in the sampler
4600 * when we blit to the single-sampled resolve target.
4602 cmd_buffer
->state
.pending_pipe_bits
|=
4603 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4604 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4606 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4607 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4608 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4610 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4613 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4614 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4616 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4617 /* From the Vulkan 1.0 spec:
4619 * If the first use of an attachment in a render pass is as a
4620 * resolve attachment, then the loadOp is effectively ignored
4621 * as the resolve is guaranteed to overwrite all pixels in the
4624 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4627 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4628 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4630 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4632 enum isl_aux_usage src_aux_usage
=
4633 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4634 enum isl_aux_usage dst_aux_usage
=
4635 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4637 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4638 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4640 anv_image_msaa_resolve(cmd_buffer
,
4641 src_iview
->image
, src_aux_usage
,
4642 src_iview
->planes
[0].isl
.base_level
,
4643 src_iview
->planes
[0].isl
.base_array_layer
,
4644 dst_iview
->image
, dst_aux_usage
,
4645 dst_iview
->planes
[0].isl
.base_level
,
4646 dst_iview
->planes
[0].isl
.base_array_layer
,
4647 VK_IMAGE_ASPECT_COLOR_BIT
,
4648 render_area
.offset
.x
, render_area
.offset
.y
,
4649 render_area
.offset
.x
, render_area
.offset
.y
,
4650 render_area
.extent
.width
,
4651 render_area
.extent
.height
,
4652 fb
->layers
, BLORP_FILTER_NONE
);
4656 if (subpass
->ds_resolve_attachment
) {
4657 /* We are about to do some MSAA resolves. We need to flush so that the
4658 * result of writes to the MSAA depth attachments show up in the sampler
4659 * when we blit to the single-sampled resolve target.
4661 cmd_buffer
->state
.pending_pipe_bits
|=
4662 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4663 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4665 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4666 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4668 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4669 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4671 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4672 /* From the Vulkan 1.0 spec:
4674 * If the first use of an attachment in a render pass is as a
4675 * resolve attachment, then the loadOp is effectively ignored
4676 * as the resolve is guaranteed to overwrite all pixels in the
4679 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4682 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4683 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4685 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4687 struct anv_attachment_state
*src_state
=
4688 &cmd_state
->attachments
[src_att
];
4689 struct anv_attachment_state
*dst_state
=
4690 &cmd_state
->attachments
[dst_att
];
4692 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4693 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4695 /* MSAA resolves sample from the source attachment. Transition the
4696 * depth attachment first to get rid of any HiZ that we may not be
4699 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4700 src_state
->current_layout
,
4701 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4702 src_state
->aux_usage
=
4703 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4704 VK_IMAGE_ASPECT_DEPTH_BIT
,
4705 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4706 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4708 /* MSAA resolves write to the resolve attachment as if it were any
4709 * other transfer op. Transition the resolve attachment accordingly.
4711 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4713 /* If our render area is the entire size of the image, we're going to
4714 * blow it all away so we can claim the initial layout is UNDEFINED
4715 * and we'll get a HiZ ambiguate instead of a resolve.
4717 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4718 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4719 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4720 render_area
.extent
.height
== dst_iview
->extent
.height
)
4721 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4723 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4725 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4726 dst_state
->aux_usage
=
4727 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4728 VK_IMAGE_ASPECT_DEPTH_BIT
,
4729 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4730 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4732 enum blorp_filter filter
=
4733 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4735 anv_image_msaa_resolve(cmd_buffer
,
4736 src_iview
->image
, src_state
->aux_usage
,
4737 src_iview
->planes
[0].isl
.base_level
,
4738 src_iview
->planes
[0].isl
.base_array_layer
,
4739 dst_iview
->image
, dst_state
->aux_usage
,
4740 dst_iview
->planes
[0].isl
.base_level
,
4741 dst_iview
->planes
[0].isl
.base_array_layer
,
4742 VK_IMAGE_ASPECT_DEPTH_BIT
,
4743 render_area
.offset
.x
, render_area
.offset
.y
,
4744 render_area
.offset
.x
, render_area
.offset
.y
,
4745 render_area
.extent
.width
,
4746 render_area
.extent
.height
,
4747 fb
->layers
, filter
);
4750 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4751 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4753 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4754 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4756 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4757 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4759 enum blorp_filter filter
=
4760 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4762 anv_image_msaa_resolve(cmd_buffer
,
4763 src_iview
->image
, src_aux_usage
,
4764 src_iview
->planes
[0].isl
.base_level
,
4765 src_iview
->planes
[0].isl
.base_array_layer
,
4766 dst_iview
->image
, dst_aux_usage
,
4767 dst_iview
->planes
[0].isl
.base_level
,
4768 dst_iview
->planes
[0].isl
.base_array_layer
,
4769 VK_IMAGE_ASPECT_STENCIL_BIT
,
4770 render_area
.offset
.x
, render_area
.offset
.y
,
4771 render_area
.offset
.x
, render_area
.offset
.y
,
4772 render_area
.extent
.width
,
4773 render_area
.extent
.height
,
4774 fb
->layers
, filter
);
4779 /* On gen7, we have to store a texturable version of the stencil buffer in
4780 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4781 * forth at strategic points. Stencil writes are only allowed in following
4784 * - VK_IMAGE_LAYOUT_GENERAL
4785 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4786 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4787 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4788 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
4790 * For general, we have no nice opportunity to transition so we do the copy
4791 * to the shadow unconditionally at the end of the subpass. For transfer
4792 * destinations, we can update it as part of the transfer op. For the other
4793 * layouts, we delay the copy until a transition into some other layout.
4795 if (subpass
->depth_stencil_attachment
) {
4796 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
4797 assert(a
!= VK_ATTACHMENT_UNUSED
);
4799 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4800 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
4801 const struct anv_image
*image
= iview
->image
;
4803 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4804 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
4805 VK_IMAGE_ASPECT_STENCIL_BIT
);
4807 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
4808 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4809 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
4810 anv_image_copy_to_shadow(cmd_buffer
, image
,
4811 VK_IMAGE_ASPECT_STENCIL_BIT
,
4812 iview
->planes
[plane
].isl
.base_level
, 1,
4813 iview
->planes
[plane
].isl
.base_array_layer
,
4818 #endif /* GEN_GEN == 7 */
4820 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4821 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4822 if (a
== VK_ATTACHMENT_UNUSED
)
4825 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4828 assert(a
< cmd_state
->pass
->attachment_count
);
4829 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4830 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4831 const struct anv_image
*image
= iview
->image
;
4833 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4834 image
->vk_format
!= iview
->vk_format
) {
4835 enum anv_fast_clear_type fast_clear_type
=
4836 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4837 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4838 att_state
->current_layout
);
4840 /* If any clear color was used, flush it down the aux surfaces. If we
4841 * don't do it now using the view's format we might use the clear
4842 * color incorrectly in the following resolves (for example with an
4843 * SRGB view & a UNORM image).
4845 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4846 anv_perf_warn(cmd_buffer
->device
->instance
, iview
,
4847 "Doing a partial resolve to get rid of clear color at the "
4848 "end of a renderpass due to an image/view format mismatch");
4850 uint32_t base_layer
, layer_count
;
4851 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4853 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4854 iview
->planes
[0].isl
.base_level
);
4856 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4857 layer_count
= fb
->layers
;
4860 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4861 uint32_t array_layer
= base_layer
+ a
;
4862 if (image
->samples
== 1) {
4863 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4864 iview
->planes
[0].isl
.format
,
4865 VK_IMAGE_ASPECT_COLOR_BIT
,
4866 iview
->planes
[0].isl
.base_level
,
4868 ISL_AUX_OP_PARTIAL_RESOLVE
,
4869 ANV_FAST_CLEAR_NONE
);
4871 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4872 iview
->planes
[0].isl
.format
,
4873 VK_IMAGE_ASPECT_COLOR_BIT
,
4875 ISL_AUX_OP_PARTIAL_RESOLVE
,
4876 ANV_FAST_CLEAR_NONE
);
4882 /* Transition the image into the final layout for this render pass */
4883 VkImageLayout target_layout
=
4884 cmd_state
->pass
->attachments
[a
].final_layout
;
4885 VkImageLayout target_stencil_layout
=
4886 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
4888 uint32_t base_layer
, layer_count
;
4889 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4891 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4892 iview
->planes
[0].isl
.base_level
);
4894 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4895 layer_count
= fb
->layers
;
4898 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4899 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4900 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4901 iview
->planes
[0].isl
.base_level
, 1,
4902 base_layer
, layer_count
,
4903 att_state
->current_layout
, target_layout
);
4906 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4907 transition_depth_buffer(cmd_buffer
, image
,
4908 att_state
->current_layout
, target_layout
);
4911 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4912 transition_stencil_buffer(cmd_buffer
, image
,
4913 iview
->planes
[0].isl
.base_level
, 1,
4914 base_layer
, layer_count
,
4915 att_state
->current_stencil_layout
,
4916 target_stencil_layout
);
4920 /* Accumulate any subpass flushes that need to happen after the subpass.
4921 * Yes, they do get accumulated twice in the NextSubpass case but since
4922 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4923 * ORing the bits in twice so it's harmless.
4925 cmd_buffer
->state
.pending_pipe_bits
|=
4926 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4929 void genX(CmdBeginRenderPass
)(
4930 VkCommandBuffer commandBuffer
,
4931 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4932 VkSubpassContents contents
)
4934 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4935 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4936 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4938 cmd_buffer
->state
.framebuffer
= framebuffer
;
4939 cmd_buffer
->state
.pass
= pass
;
4940 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4942 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4944 /* If we failed to setup the attachments we should not try to go further */
4945 if (result
!= VK_SUCCESS
) {
4946 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4950 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4952 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4955 void genX(CmdBeginRenderPass2KHR
)(
4956 VkCommandBuffer commandBuffer
,
4957 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4958 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4960 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4961 pSubpassBeginInfo
->contents
);
4964 void genX(CmdNextSubpass
)(
4965 VkCommandBuffer commandBuffer
,
4966 VkSubpassContents contents
)
4968 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4970 if (anv_batch_has_error(&cmd_buffer
->batch
))
4973 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4975 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4976 cmd_buffer_end_subpass(cmd_buffer
);
4977 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4980 void genX(CmdNextSubpass2KHR
)(
4981 VkCommandBuffer commandBuffer
,
4982 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4983 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4985 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4988 void genX(CmdEndRenderPass
)(
4989 VkCommandBuffer commandBuffer
)
4991 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4993 if (anv_batch_has_error(&cmd_buffer
->batch
))
4996 cmd_buffer_end_subpass(cmd_buffer
);
4998 cmd_buffer
->state
.hiz_enabled
= false;
5001 anv_dump_add_attachments(cmd_buffer
);
5004 /* Remove references to render pass specific state. This enables us to
5005 * detect whether or not we're in a renderpass.
5007 cmd_buffer
->state
.framebuffer
= NULL
;
5008 cmd_buffer
->state
.pass
= NULL
;
5009 cmd_buffer
->state
.subpass
= NULL
;
5012 void genX(CmdEndRenderPass2KHR
)(
5013 VkCommandBuffer commandBuffer
,
5014 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5016 genX(CmdEndRenderPass
)(commandBuffer
);
5020 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5022 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5023 struct gen_mi_builder b
;
5024 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5026 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5027 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5028 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5030 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5031 mip
.LoadOperation
= LOAD_LOADINV
;
5032 mip
.CombineOperation
= COMBINE_SET
;
5033 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5038 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5039 void genX(CmdBeginConditionalRenderingEXT
)(
5040 VkCommandBuffer commandBuffer
,
5041 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5043 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5044 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5045 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5046 struct anv_address value_address
=
5047 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5049 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5050 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5052 cmd_state
->conditional_render_enabled
= true;
5054 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5056 struct gen_mi_builder b
;
5057 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5059 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5061 * If the value of the predicate in buffer memory changes
5062 * while conditional rendering is active, the rendering commands
5063 * may be discarded in an implementation-dependent way.
5064 * Some implementations may latch the value of the predicate
5065 * upon beginning conditional rendering while others
5066 * may read it before every rendering command.
5068 * So it's perfectly fine to read a value from the buffer once.
5070 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5072 /* Precompute predicate result, it is necessary to support secondary
5073 * command buffers since it is unknown if conditional rendering is
5074 * inverted when populating them.
5076 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5077 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5078 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5081 void genX(CmdEndConditionalRenderingEXT
)(
5082 VkCommandBuffer commandBuffer
)
5084 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5085 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5087 cmd_state
->conditional_render_enabled
= false;
5091 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5092 * command streamer for later execution.
5094 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5095 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5096 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5097 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5098 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5099 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5100 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5101 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5102 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5103 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5104 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5105 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5106 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5107 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5108 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5110 void genX(CmdSetEvent
)(
5111 VkCommandBuffer commandBuffer
,
5113 VkPipelineStageFlags stageMask
)
5115 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5116 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5118 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5119 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5120 pc
.StallAtPixelScoreboard
= true;
5121 pc
.CommandStreamerStallEnable
= true;
5124 pc
.DestinationAddressType
= DAT_PPGTT
,
5125 pc
.PostSyncOperation
= WriteImmediateData
,
5126 pc
.Address
= (struct anv_address
) {
5127 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5130 pc
.ImmediateData
= VK_EVENT_SET
;
5134 void genX(CmdResetEvent
)(
5135 VkCommandBuffer commandBuffer
,
5137 VkPipelineStageFlags stageMask
)
5139 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5140 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5142 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5143 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5144 pc
.StallAtPixelScoreboard
= true;
5145 pc
.CommandStreamerStallEnable
= true;
5148 pc
.DestinationAddressType
= DAT_PPGTT
;
5149 pc
.PostSyncOperation
= WriteImmediateData
;
5150 pc
.Address
= (struct anv_address
) {
5151 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5154 pc
.ImmediateData
= VK_EVENT_RESET
;
5158 void genX(CmdWaitEvents
)(
5159 VkCommandBuffer commandBuffer
,
5160 uint32_t eventCount
,
5161 const VkEvent
* pEvents
,
5162 VkPipelineStageFlags srcStageMask
,
5163 VkPipelineStageFlags destStageMask
,
5164 uint32_t memoryBarrierCount
,
5165 const VkMemoryBarrier
* pMemoryBarriers
,
5166 uint32_t bufferMemoryBarrierCount
,
5167 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5168 uint32_t imageMemoryBarrierCount
,
5169 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5172 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5174 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5175 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5177 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5178 sem
.WaitMode
= PollingMode
,
5179 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5180 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5181 sem
.SemaphoreAddress
= (struct anv_address
) {
5182 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5188 anv_finishme("Implement events on gen7");
5191 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5192 false, /* byRegion */
5193 memoryBarrierCount
, pMemoryBarriers
,
5194 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5195 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5198 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5199 VkCommandBuffer commandBuffer
,
5200 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5202 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5204 switch (pOverrideInfo
->type
) {
5205 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5209 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5210 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5211 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5212 ._3DRenderingInstructionDisableMask
= true,
5213 .MediaInstructionDisableMask
= true);
5214 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5216 anv_pack_struct(&dw
, GENX(INSTPM
),
5217 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5218 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5219 ._3DRenderingInstructionDisableMask
= true,
5220 .MediaInstructionDisableMask
= true);
5221 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5226 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5227 if (pOverrideInfo
->enable
) {
5228 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5229 cmd_buffer
->state
.pending_pipe_bits
|=
5230 ANV_PIPE_FLUSH_BITS
|
5231 ANV_PIPE_INVALIDATE_BITS
;
5232 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5237 unreachable("Invalid override");
5243 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
5244 VkCommandBuffer commandBuffer
,
5245 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
5247 /* TODO: Waiting on the register to write, might depend on generation. */